WO2018103275A1

WO2018103275A1 - Soc chip having debugging interface security mechanism, and method

Info

Publication number: WO2018103275A1
Application number: PCT/CN2017/085624
Authority: WO
Inventors: 王健; 杨灿华
Original assignee: 上海新微技术研发中心有限公司
Priority date: 2016-12-09
Filing date: 2017-05-24
Publication date: 2018-06-14
Also published as: CN108460296A

Abstract

Provided are a SOC chip having a debugging interface security mechanism, and a method. The chip comprises: a debugging port; a microprocessor, comprising a debugging interface; a storage unit used for pre-storing a security access password of the debugging interface; and a security control unit connected between the debugging port and the debugging interface, and used for monitoring an input timing of an external device connected to the debugging port. When the input timing is correct, an input password is compared with the security access password of the debugging interface; if the comparison result is consistent, a channel from the debugging port to the debugging interface is opened; and if the comparison result is inconsistent, the channel is closed. The present invention adds a security control unit between a physical debugging port and an internal debugging interface, so as to isolate same in terms of physical connection, and the debugging port and the internal debugging interface can be physically connected only when a timing waveform signal including a correct password is input on the debugging port, thereby acquiring a right to access an internal resource.

Description

SOC chip and method with debugging interface security mechanism

Technical field

The invention belongs to the field of system on chip, and relates to a SOC chip and method with a debugging interface security mechanism.

Background technique

System on Chip (SOC), in a narrow sense, is the core of information system integration, is the integration of key components of the system on a chip; in a broad sense, SOC is a micro-mini system, which will Microprocessors, analog IP cores, digital IP cores, and memory (or off-chip memory control interfaces) are integrated on a single chip and are typically custom-tailored or standard-oriented for specific applications.

The hardware debug interface provides an effective method for system testing and on-chip debugging of the SoC chip, but it also poses a security risk.

The current SoC chip will be integrated with the debug interface for chip testing and system debugging. Users can use the PC software for application development or use the programmer to program user programs. However, it provides convenience and brings security risks. The debug interface has been called the "back door" in the industry, that is, by applying specific incentives to the debug port, the purpose of acquiring and modifying the internal resources of the chip and the memory data can be achieved.

Therefore, how to provide a SOC chip and method with a debug interface security mechanism to improve chip security has become an important technical problem to be solved by those skilled in the art.

Summary of the invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a SOC chip and method having a debug interface security mechanism for solving the problem of high security risk of the SOC chip in the prior art.

To achieve the above and other related objects, the present invention provides a SOC chip and method having a debug interface security mechanism, including:

Debug port;

Microprocessor, including debug interface;

a storage unit, configured to pre-store a debug interface security access password;

a security control unit, connected between the debug port and the debug interface, for monitoring an input timing of an external device connected to the debug port; when the input timing is correct, the password is entered and the debug interface is securely accessed. The password is compared; if the comparison result is consistent, the channel between the debug port and the debug interface is opened; if the comparison result is inconsistent, the channel between the debug port and the debug interface is closed.

Optionally, the security control unit includes:

a first password register, connected to the storage unit, for receiving and temporarily storing a debug interface secure access password from the storage unit after the chip is powered on and completing the reset operation;

a second password register for temporarily storing an input password from the external device;

An input timing monitoring unit connected to the debug port and the second password register for monitoring an input timing of an external device connected to the debug port, and writing an input password to the second when the input timing is correct Password register

And a comparator, wherein the two inputs of the comparator are respectively connected to the first password register and the second password register, and are used for comparing the input password with the debug interface security access password.

Optionally, after the chip is powered on and the reset operation is completed, the debug interface secure access password from the storage unit is written to the first password register by pure hardware logic, and the first password register cannot be Processor access.

Optionally, the security control unit is configured to lock the chip when the number of password comparisons exceeds a preset number of times.

Optionally, after the security control unit is configured to lock the chip, the password comparison data is no longer received, and only the memory erase command is received.

Optionally, the preset number of times is 1 to 10.

Optionally, the debug interface security access password is 128 bits.

Optionally, the storage unit is a non-volatile memory.

Optionally, the external device is a host computer or a programmer.

The invention also provides a method for debugging an interface security mechanism, which is applied to a SOC chip with a debug interface security mechanism according to any of the preceding claims, the method comprising:

After the chip is powered on and the reset operation is completed, the debug interface security access password pre-stored in the storage unit is written into the first password register by pure hardware logic, and the first password register cannot be used by the microprocessor. access;

The security control unit constantly monitors an input timing of an external device connected to the debug port, and when the timing is correct, writes an input password to the password register;

After the input password is received, the security control unit compares the input password with the debug interface secure access password;

If the comparison result is consistent, the channel between the debug port and the debug interface is opened; if the comparison result is inconsistent, the channel between the debug port and the debug interface is closed.

As described above, the SOC chip and method having the debug interface security mechanism of the present invention have the following beneficial effects: the present invention adopts a digital circuit architecture to implement secure access of the debug interface, and adds security between the physical debug port and the internal debug interface. Control unit, isolated from the physical connection. The debug port can be physically connected to the internal debug interface only by entering a timing waveform signal containing the correct password on the debug port to gain access to internal resources. The security control unit is responsible for verifying the password and counting the number of comparisons. If the number of comparisons exceeds 3, it is automatically locked. After the chip is locked, the security control unit no longer receives the password comparison data and only receives the NVM memory erase command. The user can only regain the chip control right after executing the NVM memory erase command, and the user data stored in the NVM memory has been erased at this time, thereby realizing the purpose of protecting the user data in the NVM memory unit.

DRAWINGS

FIG. 1 is a schematic diagram showing the structure of a SOC chip with a debug interface security mechanism according to the present invention.

Fig. 2 is a circuit diagram showing the safety control unit.

FIG. 3 is a schematic flow chart showing a method for debugging an interface security mechanism according to the present invention.

Component label description

1 debug port

2 microprocessor

201 debug interface

3 storage unit

4 security control unit

401 first password register

402 second password register

403 input timing monitoring unit

404 comparator

5 external equipment

S1 to S4 steps

detailed description

The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure of the present disclosure. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention.

Please refer to Figure 1 to Figure 3. It should be noted that the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention in a schematic manner, and only the components related to the present invention are shown in the drawings, instead of the number and shape of components in actual implementation. Dimensional drawing, the actual type of implementation of each component's type, number and proportion can be a random change, and its component layout can be more complicated.

The present invention provides a SOC chip and method having a debug interface security mechanism. Referring to FIG. 1, a schematic structural diagram of the SOC chip is shown, including a debug port 1, a microprocessor 2, and a microprocessor. The debug interface 201, the storage unit 3 and the security control unit 4.

Specifically, the storage unit 3 is configured to pre-store the debug interface security access password, and the chip production provider is responsible for maintenance. In this embodiment, the storage unit 3 uses a non-volatile memory (NVM), and when the power is turned off, the stored data does not disappear. The debug interface secure access password is 128 bits.

The security control unit 4 is connected between the debug port 1 and the debug interface 201 for monitoring an input timing of an external device 5 connected to the debug port 1; when the input timing is correct, a password is input. Comparing with the debug interface security access password; if the comparison result is consistent, the channel between the debug port 1 and the debug interface 201 is opened; if the comparison result is inconsistent, the debug port 1 is closed to the debug The channel between the interfaces 201.

In this embodiment, the external device includes but is not limited to a programmer or a host computer.

The invention adopts a digital circuit architecture to realize secure access of the debug interface, and a security control unit is added between the physical debug port and the internal debug interface, and the debug interface of the SOC chip is isolated from the internal debug interface of the chip from the physical connection. The debug port can be physically connected to the internal debug interface only by entering a timing waveform signal containing the correct password on the debug port to gain access to internal resources.

As an example, a circuit configuration diagram of the security control unit 4 is shown in FIG. 2, which includes a first password register 401, a second password register 402, an input timing detection unit 403, and a comparator 404;

The first password register 401 is connected to the storage unit 3 for receiving and temporarily storing the debug interface secure access password from the storage unit 3 after the chip is powered on and the reset operation is completed.

In this embodiment, the debug interface security access password stored in the storage unit 3 can be written into the specific register by the hardware logic only after the system is powered on, and the CPU and the debug interface cannot access the storage unit 3 and The first password register 401.

The second password register 402 is used to temporarily store an input password from the external device 1.

The input timing monitoring unit 403 and the debug port 1 and the second password register 402 Connected for monitoring the input timing of an external device connected to the debug port 1, and writing an input password to the second password register 402 when the input timing is correct.

The two inputs of the comparator 404 are respectively connected to the first password register 401 and the second password register 402 for comparing the input password with the debug interface secure access password.

Specifically, the security control unit 4 is configured to count the number of comparisons when verifying the password, and lock the chip when the number of password comparisons exceeds a preset number of times.

As an example, the preset number of times may be 1 to 10. In this embodiment, the preset number of times is preferably 3, that is, when the password comparison fails more than 3 times, the chip is automatically locked.

In this embodiment, the security control unit 4 is further configured to receive no password comparison data and only receive the memory erase command after the chip is locked. That is, the user can only regain the control of the chip after executing the memory erase command, and the user data stored in the memory has been erased at this time, even if the chip is illegally acquired, only the "white film" is obtained, thereby The purpose of protecting the user program in the memory is achieved.

3 is a schematic flow chart of a method for modulating an interface security mechanism according to the present invention, where the method includes:

Step S1: After the chip is powered on and the reset operation is completed, the debug interface security access password pre-stored in the storage unit 3 is written into the first password register by pure hardware logic, and the first password register cannot be used. Microprocessor 2 access;

Step S2: The security control unit 4 monitors the input timing of the external device 5 connected to the debug port 1 at a time, and when the timing is correct, writes the input password into the second password register;

Step S3: After the input password is received, the security control unit 4 compares the input password with the debug interface security access password;

Step S4: If the comparison result is consistent, the channel between the debug port 1 and the debug interface 201 is opened; if the comparison result is inconsistent, the channel between the debug port 1 and the debug interface 201 is closed.

The method for modulating the interface security mechanism of the present invention saves the 128-bit debug interface secure access password in a specific non-volatile memory, and the system configuration phase can be written into the specific password register by the hardware logic after the chip is powered on, the CPU and the debug The interface cannot access the non-volatile memory and the password register. When the password comparison fails more than a certain number of times, the chip is locked. After the chip is locked, the security control unit no longer accepts the password comparison data, and only accepts the non-volatile memory wipe. In addition to instructions, it is possible to effectively prevent illegal acquisition and modification of internal resources of the chip as well as memory data.

In summary, the SOC chip and method with the internal data anti-tampering mechanism of the invention adopts a digital circuit architecture to implement secure access of the debug interface, and a security control unit is added between the physical debug port and the internal debug interface, and the physical connection is obtained. Isolated on. The debug port can be physically connected to the internal debug interface only by entering a timing waveform signal containing the correct password on the debug port to gain access to internal resources. The security control unit is responsible for verifying the password and counting the number of comparisons. If the number of comparisons exceeds 3, it is automatically locked. After the chip is locked, the security control unit no longer receives the password comparison data and only receives the NVM memory erase command. The user can only regain the chip control right after executing the NVM memory erase command, and the user data stored in the NVM memory has been erased at this time, thereby realizing the purpose of protecting the user data in the NVM memory unit. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications or variations of the above-described embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and scope of the invention will be covered by the appended claims.

Claims

A SOC chip and method having a debug interface security mechanism, comprising:

Debug port;

Microprocessor, including debug interface;

a storage unit, configured to pre-store a debug interface security access password;

a security control unit, connected between the debug port and the debug interface, for monitoring an input timing of an external device connected to the debug port; when the input timing is correct, the password is entered and the debug interface is securely accessed. The password is compared; if the comparison result is consistent, the channel between the debug port and the debug interface is opened; if the comparison result is inconsistent, the channel between the debug port and the debug interface is closed.
The SOC chip and method with a debug interface security mechanism according to claim 1, wherein the security control unit comprises:

a first password register, connected to the storage unit, for receiving and temporarily storing a debug interface secure access password from the storage unit after the chip is powered on and completing the reset operation;

a second password register for temporarily storing an input password from the external device;

An input timing monitoring unit connected to the debug port and the second password register for monitoring an input timing of an external device connected to the debug port, and writing an input password to the second when the input timing is correct Password register

And a comparator, wherein the two inputs of the comparator are respectively connected to the first password register and the second password register, and are used for comparing the input password with the debug interface security access password.
The SOC chip and method with a debug interface security mechanism according to claim 2, wherein after the chip is powered on and the reset operation is completed, the debug interface secure access password from the storage unit is written by pure hardware logic. The first password register, the first password register is inaccessible to the microprocessor.
The SOC chip and method with a debug interface security mechanism according to claim 1, wherein the security control unit is configured to lock the chip when the number of password comparisons exceeds a preset number of times.
The SOC chip and method with a debug interface security mechanism according to claim 4, wherein the security control unit is configured to lock the chip, no longer receive the password comparison data, and only receive the memory erase command.
The SOC chip and method with a debug interface security mechanism according to claim 4, wherein the preset number of times is 1 to 10.
The SOC chip and method with a debug interface security mechanism according to claim 1, wherein the debug interface secure access password is 128 bits.
The SOC chip and method having a debug interface security mechanism according to claim 1, wherein the storage unit is a non-volatile memory.
The SOC chip and method with a debug interface security mechanism according to claim 1, wherein the external device is a host computer or a programmer.
A method for debugging an interface security mechanism, which is characterized in that it is applied to a SOC chip having a debug interface security mechanism according to any one of claims 1-9, the method comprising:

After the chip is powered on and the reset operation is completed, the debug interface security access password pre-stored in the storage unit is written into the first password register by pure hardware logic, and the first password register cannot be used by the microprocessor. access;

The security control unit constantly monitors an input timing of an external device connected to the debug port, and when the timing is correct, writes the input password to the second password register;

After the input password is received, the security control unit compares the input password with the debug interface secure access password;

If the comparison result is consistent, the channel between the debug port and the debug interface is opened; if the comparison result is inconsistent, the channel between the debug port and the debug interface is closed.