WO2018102365A1 - Injection d'énergie dans un circuit résonnant avec des conditions initiales - Google Patents

Injection d'énergie dans un circuit résonnant avec des conditions initiales Download PDF

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Publication number
WO2018102365A1
WO2018102365A1 PCT/US2017/063632 US2017063632W WO2018102365A1 WO 2018102365 A1 WO2018102365 A1 WO 2018102365A1 US 2017063632 W US2017063632 W US 2017063632W WO 2018102365 A1 WO2018102365 A1 WO 2018102365A1
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Prior art keywords
voltage
circuit
current
energy
resonant
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PCT/US2017/063632
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English (en)
Inventor
Ionel Jitaru
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Ionel Jitaru
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Publication of WO2018102365A1 publication Critical patent/WO2018102365A1/fr

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/083—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the ignition at the zero crossing of the voltage or the current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H02M1/4258—Arrangements for improving power factor of AC input using a single converter stage both for correction of AC input power factor and generation of a regulated and galvanically isolated DC output voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33538—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only of the forward type
    • H02M3/33546—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only of the forward type with automatic control of the output voltage or current
    • H02M3/33553—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only of the forward type with automatic control of the output voltage or current with galvanic isolation between input and output of both the power stage and the feedback loop
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F38/00—Adaptations of transformers or inductances for specific applications or functions
    • H01F38/42—Flyback transformers
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H02M1/0058—Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H02M1/34—Snubber circuits
    • H02M1/342—Active non-dissipative snubbers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the resonant circuit formed by an inductive element and the parasitic capacitance across a switching element is part of many topologies used in power conversion. Traditionally this resonant circuit causes ringing across the switching element and the energy contained in the resonant circuit is dissipated. The continuous quest for higher efficiency and higher power density lead to a detailed study of this resonant circuit and several solutions to harvest this energy are presented in this patent application. In this application are also described several solutions to inject additional energy in the resonant circuit with initial conditions previously described in order to create zero voltage switching conditions across the switching element at the time when the switching elements turns on.
  • the resonant circuit with initial condition is part of many topologies presently used, such as flyback topology, boost topology, sepic topology, buck topology two transistor forward topology and many others.
  • This application will focus mostly on the flyback and boost topology, though the same concept claimed in this patent will also apply to the rest of topologies.
  • This patent application will offer solutions to harvest the energy in the resonant circuit with initial conditions and also solution of energy injection into the resonant circuit in order to accomplish certain goals such as zero voltage switching conditions across the switching element.
  • the resonant circuit with initial conditions is depicted in Figure 1 A. It is composed by a voltage source, Vin, an inductive element, Lm, a switching device SW, and a capacitor across SW, Ceq.
  • the initial conditions are the voltage across the Ceq, Vr, and the current flowing through Lm, lm.
  • IB are presented the key parameters associated with the resonant circuit with initial conditions such as, the characteristic impedance, Zc, the resonant frequency, ⁇ , the phase lag and the equation for the voltage across Ceq and the current through Lm.
  • FIG 1C is depicted the voltage across Ceq, based on the equations from Figure IB and the current through the inductive element Lm.
  • the voltage across Ceq will start ringing with a frequency given by ⁇ . It will start decaying in a resonant manner from the initial value Vr, decaying to a lowest level, referred also as the first valley and continue to ring.
  • the inductive element Lm and the capacitance Ceq are not ideal devices as a result there will be power dissipation and the amplitude of the ringing will decay as depicted by the dotted line.
  • the energy contained in the resonant circuit with initial conditions will dissipate the voltage across Ceq will be settled to the level of input voltage source, Vin.
  • the current through the inductive element will start from its initial conditions, lm, and ring with the same frequency as the voltage across the Ceq.
  • the initial energy stored in the resonant circuit with initial conditions is the summation of the energy stored in the capacitor Ceq charged with the voltage Vr and the energy contained in the inductive element Lm with the initial current flowing through it, lm. 0009 This resonant circuit with initial conditions is a key part of many topologies.
  • Figure 2A is depicted a flyback topology using a transformer with Nl turns in the primary and N2 turns in the secondary.
  • the dotted line in figure 2A carves out the resonant circuit with initial conditions, which in this case is formed by the primary of the transformer, the Ceq which is the parasitic capacitance reflected across the switch SW.
  • the resonant circuit with initial conditions is also part of the traditional boost converter operating in discontinuous mode as depicted in Figure 3A. It is composed by the primary voltage source, Vin, the inductive element Lm, the switching element SW, and the parasitic capacitance across the switching element SW, Ceq, which is formed by the parasitic capacitance across Lm, SW, and the rectifier Do.
  • the initial voltage conditions across Ceq are the output voltage, Vo. If the rectifier means , Do, does not conduct in reverse and the operation of the boost converter is done only in discontinuous mode there will not be any initial current through Lm.
  • the voltage in the switching node (A) is ringing as depicted in Figure 3B and the amplitude of the ringing will decay as a result of the losses in Lm and Ceq, settling to the level of Vin.
  • the voltage ringing in the switching node (A) will reach zero voltage.
  • FIG. 4 A we identify the resonant circuit with initial conditions as part of the buck topology.
  • the resonant circuit is formed by the inductance element Lm, and the parasitic capacitance across SWl,Ceq, which combines the parasitic capacitance across SW1, SW2 and Lm.
  • the initial voltage condition across Ceql is the input voltage, Vin. The ringing caused by the resonant circuit with initial condition will settle to the Vo voltage level.
  • Figure 5 A depicts the two transistor forward topology wherein we can identify the resonant circuit with initial conditions formed by the primary of the transformer TR1, and the parasitic capacitances Ceql and Ceq2.
  • the initial voltage across the Ceql and Ceq2 is Vin.
  • the voltage across Ceql and Ceq2 will ring as described in Figure 5B and will settle at the voltage which is half of the input voltage Vin/2 across each switching element.
  • the resonant circuit with initial conditions it is present in many topologies and the energy contained in the resonant circuit with initial conditions traditionally has been dissipated. In addition to the energy loss the ringing in the switching node of the resonant circuit with initial conditions create additional noise in the circuit and creates problem in meeting the EMI compliance.
  • FIG. 6A In Figure 6A is presented a Prior Art concept wherein the energy existing in the resonant circuit with initial conditions it is preserved for a period of time when SW aux is turn on. While SWaux is turned on the voltage in the switching node A is not allowed to go below the Vin level. The resonant transition in A starts when the voltage in A is Vr. While the energy containing in Ceq is decreasing by the decrease in the voltage across Ceq, the current through lm is increasing. As depicted in Figure 5B. In the circuit depicted in Figure 6A the current through Im reaches its peak when the voltage in the switching node A reaches Vin.
  • the present invention does offer several solutions wherein the voltage in A will reach zero regardless of the value of Vin and Vr.
  • FIG. 7A and Figure 7B One embodiment of this invention is described in Figure 7A and Figure 7B.
  • the circuit placed across Lm is composed by a voltage source Vinj, a diode Dl and a controlled switching element SWaux.
  • the diode Dl may not be necessary if by sensing and control SWaux will conduct in only one direction.
  • the controlled switching element SWaux is turned on prior the resonant transition which starts at the time tl .
  • Ay time tl the resonant transition starts and the voltage in switch node A starts to decay in a resonant manner.
  • the energy from Ceq is transferred to Lm, and the current through Lm is increasing accordingly.
  • the voltage in the switching node A reaches Vin + Vinj level and the current through Lm reaches the I ring(t2) level as described in Figure 7B.
  • the voltage in A cannot decrease under the level of Vin + Vinj because the SWaux is already on and the voltage in A is clamped to Vin+Vinj level.
  • the voltage across Lm is held at Vinj level.
  • This voltage applied across Lm will generate a current above the Iring (t2) level, additional current which is described by the Iring (t) equation in Figure 7B.
  • Vinj level would be the same as the voltage drop on Dl and the voltage drop across SWaux due to its impedance, then the Iring ( t) will have a constant amplitude. That means that the energy contained in the resonant circuit with initial conditions at time t2 will be perfectly preserved regardless of the losses in Dl, SWaux and Lm.
  • Vinj is tailored to be equal to the voltage drop across Dl and the voltage across SWaux, the voltage in A will decay to the level of the first valley of the natural ringing which will occur if the circuit composed by Vin, Dl, and SWaux would not be placed across Lm.
  • the goal is to inject additional energy in the resonant circuit with initial conditions to obtain lower voltage in A at t4, preferable zero voltage level.
  • the Vinj is tailored accordingly. This circuit offers a very high degree of flexibility to allow the voltage at t4 to reach the desired level. This is a big difference from the Prior Art circuit wherein the voltage in the switching node A will reach the lowest level in the ideal condition equal with the first valley of the natural ringing. In many applications that level is not satisfactory and creates only limited performance enhancement.
  • this embodiment of this invention does offer a very high degree of flexibility in controlling the voltage in A at t4 to reach any desired voltage level, regardless of the transition between Vr and Vin, or the value of the Lm and Ceq or the losses in the resonant circuit with initial conditions and the auxiliary circuit formed by Vin, Dl and SWaux.
  • figure 9A we present an implementation of the embodiment depicted in Figure 7A.
  • the implementation it is in a flyback topology operating in discontinuous mode.
  • the transformer Trl has a primary winding LI, a secondary winding L2 through which the power is delivered to the load connected across Vo. In addition to that there is another winding L3, in the primary side, which is responsible to provide the bias power.
  • the resonant circuit with initial conditions is formed by Vin, LI and Ml controlled by the control signal VCM1, and the parasitic capacitance reflected across Ml .
  • the bias circuit is formed by the bias winding L3, the bias rectifier means M3 controlled by the control signal VCM3. and the bias capacitor C biass.
  • the secondary power circuit is formed by the secondary winding L2, the output capacitor Co and the secondary rectifier means M2 controlled by the control signal VCM2.
  • the additional circuit which is added to this conventional flyback circuit is formed by SWinj, the diode Dl and the Vinj . This additional circuit is placed across the bias winding. It has to be noted that this additional circuit can be placed on any additional winding in the transformer or across secondary winding L2 or primary winding LI .
  • the SWinj can be implemented by an N channel Mosfet driven from the ground level as described in Figure 32, by the driving circuit Db2, Cbl and Rbl .
  • FIG. 9B In Figure 9B are presented the key waveforms associated with the circuit depicted in Figure 9 A.
  • VcMl which is the control signal for the main switch
  • VcM2 which is the control signal for the secondary rectifier means M2
  • VcSWinj which is the control signal for SWinj
  • Vds(Ml) which represents the voltage across the main switch Ml, which is the same as the voltage in the switching node A
  • Imag(Trl) which is the magnetizing current through the transformer
  • I(M1) which is the current through the main switch, Ml .
  • the main switch Ml is turned on.
  • the magnetizing current will built up during this time accumulating energy in the transformer.
  • the current will build up through the main switch as well.
  • FIG. 11A In Figure 11A is presented such a Cinj Charger circuit.
  • the energy for the Vinj is taking during the on time of the main switch Ml in a forward mode.
  • V3 represents the voltage across the Vinj winding, the current through the Lo (inj) inductor element, the voltage across the Cinj capacitor and the injection current I (Dl).
  • V3 changes its polarity and the current through D(inj) will start decaying until reaches zero current level at t2.
  • the primary switch Ml is turned on and the cycle repeats.
  • the average current through Lo(inj) which controls the Vinj level is function of the input voltage and the on time of the primary switch.
  • the proportionality with Vin is desired, the proportionality with on time of the main switch conduction time is not desirable, because the on time is larger at high line and lower at high line makes the Vinj voltage level less dependent of the Vin and makes the Vinj also dependent on the power level which is not one of the goals.
  • the main goal is to make the Vinj proportional with the input voltage and independent of the power level. That is because we want to increase the energy injection into the resonant circuit with initial conditions at higher input voltage where the energy requited to discharge the parasitic capacitance is higher.
  • FIG. 12A is presented another embodiment of this invention wherein the voltage across Cinj, which represents Vinj is proportional with the input voltage and independent of the power level. That is accomplished by using a quasiresonant circuit formed by Lr and Cr.. The circuit functionality is described by the key waveforms depicted in Figure 12B
  • a voltage is applied to the Linj winding which has amplitude of Vin*(N4/Nl).
  • the resonant inductor Lr and the resonant capacitor Cr will resonate creating a resonant current I(Lr) with an amplitude described by the formula from Figure 12B.
  • the current has the half sinusoidal shape because the presence of the diode Drl which does not allow the current to flow in reverse.
  • the resonant current will reach a peak at tl and becomes zero at t2.
  • the voltage across the resonant capacitor reaches amplitude of Vin*(N4/Nl) at tl and twice that amplitude at t2.
  • the energy transfer to the resonant circuit ends and the energy is stored in Cr at t2. That energy is further transferred to the Cinj by the current flowing through Lo(inj) which acts as a current source discharging the voltage across the Cr in between t2 to t4.
  • Lo(inj) acts as a current source discharging the voltage across the Cr in between t2 to t4.
  • a quantum of energy is transferred from the input source Vin, in a forward mode to the resonant capacitor Cr.
  • the energy stored in Cr is proportional with the value of Cr and proportional with the square of the input voltage Vin.
  • the energy contained in the parasitic capacitance reflected across Ml it is also proportional with the square of the input voltage.
  • FIG. 13 is presented another implementation of this concept wherein the additional winding Linj is replaced by a small transformer Tr2 which is connected to the bias winding via a capacitor Cc.
  • This concept has the advantage that the voltage applied to the resonant circuit formed by Cr and Lr can be easily tailored by the turn ratio of the transfer Tr2, N21/N22. In many applications the leakage inductance between L21 and L22 will be forming the resonant inductor Lr. In application wherein this leakage inductance it is not sufficient and additional resonant inductor Lr' is added as per figure 13.
  • the additional transformer can be implemented on a small toroid. This solution it is simpler from manufacturing perspective than adding another winding on the main transformer Trl .
  • the energy injection method claimed in this patent application does also apply to buck topology as the one described in Figure 14 A.
  • the simple buck topology has an input voltage source, Vin, two switching devices, Ml and M2, and inductive element Lo and an output capacitor Co .
  • the additional circuit for energy injection is composed by a diode Dl, a voltage source, Vinj, and a switching element SW1.
  • FIG 14B In Figure 14B are depicted the key waveforms of the topology presented in Figure 14A.
  • the key waveforms are: VcMl which is the driving signal of Ml, VcM2 which is the driving signal of M2, VcSWl which is the driving signal of SW1, the voltage in switching node A, V(A), and the current through Lo, I(Lo).
  • M2 is turned on and the current will continue the conduction through M2.
  • the current through Lo becomes Io(Lo) t4, through at t3 the current through Lo was zero.
  • the current I(Lo)t4 flowing through Lo in the direction from Vo towards A is the expression of the energy contained in the parasitic capacitance between A and ground, at t3. That energy is transferred into the energy of the magnetic field stored in Lo.
  • the two transistor forward topology depicted in Figure 15A is composed by a transformer Trl with a primary winding LI, a secondary winding L2, two primary switchers Ml and M2 and two reset diodes, Drl and Dr2.
  • the forward rectifier means SRI the freewheeling diode means SR2
  • the output inductor Lo the output capacitor Co.
  • VcMl and VcM2 are the control signals for Ml and M2.
  • the control signals for Ml and M2 are the same in this topology.
  • the other key waveforms depicted in Figure 15B are, VcSRl, which is the control signal for SRI, VcSR2 which is the control signal for SR2, Vc(SWinj) which is the control signal for SWinj, FM which represents the magnetizing current and the voltage across M2, Vds( M2).
  • the resonant circuit with initial conditions starts the resonant transitions.
  • the resonant circuit is composed by the primary inductance LI and the parasitic capacities reflected across Ml and M2.
  • the initial condition is the voltage across the parasitic capacitances reflected across Ml and M2 which is Vin.
  • the negative magnetizing current is FM(t3). From, t3 to t4 the negative magnetizing current is built up from EVI(t3) to FM(t4) by the voltage source Vinj (Vin) placed across L3.
  • the resonant circuit with initial condition it is also part of the boost topology operating in discontinuous mode circuit described in Figure 3A and B.
  • FIG 16A is depicted a boost converter with the energy injection circuit.
  • the basic boost converter is composed by an inductive element LI, Ml, M2 and the output capacitor Co.
  • the key waveforms of the circuit depicted in 16A are presented in figure 16B. These waveforms are : the control signal for Ml, VcMl, the control signal for M2, Vc M2, the control signal for M3, VcM3, the voltage in the switching node A, the magnetizing current through Tl, Imag(Tl), and the current through M, I(M1).
  • M2 is on and the magnetizing current start decaying towards zero as depicted in Figure 16B.
  • the energy stored in LI is transferred to the output, Vo, flowing through Co and the load placed across Vo.
  • the resonant transition is initiated by the resonant circuit with initial conditions.
  • the voltage in switching node A start decaying in a resonant manner.
  • the energy stored in the parasitic capacitance between A and ground which contains the parasitic capacitance across Ml, M2 and LI, is discharging and that energy and transferred to Tl by building up the magnetizing current in Tl from zero to Imag(Tl)t4.
  • M3 was turned on sometime in between t2 and t3.
  • FIG 17 is presented a bridgeless PFC implementation using one of the embodiments of this invention.
  • the voltage injection which is tailored to ensure zero voltage switching is placed in series with Dl .
  • M3 and M4 will control the energy injection on both phases of the AC line.
  • GaNs switchers are used for Ml and M2 .
  • the diodes D4, D5, D6 and D7 are used to prevent the body conduction of M2 and Ml .
  • the operation of the boost topology in Figure 18 can be done only in discontinuous mode and only in extremes to the boundary conditions. In such a case the diodes D4, D5, D6 and D7 may not be necessary to be placed in the circuit.
  • the low frequency diodes, DLF1 and DLF2 can be replaced by active synchronous rectifiers to further improve the efficiency as depicted in figure 17 and Figure 18.
  • the bridgeless PFC as depicted in Figure 17 and 18 are operating in critical conduction time to obtain zero voltage switching
  • the bridgeless PFC can operate in discontinuous mode and critical conduction as well. In this way the frequency variation it is much narrower than in the operation in critical conduction only.
  • Figure 19A is presented a resonant circuit with initial conditions formed by the input voltage source Vin, an inductive element Lm, a switching element SW, a capacitor Ceq and the initial condition is the voltage Vr across Ceq.
  • FIG 19B are described the key waveforms such as the control of the switching element SW, VcSW, the voltage in the switching node A, and the current injection Iinj .
  • the voltage in switching node A depicts the natural ringing due to the resonance between Lm and Ceq.
  • the current source Iinj which is presented as a half sinusoidal shape is applied just before Vcsw is on with some overlapping with VcSW.
  • the current source Iinj which can be shaped in any form, such as triangle, trapezoidal to rectangular shape, though the easiest implementation and described in details in this patent application, is half sinusoidal.
  • FIG 20 is presented the same concept described in Figure 19A but the current source, Iinj it is placed on the separate winding coupled with the main winding which is part of the resonant circuit with initial conditions. Placing the current source Iinj in a separate winding does offer some key advantages in simplicity.
  • FIG 21A is presented a circuit which employs the energy injection circuit previously presented in this patent and formed by Vinj, Dl and SWaux together with the Iinj circuit. This combination does have several advantages.
  • the voltage in the switching node A does not have the natural ringing as the circuit in figure 19 A.
  • the energy contained in the natural ringing it is harvested and additional energy is further injected in the resonant circuit with initial conditions between t3 to t4 as depicted in Figure 21B.
  • the resonant circuit with initial condition has as initial voltage across Ceq which is Vr. At to the resonant transition starts and the voltage across Ceq is decaying in a resonant manner until the voltage in A reaches Vin+Vinj level which is occurs at tl. At tl the current through Lm which was zero at tO also reaches the level of Im(tl). In between tl to t2 the Vinj is injecting additional energy into the Lm , and at t2 the current through Lm reaches the level of Im(tl) as per equation of Im(t) presented in Figure 2 IB. This mode of energy injection was previously described in this patent application and it is one of the key embodiments of this patent application.
  • the current source Iinj will further discharge the parasitic capacitance reflected across SW towards zero reaching zero level at t4.
  • the switching element SW is turned on by VcSW at t4 when the voltage across SW is zero.
  • the energy injection circuit formed by SWinj,Dl and Vinj is placed across the auxiliary winding L3.
  • a resonant circuit formed by M4, Lr and Cr which is designed to generate the Iinj as per Figure 21 and Figure 20.
  • FIG. 23 Another implementation of the circuit described in Figure 22 is presented in Figure 23.
  • the resonant circuit which generates the Iinj shaped in a half sinusoidal shape is generated by Lr', Cr and the control switch M4.
  • the leakage inductance between the primary winding LI and the auxiliary winding L4 is part of the resonant circuit in series with Lr', which is placed in the event that the leakage inductance value it is not adequate as depicted in Figure 23.
  • VcMl which is the control signal for Ml
  • VcM2 which is the control signal for M2
  • VcSWinj which is the control signal for SWinj
  • Vds(Ml) which is the voltage across Ml
  • Imag(Trl) which is the magnetizing current though the transformer Trl
  • I(M1) which is the current throughMl
  • Iinj which is the resonant current through the Lr
  • VcM4 which is the control signal for M4.
  • the primary switch Ml turns off and the magnetizing current starts flowing towards the secondary winding L2, initially through the body diode of M2 until M2 is turned on.
  • the energy transfer to the secondary will continue between tl to t2 when the current through M2 will reach zero level and the entire energy stored in the transformer is delivered to the output, to Co and the load placed across Vo.
  • the resonant circuit with initial condition formed by LI and the parasitic capacitance reflected across Ml will start the resonant transition.
  • the initial condition for their resonant circuit it is the voltage across the parasitic capacitance reflected across Ml which is Vin+ (Nl/N2)*Vo.
  • the voltage across Ml will start decaying in a resonant manner until reaches the level of Vin+Vinj *(N1/N3).
  • the natural ringing displayed with dotted line will occur if the energy injection circuit formed by SWinj, Dl and Vinj will not be placed across L3.
  • the energy contained in the resonant circuit with initial conditions previously described is preserved and additional energy injected by Vinj will add to the amplitude of the magnetizing current Imag(Trl) as described in Figure 24, increasing the magnetizing current from Imag(Trl)t3 to Imag(Trl) t4.
  • M4 is turned on and a resonant current Iinj starts flowing through Lr and L3in Figure 22 and through Cr and L4 in Figure 23.
  • the energy is provided by the charge in the resonant capacitor Cr which was charged in the previous cycle.
  • the resonant current Iinj will be transferred to the primary winding and discharge the parasitic capacitance reflected across Ml towards zero.
  • the resonant current Iinj is chosen to be enough to discharge the parasitic capacitance across Ml to zero or slight higher than zero if that would provide the highest efficiency.
  • the primary switching element Ml turns on at zero voltage switching conditions.
  • the resonant current, Iinj will reach zero level at t7 and after that the polarity will change and become negative as depicted in figure 24.
  • the input voltage reflects across L3 with amplitude of Vin*(N3/Nl) in Figure 22.
  • This voltage source is applied across the resonant circuit formed by Lr and Cr and charges Cr in the resonant manner. This energy will be used in the next cycle to discharge the parasitic capacitance reflected across Ml .
  • the Iinj circuit methods of obtaining zero voltage switching can work without the energy injection circuit formed by SWinj, Dl and Vinj . In such a case we will have the natural ringing across Ml but zero voltage switching will be accomplished by the energy stored in Cr.
  • the Iinj methodology can work with more traditional flyback topologies such as the ones using valley detection circuit wherein the main switch turns on at the lowest point of the valley to minimize the switching losses.
  • the energy injection method and the Iinj method can work very well together with the energy injection circuit as described in Figure 22, 23 and 24.
  • the energy injection circuit formed by SWinj, Dl and Vinj may not be as efficienct in injecting the necessary energy for zero voltage switching and the Iinj circuit will add to it helping in getting zero voltage switching.
  • the energy injection circuit has the disadvantage that the energy injection it is function of the dead time period which is the time interval between t3 to t4. That means that at high line and lower power wherein the frequency is lower in order to maximize the efficiency the energy injection it is higher even more than the energy required for zero voltage switching. That may negatively impact the efficiency at light load . For that reason the energy injection may be kept lower in such conditions and use the Iinj to achieve the final zero voltage transition.
  • the on time of M4 it is difficult to tailor to be exactly the duration of a full cycle of the resonant circuit formed by Lr and Cr.
  • the on time of M4 can be smaller than the full cycle because the current of negative polarity of Iinj can also flow through the body diode of M4 , as a result the VcM4 can end sometime between t7 to t8.
  • the engineers with the skills in the art will optimize the balance of energy injection and Iinj for best efficiency or any other design goals.
  • the Iinj circuit it is much simpler to implement and the energy is extracted from the primary during the on time of Ml in a very efficient way.
  • the energy injection circuit has the advantage of harvesting the energy contained in the resonant circuit with initial conditions. Both circuits will work quite well together for maximum efficiency though will add somewhat to the complexity.
  • Figure 25 is presented a boost converter with energy injection circuit formed by Dl,Vinj and M3, all in series and placed across the L2 winding coupled with the main inductor LI .
  • Iinj current source also placed across the L2 winding.
  • Figure 26A is presented the same circuit as Figure 25 with the difference that there is a proposed circuit to implement Iinj .
  • the Iinj current source is implemented by a resonant inductor Lr, a resonant capacitor Cr and a control Mosfet M4.
  • a current source of a given duration, amplitude and phase shift in report to Ml can be constructed.
  • the resonant implementation it is just one of it described in details in Figure 26A.
  • the Iinj circuit can be placed across the L2 winding as per Figure 26A or it can be placed on another independent winding in a way that M4 can be easily driven from the ground as per Figure 23.
  • FIG 26B depicted the key waveforms of the circuit presented in Figure 26A.
  • the key waveforms are: VcMl, which is the control signal for Ml, VcM2 which is the control signal for M2, VcM3 which is the control signal for M3, the voltage in the switching node A, V(A), the magnetizing current through Tl, Imag(Trl), the current through Ml, Id(Ml), the Iinj flowing through Lr and the control signal from M4, VcM4.
  • Ml is on and the magnetizing current is building up through Tl . That is also reflected in the current through Ml .
  • Ml is turned off and the current will continue to flow through LI initially through the body diode of M2 and after that through M2, after M2 is turned on.
  • the energy injection switch M3 is turned on.
  • the M2 is turned off when the current through it reaches zero or slight negative.
  • the initial condition for the resonant circuit wilt initial conditions previously presented is the voltage across the parasitic capacitance reflected between switch node A and ground, which is Vo.
  • the voltage in A starts decaying in a resonant manner until reached the level of Vin+Vinj(Nl/N2).
  • Vin+Vinj(Nl/N2) When the voltage in A reaches Vin+Vinj(Nl/N2), then the magnetizing current will reach Imag(Tl)t3.
  • the magnetizing current started from zero at t2.
  • the Vinj source will build up the magnetizing current to Imag(Tl)t4, at t4.
  • the M3 is turned off.
  • the magnetizing current in Tl will transfer to LI winding and start discharging the parasitic capacitance reflected between switching node A and ground.
  • This parasitic capacitance it is the summation of the parasitic capacitance across Ml and M2, and also the parasitic capacitance across LI winding in parallel with the parasitic capacitance across L2, reflected to the primary across LI .
  • the resonant circuit formed by Lr and Cr is activated by turning on M4.
  • the resonant capacitor Cr was charged from the previous cycle.
  • the current start building up through Lr in a sinusoidal shape reaching a peak level at t6 and after that decaying toward zero at t7. This current will reflect in the primary through LI and start discharging the parasitic capacitance reflected between A and ground.
  • the voltage in A reaches zero.
  • Zero voltage in A can be reached anywhere between t5 to t7, function of the amplitude o Iinj, and the parasitic capacitance reflected between A and ground.
  • the voltage in A reaches zero at t6.
  • the resonant current through Lr will become negative between t7 to t8.
  • the resonant capacitor Cr gets charged in a resonant way from the input voltage reflected across L2. This energy will be used in the next cycle to discharge the parasitic capacitance reflected between A and ground.
  • the energy transferred from Vin to Cr is proportionate with Vin, which is desirable because the energy in the reflected parasitic capacitance between A and ground which has to be discharged is also proportional with the input voltage. .
  • the Iinj methodology wherein a narrow pulse of current is used to discharge the reflected parasitic capacitance between A an ground has an advantage over the energy injection method described in the first part of the patent due to the fact that the cycle of energy extraction form the Vin and the discharging cycle of the parasitic capacitance it is very short and very efficient.
  • This method will also work in the event the boost topology, buck topology, sepic topology or the flyback topology and also the two transistor forward topology and all other topologies which contain a resonant circuit with initial condition as described in figure 1 A, do operate in continuous mode.
  • the boost converter can operate in continuous mode wherein the Ml will turn on when M2 is conducting.
  • the Iinj is activated like in discontinuous mode operation prior to the turn on of Ml .
  • the peak resonant current through Lr reflected in the primary shall be larger than the current flowing through M2.
  • the resonant current inj ected will overwhelmed the current through M2 and it will create zero current condition for M2 to turn off. Further, the injected resonant current will discharge the parasitic capacitance between A and ground and will create zero voltage switching conditions for Ml at turn on.
  • This resonant current injection technology will work very well in conjunction with the energy injection method when the operation is done in discontinuous mode.
  • the boost, buck, flyback, sepic, two transistor forward and others operates in continuous mode the resonant current injection will be used and when these topologies operate in discontinuous mode, the energy injection technology will be activated in order to harvest the energy contained in the resonant circuit with initial conditions which otherwise will create natural ringing and that energy will be dissipated.
  • the energy injection circuit is activate the resonant current injection may still operate or it can be deactivated function of the design targets.
  • a clamp circuit is used as an active clamp with with the purpose of recycling the leakage inductance energy and to eliminate the spikes across the main switching element due to the leakage inductance.
  • a clamp circuit is used as an active clamp with the clamp circuit driven by a controller from the ground level via a driving transformer circuit. This method does add complexity and cost. In application such as AC -DC adapters the additional cost may be prohibitive due to tremendous price pressure in the consumer market where these adapters are used.
  • FIG 27 is presented a circuit using this embodiment.
  • the drive circuit is connected to a driving winding in the main transformer and the clamp switch is self driven in this way from the main transformer.
  • This concept it is very simple and very low cost comparative with the solution proposed in the patent application'Tartial Time Active Clamp Flyback" , application # 62075518.
  • the input voltage Vin in AC -DC adapter application will vary to a range of almost 4: 1.
  • the output voltage in the latest generation of adapters has to comply with the Power Delivery Specification version 2.0 for at least two USB 3.1 ports.
  • the output voltage will vary between 5V to 20V This will allow power supplies complying with the new specification to be used universally, which promotes reuse and reduces waste.
  • the old USB standard has been used in this way and has been mandated in several countries, the new specification expands on this universal use by allowing multiple voltages on the USB bus. This is needed since most laptop computers consume more than 10W which is what the old USB standard allowed. By allowing higher voltage more power can be delivered on the new 3 A rated cable and connector.
  • Figure 28A is presented such a circuit. It is a simple circuit using a resistor divider Rl and R2 in order to minimize the reverse voltage in gate of Ml during the on time of Ml .
  • a diode Dl across Rl will apply the full voltage reflected from the secondary which which is proportionate with the output voltage in the range from 5 V to 20V.
  • FIG 28B are presented the key waveforms of this drive circuit described in Figure 27 and 28A.
  • the waveforms depicted are: VcMl, which is the control signal for Ml, VcM2, which is the control signal for M2, Vds(Ml) which is the voltage in drain of Ml, the voltage in the switching node A and the voltage in the switching node B as presented in Figure 28 A, and the current through the clamp switch M3.
  • VcMl which is the control signal for Ml
  • VcM2 which is the control signal for M2
  • Vds(Ml) which is the voltage in drain of Ml
  • the voltage in the switching node A and the voltage in the switching node B as presented in Figure 28 A and the current through the clamp switch M3.
  • the primary switch Ml is on and the energy is stored in the transformer Trl .
  • the voltage in the switching node A is negative and has an amplitude of Vin (N3/N1).
  • the voltage in the switching node B is lower due to the voltage divider and it is Vin(N3/Nl)*( R2/(R1+R2)).
  • Rl and R2 will be chosen to ensure that the voltage in gate in the worst case, which is the highest input voltage, will not exceed the gate to source rating of M3.
  • the circuit depicted in Figure 28A does have some key advantages as simplicity but does have several limitations.
  • One of the limitations is the fact that M3 is still on for the time interval t2 to t3 until the voltage in B decreases under the threshold level.
  • M3 may be on when the main switch Ml will turn on. Though when that will happen the voltage in B will collapse rapidly there may be still risk of cross conduction.
  • the main switch Ml In between tO to tl the main switch Ml is on and the energy from Vin is stored in the transformer Trl in magnetic field energy. At tl the main switch Ml turns off and the magnetizing current will flow towards the secondary through synchronized rectifier Ml . At t2 the energy stored in the magnetic field of Trl is totally transferred to the secondary and M2 is turned off.
  • the voltage in the switching node A collapses the voltage in B will start collapsing by AV due to the redistribution of charges between the gate to source capacitor and CI . That will happen in at t2.
  • the circuit depicted in 29A is designed to react to the AV collapsed in the gate of M3 and ensure that the voltage in B becomes zero.
  • the circuit formed by D2 and C2 is designed to work as peak detector which memorized the voltage in A during the time interval tl to t2.
  • the circuit formed by Ql, R3 and R4 act as a AV detection.
  • Ql turns on and turns on Ml which will discharge the gate to source to zero.
  • the voltage in gate of M3 is zero during the dead time period. This circuit will also work in the event that there is an additional dc voltage in A due to the energy injection circuit.
  • the gate drive circuit There are many other ways to implement the gate drive circuit.
  • the key feature of this circuit is that it reacts to a AV decay in the gate of M3 because the charge redistribution between the gate to source capacitor and CI .
  • That AV sensor can be implemented in many other ways not deviating from the spirit of this invention, wherein we use a winding in the transformer to turn on and off the clamp switch M3 and that we ensure a proper off for M3 by sensing the voltage decay AV in the gate after t2.
  • the output voltage will vary between 5 V to 20V.
  • the bias circuit in flyback topology the bias is obtained using a bias winding in the transformer and a diode of a small synchronous rectifier to generate a voltage proportional with the output voltage.
  • the bias supply in the primary becomes a challenge.
  • the bias power has to be also obtained in a very efficient way especially at light loads to meet the demanding specification for efficiently.
  • FIG 30A is presented a concept of deriving the bias power using active regulator.
  • the regulator is formed by a diode Db, an inductive element Lb, and a controlled switching device Mbl .
  • a level shifter is utilized, formed by Dl, Cbl and Rbl .
  • the key waveforms are depicted in Figure 30B.
  • the key waveforms are: VcMl, the control signal for Ml, VcM2, the control signal for M2, Vd(Ml) the voltage across Ml, V(A) the voltage in the switching node A , VcMbl the control signal for Mbl and the current through Lb, I(Lb).
  • the voltage in the switching node A becomes negative and the current is ramped down with a slope proportional with Vo*(N4/N2) +Vbias.
  • the current through Lb will reach zero at t3 and the diode Db does not allow conduction in reverse.
  • Mbl will turn off later at t4. Ideally Mbl shall turn off shortly after t3 to prevent ringing between Lb and the parasitic capacitnaces reflected across Lb.
  • a triangular current I(Lb) is transferred in a forward mode from the input voltage to the Vbias load.
  • To regulate the Vbias the turn on of Mbl is delayed accordigly.
  • To decrease the voltage Vbias the turning on of Mbl is delayed from tl to tl '.
  • the I(Lb) amplitude is decreased and so is the average current flowing through Lb and as result for the same load the Vbias will decrease.
  • This bias circuit it is very simple and low cost and the energy is delivered in a forward mode not impacting the flux swing in the transformer and it is not increasing the core loss of Trl .
  • FIG 31A is depicted a flyback which requires two bias voltages.
  • the second bias voltage is obtained using the method described in Figure 30A and 30B.
  • the waveforms are very similar with the waveforms from Figure 30B.
  • the main difference is the voltage in A which is Vin*(N4/Nl) + Vbiasl .
  • the regulation mode is the same as figure 30B wherein the peak current through Lb is controlled by controlling the delay between tO and the time Mb2 is turned on. For example to increase the average current through Lb de delay from tO will be smaller like dl, and to decrease the average current through Lb the delay should be larger like d2.
  • the traditional bias circuit employing a bias winding and a synchronized rectifier synchronized with M2 is utilized.
  • the additional bias power circuit is activated and the bias circuit using Dbl, Lb, Mb2 will be activated and controlled in a such way that the Vbias is properly regulated.
  • This additional bias circuit is designed to inject additional current in Vbias to regulate the desired voltage. This circuit will inject more current if Vo is lower and if the Vo is set at the highest level presently 20V the circuit will not be activated.
  • Figure 1 A depicts the resonant circuit with initial conditions
  • Figure IB depicts the key equations associated with the resonant circuit with initial conditions
  • Figure 1C depicts the voltage and the current in the resonant circuit with initial conditions
  • Figure 2A presents the resonant circuit with initial conditions a part of a flyback topology
  • Figure 2B depicts the natural ringing associated with the circuit from Figure
  • Figure 3 A presents the resonant circuit with initial conditions a part of a boost topology
  • Figure 3B depicts the natural ringing associated with the circuit from Figure3 A
  • Figure 4A presents the resonant circuit with initial conditions a part of a buck topology
  • Figure 4B depicts the natural ringing associated with the circuit from Figure 4A.
  • Figure 5A depicts the resonant circuit with initial conditions as part of the two transistor forward topology.
  • Figure 5B depicts the natural ringing associated with the circuit from Figure 5 A
  • Figure 6A presents a resonant circuit with initial conditions wherein the energy is preserved by using a shorting switch, which is Prior Art.
  • Figure 6B depicts the key waveforms associated with the circuit from Figure 6A
  • Figure 7 A presents a resonant circuit with initial conditions with the energy injection circuit.
  • Figure 7B depicts the key waveforms associated with the circuit in Figure 7A.
  • Figure 8 depicts a practical implementation of the concept from Figure 7A
  • Figure 9A depicts an implementation of the concept from Figure 7A in a flyback topology.
  • Figure 9B presents the key waveforms associated with the circuit from Figure 9A.
  • Figure 10 presents an implementation of the concept presented in Figure 9 A
  • Figure 11 A presents a practical implementation of the concept from Figure 9 A
  • Figure 1 IB depicts the key waveforms associated with the circuit from Figure 11 A
  • Figure 12A presents another practical implementation of the concept from Figure 9 A
  • Figure 12B depicts the key waveforms of the circuit presented in Figure 12 A.
  • Figure 13 presents another practical implementation of the concept from Figure 9A.
  • Figure 14A is presented the buck topology with energy injection circuit.
  • Figure 14B depicts the key waveforms of the circuit presented in Figure 14 A.
  • Figure 15A depicts the two transistor forward topology with the energy injection circuit.
  • Figure 15B depicts the key waveforms of the topology depicted in Figure 15 A.
  • Figure 16A depicts the boost topology with energy injection circuit.
  • Figure 16B depicts the key waveforms of the topology depicted in Figure 16A.
  • Figure 17 presents the bridgeless totem pole PFC with the energy injection circuit.
  • Figure 18 presents another implementation of the bridgeless totem pole PFC with the energy injection circuit.
  • Figure 19A depicts the resonant circuit with initial conditions with current injection.
  • Figure 19B depicts the key waveforms of the topology depicted in Figure 19A.
  • Figure 20 presents an implementation of the concept depicted in Figure 19 A.
  • Figure 21 A presents a resonant circuit with initial conditions employing energy injection circuit and current injection circuit.
  • Figure 2 IB depicts the key waveforms of the topology depicted in Figure 21 A.
  • Figure 22 presents the flyback topology employing the energy injection circuit and current injection.
  • Figure 23 presents a practical implementation of the flyback topology employing the energy injection circuit and current injection
  • Figure24 depicts the key waveforms of the topology depicted in Figure 23.
  • Figure 25 presents an implementation of the boost topology employing the energy inj ection circuit and current injection.
  • Figure 26A presents a practical implementation of the boost topology employing the energy injection circuit and current injection
  • Figure26B depicts the key waveforms of the topology depicted in Figure 26A.
  • Figure 27 presents a self-driven driving circuit for the clamp circuit.
  • Figure 28A presents the circuity associated with the drive circuit from Figure 27.
  • Figure28B presents the key waveforms of the circuit depicted in Figure 28A.
  • Figure 29A presents another circuit implementation of the drive circuit from Figure 27.
  • Figure 29B presents the key waveforms of the circuit depicted in Figure 29A.
  • Figure 30A presents a bias circuit for a flyback topology
  • Figure 3 OB presents the key waveforms of the circuit depicted in Figure 3 OA
  • Figure 31A presents another implementation of a bias circuit for a flyback topology.
  • Figure 31 B presents the key waveforms of the circuit depicted in Figure 31 A.
  • Figure 32 presents another implementation of a bias circuit for a flyback topology compatible with variable output voltage.

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Abstract

La présente invention introduit le concept d'injection d'énergie dans un circuit résonnant avec des conditions initiales qui fait partie de la quasi-totalité des topologies actuelles. L'invention concerne plusieurs procédés d'injection d'énergie dans un circuit résonnant avec des conditions initiales et la manière dont celle-ci s'applique à différentes topologies. L'invention concerne également un procédé simple et économique d'attaque du commutateur de serrage dans une topologie de retour fonctionnant en mode discontinu et un circuit de polarisation dans une topologie de retour, la tension de sortie variant sur une large plage.
PCT/US2017/063632 2016-12-02 2017-11-29 Injection d'énergie dans un circuit résonnant avec des conditions initiales WO2018102365A1 (fr)

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US20220029523A1 (en) 2022-01-27

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