WO2018099014A1 - 一种基带中频交互方法、系统及存储介质 - Google Patents

一种基带中频交互方法、系统及存储介质 Download PDF

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WO2018099014A1
WO2018099014A1 PCT/CN2017/085572 CN2017085572W WO2018099014A1 WO 2018099014 A1 WO2018099014 A1 WO 2018099014A1 CN 2017085572 W CN2017085572 W CN 2017085572W WO 2018099014 A1 WO2018099014 A1 WO 2018099014A1
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data
intermediate frequency
baseband
configuration information
parameter configuration
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English (en)
French (fr)
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周畅
徐超
龚晓亮
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Sanechips Technology Co Ltd
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Sanechips Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4031—Coupling between buses using bus bridges with arbitration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/003—Arrangements for allocating sub-channels of the transmission path
    • H04L5/0053—Allocation of signalling, i.e. of overhead other than pilot signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/003—Arrangements for allocating sub-channels of the transmission path
    • H04L5/0058—Allocation criteria

Definitions

  • the present invention relates to data transmission technologies in the field of wireless communication, and in particular, to a baseband intermediate frequency interaction method, system and storage medium.
  • a radio frequency signal is mainly used for propagation in space
  • a baseband signal is an original electrical signal that has not undergone spectrum shifting
  • an intermediate frequency signal is a frequency signal that transitions between a radio frequency signal and a baseband signal.
  • the implementation of the baseband and intermediate frequency data interface is to base the baseband part such as a central processing unit (CPU) and an intermediate frequency part such as a Field Programmable Gate Array (FPGA) module as two independent chips.
  • the common public radio interface (CPRI) protocol is used for data transmission between the CPU and the FPGA.
  • this CPRI optical port hardware circuit realizes the independent interaction between the baseband and the intermediate frequency, which not only occupies more circuit area, but also has complicated functions and is not easy to be integrated in a large-scale system-on-chip (SoC). .
  • an existing baseband control chip uses an Advanced High Performance Bus (AHB) interface on-chip to implement data interaction between baseband intermediate frequencies.
  • AHB Advanced High Performance Bus
  • the AHB protocol has poor security and low efficiency. And does not support Out of order data transmission and other characteristics, therefore, has not been widely used by users.
  • the embodiments of the present invention are expected to provide a baseband intermediate frequency interaction method, system, and storage medium, which can save circuit area, improve data transmission efficiency, and support parameter configuration of various LTE standards.
  • the embodiment of the present invention provides a baseband intermediate frequency interaction method, in which a baseband part and an intermediate frequency part are integrated on the same SoC, and parameter configuration information of the LTE system is preset in the baseband part, and the parameter configuration information includes a sampling rate;
  • the method also includes:
  • the data of the corresponding capacity is read from the memory through the AXI bus in each preset time slice, and stored in the cache;
  • Data is read from the cache based on the sampling rate, and the read data is transmitted to the intermediate frequency portion.
  • the parameter configuration information further includes: a Time Division Duplexing (TDD) mode or a Frequency Division Duplexing (FDD) mode, a number of cells, a number of carriers, and an extended performance port (ECP). (Enhanced Capability Port) or Network Control Protocol (NCP), symbol service type.
  • TDD Time Division Duplexing
  • FDD Frequency Division Duplexing
  • ECP extended performance port
  • NCP Network Control Protocol
  • the method further includes: dividing each downlink subframe or symbol into at least two mutually independent preset time slices, and each of the preset time slices has the same cache time.
  • the embodiment of the present invention provides a baseband intermediate frequency interaction method, in which a baseband part and an intermediate frequency part are integrated on the same SoC, and parameter configuration information of the LTE system is preset in the baseband part, and the parameter configuration information includes a sampling rate;
  • the method also includes:
  • data of a corresponding capacity is read from the cache in each preset time slice, and the read data is written into the memory through the AXI bus.
  • the parameter configuration information further includes: a TDD mode or an FDD mode, a number of cells, a number of carriers, an ECP or an NCP, and a symbol service type.
  • the method before the reading the data of the corresponding capacity from the cache, the method further includes: dividing each uplink subframe or symbol into at least two mutually independent preset time slices, each pre-pre- Let the time slice have the same cache time.
  • An embodiment of the present invention provides a baseband intermediate frequency interaction system, where the system includes: a preset module, a first processing module, and a second processing module;
  • the preset module is configured to integrate the baseband portion and the intermediate frequency portion on the same SoC, and preset parameter configuration information of the LTE system in the baseband portion, where the parameter configuration information includes a sampling rate;
  • the first processing module is configured to, according to the parameter configuration information, read data of a corresponding capacity from the memory through the AXI bus in each preset time slice, and store the data in the cache;
  • the second processing module is configured to read data from the cache based on the sampling rate and transmit the read data to the intermediate frequency portion.
  • the first processing module is further configured to divide each downlink subframe or symbol into at least two independent preset times before reading the data of the corresponding capacity from the memory through the AXI bus.
  • the cache time of each preset time slice is the same.
  • the embodiment of the present invention further provides a baseband intermediate frequency interaction system, where the system includes: a preset module, a third processing module, and a fourth processing module;
  • the preset module is configured to integrate the baseband portion and the intermediate frequency portion on the same SoC, and preset parameter configuration information of the LTE system in the baseband portion, where the parameter configuration information includes a sampling rate;
  • the third processing module is configured to write data of the intermediate frequency portion into a cache based on the sampling rate
  • the fourth processing module is configured to read data of a corresponding capacity from the cache in each preset time slice according to the parameter configuration information, and write the read data into the memory through the AXI bus.
  • the fourth processing module is further configured to: after reading the data of the corresponding capacity from the cache, divide each uplink subframe or symbol into at least two mutually independent preset time slices.
  • the cache time of each preset time slice is the same.
  • the embodiment of the invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the baseband intermediate frequency interaction method.
  • the baseband intermediate frequency interaction method, system, and storage medium provided by the embodiments of the present invention integrate the baseband part and the intermediate frequency part on the same SoC, and preset parameter configuration information of the LTE system in the baseband part, where the parameter configuration information includes sampling.
  • the parameter configuration information includes sampling.
  • the corresponding capacity data is read from the memory through the AXI (Advanced Extensible Interface) bus in each preset time slice, and stored in the cache; and the cache is obtained from the cache based on the sampling rate.
  • the data is read and the read data is sent to the intermediate frequency portion.
  • AXI Advanced Extensible Interface
  • the baseband part and the intermediate frequency part are integrated on the same SoC, and the on-chip baseband intermediate frequency interaction based on the AXI bus can not only satisfy the arbitration of the uplink and downlink data requests of multiple cells, but also support various parameter configurations of the LTE system, and also enable the SoC. Get better performance with smaller area and lower power consumption; at the same time, Compared with the standard AHB or APB bus, the AXI bus is used to achieve data exchange with low hardware cost, high bus transmission efficiency, good security, and support for out-of-order data transmission.
  • FIG. 1 is a schematic flowchart of a baseband intermediate frequency interaction method according to Embodiment 1 of the present invention
  • FIG. 2 is a schematic flowchart of a baseband intermediate frequency interaction method according to Embodiment 2 of the present invention.
  • FIG. 3 is a schematic flowchart of a specific implementation process of a baseband intermediate frequency interaction method according to Embodiment 3 of the present invention.
  • FIG. 5 is a schematic flowchart of a specific implementation process of a baseband intermediate frequency interaction method according to Embodiment 4 of the present invention.
  • FIG. 6 is a schematic flowchart of uplink transmission control according to Embodiment 4 of the present invention.
  • FIG. 7 is a schematic structural diagram of a baseband intermediate frequency interaction system according to Embodiment 5 of the present invention.
  • FIG. 8 is a schematic structural diagram of a baseband intermediate frequency interaction system according to Embodiment 6 of the present invention.
  • This embodiment uses the downlink interaction as an example to describe the implementation process of the baseband intermediate frequency interaction method in detail.
  • the implementation process of the baseband intermediate frequency interaction method in the embodiment of the present invention includes the following steps:
  • Step 101 Integrate the baseband part and the intermediate frequency part on the same SoC, and preset parameter configuration information of the LTE system in the baseband part, where the parameter configuration information includes a sampling rate;
  • the parameter configuration information further includes: a TDD mode or an FDD mode, a number of cells, a number of carriers, an ECP or an NCP, and a symbol service type.
  • the symbol service type includes: a normal uplink service and a normal downlink service. All parameter configuration information is stored in the baseband portion.
  • Step 102 Read, according to the parameter configuration information, the data of the corresponding capacity from the memory through the AXI bus in each preset time slice, and store the data in the cache;
  • AXI is a bus protocol, which is the most important part of ARM's AMBA (Advanced Microcontroller Bus Architecture) 3.0 protocol. It is an on-chip bus for high performance, high bandwidth and low latency; AXI Address/control and data phase are separated, support out-of-order data transmission, and in burst transmission, only the first address is needed, the read-write data channel can be separated, and Outstanding transmission access and out-of-order access are supported, and it is easier. Perform timing closure. Therefore, AXI is a new high performance protocol in AMBA.
  • the embodiment of the invention realizes the interaction of the on-chip baseband intermediate frequency based on the AXI bus, and can meet the requirements of ultra-high performance and complex SoC design.
  • the field bus is a device that shares a bus for data communication.
  • An arbitration mechanism to determine who will occupy the bus communication at what time for example: Controller Area Network (CAN, Controller Area Network) adopts priority mode, Transmission Control Protocol/Internet Protocol (TCP/IP, Transmission Control Protocol/Internet) Protocol) uses Carrier Sense Multiple Access with Collision Detection (CSMA/CD) mechanism, while RS-485 uses host polling mechanism.
  • Controller Area Network Controller Area Network
  • TCP/IP Transmission Control Protocol/Internet Protocol
  • CSMA/CD Carrier Sense Multiple Access with Collision Detection
  • RS-485 uses host polling mechanism.
  • the embodiment of the present invention adopts an AXI bus based on arbitration.
  • the method further includes: dividing each downlink subframe or symbol into at least two mutually independent preset time slices, each pre- Let the time slice have the same cache time.
  • the size of the preset time slice is determined by the data length of each downlink subframe or symbol and the size of the storage space, and is not a fixed parameter value.
  • the preset time slice of the embodiment of the present invention has a size of 6.25 us; 6.25us is an empirical value selected by the user according to experience.
  • the sampling rate is 30.72 MHz
  • the buffer here can adopt a ping-pong caching mechanism to save buffer space, thereby achieving seamless buffering and processing of the data stream.
  • Step 103 Read data from the cache based on the sampling rate, and send the read data to the intermediate frequency portion.
  • the downlink data flow control can be realized, and the data can be correctly transmitted without interruption.
  • an uplink interaction is taken as an example to describe the implementation process of the baseband intermediate frequency interaction method in detail.
  • the implementation process of the baseband intermediate frequency interaction method in the embodiment of the present invention includes the following steps:
  • Step 201 Integrate the baseband part and the intermediate frequency part on the same SoC, and preset parameter configuration information of the LTE system in the baseband part, where the parameter configuration information includes a sampling rate;
  • the parameter configuration information further includes: a TDD mode or an FDD mode, a number of cells, a number of carriers, an ECP or an NCP, and a symbol service type.
  • the symbol service type includes: a normal uplink service and a normal downlink service. All parameter configuration information is stored in the baseband portion.
  • Step 202 Write data of the intermediate frequency portion into a buffer based on the sampling rate
  • Step 203 Read data of a corresponding capacity from the cache in each preset time slice according to the parameter configuration information, and write the read data into the memory through the AXI bus.
  • AXI is a bus protocol, which is the AMBA3.0 protocol proposed by ARM.
  • the most important part of the discussion is a high-performance, high-bandwidth, low-latency on-chip bus; AXI's address/control and data phase are separate, supporting out-of-order data transmission, and in burst transmission, Only the first address is needed to separate the read and write data channels, and support Outstanding transport access and out-of-order access, and easier timing closure. Therefore, AXI is a new high performance protocol in AMBA.
  • the embodiment of the invention realizes the interaction of the on-chip baseband intermediate frequency based on the AXI bus, and can meet the requirements of ultra-high performance and complex SoC design.
  • the field bus is a device that shares a bus for data communication.
  • bus contention will occur, which will lead to communication conflict or failure. Therefore, it needs to be introduced on the bus.
  • An arbitration mechanism to determine who will occupy the bus communication at what time for example, CAN uses priority, TCP/IP uses CSMA/CD mechanism, and RS-485 uses host polling mechanism.
  • the embodiment of the present invention adopts an AXI bus based on arbitration.
  • the method further includes: dividing each uplink subframe or symbol into at least two mutually independent preset time slices, each preset The time slice has the same cache time.
  • the size of the preset time slice is determined by the data length of each uplink subframe or symbol and the size of the storage space, and is not a fixed parameter value.
  • the preset time slice of the embodiment of the present invention has a size of 6.25 us; 6.25us is an empirical value selected by the user according to experience.
  • the sampling rate is 30.72 MHz
  • the buffer here can adopt a ping-pong caching mechanism to save buffer space, thereby achieving seamless buffering and processing of the data stream.
  • the uplink data flow control can be realized, and the data can be correctly received without interruption.
  • FIG. 3 is a schematic flowchart of a specific implementation process of a baseband intermediate frequency downlink interaction method according to an embodiment of the present invention. As shown in FIG. 3, the method includes the following steps:
  • Step 301 The baseband unit 301 writes data to be sent in a downlink subframe or symbol into the memory unit 304.
  • each downlink subframe or symbol is divided into at least two mutually independent preset time slices, and the buffer time of each preset time slice is the same.
  • the size of the preset time slice is determined by the data length of each downlink subframe or symbol and the size of the storage space, and is not a fixed parameter value.
  • the preset time slice of the embodiment of the present invention has a size of 6.25 us; 6.25us is an empirical value selected by the user according to experience.
  • Step 302 The baseband unit 301 writes the configuration parameters of the LTE system into the parameter configuration unit 302.
  • the parameter configuration unit 302 obtains the symbol length of each downlink subframe or symbol by looking up Table 1 according to the configured parameters, and calculates Obtaining the number of data to be transmitted in the preset time slice of 6.25us; wherein, Table 1 is the symbol length of the LTE system;
  • the configuration parameters include: TDD/FDD, number of cells, number of carriers, sampling rate, ECP/NCP, and symbol service type; wherein the symbol service type includes: normal uplink service And the normal downlink service, all parameter configuration information is stored in the baseband unit 301.
  • Step 303 The transmission control unit 303 sends a data transmission command to the data transmission unit 306 according to the current symbol length, the number of data transmissions, and the frame start signal;
  • Step 304 The data transmission unit 306 requests data from the memory unit 304 through the AXI bus according to the access timing required by the AXI bus driving unit 305.
  • an AXI bus based on arbitration is employed.
  • Step 305 After receiving the response data of the AXI bus driving unit 305, the data transfer unit 306 writes the data into the buffer unit 307.
  • control data transfer unit 306 reads the corresponding number of data from the memory unit 304 in each preset time slice, that is, 6.25 us, and stores it in the cache.
  • the random access memory RAM, Random Access Memory
  • the data is read from the buffer unit 307 according to a fixed sampling rate, and the time taken to read one side of the RAM is just right. It is 6.25us.
  • the starting address of each symbol in each subframe is different, it is likely that the boundary of the subframe or symbol appears in the same 6.25us time slice. In this case, the data request of the different address needs to be divided into two. Commands that read the data in the entire time slice by two commands.
  • the cache unit 307 can employ a ping-pong caching mechanism to save buffer space, thereby achieving seamless buffering and processing of the data stream.
  • Step 306 The buffer unit 307 outputs data according to the sampling rate configured by the baseband unit 301 for use by the intermediate frequency unit 308 of the lower stage.
  • the baseband unit 301 and the intermediate frequency unit 308 are integrated on the same SoC in advance.
  • FIG. 4 is a schematic flowchart of downlink transmission control according to an embodiment of the present invention. As shown in FIG. 4, the method includes the following steps:
  • Step 401 Determine whether the RAM of either side of the cache unit is empty. If yes, execute step 402; otherwise, end the current processing flow;
  • the control data transmission unit reads a corresponding number of data from the memory into the buffer in each preset time slice.
  • Step 402 Determine whether the number of data to be sent in a symbol is less than 24 chip, and if so, step 403 is performed; otherwise, step 410 is performed;
  • Step 403 Update the memory access length and address of the carrier 1 until the memory access is completed, and update the memory access length and address of the carrier 2 until the memory access is completed.
  • Step 404 Determine whether the current symbol is the last symbol in a subframe, and if so, proceed to step 405, otherwise, perform step 408;
  • Step 405 Send a symbol synchronization header and a subframe synchronization header, and continue to wait in a preset time slice;
  • the boundary is between two sub-frames and appears in the same 6.25us time slice.
  • Step 406 In the waiting process, it is determined whether the next subframe is an uplink subframe, and if so, step 407 is performed, otherwise, step 409 is performed;
  • Step 407 Force the RAM to be full, wait for the subframe synchronization header in the preset time slice, until the next subframe is the downlink subframe, clear the state of the RAM, and return to step 401;
  • Step 408 Send a symbol synchronization header, and continue to wait in the preset time slice;
  • the boundary is between two symbols of one subframe and appears in the same 6.25us time slice.
  • Step 409 During the waiting process, if the next subframe is a downlink subframe, update the memory access length and address of the carrier 1 until the memory access is completed, and update the memory access length and address of the carrier 2 until the memory access is completed.
  • Step 410 Update the memory access length and address of carrier 1 until the memory access is completed, update the memory access length and address of carrier 2, until the memory access is completed, and update the number of sent data;
  • Step 411 Determine whether the current symbol length is equal to the number of updated transmission data, and if so, proceed to step 412, otherwise, return to step 401;
  • Step 412 Determine whether the current symbol is the last symbol in a subframe, and if so, proceed to step 413, otherwise, perform step 415;
  • Step 413 Send a symbol synchronization header and a subframe synchronization header, and continue to wait in a preset time slice;
  • Step 414 In the waiting process, determine whether the next subframe is an uplink subframe, and if yes, return to step 407, otherwise, return to step 401;
  • Step 415 Send the symbol synchronization header, continue to wait in the preset time slice until the preset time slice expires, and return to step 401.
  • FIG. 5 is a schematic flowchart of a specific implementation process of a baseband uplink uplink interaction method according to an embodiment of the present invention. As shown in FIG. 5, the method includes the following steps:
  • Step 501 The baseband unit 501 writes the configuration parameters of the LTE system into the parameter configuration unit 502.
  • the parameter configuration unit 502 obtains the symbol length of each uplink subframe or symbol by looking up Table 1 according to the configured parameters, and calculates Obtaining the number of data to be transmitted within the preset time slice of 6.25us;
  • the configuration parameters include: TDD/FDD, the number of cells, the number of carriers, the sampling rate, the ECP/NCP, and the symbol service type.
  • the symbol service type includes: a normal uplink service and a normal downlink service, and all The parameter configuration information is stored in the baseband unit 501.
  • each uplink subframe or symbol is divided into at least two mutually independent preset time slices, and the buffer time of each preset time slice is the same.
  • the size of the preset time slice is determined by the data length of each uplink subframe or symbol and the size of the storage space, and is not a fixed parameter value.
  • the size of the preset time slice in the embodiment of the present invention is 6.25us; 6.25us is the empirical value chosen by the user based on experience.
  • Step 502 Write the data input by the intermediate frequency unit 508 into the buffer unit 507 according to the sampling rate configured by the baseband unit 501;
  • the cache unit 507 can employ a ping-pong caching mechanism to save buffer space, thereby achieving seamless buffering and processing of the data stream.
  • Step 503 The transmission control unit 503 sends a data transmission command to the data transmission unit 506 according to the current symbol length, the number of data transmissions, and the frame start signal;
  • Step 504 The data transfer unit 506 reads data from the cache unit 507, and writes data to the memory unit 504 through the AXI bus according to the access timing required by the AXI bus drive unit 505.
  • control data transmission unit 506 reads the corresponding number of data from the buffer unit 507 in each preset time slice, that is, 6.25 us, and stores it in the memory.
  • the buffer unit 507 writes data according to a fixed sampling rate, and the time taken to fill the RAM on one side is exactly 6.25 us.
  • the data request of the different address needs to be divided into two. Commands that read the data in the entire time slice by two commands.
  • an AXI bus based on arbitration is employed.
  • the transmission control unit 503 transmits an interrupt to the baseband unit 501.
  • the baseband unit 501 and the intermediate frequency unit 508 are integrated on the same SoC in advance.
  • FIG. 6 is a schematic flowchart of uplink transmission control according to an embodiment of the present invention. As shown in FIG. 6, the method includes the following steps:
  • Step 601 Determine whether the RAM of either side of the cache unit is full, and if yes, execute step 602; otherwise, end the current processing flow;
  • control data transfer unit reads a corresponding number of data from the cache into the memory in each preset time slice.
  • Step 602 Determine whether the number of data to be sent in a symbol is less than 24 chip, and if so, step 603 is performed, otherwise, step 610 is performed;
  • Step 603 Update the memory access length and address of the carrier 1 until the memory write access is completed, and update the memory access length and address of the carrier 2 until the memory write access is completed;
  • Step 604 Determine whether the current symbol is the last symbol in a subframe, and if so, proceed to step 605, otherwise, perform step 608;
  • Step 605 Send a symbol synchronization header and a subframe synchronization header, and continue to wait in a preset time slice;
  • the boundary is between two sub-frames and appears in the same 6.25us time slice.
  • Step 606 In the waiting process, it is determined whether the next subframe is an uplink subframe, and if so, step 607 is performed; otherwise, step 609 is performed;
  • Step 607 Waiting for the subframe synchronization header until the next subframe is an uplink subframe, returning to step 601;
  • Step 608 Send a symbol synchronization header, and continue to wait in the preset time slice;
  • the boundary is between two symbols of one subframe and appears in the same 6.25us time slice.
  • Step 609 During the waiting process, if the next subframe is a downlink subframe, update the memory access length and address of the carrier 1 until the memory write access is completed, and update the memory access length and address of the carrier 2 until the memory write access is completed. Afterwards, return to step 601;
  • Step 610 Update the memory access length and address of the carrier 1 until the memory write access is completed, and update the memory access length and address of the carrier 2 until the memory write access is completed, and update the number of sent data.
  • Step 611 Determine whether the current symbol length is equal to the number of updated transmission data, and if so, proceed to step 612, otherwise, return to step 601;
  • Step 612 Determine whether the current symbol is the last symbol in a subframe, and if so, proceed to step 613, otherwise, perform step 615;
  • Step 613 Send a symbol synchronization header and a subframe synchronization header, and continue to wait in a preset time slice;
  • Step 614 In the waiting process, determine whether the next subframe is a downlink subframe, and if yes, return to step 607, otherwise, return to step 601;
  • Step 615 Send a symbol synchronization header, continue to wait in the preset time slice until the preset time slice expires, and return to step 601.
  • the embodiment of the present invention further provides a baseband intermediate frequency interaction system.
  • the system includes a preset module 701, a first processing module 702, and a second processing module 703.
  • the preset module 701 is configured to integrate the baseband part and the intermediate frequency part on the same SoC, and preset parameter configuration information of the LTE system in the baseband part, where the parameter configuration information includes a sampling rate;
  • the first processing module 702 is configured to: according to the parameter configuration information, read data of a corresponding capacity from the memory through the AXI bus in each preset time slice, and store the data in the cache;
  • the second processing module 703 is configured to read data from the cache based on the sampling rate and transmit the read data to the intermediate frequency portion.
  • the parameter configuration information further includes: a TDD mode or an FDD mode, a number of cells, a number of carriers, an ECP or an NCP, and a symbol service type.
  • the first processing module 702 is further configured to divide each downlink subframe or symbol into at least two mutually independent preset time slices before the data of the corresponding capacity is read from the memory through the AXI bus.
  • the cache time of each preset time slice is the same.
  • the embodiment of the present invention further provides a baseband intermediate frequency interaction system.
  • the system includes a preset module 801, a third processing module 802, and a fourth processing module 803.
  • the preset module 801 is configured to integrate the baseband part and the intermediate frequency part on the same SoC, and preset parameter configuration information of the LTE system in the baseband part, where the parameter configuration information includes a sampling rate;
  • the third processing module 802 is configured to write data of the intermediate frequency portion into a cache based on the sampling rate
  • the fourth processing module 803 is configured to read data of a corresponding capacity from the cache in each preset time slice according to the parameter configuration information, and write the read data into the memory through the AXI bus. .
  • the parameter configuration information further includes: a TDD mode or an FDD mode, a number of cells, a number of carriers, an ECP or an NCP, and a symbol service type.
  • the fourth processing module 803 is further configured to divide each uplink subframe or symbol into at least two mutually independent preset time slices before reading the data of the corresponding capacity from the cache.
  • the cache time is the same for each preset time slice.
  • the preset module 701, the first processing module 702, the second processing module 703, the preset module 801, the third processing module 802, and the fourth processing module 803 may all be configured by a CPU and a micro terminal located on the mobile terminal.
  • a processor MPU, Micro Processor Unit
  • DSP digital signal processor
  • FPGA field-programmable gate array
  • the embodiment of the present invention integrates the baseband part and the intermediate frequency part on the same SoC, and preset parameter configuration information of the LTE system in the baseband part, where the parameter configuration information includes a sampling rate; according to the parameter configuration information, each Reading data of a corresponding capacity from the memory through the AXI bus in a preset time slice, and storing the data in the cache; reading data from the cache based on the sampling rate, The read data is sent to the intermediate frequency portion.
  • the baseband part and the intermediate frequency part are integrated on the same SoC, and the on-chip baseband intermediate frequency interaction based on the AXI bus can not only satisfy the arbitration of the uplink and downlink data requests of multiple cells, but also support various parameter configurations of the LTE system, and also enable the SoC. Get better performance with smaller area and lower power consumption.
  • the AXI bus is used for data exchange with low hardware cost, high bus transmission efficiency and good security. And support for out-of-order data transmission.
  • the above-mentioned baseband intermediate frequency interaction method is implemented in the form of a software function module and sold or used as a separate product, it may also be stored in a computer readable storage medium.
  • the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions.
  • a computer device (which may be a personal computer, server, or network device, etc.) is caused to perform all or part of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read only memory (ROM), a magnetic disk, or an optical disk.
  • program codes such as a USB flash drive, a mobile hard disk, a read only memory (ROM), a magnetic disk, or an optical disk.
  • an embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores a computer program for performing the above-mentioned baseband intermediate frequency interaction method according to an embodiment of the present invention.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.
  • the baseband part and the intermediate frequency part are integrated on the same system-on-chip SoC, and parameter configuration information of the long-term evolution LTE system is preset in the baseband part, where the parameter configuration information includes a sampling rate; Configuration information, reading the corresponding capacity data from the memory through the AXI bus in each preset time slice, and storing the data in the cache; reading data from the cache based on the sampling rate, and reading the data Sent to the intermediate frequency portion.
  • the parameter configuration information includes a sampling rate; Configuration information, reading the corresponding capacity data from the memory through the AXI bus in each preset time slice, and storing the data in the cache; reading data from the cache based on the sampling rate, and reading the data Sent to the intermediate frequency portion.
  • the AXI bus is used for data exchange with low hardware cost and bus transmission efficiency. High, secure, and support for out-of-order data transmission.

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Abstract

本发明公开了一种基带中频交互方法，包括：将基带部分和中频部分集成于同一片上系统(SoC)上，并在所述基带部分预先设置长期演进(LTE)制式的参数配置信息，所述参数配置信息包括采样率；所述方法还包括：根据所述参数配置信息，在每个预设时间片内通过AXI总线从内存中读取相应容量的数据，并存入缓存中；基于所述采样率从所述缓存中读取数据，并将读出的数据发送给所述中频部分。本发明还同时公开了一种基带中频交互系统、另一种基带中频交互方法、系统及存储介质。

Description

一种基带中频交互方法、系统及存储介质
相关申请的交叉引用
本申请基于申请号为201611090576.7、申请日为2016年12月01日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明涉及无线通讯领域中的数据传输技术，尤其涉及一种基带中频交互方法、系统及存储介质。
背景技术
在无线通讯系统中，射频信号主要用于空间中的传播，基带信号是没有经过频谱搬移的原始电信号，而中频信号是射频信号与基带信号之间过渡的频率信号。目前，基带与中频数据接口的实现方案是将基带部分如中央处理器单元(CPU，Central Processing Unit)和中频部分如现场可编程门阵列(FPGA，Field Programmable Gate Array)模块作为两个独立的芯片，且CPU与FPGA之间采用通用公共无线电接口(CPRI，Common Public Radio Interface)协议进行数据传输。然而，这种采用CPRI光口硬件电路实现独立的基带与中频之间的交互，不仅占用更多的电路面积，功能实现复杂，还不易集成在大规模的片上系统(SoC，System on Chip)中。
随着大规模SoC技术的不断发展和进步，人们对于在片上集成基带和中频部分的需求变得越来越多，因此，如何实现各种片上总线接口的交互是亟待解决的问题。例如，现有的一种基带控制芯片是在片内应用高级高性能总线(AHB，Advanced High Performance Bus)接口，以实现基带中频之间的数据交互，然而，由于AHB协议具有安全性差、效率低，且不支持 乱序数据传输等特点，因此，一直未得到用户的广泛使用。
另外，一些基于各种片上总线接口的交互电路，虽有的集成在SoC系统中，但交互电路的设计原理中多有内部先入先出队列(FIFO，First Input First Output)模块，导致功能实现复杂；或者，有的交互电路的设计原理虽过于简单，但多数是在片内应用外围总线(APB，Advanced Peripheral Bus)接口，由于APB协议主要用于低带宽的周边外设之间的连接，导致适用范围较小。综上可见，现有技术中并未发现一种应用于SoC系统中的长期演进(LTE，Long Term Evolution)制式通用的基带中频交互方法。
发明内容
有鉴于此，本发明实施例期望提供一种基带中频交互方法、系统及存储介质，能够节省电路面积，提高数据传输效率，且支持各种LTE制式的参数配置。
为达到上述目的，本发明实施例的技术方案是这样实现的：
本发明实施例提供一种基带中频交互方法，将基带部分和中频部分集成于同一SoC上，并在所述基带部分预先设置LTE制式的参数配置信息，所述参数配置信息包括采样率；所述方法还包括：
根据所述参数配置信息，在每个预设时间片内通过AXI总线从内存中读取相应容量的数据，并存入缓存中；
基于所述采样率从所述缓存中读取数据，并将读出的数据发送给所述中频部分。
上述方案中，所述参数配置信息还包括：时分双工(TDD，Time Division Duplexing)模式或频分双工(FDD，Frequency Division Duplexing)模式、小区个数、载波个数、扩展性能端口(ECP，Enhanced Capability Port)或网络控制协议(NCP，Network control protocol)、符号业务类型。
上述方案中，在所述通过AXI总线从内存中读取相应容量的数据之前， 所述方法还包括：将每个下行子帧或符号划分为至少两个相互独立的预设时间片，每个预设时间片的缓存时间相同。
本发明实施例提供一种基带中频交互方法，将基带部分和中频部分集成于同一SoC上，并在所述基带部分预先设置LTE制式的参数配置信息，所述参数配置信息包括采样率；所述方法还包括：
基于所述采样率，将所述中频部分的数据写入缓存中；
根据所述参数配置信息，在每个预设时间片内从所述缓存中读取相应容量的数据，并通过AXI总线将读出的数据写入内存中。
上述方案中，所述参数配置信息还包括：TDD模式或FDD模式、小区个数、载波个数、ECP或NCP、符号业务类型。
上述方案中，在所述从所述缓存中读取相应容量的数据之前，所述方法还包括：将每个上行子帧或符号划分为至少两个相互独立的预设时间片，每个预设时间片的缓存时间相同。
本发明实施例提供一种基带中频交互系统，所述系统包括：预设模块、第一处理模块、第二处理模块；其中，
所述预设模块，配置为将基带部分和中频部分集成于同一SoC上，并在所述基带部分预先设置LTE制式的参数配置信息，所述参数配置信息包括采样率；
所述第一处理模块，配置为根据所述参数配置信息，在每个预设时间片内通过AXI总线从内存中读取相应容量的数据，并存入缓存中；
所述第二处理模块，配置为基于所述采样率从所述缓存中读取数据，并将读出的数据发送给所述中频部分。
上述方案中，所述第一处理模块，还配置为在所述通过AXI总线从内存中读取相应容量的数据之前，将每个下行子帧或符号划分为至少两个相互独立的预设时间片，每个预设时间片的缓存时间相同。
本发明实施例还提供一种基带中频交互系统，所述系统包括：预设模块、第三处理模块、第四处理模块；其中，
所述预设模块，配置为将基带部分和中频部分集成于同一SoC上，并在所述基带部分预先设置LTE制式的参数配置信息，所述参数配置信息包括采样率；
所述第三处理模块，配置为基于所述采样率，将所述中频部分的数据写入缓存中；
所述第四处理模块，配置为根据所述参数配置信息，在每个预设时间片内从所述缓存中读取相应容量的数据，并通过AXI总线将读出的数据写入内存中。
上述方案中，所述第四处理模块，还配置为在所述从所述缓存中读取相应容量的数据之前，将每个上行子帧或符号划分为至少两个相互独立的预设时间片，每个预设时间片的缓存时间相同。
本发明实施例还提供一种计算机存储介质，计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行上述的基带中频交互方法。
本发明实施例提供的基带中频交互方法、系统及存储介质，将基带部分和中频部分集成于同一SoC上，并在所述基带部分预先设置LTE制式的参数配置信息，所述参数配置信息包括采样率；根据所述参数配置信息，在每个预设时间片内通过AXI(Advanced Extensible Interface)总线从内存中读取相应容量的数据，并存入缓存中；基于所述采样率从所述缓存中读取数据，并将读出的数据发送给所述中频部分。如此，将基带部分和中频部分集成于同一SoC上，基于AXI总线实现片上基带中频的交互，不仅可以满足多个小区上下行数据请求的仲裁，支持LTE制式的多种参数配置，还能够使SoC以更小的面积、更低的功耗，获得更加优异的性能；同时， 相对于标准的AHB或APB总线，采用AXI总线来实现数据交互的硬件成本低、总线传输效率高、安全性好，且支持乱序数据传输。
附图说明
图1为本发明实施例一提供的基带中频交互方法的流程示意图；
图2为本发明实施例二提供的基带中频交互方法的流程示意图；
图3为本发明实施例三提供的基带中频交互方法的具体实现流程示意图；
图4为本发明实施例三提供的下行传输控制的流程示意图；
图5为本发明实施例四提供的基带中频交互方法的具体实现流程示意图；
图6为本发明实施例四提供的上行传输控制的流程示意图；
图7为本发明实施例五提供的基带中频交互系统的组成结构示意图；
图8为本发明实施例六提供的基带中频交互系统的组成结构示意图。
具体实施方式
为了能够更加详尽地了解本发明实施例的特点与技术内容，下面结合附图对本发明实施例的实现进行详细阐述，所附附图仅供参考说明之用，并非用来限定本发明。
实施例一
本实施例是以下行交互为例来详细说明基带中频交互方法的实现过程。
如图1所示，本发明实施例中基带中频交互方法的实现流程，包括以下步骤：
步骤101：将基带部分和中频部分集成于同一SoC上，并在所述基带部分预先设置LTE制式的参数配置信息，所述参数配置信息包括采样率；
这里，所述参数配置信息还包括：TDD模式或FDD模式、小区个数、载波个数、ECP或NCP、符号业务类型；其中，所述符号业务类型包括：正常上行业务和正常下行业务。将所有的参数配置信息存储于基带部分中。
步骤102：根据所述参数配置信息，在每个预设时间片内通过AXI总线从内存中读取相应容量的数据，并存入缓存中；
通常，AXI是一种总线协议，该协议是ARM公司提出的AMBA(Advanced Microcontroller Bus Architecture)3.0协议中最重要的部分，是一种面向高性能、高带宽、低延迟的片内总线；AXI的地址/控制和数据相位是分离的，支持乱序的数据传输，且在突发传输中，只需要首地址，就可分离读写数据通道，并支持Outstanding传输访问和乱序访问，并更加容易进行时序收敛。因此，AXI是AMBA中的一种新的高性能协议。本发明实施例基于AXI总线实现片上基带中频的交互，能够满足超高性能和复杂的SoC设计的需求。
另外，现场总线是由多个设备共享一条总线来进行数据通信，然而，如果多个设备同时进行发送或接收数据时，会产生总线竞争，进而导致通信冲突或失败，因此，需要在总线上引入一个仲裁机制来决定什么时间由谁来占用总线的通信，例如：控制器局域网络(CAN，Controller Area Network)采用优先级方式，传输控制协议/因特网互联协议(TCP/IP，Transmission Control Protocol/Internet Protocol)采用载波监听多路访问(CSMA/CD，Carrier Sense Multiple Access with Collision Detection)机制，而RS-485则采用主机轮询的机制。综上，为避免总线竞争产生的冲突，本发明实施例采用基于带仲裁的AXI总线。
这里，在本步骤中通过AXI总线从内存中读取相应容量的数据之前，所述方法还包括：将每个下行子帧或符号划分为至少两个相互独立的预设时间片，每个预设时间片的缓存时间相同。
其中，所述预设时间片的大小是由每个下行子帧或符号的数据长度，以及存储空间的大小共同决定的，并非为一固定参数值。优选地，本发明实施例的预设时间片的大小为6.25us；6.25us是用户根据经验选择的经验值。这样，例如在采样率为30.72MHz的情况下，就可以确定出6.25us的时间片内所要传输的数据个数为6.25us*30.72M＝192个。
需要说明的是，这里的缓存可采用乒乓缓存机制，以节省缓冲区空间，从而实现数据流的无缝缓冲与处理。
步骤103：基于所述采样率从所述缓存中读取数据，并将读出的数据发送给所述中频部分。
通过上述步骤101-103，即可实现下行链路的数据流控制，保证数据不间断的正确发送。
实施例二
本实施例是以上行交互为例来详细说明基带中频交互方法的实现过程。
如图2所示，本发明实施例中基带中频交互方法的实现流程，包括以下步骤：
步骤201：将基带部分和中频部分集成于同一SoC上，并在所述基带部分预先设置LTE制式的参数配置信息，所述参数配置信息包括采样率；
这里，所述参数配置信息还包括：TDD模式或FDD模式、小区个数、载波个数、ECP或NCP、符号业务类型；其中，所述符号业务类型包括：正常上行业务和正常下行业务。将所有的参数配置信息存储于基带部分中。
步骤202：基于所述采样率，将所述中频部分的数据写入缓存中；
步骤203：根据所述参数配置信息，在每个预设时间片内从所述缓存中读取相应容量的数据，并通过AXI总线将读出的数据写入内存中。
通常，AXI是一种总线协议，该协议是ARM公司提出的AMBA3.0协 议中最重要的部分，是一种面向高性能、高带宽、低延迟的片内总线；AXI的地址/控制和数据相位是分离的，支持乱序的数据传输，且在突发传输中，只需要首地址，就可分离读写数据通道，并支持Outstanding传输访问和乱序访问，并更加容易进行时序收敛。因此，AXI是AMBA中的一种新的高性能协议。本发明实施例基于AXI总线实现片上基带中频的交互，能够满足超高性能和复杂的SoC设计的需求。
另外，现场总线是由多个设备共享一条总线来进行数据通信，然而，如果多个设备同时进行发送或接收数据时，会产生总线竞争，进而导致通信冲突或失败，因此，需要在总线上引入一个仲裁机制来决定什么时间由谁来占用总线的通信，例如：CAN采用优先级方式，TCP/IP采用CSMA/CD机制，而RS-485则采用主机轮询的机制。综上，为避免总线竞争产生的冲突，本发明实施例采用基于带仲裁的AXI总线。
这里，在本步骤中从所述缓存中读取相应容量的数据之前，所述方法还包括：将每个上行子帧或符号划分为至少两个相互独立的预设时间片，每个预设时间片的缓存时间相同。
其中，所述预设时间片的大小是由每个上行子帧或符号的数据长度，以及存储空间的大小共同决定的，并非为一固定参数值。优选地，本发明实施例的预设时间片的大小为6.25us；6.25us是用户根据经验选择的经验值。这样，例如在采样率为30.72MHz的情况下，就可以确定出6.25us的时间片内所要传输的数据个数为6.25us*30.72M＝192个。
需要说明的是，这里的缓存可采用乒乓缓存机制，以节省缓冲区空间，从而实现数据流的无缝缓冲与处理。
通过上述步骤201-203，即可实现上行链路的数据流控制，保证数据不间断的正确接收。
实施例三
下面对本发明实施例基带中频下行交互方法的具体实现过程做进一步地详细说明。
图3给出了本发明实施例基带中频下行交互方法的具体实现流程示意图，如图3所示，包括以下步骤：
步骤301：由基带单元301将一个下行子帧或符号中待发送的数据写入内存单元304中；
这里，预先将每个下行子帧或符号划分为至少两个相互独立的预设时间片，每个预设时间片的缓存时间相同。其中，所述预设时间片的大小是由每个下行子帧或符号的数据长度，以及存储空间的大小共同决定的，并非为一固定参数值。优选地，本发明实施例的预设时间片的大小为6.25us；6.25us是用户根据经验选择的经验值。
步骤302：由基带单元301将LTE制式的配置参数写入参数配置单元302中，参数配置单元302根据所配置的参数，通过查表1得到每个下行子帧或符号的符号长度，并通过计算得到6.25us的预设时间片内所要传输的数据个数；其中，表1为LTE制式的符号长度；
Figure PCTCN2017085572-appb-000001
表1
这里，所述配置参数包括：TDD/FDD、小区个数、载波个数、采样率、ECP/NCP、符号业务类型；其中，所述符号业务类型包括：正常上行业务 和正常下行业务，将所有的参数配置信息存储于基带单元301中。
步骤303：传输控制单元303根据当前的符号长度、数据传输个数，以及帧头开始信号，将数据传输命令发送给数据传输单元306；
步骤304：数据传输单元306根据AXI总线驱动单元305要求的访问时序，通过AXI总线向内存单元304请求数据；
这里，为避免总线竞争产生的冲突，采用基于带仲裁的AXI总线。
步骤305：数据传输单元306收到AXI总线驱动单元305的响应数据后，将数据写入缓存单元307中；
这里，在每个预设时间片即6.25us内控制数据传输单元306从内存单元304中读取相应个数的数据，并存入缓存中。其中，以缓存单元307任一侧的随机存储器(RAM，Random Access Memory)为空开始，在正常情况下，按照固定采样率从缓存单元307中读取数据，读完一侧RAM所用的时间恰好为6.25us。另外，由于每个子帧中的各个符号的起始地址不同，很可能会造成子帧或符号的分界出现在同一个6.25us的时间片内，此时，需要将不同地址的数据请求分为两个命令，通过两次的命令来读取完成整个时间片内的数据。
这里，缓存单元307可采用乒乓缓存机制，以节省缓冲区空间，从而实现数据流的无缝缓冲与处理。
步骤306：缓存单元307按照基带单元301配置的采样率输出数据，供下级的中频单元308使用。
需要特别指出的是，事先将基带单元301和中频单元308集成于同一SoC上。
下面对下行传输控制单元303的实现过程做进一步地详细说明。
图4为本发明实施例下行传输控制的流程示意图，如图4所示，包括以下步骤：
步骤401：判断缓存单元任一侧RAM是否为空，若是，则执行步骤402；否则，结束当前处理流程；
这里，从缓存单元的一侧RAM为空开始，在每个预设时间片内控制数据传输单元从内存中读取相应个数的数据存入缓存中。
步骤402：判断一个符号中剩余的待发送数据的个数是否小于24chip，若是，则执行步骤403，否则，执行步骤410；
步骤403：更新载波1的内存访问长度和地址，直至内存访问完成，更新载波2的内存访问长度和地址，直至内存访问完成；
步骤404：判断当前符号是否为一个子帧中的最后一个符号，若是，则执行步骤405，否则，执行步骤408；
步骤405：发送符号同步头和子帧同步头，继续在预设时间片内等待；
这里，分界处于两个子帧之间，且出现在同一个6.25us的时间片内。
步骤406：在等待过程中，判断下一个子帧是否为上行子帧，若是，则执行步骤407，否则，执行步骤409；
步骤407：强制RAM为满，在预设时间片内等待子帧同步头，直到下一个子帧为下行子帧时，清空RAM的状态，并返回步骤401；
步骤408：发送符号同步头，继续在预设时间片内等待；
这里，分界处于一个子帧的两个符号之间，且出现在同一个6.25us的时间片内。
步骤409：在等待过程中，若下一个子帧为下行子帧，则更新载波1的内存访问长度和地址，直至内存访问完成，更新载波2的内存访问长度和地址，直至内存访问完成后，返回步骤401；
步骤410：更新载波1的内存访问长度和地址，直至内存访问完成，更新载波2的内存访问长度和地址，直至内存访问完成，更新发送数据的个数；
步骤411：判断当前符号长度是否等于更新的发送数据的个数，若是，则执行步骤412，否则，返回步骤401；
步骤412：判断当前符号是否为一个子帧中的最后一个符号，若是，则执行步骤413，否则，执行步骤415；
步骤413：发送符号同步头和子帧同步头，继续在预设时间片内等待；
步骤414：在等待过程中，判断下一个子帧是否为上行子帧，若是，则返回步骤407，否则，返回步骤401；
步骤415：发送符号同步头，继续在预设时间片内等待，直至预设时间片超时，返回步骤401。
实施例四
下面对本发明实施例基带中频上行交互方法的具体实现过程做进一步地详细说明。
图5给出了本发明实施例基带中频上行交互方法的具体实现流程示意图，如图5所示，包括以下步骤：
步骤501：由基带单元501将LTE制式的配置参数写入参数配置单元502中，参数配置单元502根据所配置的参数，通过查表1得到每个上行子帧或符号的符号长度，并通过计算得到6.25us的预设时间片内所要传输的数据个数；
这里，所述配置参数包括：TDD/FDD、小区个数、载波个数、采样率、ECP/NCP、符号业务类型；其中，所述符号业务类型包括：正常上行业务和正常下行业务，将所有的参数配置信息存储于基带单元501中。
这里，预先将每个上行子帧或符号划分为至少两个相互独立的预设时间片，每个预设时间片的缓存时间相同。其中，所述预设时间片的大小是由每个上行子帧或符号的数据长度，以及存储空间的大小共同决定的，并非为一固定参数值。优选地，本发明实施例的预设时间片的大小为6.25us； 6.25us是用户根据经验选择的经验值。
步骤502：按照基带单元501配置的采样率，将中频单元508输入的数据写入缓存单元507中；
这里，缓存单元507可采用乒乓缓存机制，以节省缓冲区空间，从而实现数据流的无缝缓冲与处理。
步骤503：传输控制单元503根据当前的符号长度、数据传输个数，以及帧头开始信号，将数据传输命令发送给数据传输单元506；
步骤504：数据传输单元506从缓存单元507中读取数据，并根据AXI总线驱动单元505要求的访问时序，通过AXI总线向内存单元504写入数据。
这里，在每个预设时间片即6.25us内控制数据传输单元506从缓存单元507中读取相应个数的数据，并存入内存中。其中，以缓存单元507任一侧的RAM为满开始，在正常情况下，缓存单元507按照固定采样率写入数据，其写满一侧RAM所用的时间恰好为6.25us。另外，由于每个子帧中的各个符号的起始地址不同，很可能会造成子帧或符号的分界出现在同一个6.25us的时间片内，此时，需要将不同地址的数据请求分为两个命令，通过两次的命令来读取完成整个时间片内的数据。
这里，为避免总线竞争产生的冲突，采用基于带仲裁的AXI总线。
这里，当将一个子帧或符号长度的数据写成功后，传输控制单元503发送中断给基带单元501。
需要特别指出的是，事先将基带单元501和中频单元508集成于同一SoC上。
下面对上行传输控制单元503的实现过程做进一步地详细说明。
图6为本发明实施例上行传输控制的流程示意图，如图6所示，包括以下步骤：
步骤601：判断缓存单元任一侧RAM是否为满，若是，则执行步骤602；否则，结束当前处理流程；
这里，从缓存单元的一侧RAM为满开始，在每个预设时间片内控制数据传输单元从缓存中读取相应个数的数据写入内存中。
步骤602：判断一个符号中剩余的待发送数据的个数是否小于24chip，若是，则执行步骤603，否则，执行步骤610；
步骤603：更新载波1的内存访问长度和地址，直至内存写访问完成，更新载波2的内存访问长度和地址，直至内存写访问完成；
步骤604：判断当前符号是否为一个子帧中的最后一个符号，若是，则执行步骤605，否则，执行步骤608；
步骤605：发送符号同步头和子帧同步头，继续在预设时间片内等待；
这里，分界处于两个子帧之间，且出现在同一个6.25us的时间片内。
步骤606：在等待过程中，判断下一个子帧是否为上行子帧，若是，则执行步骤607，否则，执行步骤609；
步骤607：等待子帧同步头，直至下一个子帧为上行子帧时，返回步骤601；
步骤608：发送符号同步头，继续在预设时间片内等待；
这里，分界处于一个子帧的两个符号之间，且出现在同一个6.25us的时间片内。
步骤609：在等待过程中，若下一个子帧为下行子帧，则更新载波1的内存访问长度和地址，直至内存写访问完成，更新载波2的内存访问长度和地址，直至内存写访问完成后，返回步骤601；
步骤610：更新载波1的内存访问长度和地址，直至内存写访问完成，更新载波2的内存访问长度和地址，直至内存写访问完成，更新发送数据的个数；
步骤611：判断当前符号长度是否等于更新的发送数据的个数，若是，则执行步骤612，否则，返回步骤601；
步骤612：判断当前符号是否为一个子帧中的最后一个符号，若是，则执行步骤613，否则，执行步骤615；
步骤613：发送符号同步头和子帧同步头，继续在预设时间片内等待；
步骤614：在等待过程中，判断下一个子帧是否为下行子帧，若是，则返回步骤607，否则，返回步骤601；
步骤615：发送符号同步头，继续在预设时间片内等待，直至预设时间片超时，返回步骤601。
实施例五
为实现上述方法，本发明实施例还提供了一种基带中频交互系统，如图7所示，该系统包括预设模块701、第一处理模块702、第二处理模块703；其中，
所述预设模块701，配置为将基带部分和中频部分集成于同一SoC上，并在所述基带部分预先设置LTE制式的参数配置信息，所述参数配置信息包括采样率；
所述第一处理模块702，配置为根据所述参数配置信息，在每个预设时间片内通过AXI总线从内存中读取相应容量的数据，并存入缓存中；
所述第二处理模块703，配置为基于所述采样率从所述缓存中读取数据，并将读出的数据发送给所述中频部分。
这里，所述参数配置信息还包括：TDD模式或FDD模式、小区个数、载波个数、ECP或NCP、符号业务类型。
这里，所述第一处理模块702，还配置为在所述通过AXI总线从内存中读取相应容量的数据之前，将每个下行子帧或符号划分为至少两个相互独立的预设时间片，每个预设时间片的缓存时间相同。
实施例六
为实现上述方法，本发明实施例还提供了一种基带中频交互系统，如图8所示，该系统包括预设模块801、第三处理模块802、第四处理模块803；其中，
所述预设模块801，配置为将基带部分和中频部分集成于同一SoC上，并在所述基带部分预先设置LTE制式的参数配置信息，所述参数配置信息包括采样率；
所述第三处理模块802，配置为基于所述采样率，将所述中频部分的数据写入缓存中；
所述第四处理模块803，配置为根据所述参数配置信息，在每个预设时间片内从所述缓存中读取相应容量的数据，并通过AXI总线将读出的数据写入内存中。
这里，所述参数配置信息还包括：TDD模式或FDD模式、小区个数、载波个数、ECP或NCP、符号业务类型。
这里，所述第四处理模块803，还配置为在所述从所述缓存中读取相应容量的数据之前，将每个上行子帧或符号划分为至少两个相互独立的预设时间片，每个预设时间片的缓存时间相同。
在实际应用中，所述预设模块701、第一处理模块702、第二处理模块703、预设模块801、第三处理模块802、第四处理模块803均可由位于移动终端上的CPU、微处理器(MPU，Micro Processor Unit)、数字信号处理器(DSP，Digital Signal Processor)、或FPGA等实现。
本发明实施例将基带部分和中频部分集成于同一SoC上，并在所述基带部分预先设置LTE制式的参数配置信息，所述参数配置信息包括采样率；根据所述参数配置信息，在每个预设时间片内通过AXI总线从内存中读取相应容量的数据，并存入缓存中；基于所述采样率从所述缓存中读取数据， 并将读出的数据发送给所述中频部分。如此，将基带部分和中频部分集成于同一SoC上，基于AXI总线实现片上基带中频的交互，不仅可以满足多个小区上下行数据请求的仲裁，支持LTE制式的多种参数配置，还能够使SoC以更小的面积、更低的功耗，获得更加优异的性能；同时，相对于标准的AHB或APB总线，采用AXI总线来实现数据交互的硬件成本低、总线传输效率高、安全性好，且支持乱序数据传输。
本发明实施例中，如果以软件功能模块的形式实现上述基带中频交互方法，并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明实施例的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机、服务器、或者网络设备等)执行本发明各个实施例所述方法的全部或部分。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read Only Memory，ROM)、磁碟或者光盘等各种可以存储程序代码的介质。这样，本发明实施例不限制于任何特定的硬件和软件结合。
相应地，本发明实施例还提供一种计算机存储介质，该计算机存储介质中存储有计算机程序，该计算机程序用于执行本发明实施例的上述基带中频交互方法。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程 图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。
工业实用性
本发明实施例中，将基带部分和中频部分集成于同一片上系统SoC上，并在所述基带部分预先设置长期演进LTE制式的参数配置信息，所述参数配置信息包括采样率；根据所述参数配置信息，在每个预设时间片内通过AXI总线从内存中读取相应容量的数据，并存入缓存中；基于所述采样率从所述缓存中读取数据，并将读出的数据发送给所述中频部分。如此，不仅可以满足多个小区上下行数据请求的仲裁，支持LTE制式的多种参数配 置，还能够使SoC以更小的面积、更低的功耗，获得更加优异的性能；同时，相对于标准的AHB或APB总线，采用AXI总线来实现数据交互的硬件成本低、总线传输效率高、安全性好，且支持乱序数据传输。

Claims (14)

  1. 一种基带中频交互方法，将基带部分和中频部分集成于同一片上系统SoC上，并在所述基带部分预先设置长期演进LTE制式的参数配置信息，所述参数配置信息包括采样率；所述方法还包括：
    根据所述参数配置信息，在每个预设时间片内通过AXI总线从内存中读取相应容量的数据，并存入缓存中；
    基于所述采样率从所述缓存中读取数据，并将读出的数据发送给所述中频部分。
  2. 根据权利要求1所述的方法，其中，所述参数配置信息还包括：时分双工TDD模式或频分双工FDD模式、小区个数、载波个数、扩展性能端口ECP或网络控制协议NCP、符号业务类型。
  3. 根据权利要求1所述的方法，其中，在所述通过AXI总线从内存中读取相应容量的数据之前，所述方法还包括：将每个下行子帧或符号划分为至少两个相互独立的预设时间片，每个预设时间片的缓存时间相同。
  4. 一种基带中频交互方法，将基带部分和中频部分集成于同一SoC上，并在所述基带部分预先设置LTE制式的参数配置信息，所述参数配置信息包括采样率；所述方法还包括：
    基于所述采样率，将所述中频部分的数据写入缓存中；
    根据所述参数配置信息，在每个预设时间片内从所述缓存中读取相应容量的数据，并通过AXI总线将读出的数据写入内存中。
  5. 根据权利要求4所述的方法，其中，所述参数配置信息还包括：TDD模式或FDD模式、小区个数、载波个数、ECP或NCP、符号业务类型。
  6. 根据权利要求4所述的方法，其中，在所述从所述缓存中读取相应容量的数据之前，所述方法还包括：将每个上行子帧或符号划分为至少两个相互独立的预设时间片，每个预设时间片的缓存时间相同。
  7. 一种基带中频交互系统，所述系统包括：预设模块、第一处理模块、第二处理模块；其中，
    所述预设模块，配置为将基带部分和中频部分集成于同一SoC上，并在所述基带部分预先设置LTE制式的参数配置信息，所述参数配置信息包括采样率；
    所述第一处理模块，配置为根据所述参数配置信息，在每个预设时间片内通过AXI总线从内存中读取相应容量的数据，并存入缓存中；
    所述第二处理模块，配置为基于所述采样率从所述缓存中读取数据，并将读出的数据发送给所述中频部分。
  8. 根据权利要求7所述的系统，其中，所述参数配置信息还包括：TDD模式或FDD模式、小区个数、载波个数、ECP或NCP、符号业务类型。
  9. 根据权利要求7所述的系统，其中，所述第一处理模块，还配置为在所述通过AXI总线从内存中读取相应容量的数据之前，将每个下行子帧或符号划分为至少两个相互独立的预设时间片，每个预设时间片的缓存时间相同。
  10. 一种基带中频交互系统，所述系统包括：预设模块、第三处理模块、第四处理模块；其中，
    所述预设模块，配置为将基带部分和中频部分集成于同一SoC上，并在所述基带部分预先设置LTE制式的参数配置信息，所述参数配置信息包括采样率；
    所述第三处理模块，配置为基于所述采样率，将所述中频部分的数据写入缓存中；
    所述第四处理模块，配置为根据所述参数配置信息，在每个预设时间片内从所述缓存中读取相应容量的数据，并通过AXI总线将读出的数据写入内存中。
  11. 根据权利要求10所述的系统，其中，所述参数配置信息还包括：TDD模式或FDD模式、小区个数、载波个数、ECP或NCP、符号业务类型。
  12. 根据权利要求10所述的系统，其中，所述第四处理模块，还配置为在所述从所述缓存中读取相应容量的数据之前，将每个上行子帧或符号划分为至少两个相互独立的预设时间片，每个预设时间片的缓存时间相同。
  13. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行权利要求1至3任一项所述的基带中频交互方法。
  14. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行权利要求4至6任一项所述的基带中频交互方法。
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