WO2018090564A1 - 一种zc序列的生成方法、装置及存储介质 - Google Patents

一种zc序列的生成方法、装置及存储介质 Download PDF

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WO2018090564A1
WO2018090564A1 PCT/CN2017/081972 CN2017081972W WO2018090564A1 WO 2018090564 A1 WO2018090564 A1 WO 2018090564A1 CN 2017081972 W CN2017081972 W CN 2017081972W WO 2018090564 A1 WO2018090564 A1 WO 2018090564A1
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vector
address
sequence
generated
current
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French (fr)
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王辉
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Sanechips Technology Co Ltd
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Sanechips Technology Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J13/00—Code division multiplex systems
    • H04J13/0007—Code type
    • H04J13/0055—ZCZ [zero correlation zone]
    • H04J13/0059—CAZAC [constant-amplitude and zero auto-correlation]
    • H04J13/0062—Zadoff-Chu
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J13/00—Code division multiplex systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J13/00—Code division multiplex systems
    • H04J13/10—Code generation
    • H04J13/14—Generation of codes with a zero correlation zone

Definitions

  • the present invention relates to the field of digital signal processing, and in particular, to a method, an apparatus, and a storage medium for generating a ZC sequence.
  • Zadoff-Chu (ZC) sequences are widely used in Long Term Evolution (LTE) systems due to their good autocorrelation and cross-correlation, for example, primary synchronization signals in the LTE downlink, uplink The demodulated signal and the sounding signal, and the preamble of the random access channel.
  • LTE Long Term Evolution
  • the signal processing device often uses a look-up table method to store the ZC sequence in the signal processing device, and then reads it in use.
  • the ZC sequence there are multiple ZC sequences in the LTE system, and if all are stored, the consumption is very large.
  • the storage space needs to calculate the ZC sequence in real time, but the existing method of calculating the ZC sequence in real time is to calculate the ZC sequence in real time according to the order. Such a method has a long calculation time and consumes a large storage space.
  • the embodiment of the present invention is to provide a method, a device, and a storage medium for generating a ZC sequence, so as to solve the technical problem that the calculation time is long when generating a ZC sequence in the prior art.
  • the time for generating the ZC sequence is shortened, and the generation efficiency of the ZC sequence is improved.
  • an embodiment of the present invention provides a method for generating a ZC sequence, including: determining an initial address vector and an initial address increment vector of a ZC sequence to be generated; according to an initial address vector, an initial address increment vector, and a preset
  • the address increment step is performed by using a preset vector iterative algorithm to generate a current vector, a next address vector, and a next address increment vector of the ZC sequence to be generated; when the current iteration number is equal to the preset number of iterations I, Obtaining the to-be-generated ZC sequence according to the generated elements of the respective vectors of the ZC sequence to be generated; wherein the preset number of iterations I is:
  • N is the length of the ZC sequence to be generated
  • P is a preset value
  • P is greater than 1.
  • the vector and the next address increment vector include: determining, according to the initial address vector, the initial address increment vector, and the preset address increment step, a current vector of the ZC sequence to be generated, and a current An address vector and a current address increment vector; when the current number of iterations is less than the preset number of iterations, stepping according to the current address vector, the current address increment vector, and the preset address increment Determining a next address vector and a next address increment vector; updating the current number of iterations, and returning to the according to the current address vector, the current address increment vector, and the preset address increment Stepping to determine the current vector of the ZC sequence to be generated.
  • the determining, according to the initial address vector, the initial address increment vector, and the preset address increment step determining a current vector of the to-be-generated ZC sequence, including: the current iteration The number of times is divided by the preset iteration depth to obtain a remainder; when the remainder is equal to 0, the table looks for the current vector, the current increment vector, and the current step of the ZC sequence to be generated; When the remainder is not equal to 0, the current vector and the current increment vector of the to-be-generated ZC sequence are generated according to the previous vector of the ZC sequence to be generated, the previous increment vector, and the previous step.
  • the determining, according to the current address vector, the current address increment vector, and the preset address increment step, determining a next address vector and a next address increment vector including: Describe a current address vector, the current address increment vector, and a length of the to-be-generated ZC sequence, and use a remainder function to determine the next address vector; according to the current address increment vector, the preset The address increment step and the length of the ZC sequence to be generated are determined by the remainder function to determine the next address increment vector.
  • the initial address vector and the initial address increment vector of the ZC sequence to be generated are determined, including: a root index of the ZC sequence to be generated, a length N of the ZC sequence to be generated, and the preset value.
  • P and a preset P number, using a remainder function, respectively determining an address corresponding to each preset number and an address increment corresponding to each preset number; corresponding to each preset number
  • the address forms the initial address vector; the initial address increment vector is formed by an address increment corresponding to the preset respective number.
  • the ZC sequence to be generated is obtained according to the generated elements of the respective vectors of the ZC sequence to be generated, including: according to the symmetry of the ZC sequence to be generated, and according to the generated An element of each vector of the ZC sequence is generated to generate the ZC sequence to be generated.
  • An embodiment of the present invention provides a ZC sequence generating apparatus, including: a determining module configured to determine an initial address vector and an initial address increment vector of a ZC sequence to be generated; and an iterative module configured to increase according to an initial address vector and an initial address.
  • the quantity vector and the preset address increment step are performed, and the current vector, the next address vector and the next address increment vector of the ZC sequence to be generated are generated by using a preset vector iterative algorithm; and the generating module is configured to be current
  • the number of iterations is equal to the preset number of iterations I
  • the ZC sequence to be generated is obtained according to the generated elements of the vector of the ZC sequence to be generated; wherein the preset number of iterations I is:
  • N is the length of the ZC sequence to be generated
  • P is a preset value
  • P is greater than 1.
  • the iterative module includes: a first determining submodule configured to determine, according to the initial address vector, the initial address increment vector, and the preset address increment step, to determine the to-be-generated a current vector, a current address vector, and a current address increment vector of the ZC sequence; the second determining submodule is configured to: when the current number of iterations is less than the preset number of iterations, according to the current address vector, the current The address increment vector and the preset address increment step are performed to determine a next address vector and a next address increment vector; the triggering submodule is configured to update the current iteration number and trigger the first determination And the sub-module, so that the first determining sub-module determines the current vector of the ZC sequence to be generated according to the current address vector, the current address increment vector, and the preset address increment step.
  • a first determining submodule configured to determine, according to the initial address vector, the initial address increment vector, and the preset address increment step, to determine the to-be-
  • the first determining sub-module is configured to divide the current iteration number by a preset iteration depth to obtain a remainder; when the remainder is equal to 0, look up the table to obtain a current vector of the ZC sequence to be generated. a current incremental vector and a current step; when the remainder is not equal to 0, generating the ZC sequence to be generated according to the previous vector, the previous incremental vector, and the previous step of the ZC sequence to be generated. Current vector and current incremental vector.
  • the second determining submodule is configured to: according to the current address vector, the current address increment vector, and the to-be-generated, when the current number of iterations is greater than or equal to the preset number of iterations
  • the length of the ZC sequence is determined by using a remainder function to determine the next address vector; according to the current address increment vector, the preset address increment step, and the length of the to-be-generated ZC sequence, The remainder function determines the next address increment vector.
  • the determining module is configured to adopt a residual function according to a root index of a ZC sequence to be generated, a length N of the ZC sequence to be generated, the preset value P, and a preset P number. Determining, respectively, an address corresponding to each preset number and an address increment corresponding to each preset number; forming the initial address vector by using an address corresponding to each preset number The initial address increment vector is formed by an address increment corresponding to each of the preset respective numbers.
  • the generating module is configured to generate the ZC sequence to be generated according to the symmetry of the ZC sequence to be generated, and according to the generated elements of the vector of the ZC sequence to be generated.
  • the embodiment of the present invention further provides a method for generating a ZC sequence, including: determining an initial address vector and an initial address increment vector of a ZC sequence to be generated; the ZC sequence includes one first vector and one second vector, a positive integer; determining the first first vectors according to the initial address vector, the initial address increment vector, and a preset address increment step; determining the first symmetry policy based on the first vector a second vector to generate the ZC sequence.
  • the determining the first first vector according to the initial address vector, the initial address increment vector, and a preset address increment step comprises:
  • the first mapping table is configured to represent a mapping relationship between an address vector and a first vector, an address increment vector and an increment vector, an address increment step, and a vector increment step; according to the first first vector, The first incremental vector and the vector incremental step determine a second first vector, and so on, until the (I-1)th first vector is determined; according to the initial address vector, The initial address increment vector and the preset address increment step calculate the second address vector and the second address increment vector up to the first address vector and the first address increment vector; The first address vector is searched for the first address table by the first address vector, and the first first vector is obtained.
  • the determining the second first vector and the second incremental vector according to the first first vector, the first incremental vector, and the vector increment step comprises:
  • the determining, according to the symmetry policy, the second vector based on the first vector includes:
  • the first first vector is a first second vector; determining that the first one first vector is a second second vector, until determining that the first first vector is The first second vector.
  • An embodiment of the present invention further provides a device for generating a ZC sequence, including an initial module, configured to determine an initial address vector and an initial address increment vector of a ZC sequence to be generated, where the ZC sequence includes one first vector and one first Two vectors, I is a positive integer;
  • a first determining module configured to determine the first first vector according to the initial address vector, the initial address increment vector, and a preset address increment step
  • a second determining module configured to determine the second vector according to a symmetry policy based on the first vector to generate the ZC sequence.
  • the first determining module is configured to search the first mapping table according to the initial address vector, the initial address increment vector, and the preset address increment to obtain the first first vector, a first incremental vector and a vector incremental step;
  • the first mapping table is used to represent the address vector and the first vector, the address increment vector and the increment vector, the address increment step, and the vector increment step Mapping relations;
  • the first determining module is configured to search the first mapping table according to the initial address vector, the initial address increment vector, and the preset address increment to obtain the first first vector, a first incremental vector and a vector incremental step;
  • the first mapping table is used to represent the address vector and the first vector, the address increment vector and the increment vector, the address increment step, and the vector increment step Mapping relations;
  • the first determining module is configured to calculate a product of the first first vector and the first incremental vector to obtain the second first vector
  • the second determining module is configured to determine, according to the symmetry policy, that the first first vector is the first second vector
  • the embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores computer executable instructions for executing the foregoing ZC sequence generation method.
  • the method, device and storage medium for generating a ZC sequence provided by an embodiment of the present invention firstly determine an initial address vector and an initial address increment vector of a ZC sequence to be generated, and then, according to a current address vector, a current address increment vector and The preset address increment step is performed by using a preset vector iterative algorithm to generate a current vector, a next address vector, and a next address increment vector of the ZC sequence to be generated, so that a plurality of values may be included in the vector.
  • N is the length of the ZC sequence to be generated
  • P is a preset value
  • P is greater than 1. It can be seen that, in the embodiment of the present invention, the ZC sequence element to be generated can be generated in parallel by using a preset vector iterative algorithm. The time to generate the ZC sequence increases the efficiency of ZC sequence generation.
  • FIG. 1 is a schematic flowchart of a method for generating a ZC sequence according to an embodiment of the present invention
  • FIG. 2 is an optional schematic flowchart of a method for generating a ZC sequence according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a device for generating a ZC sequence according to an embodiment of the present invention.
  • the embodiment of the invention provides a method for generating a ZC sequence, which can be applied to a vector digital processor (DSP) commonly used in base station side baseband signal processing in an LTE system;
  • DSP vector digital processor
  • FIG. 1 is a schematic flowchart of a method for generating a ZC sequence according to an embodiment of the present invention. As shown in FIG. 1, the method includes:
  • S101 Determine an initial address vector and an initial address increment vector of the ZC sequence to be generated.
  • N is the length of the ZC sequence
  • u is the root index of the ZC sequence
  • n is the element index of the ZC sequence.
  • the ZC sequence generated by the serial processing method one by one takes a long time.
  • a parallel calculation method can be used to generate the ZC sequence, specifically First, it is necessary to determine an initial address vector and an initial address increment vector of the ZC sequence to be generated;
  • the initial address vector and the initial address increment vector of the ZC sequence to be generated may be used to determine a vector of a corresponding ZC sequence to be generated, and each vector of the ZC sequence to be generated includes a preset value P sequence elements;
  • the initial address vector and the initial address increment vector of the ZC sequence to be generated may be a preset vector, or may be calculated according to a preset algorithm; here, the embodiment of the present invention is not specifically limited.
  • S101 in order to calculate the initial address vector and the initial address increment vector of the ZC sequence to be generated according to the preset algorithm, S101 may include:
  • the remainder function is used to determine the address and preset corresponding to each preset number.
  • the root index of the ZC sequence to be generated is represented by u
  • the length of the ZC sequence to be generated is represented by N
  • the preset value P is the parallel capability of the vector DSP, that is, one for each vector calculation.
  • the P numbers p can be 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15; then, according to N, u, P, p Parallel computing is performed by using the remainder function to obtain the address corresponding to each p and the address increment corresponding to each p.
  • the initial address vector a 0 of the ZC sequence to be generated can be formed by using the address corresponding to each p.
  • the address increment corresponding to p may form an initial address increment vector s 0 of the ZC sequence to be generated;
  • the initial address vector and the initial address increment vector of the ZC sequence to be generated are determined.
  • S102 Generate a current vector, a next address vector, and a next ZC sequence to be generated according to the initial address vector, the initial address increment vector, and the preset address increment step by using a preset vector iterative algorithm.
  • Address increment vector
  • the preset vector iterative algorithm can be used not only to generate The current vector, the current address vector, and the current address increment vector of the ZC sequence to be generated, and the next address vector and the next address increment vector of the ZC sequence to be generated may be generated, and so on, and the preset number of iterations is performed ( Iteration operation of I times);
  • S102 may include:
  • the quantity vector and the preset address increment step determine the next address vector and the next address increment vector; update the current iteration number, and return to increase according to the current address vector, the current address increment vector, and the preset address.
  • the current vector of the ZC sequence to be generated may be by way of table lookup, and/or The manner in which the algorithm is calculated is not limited in the embodiment of the present invention.
  • N is the length of the ZC sequence to be generated
  • P is a preset value, and P is greater than 1; that is, when only I is within the above range, the iterative calculation can be ended to generate the ZC sequence to be generated.
  • the current vector of the ZC sequence to be generated is determined according to the current address vector, the current address increment vector, and the preset address increment step. Then, in the specific implementation process, according to the current address.
  • the vector, the current address increment vector, and the preset address increment step are determined, and the current vector of the ZC sequence to be generated is determined, including: the current iteration number is divided by the preset iteration depth to obtain a remainder; when the remainder is equal to 0, the check is performed.
  • the table obtains the current vector, the current incremental vector, and the current step of the ZC sequence to be generated; when the remainder is not equal to 0, generates a to-be-generated according to the previous vector, the previous incremental vector, and the previous step of the ZC sequence to be generated.
  • the current vector and current incremental vector of the ZC sequence are the current vector and current incremental vector of the ZC sequence.
  • the preset iteration depth is proportional to the cumulative error, so the preset iteration depth can be flexibly selected according to the required precision; the larger the preset iteration depth, the larger the cumulative error, and the preset The iteration depth is a positive integer.
  • the remainder obtained by dividing the current iteration number by the preset iteration depth may be 0, 1, 2, 3, and only when the remainder is equal to 0, the table is checked.
  • Obtaining the current vector, the current incremental vector, and the current step of the ZC sequence to be generated; when the remainder is 1, 2, 3, generating according to the previous vector of the ZC sequence to be generated, the previous incremental vector, and the previous step The current vector and the current incremental vector of the ZC sequence to be generated; however, according to the previous vector, the previous incremental vector and the previous step of the ZC sequence to be generated, the current vector and the current incremental vector of the ZC sequence to be generated are generated.
  • the error is large, so in order to reduce the accumulated error, the preset iteration depth can be reduced.
  • the next address vector and the next address increase are determined according to the current address vector, the current address increment vector, and the preset address increment step.
  • the quantity vector includes: determining the next address vector according to the current address vector, the current address increment vector, and the length of the ZC sequence to be generated, and using the remainder function; stepping according to the current address increment vector and the preset address increment And the length of the ZC sequence to be generated, using the remainder function to determine the next address increment vector.
  • the ZC sequence to be generated can be generated between the minimum value and the maximum value of the above I; in an optional embodiment, when When the preset vector iterative calculation method is used, the ZC sequence to be generated of length N can be directly generated;
  • S103 may include:
  • the ZC sequence to be generated is generated according to the symmetry of the ZC sequence to be generated and based on the elements of the generated vectors of the ZC sequences to be generated.
  • the iterative calculation is ended.
  • the preset number of iterations is based on the length of the ZC sequence to be generated and the preset value P. Therefore, the generated ZC to be generated is generated.
  • the number of elements in each vector of the sequence is 2PI, and 2PI is greater than or equal to N/2. It is less than N, so after the 2PI sequence elements are generated, the remaining elements of the ZC sequence to be generated may be generated according to the symmetry of the ZC sequence to be generated, so that the calculation amount can be further reduced;
  • Step a determining the first first vector according to the initial address vector, the initial address increment vector, and a preset address increment step
  • first searching a pre-stored first mapping table according to the initial address vector, an initial address increment vector, and a preset address increment to obtain the first first vector and the first increment.
  • Vector and vector incremental steps the first mapping table is used to characterize the mapping relationship between the address vector and the first vector, the address increment vector and the increment vector, the address increment step, and the vector increment step.
  • the second address vector and the second address increment are calculated according to the initial address vector, the initial address increment vector, and the preset address increment step by using the following formula (7).
  • Vector up to the first address vector and the first address increment vector; searching the first mapping table based on the first address vector and the first address increment vector to obtain the first A vector; thus, all the first vectors are obtained.
  • Step c determining the second vector according to the symmetry policy based on the first vector, to generate the ZC sequence
  • the second vector can be obtained according to formula (3). Determine the institute Determining that the first first vector is a first second vector; determining that the first one first vector is a second second vector until determining that the first first vector is the first second vector;
  • the ZC sequence has symmetry, that is, the ZC sequence is divided into a first vector and a second vector, the first vector and the second vector are the same number, and the first vector queue is the same a first vector is the same as a last second vector in the second vector queue, and the second first vector is the same as the second vector in the second vector queue adjacent to the last second vector. analogy.
  • FIG. 2 is an optional schematic flowchart of a method for generating a ZC sequence according to an embodiment of the present invention
  • the address vector can be iteratively calculated in parallel, and P addresses can be calculated at one time. Since the ZC sequence index portion is in the period of 2 ⁇ , the address vector a i , the address increment vector s i , and the address step ⁇ are both 2N. cycle.
  • the method for generating the ZC sequence includes:
  • S201 initializing an initial address vector and an initial address increment vector
  • the initial address vector a 0 and the initial address increment vector s 0 are initialized by using the following formula, and the preset address increment step ⁇ is calculated:
  • the initialization losses a 0 , s 0 can be stored in the memory according to requirements, or Calculated in real time.
  • the iterative process is the addition of two numbers, so the remainder function can be replaced by a judgment, that is, the addition result is greater than or equal to 2N, and the addition result is subtracted by 2N to obtain the final result; otherwise, the addition result For the end result.
  • the ZC sequence is calculated using an iterative method, and it is not necessary to store all the sequences, thereby reducing the storage amount, and also avoiding the multiplication of the 3 items of the ZC sequence index part beyond the DSP multiplier range; and the conventional method uses scalar iteration
  • the address is calculated, and the vector DSP processing is not applicable.
  • the address is calculated by parallel iteration, and the parallel computing resources of the vector DSP are fully utilized to reduce the address calculation time.
  • the entire ZC sequence is directly obtained by looking up the table. There is a large amount of data interaction between the DSP and the external memory, and the system with large interaction cost is not applicable.
  • a partial ZC sequence is obtained by using a look-up table, and all ZC sequences are calculated through partial ZC sequences, thereby reducing data interaction between the DSP and the external memory. , reduce the sequence generation time.
  • the embodiment of the present invention converts the method of generating an address by element by iteratively into a vector iteratively generating an address, fully utilizing the vector DSP parallel computing resources, and simultaneously calculating the entire sequence by using a partial ZC sequence, reducing the DSP and the external memory. Interaction between.
  • an initial address vector and an initial address increment vector of a ZC sequence to be generated are determined, and then, according to a current address vector, a current address increment vector, and a preset address increase.
  • the stepping method uses a preset vector iterative algorithm to generate a current vector, a next address vector, and a next address increment vector of the ZC sequence to be generated, so that multiple values can be included in the vector to calculate multiple times in parallel.
  • the ZC sequence to be generated may be generated according to the generated elements of each vector of the ZC sequence to be generated.
  • the preset iteration number I is calculated as:
  • N is the length of the ZC sequence to be generated
  • P is a preset value
  • P is greater than 1. It can be seen that the embodiment of the present invention can generate the ZC sequence elements to be generated in parallel by using a preset vector iterative algorithm, thereby shortening the generation. The time of the ZC sequence increases the efficiency of ZC sequence generation.
  • FIG. 3 is a schematic structural diagram of a device for generating a ZC sequence according to an embodiment of the present invention.
  • the device for generating a ZC sequence includes: Determining module 31, iterating module 32 and generating module 33;
  • the determining module 31 is configured to determine an initial address vector and an initial address increment vector of the ZC sequence to be generated; the iteration module 32 is configured to step according to the initial address vector, the initial address increment vector, and the preset address increment. a preset vector iterative algorithm is used to generate a current vector, a next address vector, and a next address increment vector of the ZC sequence to be generated.
  • the generating module 33 is configured to: when the current iteration number is equal to the preset number of iterations I, according to The generated elements of the respective vectors of the ZC sequence to be generated obtain the ZC sequence to be generated.
  • N is the length of the ZC sequence to be generated
  • P is a preset value
  • P is greater than 1.
  • the iterative module 32 includes: a first determining submodule configured to increase according to an initial address vector and an initial address, in order to obtain a ZC sequence to be generated by using a preset vector iterative algorithm.
  • the quantity vector and the preset address increment step are determined to determine the current vector of the ZC sequence to be generated;
  • the second determining sub-module is configured to increase according to the current address vector and the current address when the current iteration number is less than the preset number of iterations
  • the quantity vector and the preset address increment step determine the next address vector and the next address increment vector;
  • the trigger sub-module is configured to update the current iteration number, and trigger the first determining sub-module to make the first determiner Module based
  • the current address vector, the current address increment vector, and the preset address increment step are determined to determine the current vector of the ZC sequence to be generated.
  • the current vector of the ZC sequence to be generated is determined according to the current address vector, the current address increment vector, and the preset address increment step. Then, in the specific implementation process, the first Determining a sub-module, configured to divide the current number of iterations by a preset iteration depth to obtain a remainder; when the remainder is equal to 0, the table looks for the current vector, the current increment vector, and the current step of the ZC sequence to be generated; At 0, the current vector and the current incremental vector of the ZC sequence to be generated are generated according to the previous vector of the ZC sequence to be generated, the previous increment vector, and the previous step.
  • the second determining submodule is configured to use the current address vector and the current address increment vector when the current iteration number is less than the preset number of iterations. And the length of the ZC sequence to be generated, using the remainder function to determine the next address vector; according to the current address increment vector, the preset address increment step and the length of the ZC sequence to be generated, using the remainder function to determine The next address increment vector.
  • the determining module 31 is configured to be based on the ZC sequence to be generated, in order to calculate the initial address vector and the initial address increment vector of the ZC sequence to be generated according to the preset algorithm.
  • the generating module 33 is configured as follows:
  • the ZC sequence to be generated is generated according to the symmetry of the ZC sequence to be generated and based on the elements of the generated vectors of the ZC sequences to be generated.
  • the iteration module 32 is configured to be based on the initial address vector, initial The initial address increment vector and the preset address increment step by step to find the first mapping table, and obtain the first first vector, the first incremental vector, and the vector incremental step; the first mapping table is used by And mapping a mapping relationship between the address vector and the first vector, the address increment vector and the increment vector, the address increment step, and the vector increment step; according to the first first vector, the first increment The vector and the vector increment step determine the second first vector, and so on, until the (I-1)th first vector is determined.
  • the generating module 33 is configured to determine, according to the symmetry policy, that the first first vector is a first second vector, and determine that the first one first vector is a second second vector, Determining that the first first vector is the first second vector to generate the ZC sequence.
  • the determining module 31, the iterative module 32, the generating module 33, the first determining submodule, the second determining submodule, and the triggering submodule may each be a central processing unit (CPU, Central Processing Unit) of the vector DSP located at the base station side. ), microprocessor (MPU, Microprocessor Unit), ASIC (Application Specific Integrated Circuit) or Field-Programmable Gate Array (FPGA).
  • CPU Central Processing Unit
  • MPU Microprocessor Unit
  • ASIC Application Specific Integrated Circuit
  • FPGA Field-Programmable Gate Array
  • This embodiment describes a computer readable medium, which may be a ROM (eg, a read only memory, a FLASH memory, a transfer device, etc.), a magnetic storage medium (eg, a magnetic tape, a disk drive, etc.), an optical storage medium (eg, a CD- ROM, DVD-ROM, paper card, paper tape, etc.) and other well-known types of program memory; computer-readable medium storing computer-executable instructions that, when executed, cause at least one processor to perform operations including:
  • the generation algorithm generates a current vector, a next address vector, and a next address increment vector of the ZC sequence to be generated; and when the current iteration number is greater than the preset number of iterations I, the elements of each vector according to the generated ZC sequence to be generated , the ZC sequence to be generated is obtained; the preset iteration number I is calculated as:
  • N is the length of the ZC sequence to be generated
  • P is a preset value, and P is greater than 1.
  • an initial address vector and an initial address increment vector of a ZC sequence to be generated are determined, and then, according to a current address vector, a current address increment vector, and a preset address increase.
  • the stepping method uses a preset vector iterative algorithm to generate a current vector, a next address vector, and a next address increment vector of the ZC sequence to be generated, so that multiple values can be included in the vector to calculate multiple times in parallel.
  • the ZC sequence to be generated can be generated according to the elements of the generated vectors of the ZC sequence to be generated.
  • the calculation formula of the preset number of iterations I is:
  • N is the length of the ZC sequence to be generated
  • P is a preset value
  • P is greater than 1. It can be seen that the embodiment of the present invention can generate the ZC sequence elements to be generated in parallel by using a preset vector iterative algorithm, thereby shortening the generation. The time of the ZC sequence increases the efficiency of ZC sequence generation.
  • the embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores a computer program, and the computer program is used to execute the method for generating the ZC sequence according to the embodiment of the present invention, including: determining a ZC sequence to be generated. Initial address vector, initial address increment vector; the ZC sequence includes 1 first vector and 1 second vector, I is positive Integer
  • the second vector is determined in accordance with a symmetry policy based on the first vector to generate the ZC sequence.
  • the disclosed apparatus and method can be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner such as: multiple units or components may be combined, or Can be integrated into another system, or some features can be ignored or not executed.
  • the coupling, or direct coupling, or communication connection of the components shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may be electrical, mechanical or other forms. of.
  • the units described above as separate components may or may not be physically separated, and the components displayed as the unit may or may not be physical units; they may be located in one place or distributed on multiple network units; Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may be separately used as one unit, or two or more units may be integrated into one unit;
  • the unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the foregoing program may be stored in a computer readable storage medium, and when executed, the program includes The foregoing steps of the method embodiment; and the foregoing storage medium includes: a removable storage device, a read only memory (ROM), a magnetic disk, or an optical disk, and the like, which can store program codes.
  • ROM read only memory
  • the above-described integrated unit of the present invention may be stored in a computer readable storage medium if it is implemented in the form of a software function module and sold or used as a standalone product.
  • the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions. Enabling a computer device (which may be a personal computer, server, or network device, etc.) to perform all of the methods of the various embodiments of the present invention or section.
  • the foregoing storage medium includes various media that can store program codes, such as a mobile storage device, a ROM, a magnetic disk, or an optical disk.
  • an initial address vector and an initial address increment vector of a ZC sequence to be generated are determined; the ZC sequence includes one first vector and one second vector, and I is a positive integer; according to the initial address vector Determining, by the initial address increment vector and the preset address increment step, the first first vectors; determining the second vector according to the symmetry policy based on the first vector, to generate the ZC sequence .

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Abstract

本发明实施例公开了一种ZC序列的生成方法，该方法包括：确定出待生成ZC序列的初始地址矢量和初始地址增量矢量；根据当前地址矢量、当前地址增量矢量和预设的地址增量步进，采用预设的矢量迭代算法，生成待生成ZC序列的当前矢量、下一个地址矢量和下一个地址增量矢量；在当前迭代次数等于预设的迭代次数I时，根据已生成的待生成ZC序列的各个矢量的元素，得到待生成ZC序列。本发明实施例还同时公开了另一种ZC序列的生成方法及两种ZC序列的生成装置。

Description

一种ZC序列的生成方法、装置及存储介质
相关申请的交叉引用
本申请基于申请号为201611015036.2、申请日为2016年11月18日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明涉及数字信号处理领域，尤其涉及一种ZC序列的生成方法、装置及存储介质。
背景技术
目前，Zadoff-Chu(ZC)序列因其良好的自相关和互相关性，广泛用于长期演进(LTE，Long Term Evolution)系统中，例如，LTE下行链路中的主同步信号，上行链路中的解调信号和探测信号，以及随机接入信道的前导码。
在现有技术中，信号处理设备常采用查表法，将ZC序列存储于信号处理设备中，使用时再读取，然而，LTE系统中有多种ZC序列，如果全部存储，将消耗非常大的存储空间，因此需要采用实时计算ZC序列，但是现有的实时计算ZC序列的方法是按照顺序来实时计算ZC序列的，这样的方法计算时间长，消耗的存储空间大。
发明内容
有鉴于此，本发明实施例期望提供一种ZC序列的生成方法、装置及存储介质，以解决现有技术中存在的生成ZC序列时计算时间长的技术问题， 缩短了生成ZC序列的时间，提高了ZC序列的生成效率。
为达到上述目的，本发明的技术方案是这样实现的：
第一方面，本发明实施例提供一种ZC序列的生成方法，包括：确定出待生成ZC序列的初始地址矢量和初始地址增量矢量；根据初始地址矢量、初始地址增量矢量和预设的地址增量步进，采用预设的矢量迭代算法，生成所述待生成ZC序列的当前矢量、下一个地址矢量和下一个地址增量矢量；在当前迭代次数等于预设的迭代次数I时，根据已生成的所述待生成ZC序列的各个矢量的元素，得到所述待生成ZC序列；其中，所述预设的迭代次数I为：
Figure PCTCN2017081972-appb-000001
N为所述待生成ZC序列的长度，P为预设值，且P大于1。
上述方案中，所述根据初始地址矢量、初始地址增量矢量和所述预设的地址增量步进，采用预设的矢量迭代算法，生成所述待生成ZC序列的当前矢量、下一个地址矢量和下一个地址增量矢量，包括：根据所述初始地址矢量、所述初始地址增量矢量和所述预设的地址增量步进，确定出所述待生成ZC序列的当前矢量、当前地址矢量和当前地址增量矢量；在所述当前迭代次数小于所述预设的迭代次数时，根据所述当前地址矢量、所述当前地址增量矢量和所述预设的地址增量步进，确定出下一个地址矢量和下一个地址增量矢量；更新所述当前迭代次数，并返回至所述根据所述当前地址矢量、所述当前地址增量矢量和所述预设的地址增量步进，确定出所述待生成ZC序列的当前矢量的步骤。
上述方案中，所述根据所述初始地址矢量、所述初始地址增量矢量和所述预设的地址增量步进，确定出所述待生成ZC序列的当前矢量，包括：所述当前迭代次数除以预设的迭代深度，得到余数；在所述余数等于0时，查表得到所述待生成ZC序列的当前矢量、当前增量矢量和当前步进；在所 述余数不等于0时，根据所述待生成ZC序列的上一个矢量、上一个增量矢量和上一个步进，生成所述待生成ZC序列的当前矢量和当前增量矢量。
上述方案中，所述根据所述当前地址矢量、所述当前地址增量矢量和所述预设的地址增量步进，确定出下一个地址矢量和下一个地址增量矢量，包括：根据所述当前地址矢量、所述当前地址增量矢量和所述待生成ZC序列的长度，采用求余函数，确定出所述下一个地址矢量；根据所述当前地址增量矢量、所述预设的地址增量步进和所述待生成ZC序列的长度，采用求余函数，确定出所述下一个地址增量矢量。
上述方案中，所述确定出待生成ZC序列的初始地址矢量和初始地址增量矢量，包括：根据待生成ZC序列的根指数、所述待生成的ZC序列的长度N、所述预设值P、以及预设的P个编号，采用求余函数，分别确定出预设的各个编号对应的地址和所述预设的各个编号对应的地址增量；用所述预设的各个编号对应的地址形成所述初始地址矢量；用所述预设的各个编号对应的地址增量形成所述初始地址增量矢量。
上述方案中，所述预设的迭代次数I满足如下条件：
Figure PCTCN2017081972-appb-000002
相应地，所述根据已生成的所述待生成ZC序列的各个矢量的元素，得到所述待生成ZC序列，包括：按照所述待生成ZC序列的对称性，并根据已生成的所述待生成ZC序列的各个矢量的元素，生成所述待生成ZC序列。
本发明实施例提供一种ZC序列的生成装置，包括：确定模块，配置为确定出待生成ZC序列的初始地址矢量和初始地址增量矢量；迭代模块，配置为根据初始地址矢量、初始地址增量矢量和预设的地址增量步进，采用预设的矢量迭代算法，生成所述待生成ZC序列的当前矢量、下一个地址矢量和下一个地址增量矢量；生成模块，配置为在当前迭代次数等于预设的迭代次数I时，根据已生成的所述待生成ZC序列的各个矢量的元素，得到所述待生成ZC序列；其中，所述预设的迭代次数I为：
Figure PCTCN2017081972-appb-000003
N为所述待生成ZC序列的长度，P为预设值，且P大于1。
进一步地，所述迭代模块，包括：第一确定子模块，配置为根据所述初始地址矢量、所述初始地址增量矢量和所述预设的地址增量步进，确定出所述待生成ZC序列的当前矢量、当前地址矢量和当前地址增量矢量；第二确定子模块，配置为在所述当前迭代次数小于所述预设的迭代次数时，根据所述当前地址矢量、所述当前地址增量矢量和所述预设的地址增量步进，确定出下一个地址矢量和下一个地址增量矢量；触发子模块，配置为更新所述当前迭代次数，并触发所述第一确定子模块，使得所述第一确定子模块根据所述当前地址矢量、所述当前地址增量矢量和所述预设的地址增量步进，确定出所述待生成ZC序列的当前矢量。
上述方案中，所述第一确定子模块，配置为所述当前迭代次数除以预设的迭代深度，得到余数；在所述余数等于0时，查表得到所述待生成ZC序列的当前矢量、当前增量矢量和当前步进；在所述余数不等于0时，根据所述待生成ZC序列的上一个矢量、上一个增量矢量和上一个步进，生成所述待生成ZC序列的当前矢量和当前增量矢量。
上述方案中，所述第二确定子模块，配置为在所述当前迭代次数大于等于所述预设的迭代次数时，根据所述当前地址矢量、所述当前地址增量矢量和所述待生成ZC序列的长度，采用求余函数，确定出所述下一个地址矢量；根据所述当前地址增量矢量、所述预设的地址增量步进和所述待生成ZC序列的长度，采用求余函数，确定出所述下一个地址增量矢量。
上述方案中，所述确定模块，配置为根据待生成ZC序列的根指数、所述待生成的ZC序列的长度N、所述预设值P、以及预设的P个编号，采用求余函数，分别确定出预设的各个编号对应的地址和所述预设的各个编号对应的地址增量；用所述预设的各个编号对应的地址形成所述初始地址矢 量；用所述预设的各个编号对应的地址增量形成所述初始地址增量矢量。
进一步地，所述预设的迭代次数I满足如下条件：
Figure PCTCN2017081972-appb-000004
相应地，所述生成模块，配置为按照所述待生成ZC序列的对称性，并根据已生成的所述待生成ZC序列的各个矢量的元素，生成所述待生成ZC序列。
本发明实施例还提供一种ZC序列的生成方法，包括：确定待生成ZC序列的初始地址矢量、初始地址增量矢量；所述ZC序列包括I个第一矢量和I个第二矢量，I为正整数；根据所述初始地址矢量、所述初始地址增量矢量和预设的地址增量步进，确定所述I个第一矢量；基于所述第一矢量按照对称性策略确定所述第二矢量，以生成所述ZC序列。
上述方案中，所述根据所述初始地址矢量、所述初始地址增量矢量和预设的地址增量步进，确定所述I个第一矢量，包括：
基于所述初始地址矢量、初始地址增量矢量和预设的地址增量步进查找第一映射表，获取所述第一个第一矢量、第一个增量矢量和矢量增量步进；所述第一映射表用于表征地址矢量与第一矢量、地址增量矢量与增量矢量、地址增量步进与矢量增量步进的映射关系；根据所述第一个第一矢量、所述第一个增量矢量和所述矢量增量步进确定第二个第一矢量，以此类推，直至确定第(I-1)个第一矢量；根据所述初始地址矢量、所述初始地址增量矢量和所述预设的地址增量步进计算第二个地址矢量和第二个地址增量矢量，直至第I个地址矢量和第I个地址增量矢量；基于所述第I个地址矢量、所述第I个地址增量矢量查找所述第一映射表，获取所述第I个第一矢量。
上述方案中，所述根据所述第一个第一矢量、所述第一个增量矢量和所述矢量增量步进确定第二个第一矢量和第二个增量矢量，包括：
计算所述第一个第一矢量与所述第一个增量矢量之积，得到所述第二个第一矢量；计算所述第一个增量矢量与所述矢量增量步进之积，得到所述第二个增量矢量。
上述方案中，所述基于所述第一矢量按照对称性策略确定所述第二矢量，包括：
按照对称性策略，确定所述第I个第一矢量为第一个第二矢量；确定所述第I-1个第一矢量为第二个第二矢量，直至确定第1个第一矢量为第I个第二矢量。
本发明实施例还提供一种ZC序列的生成装置，包括初始模块，配置为确定待生成ZC序列的初始地址矢量、初始地址增量矢量；所述ZC序列包括I个第一矢量和I个第二矢量，I为正整数；
第一确定模块，配置为根据所述初始地址矢量、所述初始地址增量矢量和预设的地址增量步进，确定所述I个第一矢量；
第二确定模块，配置为基于所述第一矢量按照对称性策略确定所述第二矢量，以生成所述ZC序列。
上述方案中，所述第一确定模块，配置为基于所述初始地址矢量、初始地址增量矢量和预设的地址增量步进查找第一映射表，获取所述第一个第一矢量、第一个增量矢量和矢量增量步进；所述第一映射表用于表征地址矢量与第一矢量、地址增量矢量与增量矢量、地址增量步进与矢量增量步进的映射关系；
根据所述第一个第一矢量、所述第一个增量矢量和所述矢量增量步进确定第二个第一矢量，以此类推，直至确定第(I-1)个第一矢量；
根据所述初始地址矢量、所述初始地址增量矢量和所述预设的地址增量步进计算第二个地址矢量和第二个地址增量矢量，直至第I个地址矢量和第I个地址增量矢量；
基于所述第I个地址矢量、所述第I个地址增量矢量查找所述第一映射表，获取所述第I个第一矢量。
上述方案中，所述第一确定模块，配置为基于所述初始地址矢量、初始地址增量矢量和预设的地址增量步进查找第一映射表，获取所述第一个第一矢量、第一个增量矢量和矢量增量步进；所述第一映射表用于表征地址矢量与第一矢量、地址增量矢量与增量矢量、地址增量步进与矢量增量步进的映射关系；
根据所述第一个第一矢量、所述第一个增量矢量和所述矢量增量步进确定第二个第一矢量，以此类推，直至确定第(I-1)个第一矢量；
根据所述初始地址矢量、所述初始地址增量矢量和所述预设的地址增量步进计算第二个地址矢量和第二个地址增量矢量，直至第I个地址矢量和第I个地址增量矢量；
基于所述第I个地址矢量、所述第I个地址增量矢量查找所述第一映射表，获取所述第I个第一矢量。
上述方案中，所述第一确定模块，配置为计算所述第一个第一矢量与所述第一个增量矢量之积，得到所述第二个第一矢量；
计算所述第一个增量矢量与所述矢量增量步进之积，得到所述第二个增量矢量。
上述方案中，所述第二确定模块，配置为按照对称性策略，确定所述第I个第一矢量为第一个第二矢量；
确定所述第I-1个第一矢量为第二个第二矢量，直至确定第1个第一矢量为第I个第二矢量。
本发明实施例还提供一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，该计算机可执行指令用于执行上述的ZC序列的生成方法。
本发明实施例所提供的ZC序列的生成方法、装置及存储介质，首先，确定出待生成ZC序列的初始地址矢量和初始地址增量矢量，然后，根据当前地址矢量、当前地址增量矢量和预设的地址增量步进，采用预设的矢量迭代算法，生成待生成ZC序列的当前矢量、下一个地址矢量和下一个地址增量矢量，这样，通过矢量中可以包括有多个数值，来并行地计算多个值，从而得到待生成ZC序列的当前矢量、下一个地址矢量和下一个地址增量矢量，其次，在当前迭代次数大于预设的迭代次数I时，根据已生成的待生成ZC序列的各个矢量的元素，得到待生成ZC序列，也就是说，在采用预设的矢量迭代算法进行I次迭代运算之后，根据已生成的待生成ZC序列的各个矢量的元素便可以生成待生成ZC序列，另外，预设的迭代次数I为：
Figure PCTCN2017081972-appb-000005
其中，N为所述待生成ZC序列的长度，P为预设值，且P大于1，可见，本发明实施例通过采用预设的矢量迭代算法，能够并行地生成待生成ZC序列元素，缩短了生成ZC序列的时间，提高了ZC序列的生成效率。
附图说明
图1为本发明实施例中ZC序列的生成方法的流程示意图；
图2为本发明实施例中ZC序列的生成方法的一种可选的流程示意图；
图3为本发明实施例中ZC序列的生成装置的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
本发明实施例提供一种ZC序列的生成方法，该方法可以应用于LTE系统中基站侧基带信号处理通常采用的矢量数字处理器(DSP，Digital Signal Processor)中；
图1为本发明实施例中ZC序列的生成方法的流程示意图，如图1所示，该方法包括：
S101：确定出待生成ZC序列的初始地址矢量和初始地址增量矢量；
从ZC序列的定义出发，ZC序列的定义用如下公式表示：
Figure PCTCN2017081972-appb-000006
其中，N表示为ZC序列的长度，u表示为ZC序列的根指数，n表示为ZC序列的元素下标，从ZC序列的定义可以看出，ZC序列具有对称性；
由上述ZC序列的定义可以看出，按顺序一个一个串行地处理方式来生成的ZC序列需要耗费较长的时间，为了缩短计算时间，可以采用并行的计算方法来生成ZC序列，具体来说，首先需要确定出待生成ZC序列的初始地址矢量和初始地址增量矢量；
其中，上述待生成ZC序列的初始地址矢量和初始地址增量矢量可以用于确定对应的待生成ZC序列的矢量，每一个待生成ZC序列的矢量中包括有预设值P个序列元素；并且，上述待生成ZC序列的初始地址矢量和初始地址增量矢量可以是预先设置好的矢量，也可以是根据预设的算法计算出来的；这里，本发明实施例不做具体限定。
那么，为了根据预设的算法来计算出的待生成ZC序列的初始地址矢量和初始地址增量矢量，在一种可选的实施例中，S101可以包括：
根据待生成ZC序列的根指数、待生成的ZC序列的长度N、预设值P、以及预设的P个编号，采用求余函数，分别确定出预设的各个编号对应的地址和预设的各个编号对应的地址增量；用预设的各个编号对应的地址形成初始地址矢量；用预设的各个编号对应的地址增量形成初始地址增量矢量。
需要说明的是，上述待生成ZC序列的根指数用u表示、待生成的ZC序列的长度用N表示、上述预设值P为矢量DSP的并行能力，即进行矢量 计算时，每次对一个矢量进行处理时，每个矢量中所包含的元素的个数，例如，P＝16，说明矢量DSP每次并行处理16个数值，每个数值对应一个序列元素；当P＝16时，上述预设的P个编号p可以为0，1，2，3，4，5，6，7，8，9，10，11，12，13，14，15；然后，根据N，u，P，p采用求余函数分别进行并行计算得到每个p对应的地址和每个p对应的地址增量，然后，用每个p对应的地址可以形成待生成ZC序列的初始地址矢量a0，用每个p对应的地址增量可以形成待生成ZC序列的初始地址增量矢量s0；
这样，便确定出了待生成ZC序列的初始地址矢量和初始地址增量矢量。
S102：根据所述初始地址矢量、所述初始地址增量矢量和预设的地址增量步进，采用预设的矢量迭代算法，生成待生成ZC序列的当前矢量、下一个地址矢量和下一个地址增量矢量；
具体来说，在S101中确定出初始地址矢量和初始地址增量矢量之后，根据初始地址矢量、初始地址增量矢量和预设的地址增量步进，采用预设的矢量迭代算法不仅可以生成待生成ZC序列的当前矢量、当前地址矢量和当前地址增量矢量，同时还可以生成待生成ZC序列的下一个地址矢量和下一个地址增量矢量，以此类推，进行预设的迭代次数(I次)的迭代运算；
为了通过预设的矢量迭代算法进行迭代计算获得待生成ZC序列，在一种可选的实施例中，S102可以包括：
根据初始地址矢量、初始地址增量矢量和预设的地址增量步进，确定出待生成ZC序列的当前矢量；在当前迭代次数小于预设的迭代次数时，根据当前地址矢量、当前地址增量矢量和预设的地址增量步进，确定出下一个地址矢量和下一个地址增量矢量；更新当前迭代次数，并返回至根据当前地址矢量、当前地址增量矢量和预设的地址增量步进，确定出待生成ZC序列的当前矢量的步骤。
在具体实施过程中，根据当前地址矢量、当前地址增量矢量和预设的地址增量步进，确定出待生成ZC序列的当前矢量中可以是通过查表的方式，和/或，通过设定的算法来计算的方式，这里，本发明实施例不做具体限定。
在确定出待生成ZC序列的当前矢量之后，判断当前迭代次数是否等于预设的迭代次数，在当前的迭代次数等于预设的迭代次数时，结束迭代计算，生成待生成ZC序列，相当于执行S103，在当前迭代次数小于预设的迭代次数时，继续进行迭代，即迭代次数加1，继续确定待生成ZC序列的当前矢量；其中，预设的迭代次数I为：
Figure PCTCN2017081972-appb-000007
其中，N为待生成ZC序列的长度，P为预设值，且P大于1；也就是说，一共只有I在上述范围内时才可以结束迭代计算生成待生成的ZC序列。
在每一次的迭代计算中，都是根据当前地址矢量、当前地址增量矢量和预设的地址增量步进来确定待生成ZC序列的当前矢量，那么，在具体实施过程中，根据当前地址矢量、当前地址增量矢量和预设的地址增量步进，确定出待生成ZC序列的当前矢量，包括：当前迭代次数除以预设的迭代深度，得到余数；在余数等于0时，查表得到待生成ZC序列的当前矢量、当前增量矢量和当前步进；在余数不等于0时，根据待生成ZC序列的上一个矢量、上一个增量矢量和上一个步进，生成待生成ZC序列的当前矢量和当前增量矢量。
其中，上述预设的迭代深度与累计误差成正比，所以，预设的迭代深度可以根据所需的精度灵活选取；预设的迭代深度越大，累计误差就越大，并且，上述预设的迭代深度为正整数。
例如，当预设的迭代深度等于4时，当前迭代次数除以预设的迭代深度所得到的余数可以为0，1，2，3这4个数，只有当余数等于0时，查表 得到待生成ZC序列的当前矢量、当前增量矢量和当前步进；当余数为1，2，3时，根据待生成ZC序列的上一个矢量、上一个增量矢量和上一个步进，生成待生成ZC序列的当前矢量和当前增量矢量；然而，根据待生成ZC序列的上一个矢量、上一个增量矢量和上一个步进，生成待生成ZC序列的当前矢量和当前增量矢量相比于通过查表的方式得到的待生成ZC序列的矢量，误差较大，所以，为了减小累计误差，可以减小预设的迭代深度。
采用预设的矢量迭代算法中，在一种可选的实施例中，根据当前地址矢量、当前地址增量矢量和预设的地址增量步进，确定出下一个地址矢量和下一个地址增量矢量，包括：根据当前地址矢量、当前地址增量矢量和待生成ZC序列的长度，采用求余函数，确定出下一个地址矢量；根据当前地址增量矢量、预设的地址增量步进和待生成ZC序列的长度，采用求余函数，确定出下一个地址增量矢量。
S103：在当前迭代次数等于预设的迭代次数I时，根据已生成的待生成ZC序列的各个矢量的元素，得到待生成ZC序列。
由上述公式(2)可知，上述I的在最小值和最大值之间便可以生成待生成的ZC序列；在一种可选的实施例中，当
Figure PCTCN2017081972-appb-000008
时，则，通过上述预设的矢量迭代计算方法就可以直接生成长度为N的待生成ZC序列；
当
Figure PCTCN2017081972-appb-000009
时，在一种可选的实施例中，S103可以包括：
按照待生成ZC序列的对称性，并根据已生成的待生成ZC序列的各个矢量的元素，生成待生成ZC序列。
其中，在当前迭代次数大于预设的迭代次数I时，结束迭代计算，基于上述预设的迭代次数是基于待生成ZC序列的长度和预设值P的，所以，上述已生成的待生成ZC序列的各个矢量的元素个数为2PI，2PI大于等于N/2 小于N，所以，在生成了2PI个序列元素之后，需将待生成ZC序列剩下的元素根据待生成ZC序列的对称性来生成即可，这样可以进一步地减小计算量；
在实际应用中，可以采用如下公式来生成：
Figure PCTCN2017081972-appb-000010
具体地，上述S102和S103的具体实现方式可以理解为包括以下步骤：
步骤a，根据所述初始地址矢量、所述初始地址增量矢量和预设的地址增量步进，确定所述I个第一矢量；
具体地，首先，基于所述初始地址矢量、初始地址增量矢量和预设的地址增量步进查找预先存储的第一映射表，获取所述第一个第一矢量、第一个增量矢量和矢量增量步进；所述第一映射表用于表征地址矢量与第一矢量、地址增量矢量与增量矢量、地址增量步进与矢量增量步进的映射关系。
然后，利用下述公式(10)计算所述第一个第一矢量与所述第一个增量矢量之积，得到所述第二个第一矢量，并计算所述第一个增量矢量与所述矢量增量步进之积，得到所述第二个增量矢量；以此类推，直至确定第(I-1)个第一矢量。
在上述过程中，利用下述公式(7)根据所述初始地址矢量、所述初始地址增量矢量和所述预设的地址增量步进计算第二个地址矢量和第二个地址增量矢量，直至第I个地址矢量和第I个地址增量矢量；基于所述第I个地址矢量、所述第I个地址增量矢量查找所述第一映射表，获取所述第I个第一矢量；至此，获取了全部第一矢量。
步骤c，基于所述第一矢量按照对称性策略确定所述第二矢量，以生成所述ZC序列；
具体地，按照对称性策略，可根据公式(3)获取第二矢量。确定所 述第I个第一矢量为第一个第二矢量；确定所述第I-1个第一矢量为第二个第二矢量，直至确定第1个第一矢量为第I个第二矢量；
这里，由于所述ZC序列具有对称性，即将所述ZC序列划分为第一矢量和第二矢量，所述第一矢量和所述第二矢量的数量相同，所述第一矢量队列中的第一个第一矢量与所述第二矢量队列中最后一个第二矢量相同，第二个第以矢量与所述第二矢量队列中与最后一个第二矢量相邻的第二矢量相同，以此类推。
下面举实例来对以上ZC序列的生成方法中的一个或多个实施例进行说明。
图2为本发明实施例中ZC序列的生成方法的一种可选的流程示意图；待生成ZC序列为q阶ZC序列，则q阶ZC序列的计算公式为：
Figure PCTCN2017081972-appb-000011
其中，则通过上述公式(2)计算出预设的迭代次数I，那么，在进行完I次迭代计算之后，可以确定出ZC序列前一半可以分为I个矢量，用xi来表示，其中，i＝0，1，…，I-1；第I-1个矢量中元素的个数为N/2-(I-1)P，其他矢量元素的个数为P；那么，地址矢量a(n)可以按照下列公式计算：
a(n)＝mod(qn(n+1),2N)   (5)
同样，将a(n)分段得到I个地址矢量ai，i＝0，1，…，I-1，矢量ai中第p个元素记为ai,p,表示如下：
ai,p＝mod(q(iP+p)(iP+p+1),2N)   (6)
则，经过推到可得到如下递推关系：
Figure PCTCN2017081972-appb-000012
由此可见，地址矢量可并行迭代计算，一次可计算P个地址，由于ZC 序列指数部分以2π为周期，所以，地址矢量ai、地址增量矢量si、地址步进δ均以2N为周期。
如图2所示，该ZC序列的生成方法包括：
S201：初始地址矢量和初始地址增量矢量的初始化；
具体为：当i＝0时，采用下列公式对初始地址矢量a0和初始地址增量矢量s0进行初始化，以及计算预设的地址增量步进δ：
Figure PCTCN2017081972-appb-000013
其中，p为每一个矢量中P个元素的编号，依次为0，1，…，P-1；对于初始化阶段，可根据需求，将初始化失量a0、s0存储在存储器中，也可以实时计算得到。
S202：计算下一个地址矢量ai+1和下一个地址增量矢量si+1；
Figure PCTCN2017081972-appb-000014
其中，通过上述公式(9)，迭代过程是两数相加，所以求余函数可用判断来代替，即相加结果大于等于2N，则相加结果减去2N得到最终结果，否则，相加结果为最终结果。
S203：判断mod(i,Q)是否等于0；
S204：当mod(i,Q)等于0时，根据地址矢量ai、地址增量矢量si、地址增量步进δ查表分别得到ZC序列矢量xi、增量矢量yi，步进z，
S205：当mod(i,Q)不等于0时，根据xi-1和yi-1计算xi，其中Q称为迭代计算深度，Q值与累计误差成正比，计算过程如下公式：
Figure PCTCN2017081972-appb-000015
这样，便得到了所有xi，即ZC序列前一半元素。
S206：判断i是否等于I-1；
S207：当i等于I-1时，利用ZC序列的对称性，采用上述公式(3)，复制得到ZC序列的后一半元素，最终，得到所有ZC序列元素；
S208：当i小于I-1时，令i的值加1(相当于图2中的i＝i+1)，返回执行S202。
上述ZC序列的生成方法中，使用迭代方法计算ZC序列，无需存储所有序列，减小存储量，同时也避免ZC序列指数部分3项相乘而超出DSP乘法器范围；并且，传统方法采用标量迭代计算地址，不适用矢量DSP处理，本发明实施例采用并行迭代计算地址，充分利用矢量DSP并行计算资源，减少地址计算时间；另外，传统方法得到ZC序列地址后，直接查表得到全部ZC序列，DSP与外部存储器之间存在大量数据交互，不适用交互开销大的系统，本发明实施例采用查表得到部分ZC序列，通过部分ZC序列计算得到全部ZC序列，减少DSP与外部存储器之间数据交互，降低序列生成时间。
综上所述，本发明实施例将逐元素迭代生成地址的方法转化成按矢量迭代生成地址，充分利用了矢量DSP并行计算资源，同时利用部分ZC序列计算得到全部序列，减少DSP与外部存储器之间的交互。
本发明实施例所提供的ZC序列的生成方法，首先，确定出待生成ZC序列的初始地址矢量和初始地址增量矢量，然后，根据当前地址矢量、当前地址增量矢量和预设的地址增量步进，采用预设的矢量迭代算法，生成待生成ZC序列的当前矢量、下一个地址矢量和下一个地址增量矢量，这样，通过矢量中可以包括有多个数值，来并行地计算多个值，从而得到待生成ZC序列的当前矢量、下一个地址矢量和下一个地址增量矢量，其次，在当前迭代次数大于预设的迭代次数I时，根据已生成的待生成ZC序列的各个矢量的元素，得到待生成ZC序列，也就是说，在采用预设的矢量迭代算法 进行I次迭代运算之后，根据已生成的待生成ZC序列的各个矢量的元素便可以生成待生成ZC序列，另外，预设的迭代次数I的计算公式为：
Figure PCTCN2017081972-appb-000016
其中，N为待生成ZC序列的长度，P为预设值，且P大于1，可见，本发明实施例通过采用预设的矢量迭代算法，能够并行地生成待生成ZC序列元素，缩短了生成ZC序列的时间，提高了ZC序列的生成效率。
基于同一发明构思，本发明实施例还提供一种ZC序列的生成装置，图3为本发明实施例中ZC序列的生成装置的结构示意图，如图3所示，该ZC序列的生成装置包括：确定模块31、迭代模块32和生成模块33；
其中，确定模块31，配置为确定出待生成ZC序列的初始地址矢量和初始地址增量矢量；迭代模块32，配置为根据初始地址矢量、初始地址增量矢量和预设的地址增量步进，采用预设的矢量迭代算法，生成待生成ZC序列的当前矢量、下一个地址矢量和下一个地址增量矢量；生成模块33，配置为在当前迭代次数等于预设的迭代次数I时，根据已生成的待生成ZC序列的各个矢量的元素，得到待生成ZC序列。
其中，预设的迭代次数I的计算公式为：
Figure PCTCN2017081972-appb-000017
N为待生成ZC序列的长度，P为预设值，且P大于1。
为了通过预设的矢量迭代算法进行迭代计算获得待生成ZC序列，在一种可选的实施例中，上述迭代模块32，包括：第一确定子模块，配置为根据初始地址矢量、初始地址增量矢量和预设的地址增量步进，确定出待生成ZC序列的当前矢量；第二确定子模块，配置为在当前迭代次数小于预设的迭代次数时，根据当前地址矢量、当前地址增量矢量和预设的地址增量步进，确定出下一个地址矢量和下一个地址增量矢量；触发子模块，配置为更新当前迭代次数，并触发第一确定子模块，使得第一确定子模块根据 当前地址矢量、当前地址增量矢量和预设的地址增量步进，确定出待生成ZC序列的当前矢量。
在每一次的迭代计算中，都是根据当前地址矢量、当前地址增量矢量和预设的地址增量步进来确定待生成ZC序列的当前矢量，那么，在具体实施过程中，上述第一确定子模块，配置为当前迭代次数除以预设的迭代深度，得到余数；在余数等于0时，查表得到待生成ZC序列的当前矢量、当前增量矢量和当前步进；在余数不等于0时，根据待生成ZC序列的上一个矢量、上一个增量矢量和上一个步进，生成待生成ZC序列的当前矢量和当前增量矢量。
采用预设的矢量迭代算法中，在一种可选的实施例中，上述第二确定子模块，配置为在当前迭代次数小于预设的迭代次数时，根据当前地址矢量、当前地址增量矢量和待生成ZC序列的长度，采用求余函数，确定出下一个地址矢量；根据当前地址增量矢量、预设的地址增量步进和待生成ZC序列的长度，采用求余函数，确定出下一个地址增量矢量。
那么，为了根据预设的算法来计算出的待生成ZC序列的初始地址矢量和初始地址增量矢量，在一种可选的实施例中，上述确定模块31，配置为根据待生成ZC序列的根指数、待生成的ZC序列的长度N、预设值P、以及预设的P个编号，采用求余函数，分别确定出预设的各个编号对应的地址和预设的各个编号对应的地址增量；用预设的各个编号对应的地址形成初始地址矢量；用预设的各个编号对应的地址增量形成初始地址增量矢量。
为了得到待生成ZC序列，在一种可选的实施例中，当
Figure PCTCN2017081972-appb-000018
时，上述生成模块33，配置为：
按照待生成ZC序列的对称性，并根据已生成的待生成ZC序列的各个矢量的元素，生成待生成ZC序列。
可以理解为，所述迭代模块32，配置为基于所述初始地址矢量、初 始地址增量矢量和预设的地址增量步进查找第一映射表，获取所述第一个第一矢量、第一个增量矢量和矢量增量步进；所述第一映射表用于表征地址矢量与第一矢量、地址增量矢量与增量矢量、地址增量步进与矢量增量步进的映射关系；根据所述第一个第一矢量、所述第一个增量矢量和所述矢量增量步进确定第二个第一矢量，以此类推，直至确定第(I-1)个第一矢量。
根据所述初始地址矢量、所述初始地址增量矢量和所述预设的地址增量步进计算第二个地址矢量和第二个地址增量矢量，直至第I个地址矢量和第I个地址增量矢量；基于所述第I个地址矢量、所述第I个地址增量矢量查找所述第一映射表，获取所述第I个第一矢量。
所述生成模块33，配置为按照对称性策略，确定所述第I个第一矢量为第一个第二矢量；确定所述第I-1个第一矢量为第二个第二矢量，直至确定第1个第一矢量为第I个第二矢量，以生成所述ZC序列。
在实际应用中，确定模块31、迭代模块32、生成模块33、第一确定子模块、第二确定子模块和触发子模块均可由位于基站侧的矢量DSP的中央处理器(CPU，Central Processing Unit)、微处理器(MPU，Microprocessor Unit)、专用集成电路(ASIC，Application Specific Integrated Circuit)或现场可编程门阵列(FPGA，Field-Programmable Gate Array)等实现。
本实施例记载一种计算机可读介质，可以为ROM(例如，只读存储器、FLASH存储器、转移装置等)、磁存储介质(例如，磁带、磁盘驱动器等)、光学存储介质(例如，CD-ROM、DVD-ROM、纸卡、纸带等)以及其他熟知类型的程序存储器；计算机可读介质中存储有计算机可执行指令，当执行指令时，引起至少一个处理器执行包括以下的操作：
确定出待生成ZC序列的初始地址矢量和初始地址增量矢量；根据当前地址矢量、当前地址增量矢量和预设的地址增量步进，采用预设的矢量迭 代算法，生成待生成ZC序列的当前矢量、下一个地址矢量和下一个地址增量矢量；在当前迭代次数大于预设的迭代次数I时，根据已生成的待生成ZC序列的各个矢量的元素，得到待生成ZC序列；预设的迭代次数I的计算公式为：
Figure PCTCN2017081972-appb-000019
其中，N为待生成ZC序列的长度，P为预设值，且P大于1。
本发明实施例所提供的ZC序列的生成方法，首先，确定出待生成ZC序列的初始地址矢量和初始地址增量矢量，然后，根据当前地址矢量、当前地址增量矢量和预设的地址增量步进，采用预设的矢量迭代算法，生成待生成ZC序列的当前矢量、下一个地址矢量和下一个地址增量矢量，这样，通过矢量中可以包括有多个数值，来并行地计算多个值，从而得到待生成ZC序列的当前矢量、下一个地址矢量和下一个地址增量矢量，其次，在当前迭代次数大于预设的迭代次数I时，根据已生成的待生成ZC序列的各个矢量的元素，得到待生成ZC序列，也就是说，在采用预设的矢量迭代算法进行I次迭代运算之后，根据已生成的待生成ZC序列的各个矢量的元素便可以生成待生成ZC序列，另外，预设的迭代次数I的计算公式为：
Figure PCTCN2017081972-appb-000020
其中，N为待生成ZC序列的长度，P为预设值，且P大于1，可见，本发明实施例通过采用预设的矢量迭代算法，能够并行地生成待生成ZC序列元素，缩短了生成ZC序列的时间，提高了ZC序列的生成效率。
相应地，本发明实施例还提供一种计算机存储介质，该计算机存储介质中存储有计算机程序，该计算机程序用于执行本发明实施例的上述ZC序列的生成方法，包括：确定待生成ZC序列的初始地址矢量、初始地址增量矢量；所述ZC序列包括I个第一矢量和I个第二矢量，I为正 整数；
根据所述初始地址矢量、所述初始地址增量矢量和预设的地址增量步进，确定所述I个第一矢量；
基于所述第一矢量按照对称性策略确定所述第二矢量，以生成所述ZC序列。
这里需要指出的是：以上装置实施例项的描述，与上述方法描述是类似的，具有同方法实施例相同的有益效果，因此不做赘述。对于本发明装置实施例中未披露的技术细节，本领域的技术人员请参照本发明方法实施例的描述而理解，为节约篇幅，这里不再赘述。
这里需要指出的是：
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本发明的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本发明的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本发明实施例的实施过程构成任何限定。上述本发明实施例序号仅仅为了描述，不代表实施例的优劣。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
在本申请所提供的几个实施例中，应该理解到，所揭露的设备和方法， 可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性的、机械的或其它形式的。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元；既可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
另外，在本发明各实施例中的各功能单元可以全部集成在一个处理单元中，也可以是各单元分别单独作为一个单元，也可以两个或两个以上单元集成在一个单元中；上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤；而前述的存储介质包括：移动存储设备、只读存储器(Read Only Memory，ROM)、磁碟或者光盘等各种可以存储程序代码的介质。
或者，本发明上述集成的单元如果以软件功能模块的形式实现并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明实施例的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机、服务器、或者网络设备等)执行本发明各个实施例所述方法的全部或 部分。而前述的存储介质包括：移动存储设备、ROM、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。
工业实用性
本发明实施例中，确定待生成ZC序列的初始地址矢量、初始地址增量矢量；所述ZC序列包括I个第一矢量和I个第二矢量，I为正整数；根据所述初始地址矢量、所述初始地址增量矢量和预设的地址增量步进，确定所述I个第一矢量；基于所述第一矢量按照对称性策略确定所述第二矢量，以生成所述ZC序列。采用本发明实施例，能够缩短生成ZC序列的时间，提高ZC序列的生成效率。

Claims (22)

  1. 一种ZC序列的生成方法，包括：
    确定出待生成ZC序列的初始地址矢量和初始地址增量矢量；
    根据所述初始地址矢量、所述初始地址增量矢量和预设的地址增量步进，采用预设的矢量迭代算法，生成所述待生成ZC序列的当前矢量、下一个地址矢量和下一个地址增量矢量；
    在当前迭代次数等于预设的迭代次数I时，根据已生成的所述待生成ZC序列的各个矢量的元素，得到所述待生成ZC序列；
    其中，所述预设的迭代次数I为：
    Figure PCTCN2017081972-appb-100001
    N为所述待生成ZC序列的长度，P为预设值，且P大于1。
  2. 根据权利要求1所述的方法，其中，所述根据所述初始地址矢量、所述初始地址增量矢量和所述预设的地址增量步进，采用预设的矢量迭代算法，生成所述待生成ZC序列的当前矢量、下一个地址矢量和下一个地址增量矢量，包括：
    根据所述初始地址矢量、所述初始地址增量矢量和所述预设的地址增量步进，确定出所述待生成ZC序列的当前矢量、当前地址矢量和当前地址增量矢量；
    在所述当前迭代次数小于所述预设的迭代次数时，根据所述当前地址矢量、所述当前地址增量矢量和所述预设的地址增量步进，确定出下一个地址矢量和下一个地址增量矢量；
    更新所述当前迭代次数，并返回至所述根据所述当前地址矢量、所述当前地址增量矢量和所述预设的地址增量步进，确定出所述待生成ZC序列的当前矢量的步骤。
  3. 根据权利要求2所述的方法，其中，所述根据所述初始地址矢量、所述初始地址增量矢量和所述预设的地址增量步进，确定出所述待生成ZC序列的当前矢量，包括：
    所述当前迭代次数除以预设的迭代深度，得到余数；
    在所述余数等于0时，查表得到所述待生成ZC序列的当前矢量、当前增量矢量和当前步进；
    在所述余数不等于0时，根据所述待生成ZC序列的上一个矢量、上一个增量矢量和上一个步进，生成所述待生成ZC序列的当前矢量和当前增量矢量。
  4. 根据权利要求2所述的方法，其中，所述根据所述当前地址矢量、所述当前地址增量矢量和所述预设的地址增量步进，确定出下一个地址矢量和下一个地址增量矢量，包括：
    根据所述当前地址矢量、所述当前地址增量矢量和所述待生成ZC序列的长度，采用求余函数，确定出所述下一个地址矢量；
    根据所述当前地址增量矢量、所述预设的地址增量步进和所述待生成ZC序列的长度，采用求余函数，确定出所述下一个地址增量矢量。
  5. 根据权利要求1所述的方法，其中，所述确定出待生成ZC序列的初始地址矢量和初始地址增量矢量，包括：
    根据待生成ZC序列的根指数、所述待生成的ZC序列的长度N、所述预设值P、以及预设的P个编号，采用求余函数，分别确定出预设的各个编号对应的地址和所述预设的各个编号对应的地址增量；
    用所述预设的各个编号对应的地址形成所述初始地址矢量；
    用所述预设的各个编号对应的地址增量形成所述初始地址增量矢量。
  6. 根据权利要求1所述的方法，其中，所述预设的迭代次数I满足 如下条件：
    Figure PCTCN2017081972-appb-100002
    相应地，所述根据已生成的所述待生成ZC序列的各个矢量的元素，得到所述待生成ZC序列，包括：
    按照所述待生成ZC序列的对称性，并根据已生成的所述待生成ZC序列的各个矢量的元素，生成所述待生成ZC序列。
  7. 一种ZC序列的生成装置，包括：
    确定模块，配置为确定出待生成ZC序列的初始地址矢量和初始地址增量矢量；
    迭代模块，配置为根据所述初始地址矢量、所述初始地址增量矢量和预设的地址增量步进，采用预设的矢量迭代算法，生成所述待生成ZC序列的当前矢量、下一个地址矢量和下一个地址增量矢量；
    生成模块，配置为在当前迭代次数等于预设的迭代次数I时，根据已生成的所述待生成ZC序列的各个矢量的元素，得到所述待生成ZC序列；
    其中，所述预设的迭代次数I为：
    Figure PCTCN2017081972-appb-100003
    N为所述待生成ZC序列的长度，P为预设值，且P大于1。
  8. 根据权利要求7所述的装置，其中，所述迭代模块，包括：
    第一确定子模块，配置为根据所述初始地址矢量、所述初始地址增量矢量和所述预设的地址增量步进，确定出所述待生成ZC序列的当前矢量、当前地址矢量和当前地址增量矢量；
    第二确定子模块，配置为在所述当前迭代次数小于所述预设的迭代次数时，根据所述当前地址矢量、所述当前地址增量矢量和所述预设的地址增量步进，确定出下一个地址矢量和下一个地址增量矢量；
    触发子模块，配置为更新所述当前迭代次数，并触发所述第一确定 子模块，使得所述第一确定子模块根据所述当前地址矢量、所述当前地址增量矢量和所述预设的地址增量步进，确定出所述待生成ZC序列的当前矢量。
  9. 根据权利要求8所述的装置，其中，所述第一确定子模块，配置为所述当前迭代次数除以预设的迭代深度，得到余数；在所述余数等于0时，查表得到所述待生成ZC序列的当前矢量、当前增量矢量和当前步进；在所述余数不等于0时，根据所述待生成ZC序列的上一个矢量、上一个增量矢量和上一个步进，生成所述待生成ZC序列的当前矢量和当前增量矢量。
  10. 根据权利要求8所述的装置，其中，所述第二确定子模块，配置为在所述当前迭代次数大于等于所述预设的迭代次数时，根据所述当前地址矢量、所述当前地址增量矢量和所述待生成ZC序列的长度，采用求余函数，确定出所述下一个地址矢量；根据所述当前地址增量矢量、所述预设的地址增量步进和所述待生成ZC序列的长度，采用求余函数，确定出所述下一个地址增量矢量。
  11. 根据权利要求7所述的装置，其中，所述确定模块，配置为根据待生成ZC序列的根指数、所述待生成的ZC序列的长度N、所述预设值P、以及预设的P个编号，采用求余函数，分别确定出预设的各个编号对应的地址和所述预设的各个编号对应的地址增量；用所述预设的各个编号对应的地址形成所述初始地址矢量；用所述预设的各个编号对应的地址增量形成所述初始地址增量矢量。
  12. 根据权利要求7所述的装置，其中，所述预设的迭代次数I满足如下条件：
    Figure PCTCN2017081972-appb-100004
    相应地，所述生成模块，配置为按照所述待生成ZC序列的对称性， 并根据已生成的所述待生成ZC序列的各个矢量的元素，生成所述待生成ZC序列。
  13. 一种ZC序列的生成方法，包括：
    确定待生成ZC序列的初始地址矢量和初始地址增量矢量；所述ZC序列包括I个第一矢量和I个第二矢量，I为正整数；
    根据所述初始地址矢量、所述初始地址增量矢量和预设的地址增量步进，确定所述I个第一矢量；
    基于所述第一矢量按照对称性策略确定所述第二矢量，以生成所述ZC序列。
  14. 根据权利要求13所述的方法，其中，所述根据所述初始地址矢量、所述初始地址增量矢量和预设的地址增量步进，确定所述I个第一矢量，包括：
    基于所述初始地址矢量、初始地址增量矢量和预设的地址增量步进查找第一映射表，获取所述第一个第一矢量、第一个增量矢量和矢量增量步进；所述第一映射表用于表征地址矢量与第一矢量、地址增量矢量与增量矢量、地址增量步进与矢量增量步进的映射关系；
    根据所述第一个第一矢量、所述第一个增量矢量和所述矢量增量步进确定第二个第一矢量，以此类推，直至确定第(I-1)个第一矢量；
    根据所述初始地址矢量、所述初始地址增量矢量和所述预设的地址增量步进计算第二个地址矢量和第二个地址增量矢量，直至第I个地址矢量和第I个地址增量矢量；
    基于所述第I个地址矢量、所述第I个地址增量矢量查找所述第一映射表，获取所述第I个第一矢量。
  15. 根据权利要求14所述的方法，其中，所述根据所述第一个第一矢量、所述第一个增量矢量和所述矢量增量步进确定第二个第一矢量和 第二个增量矢量，包括：
    计算所述第一个第一矢量与所述第一个增量矢量之积，得到所述第二个第一矢量；
    计算所述第一个增量矢量与所述矢量增量步进之积，得到所述第二个增量矢量。
  16. 根据权利要求13所述的方法，其中，所述基于所述第一矢量按照对称性策略确定所述第二矢量，包括：
    按照对称性策略，确定所述第I个第一矢量为第一个第二矢量；
    确定所述第I-1个第一矢量为第二个第二矢量，直至确定第1个第一矢量为第I个第二矢量。
  17. 一种ZC序列的生成装置，包括：
    初始模块，配置为确定待生成ZC序列的初始地址矢量和初始地址增量矢量；所述ZC序列包括I个第一矢量和I个第二矢量，I为正整数；
    第一确定模块，配置为根据所述初始地址矢量、所述初始地址增量矢量和预设的地址增量步进，确定所述I个第一矢量；
    第二确定模块，配置为基于所述第一矢量按照对称性策略确定所述第二矢量，以生成所述ZC序列。
  18. 根据权利要求17所述的装置，其中，所述第一确定模块，配置为基于所述初始地址矢量、初始地址增量矢量和预设的地址增量步进查找第一映射表，获取所述第一个第一矢量、第一个增量矢量和矢量增量步进；所述第一映射表用于表征地址矢量与第一矢量、地址增量矢量与增量矢量、地址增量步进与矢量增量步进的映射关系；
    根据所述第一个第一矢量、所述第一个增量矢量和所述矢量增量步进确定第二个第一矢量，以此类推，直至确定第(I-1)个第一矢量；
    根据所述初始地址矢量、所述初始地址增量矢量和所述预设的地址 增量步进计算第二个地址矢量和第二个地址增量矢量，直至第I个地址矢量和第I个地址增量矢量；
    基于所述第I个地址矢量、所述第I个地址增量矢量查找所述第一映射表，获取所述第I个第一矢量。
  19. 根据权利要求18所述的装置，其中，所述第一确定模块，配置为计算所述第一个第一矢量与所述第一个增量矢量之积，得到所述第二个第一矢量；
    计算所述第一个增量矢量与所述矢量增量步进之积，得到所述第二个增量矢量。
  20. 根据权利要求17所述的装置，其中，所述第二确定模块，配置为按照对称性策略，确定所述第I个第一矢量为第一个第二矢量；
    确定所述第I-1个第一矢量为第二个第二矢量，直至确定第1个第一矢量为第I个第二矢量。
  21. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，该计算机可执行指令用于执行权利要求1至6任一项所述的ZC序列的生成方法。
  22. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，该计算机可执行指令用于执行权利要求13至16任一项所述的ZC序列的生成方法。
PCT/CN2017/081972 2016-11-18 2017-04-26 一种zc序列的生成方法、装置及存储介质 Ceased WO2018090564A1 (zh)

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