WO2018076144A1

WO2018076144A1 - Coding and modulation method and coding and modulation device for physical layer protocol data unit

Info

Publication number: WO2018076144A1
Application number: PCT/CN2016/103109
Authority: WO
Inventors: 李德建; 刘劲楠; 张立基; 辛岩; 孙晟
Original assignee: 华为技术有限公司
Priority date: 2016-10-24
Filing date: 2016-10-24
Publication date: 2018-05-03

Abstract

Disclosed is a coding and modulation method for a physical layer protocol data unit, characterized in that the physical layer protocol data unit comprises an enhanced directional multi-gigabit header (EDMG Header) A field. The method comprises: coding and modulating an EDMG Header A field, the coded and modulated EDMG Header A field having M single carrier blocks where M is the sum of 2 and X, and X is a positive integer that is not equal to zero. It can be seen that implementing the embodiments of the present invention is beneficial for reducing the waste of time-frequency resources by an EDMG STF.

Description

Coded modulation method and code modulation device of physical layer protocol data unit

Technical field

The present invention relates to the field of communications technologies, and in particular, to a code modulation method and device for a physical layer protocol data unit.

Background technique

With the development of technologies such as ultra-high definition video, virtual reality and augmented reality, in order to improve the communication rate, the 802.11ay standard draft based on the IEEE 802.11ad standard proposes channel bonding and multiple input and multiple output ( MIMO) technology to increase the channel bandwidth and increase the spatial stream, respectively, to increase the communication rate to more than 20 gigabits per second. Channel connection technology or MIMO technology can increase the communication rate, but at the same time, the physical layer protocol data unit (PPDU) needs to be redesigned.

The format of the PPDU (ie EDMG PPDU) in the 802.11ay draft standard is shown in Figure 1. An EDMG PPDU includes the following fields in sequence: Legacy Short Training Field (L-STF), Legacy Channel Estimation Field (L-CEF), Legacy Header (L-Header) Field, Enhanced Directional Multi-Gigabit Header A (EDMG Header A) field, Enhanced Directional Multi-Gigabit Short Training Sequence Field (EDMG STF), Enhanced Directional Multi-Gigabit Channel Estimation Field (EDMG CEF) ), an enhanced directional MG header B (EDMG Header B) field, a data (Data) field, an Automatic Gain Control (AGC) field, and a Training (TRN) field. The EDMG Header B field, the AGC field, and the TRN field are optional.

In the existing practical application, starting from the time of receiving the first single carrier block or the second single carrier block of the L-Header, to using the EDMG-STF field according to the bandwidth information decoded from the L-Header After adjusting the AGC, approximately 6.5-7.5 Single Carrier Blocks (SC-BLK) are required. The length of a single carrier block (SC-BLK) is the duration of 512 chips in a single channel, and the length of time does not change with the number of channels (bandwidth). An SC-BLK can also be simply referred to as BLK or a symbol.

Since accurate AGC settings must be used due to changes in channel bandwidth (BW) before the start of EDMG-CEF, the total duration of EDMG Header A and EDMG STF is limited to 6.5-7.5 single-carrier blocks ( SC-BLK) length of time.

However, it has been found in practice that the duration of the EDMG Header A is designed to be 2 BLK durations, while the duration of the EDMG STF is 4.5 or 5.5 BLK durations, ie the duration of 18 or 22 repeated Ga sequences. Where Ga represents a subsequence in the Golay code. For the general design and production status of 60 GHz products, it takes only 4-8 Ga sequences to complete the re-adjustment and setting of AGC, even if EDMG STF is used for further time-frequency synchronization, phase tracking, and receiver bandwidth switching time. The time margin required for such factors, the effective length of the EDMG STF generally requires only 10 or 14 Ga sequences. The Ga sequence may be replaced by another sequence in the Golay code, such as a Gb sequence, or the Ga sequence may be replaced by a frequency based on Orthogonal Frequency-Division Multiplexing (OFDM) modulation. A certain sequence of domains. These redundant sequences of the EDMG STF are only used to wait for the demodulation and decoding results of the L-Header, resulting in waste of time-frequency resources.

Summary of the invention

The embodiment of the invention discloses a coding and modulation method and a code modulation device of a physical layer protocol data unit, which is beneficial to avoid waste of time-frequency resources by the EDMG STF.

In a first aspect, a code modulation method for a physical layer protocol data unit is provided, the physical layer protocol data unit comprising an enhanced directional multi-gigabit header EDMG Header A field, the method comprising: encoding a modulation device to encode an EDMG Header A field And modulation, the EDMG Header A field is encoded and modulated with M single carrier blocks, the M being the sum of 2 and X, which is a positive integer not equal to zero.

By implementing the first aspect, the EDMG Header A field can be encoded and modulated to a length greater than two single carrier blocks, such that the duration of the modulated EDMG STF can be less than the existing 4.5 or 5.5 single carrier blocks. The EDMG Header A field can increase the length of the modulated EDMG Header A field by carrying more useful information (ie, grow from two single carrier blocks to more than two single carrier blocks), or can increase modulation by repeating coding. The length of the EDMG Header A field, so that all single carrier blocks obtained after modulation carry at least two letters of the EDMG Header A field. The information improves the reliability of information transmission in the EDMG Header A field. Therefore, by implementing the first aspect, the EDMG Header A field can be carried with more useful information, or the reliability of information transmission of the EDMG Header A field can be improved, and the redundant portion of the EDMG STF can also be reduced, thereby avoiding Waste of time-frequency resources.

As an optional implementation manner, the physical layer protocol data unit further includes an enhanced directional multi-gigabit short training sequence field EDMG STF. The EDMG Header A field is located before the EDMG STF, and the code modulation device may also modulate the EDMG STF. The EDMG STF modulation has Y single carrier blocks or Z OFDM symbols, the sum of X and Y is greater than or equal to 4.5 single carrier blocks, or the total duration of X single carrier blocks and Z OFDM symbols is greater than or equal to 4.5 The duration of a single carrier block.

In the existing practical application, the EDMG STF has at least 4.5 or 5.5 single carrier blocks after being modulated, but by implementing the embodiment, the EDMG STF may have a single carrier block of less than 4.5 or 5.5 after being modulated by the code modulation device. It can be seen that by implementing this embodiment it is possible to reduce the redundant portion of the EDMG STF.

In the existing practical application, the EDMG STF has at least 4.5 or 5.5 OFDM symbols after being modulated. However, by implementing the embodiment, the EDMG STF may have an OFDM symbol of less than 4.5 or 5.5 after being modulated by the coded modulation device. Implementing this embodiment can reduce redundant portions of the EDMG STF.

As an optional implementation manner, X is equal to 1, and the EDMG Header A field includes 128 information bits. The specific implementation manner of encoding the EDMG Header A field by the code modulation device may be: the code modulation device passes the 1/2 code rate. The low density parity check code LDPC encodes the EDMG Header A field.

By implementing this embodiment, the EDMG Header A field is encoded by the 1/2 code rate low density parity check code LDPC, and 128 information bits of the EDMG Header A1 can be carried over a single carrier block. The EDMG Header A field is encoded by the low-density parity check code LDPC of 1/2 code rate three times, and then the encoded EDMG Header A field is mapped and modulated, and three pieces of information bits respectively carrying 128 information bits are obtained. Single carrier block. Therefore, by implementing this embodiment, the EDMG Header A field can be encoded by the same coding method, thereby obtaining three single carrier blocks. By encoding the EDMG Header A field by the same coding method, the decoding complexity of the receiver for the entire EDMG Header A can be reduced.

As an optional implementation manner, the EDMG Header A field includes an EDMG Header A1 and an EDMG Header A2 field, and the EDMG Header A1 field includes 128 information bits or 64 information bits, and the code modulation device encodes and modulates the EDMG Header A field. The specific implementation manner may be: the code modulation device encodes and modulates the EDMG Header A1 field and the EDMG Header A2 field, and the EDMG Header A1 field is encoded and modulated to have two single carrier blocks, and the EDMG Header A2 field is encoded and modulated. There are X single carrier blocks.

By implementing the implementation manner, the EDMG Header A field is modulated to obtain at least three single carrier blocks, which is convenient for the EDMG Header A field to carry more useful information or improve the reliability of information transmission of the EDMG Header A field. It can also reduce the redundant part of the EDMG STF, thus avoiding the waste of time-frequency resources.

As an optional implementation manner, X is equal to 2, the EDMG Header A1 field includes 128 information bits, and the EDMG Header A2 field includes 128 information bits, and the code modulation device encodes and modulates the EDMG Header A1 field and the EDMG Header A2 field. The specific implementation manner may be that the code modulation device performs coding by using the same coding mode and the same modulation mode for the EDMG Header A1 field and the EDMG Header A2 field.

In this embodiment, the 128 information bits included in the EDMG Header A1 field may be the same as or may be different from the 128 information bits included in the EDMG Header A2 field.

When the EDMG Header A1 field includes 128 information bits and the 128 information bits included in the EDMG Header A2 field, that is, the EDMG Header A only includes 128 information bits, and the EDMG Header A1 field and the EDMG Header A2 field share the same. 128 information bits.

By encoding the EDMG Header A1 field and the EDMG Header A2 field in the same coding mode and modulating the same modulation mode, the receiver can obtain higher demodulation and decoding performance for the EDMG Header A, and can be reduced. The decoding complexity of the small receiver for the entire EDMG Header A.

As an optional implementation manner, X is equal to 2, the EDMG Header A1 field includes 64 information bits, and the EDMG Header A2 field includes 64 information bits different from the EDMG Header A1 field, and the code modulation device pairs the EDMG Header A1 field and The specific implementation manner of encoding and modulating the EDMG Header A2 field may be: the code modulation device encodes and modulates the EDMG Header A1 field by the same coding mode as the traditional header L-Header field and the same modulation mode; the code modulation device passes The same encoding and phase as the traditional header L-Header field The same modulation scheme encodes and modulates the EDMG Header A2 field.

The encoding and modulation of the EDMG Header A1 field and the EDMG Header A2 field by the same encoding method and the same modulation method as the L-Header field can increase the transmission reliability of the EDMG Header A1 field and the EDMG Header A2 field, and can be reduced. The decoding complexity of the receiver for the entire EDMG Header A.

As an optional implementation manner, X is equal to 2, the EDMG Header A1 field includes 128 information bits, and the EDMG Header A2 field includes 64 information bits. The specific implementation manner in which the code modulation device encodes and modulates the EDMG Header A2 field may be Therefore, the coded modulation device modulates the EDMG Header A2 field by the same coding mode as the conventional header L-Header field and the same modulation mode.

By implementing the embodiment, the code modulation device performs coding on the EDMG Header A2 field by the same coding mode as the traditional header L-Header field and modulates the same modulation mode, which is advantageous for reducing the decoding of the entire EDMG Header A by the receiver. Complexity and improved reliability of EDMG Header A2 transmission.

As an optional implementation manner, X is equal to 1, the EDMG Header A1 field includes 128 information bits, and the EDMG Header A2 field includes 64 information bits. The code modulation device encodes and modulates the EDMG Header A1 field and the EDMG Header A2 field. The specific implementation manner may be that the code modulation device modulates the EDMG Header A1 field and the EDMG Header A2 field by the same coding mode and the same modulation mode.

By coding the EDMG Header A1 field and the EDMG Header A2 field by the same coding mode and the same modulation mode, it is advantageous to reduce the decoding complexity of the receiver for the entire EDMG Header A.

As an optional implementation manner, X is equal to 1, the EDMG Header A1 field includes 128 information bits, and the EDMG Header A2 field includes 128 information bits, and the code modulation device modulates the EDMG Header A1 field and the EDMG Header A2 field. Embodiments may be: the code modulation device modulates the EDMG Header A1 field by a binary phase shift keying BPSK or BPSK deformation; the code modulation device performs QPSK or QPSK deformation by quadrature phase shift keying (eg, π/2-QPSK) Modulate the EDMG Header A2 field. Modulation of EDMG Header A2 using QPSK yields only one single carrier block carrying 128 information bits of EDMG Header A1.

As an optional implementation, X is equal to 1, and the EDMG Header A1 field includes 128 Information bits, the EDMG Header A2 field includes 128 information bits. After the code modulation device encodes the EDMG Header A1 field, the coded modulation device can also modulate the EDMG Header A1 field by the first mapping method. The A1 field is mapped; accordingly, after the code modulation device encodes the EDMG Header A2 field, before the code modulation device modulates the EDMG Header A2 field, the encoded EDMG Header A2 field may also be mapped by the second mapping method. Obtaining X single carrier blocks, where the first mapping manner is different from the second mapping manner.

By implementing the implementation manner, the 128 information bits of the EDMG Header A2 field can be modulated into a single carrier block, and the EDMG Header A2 field is ensured to have the same encoding mode and the same modulation mode as the EDMG Header A1, which is advantageous for reducing reception. The decoding complexity of the entire EDMG Header A.

As an optional implementation manner, the information bits of the EDMG Header A1 include a payload bit and a cyclic redundancy check CRC bit, and the information bits of the EDMG Header A2 include a payload bit and a cyclic redundancy check CRC bit.

In this embodiment, when the EDMG Header A2 field and the EDMG Header A1 field respectively include a CRC, the preceding field can be used to carry higher priority, high urgency, and high demodulation and decoding delay requirements. Physical layer signaling. Assume that the EDMG Header A1 field and the EDMG Header A2 are EDMG Header AX in time, and the EDMG Header AY in time. The urgent information is included in the previous EDMG Header AX, and will not Urgent information is included in the back EDMG Header AY. The urgent information includes the transmission format information of the data field in the PPDU, and includes at least one of the following information: Aggregation mode, bandwidth, guard interval/recurrence prefix length (GI/CP Length), and beamforming ( Beamformed), Short/Long LDPC, Enhanced Directional Multi-Gigabit Modulation and Coding Strategy (EDMG-MCS), Physical Layer Service Data Unit Length (PSDU Length), Number of Spatial Streams (Number of SS), Space-time block coding (STBC Applied), primary channel number (Primary Channel Number), and open-loop precoding are applied. The non-emergency information includes information about the AGC and TRN fields in the PPDU: for example, training length, packet type, enhanced directed multi-gigabit training length, and partial information in the L-Header, such as the last received signal strength indicator RSSI. Since the EDMG Header AX uses an independent CRC for verification, these time-critical requests are made. It can be independently demodulated and decoded before the EDMG Header AY, which reduces the demodulation and decoding delay of these urgent physical layer signaling.

As an alternative embodiment, the EDMG Header A field includes only one cyclic redundancy check CRC bit.

As an optional implementation manner, the symbol of any single carrier block after EDMG Header A modulation is multiplied by r before inserting the guard interval GI, and r is equal to e ^jθ , which belongs to a closed interval [0, 2π Any value of ].

In a second aspect, there is provided a coded modulation device having the function of implementing the behavior of the coded modulation device in a possible implementation of the first aspect or the first aspect described above. This function can be implemented in hardware or in hardware by executing the corresponding software. The hardware or software includes one or more units corresponding to the functions described above. The unit can be software and/or hardware. Based on the same inventive concept, due to the principle and the beneficial effects of the code modulation device to solve the problem, reference may be made to the foregoing first aspect and the possible method embodiments of the first aspect and the beneficial effects thereof, so that the implementation of the code modulation device may Referring to the first aspect and the possible method implementation manners of the first aspect, the repeated description is not repeated.

In a third aspect, there is provided a code modulation device comprising a processor, a memory, a bus system and one or more programs, the processor and the memory being connected by a bus system, wherein one or more programs are stored in In the memory, the one or more programs include instructions that, when executed by the code modulation device, cause the coded modulation device to perform the various possible method embodiments of the first aspect and the first aspect described above. For the implementation and benefit of the above-mentioned first aspect and the first possible method of the first aspect, the implementation of the code modulation device can be referred to the implementation of the method, and the method is repeated. I won't go into details here.

In a fourth aspect, a computer readable storage medium storing one or more programs, the one or more programs comprising instructions for causing the coded modulation device to perform the method of the first aspect or first when executed by the coded modulation device Possible implementation of the aspect.

In a fifth aspect, a method for demodulating and decoding a physical layer protocol data unit is provided. The method may include: demodulating and decoding the device to demodulate and decode an EDMG Header A field of a physical layer protocol data unit, the EDMG The Header A field has M single-carrier blocks before demodulation and decoding, and M is the sum of 2 and X, which is a positive integer not equal to zero. That is to say, the demodulation and decoding device can be first In the aspect, the single carrier block of the EDMG Header A field generated by the coding modulation device is demodulated and decoded.

By implementing the demodulation and decoding method of the physical layer protocol data unit provided by the fifth aspect, the demodulation and decoding apparatus can demodulate and decode the EDMG Header A field having M single carrier blocks, and therefore, the code modulation device can The EDMG Header A field is encoded and modulated to a length greater than two single carrier blocks, such that the length of the modulated EDMG STF can be less than the existing 4.5 or 5.5 single carrier blocks. The EDMG Header A field can increase the length of the modulated EDMG Header A field by carrying more useful information (ie, grow from two single carrier blocks to more than two single carrier blocks), or can increase modulation by repeating coding. The length of the EDMG Header A field is such that all the single carrier blocks obtained after the modulation carry at least two pieces of information of the EDMG Header A field, which improves the reliability of information transmission in the EDMG Header A field.

Therefore, by implementing the demodulation and decoding method of the physical layer protocol data unit provided by the embodiment of the present invention, the code modulation device can encode and modulate the EDMG Header A field to a length greater than two single carrier blocks, so that EDMG can be obtained. The Header A field carries more useful information, or can improve the reliability of information transmission of the EDMG Header A field, and can also reduce the redundant part of the EDMG STF, thereby avoiding waste of time-frequency resources.

As an optional implementation manner, the physical layer protocol data unit further includes an EDMG STF, where the EDMG Header A field is located before the EDMG STF, and the demodulation and decoding device can also demodulate the EDMG STF. The EDMG STF has Y single-carrier blocks before demodulation, and the sum of X and Y is greater than or equal to 4.5 single-carrier blocks, or the EDMG STF has Z OFDM symbols before demodulation, and the total duration of the Z OFDM symbols is greater than Or equal to the duration of 4.5 single carrier blocks. That is to say, the demodulation decoding apparatus can demodulate and decode the single carrier block of the EDMG STF generated by the coding and modulation apparatus in the first aspect.

In existing practical applications, the EDMG STF has at least 4.5 or 5.5 single carrier blocks after modulation, however by implementing this embodiment, the demodulation decoding device can have single carrier blocks with Y (Y less than 4.5 or 5.5). The EDMG STF demodulation, and in turn the coded modulation device, modulates the EDMG STF to the length of the Y single carrier blocks. It can be seen that by implementing this embodiment, it is advantageous to reduce the redundant portion of the EDMG STF.

In existing practical applications, the EDMG STF has at least 4.5 or 5.5 after modulation. OFDM symbol, however, by implementing this embodiment, the demodulation decoding apparatus can demodulate the EDMG STF having Z (Z less than 4.5 or 5.5) single carrier blocks, and the code modulation device can then modulate the EDMG STF into an OFDM symbol. Length, it can be seen that by implementing this embodiment, it is advantageous to reduce the redundant portion of the EDMG STF.

In a sixth aspect, there is provided a demodulation decoding apparatus having a function of implementing the behavior of a demodulation decoding device in a possible implementation manner of the fifth aspect or the fifth aspect. This function can be implemented in hardware or in hardware by executing the corresponding software. The hardware or software includes one or more units corresponding to the functions described above. The unit can be software and/or hardware. Based on the same inventive concept, due to the principle and beneficial effects of the demodulation and decoding device to solve the problem, reference may be made to the possible method embodiments of the fifth and fifth aspects, and the beneficial effects, and thus the demodulation and decoding. For the implementation of the device, reference may be made to the possible method implementation manners of the fifth aspect and the fifth aspect, and the repeated description is not repeated.

In a seventh aspect, a demodulation decoding apparatus is provided, the demodulation decoding apparatus comprising a processor, a memory, a bus system, and one or more programs, wherein the processor and the memory are connected by a bus system, wherein one or more The program is stored in a memory, and the one or more programs include instructions that, when executed by the demodulation decoding device, cause the demodulation decoding device to perform the various possible method embodiments of the fifth and fifth aspects described above. For the implementation and the beneficial effects of the demodulation and decoding device to solve the problem, reference may be made to the implementation manners and the beneficial effects of the foregoing possible methods of the fifth and fifth aspects, and therefore, the implementation of the demodulation and decoding device can be referred to the method. Implementation, repetition will not be repeated.

In an eighth aspect, a computer readable storage medium storing one or more programs, the one or more programs comprising instructions for causing a demodulation decoding device to perform the fifth aspect when executed by a demodulation decoding device A possible implementation of the method or the fifth aspect.

DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings to be used in the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without paying any creative work.

FIG. 1 is a schematic diagram of a format of a PPDU in an 802.11ay standard draft according to an embodiment of the present invention; Figure

2 is a schematic diagram of a coding and modulation process of a conventional L-Header according to an embodiment of the present invention;

3 is a schematic diagram of a coding and modulation process of a conventional EDMG Header A according to an embodiment of the present invention;

4 is a schematic diagram of a format of a conventional EDMG STF according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a possible system architecture provided by an embodiment of the present invention; FIG.

FIG. 6 is a schematic diagram of a format of a PPDU according to an embodiment of the present disclosure;

7 to FIG. 15 are schematic diagrams showing a code modulation process of an EDMG Header A according to an embodiment of the present invention;

16 is a schematic structural diagram of a code modulation device according to an embodiment of the present invention;

FIG. 17 is a schematic structural diagram of a demodulation and decoding device according to an embodiment of the present invention.

detailed description

The technical solutions of the embodiments of the present invention will be described below in conjunction with the accompanying drawings.

In order to facilitate the understanding of the embodiments of the present invention, the related technical background related to the implementation of the present invention is further described below:

Please refer to FIG. 2. FIG. 2 is a coded modulation process of a conventional L-Header. As shown in FIG. 2, the existing L-Header has 48 Payload bits. The 48 payload bits of the L-Header are scrambled to obtain the scrambled 48 payload bits. The scrambled 48 payload bits plus 16 cyclic redundancy check CRC bits (i.e., CRC check sequences) form the entire information bits of the L-Header. As shown in FIG. 2, after all the information bits of the L-Header are obtained, all information bits of the L-Header are encoded, mapped, and modulated, and finally, Symbol Blocking and Guard Interval (GI) are performed. insert. For simplicity of representation, the present invention also refers to coding, mapping, modulation, symbol blocking, and guard interval insertion, etc., as a coded modulation strategy. It is worth mentioning that, as can be seen from Fig. 2, the low density parity check code LDPC can be used for encoding, and the binary phase shift keying BPSK is used for modulation. It can be seen from FIG. 2 that the 64 information bits of the L-Header are repeatedly coded, and finally two single-carrier blocks are generated, that is, one 64 bits of information bits for the L-Header are entered. Line coding, mapping and modulation, the single carrier block generated after modulation corresponds to Part A, and the other 64 bits of L-Header are encoded, mapped and modulated, and the single carrier block generated after modulation corresponds to Part B. Part A and Part B carry the same information bits. Repeat coding will achieve a 3dB coding gain, making the L-Header transmission more robust (ie, improving transmission reliability).

Please refer to FIG. 3. FIG. 3 is a code modulation process of the existing EDMG Header A. As shown in Figure 3, the existing EDMG Header A has 112 payload bits. The 112 payload bits are scrambled to obtain the scrambled 112 payload bits. The scrambled 112 payload bits plus 16 cyclic redundancy check CRC bits form the entire information bits of the EDMG Header A. As shown in FIG. 3, after all the information bits of the EDMG Header A are obtained, all the information bits of the EDMG Header A are encoded, mapped and modulated, and finally the symbol block and GI insertion are performed. It is worth mentioning that, as can be seen from Fig. 3, the low density parity check code LDPC can be used for encoding, and the binary phase shift keying BPSK is used for modulation. When coding and modulating the EDMG Header A, the 128 information bits of the EDMG Header A are split into two 64-bit parts, and the same coding, mapping, and modulation methods are respectively applied to the two 64-bit parts, and coding is performed. Mapping, modulation, symbol block and guard interval insertion, and finally two different single carrier blocks are obtained, that is, one single carrier block corresponds to Part A in FIG. 3, and the other single carrier block corresponds to Part B in FIG. It can be seen that the existing code modulation process for EDMG Header A does not repeatedly encode EDMG Header A. Therefore, the existing EDMG Header A has low transmission reliability.

In the existing practical application, as shown in FIG. 1, starting from the reception completion time of the L-Header (the first single carrier block or the second single carrier block of the L-Header), to the basis from the L-Header The decoded bandwidth information is re-adjusted by the EDMG-STF field, and approximately 6.5-7.5 single carrier blocks are required. This is determined by the receiver's pipeline structure design, which includes all physical layer processing delays: for example, Fast Fourier Transform (FFT), Equalization, and Inverse Fast Fu. Inverse FFT (IFFT), demapping and LDPC decoding; delays caused by other aspects may also include: copy/move, cache, schedule, and so on.

Since the accurate AGC setting must be adopted due to the change of the channel bandwidth (BW) before receiving the EDMG-CEF, a total of 6.5- is required from the time when the single carrier block of the L-Header is received to the start of receiving the EDMG-CEF. 7.5 single-carrier block lengths, so EDMG Header The total duration of A and EDMG STF is limited to the length of time from 6.5 to 7.5 single carrier blocks. The length of the EDMG Header A is the length of two single-carrier blocks. Therefore, it can be concluded that the length of time reserved for the EDMG STF is 4.5 or 5.5 single-carrier block lengths, that is, the length of 18 or 22 Ga sequences. Wherein, Ga represents a subsequence in the Golay code, and the length of one Ga sequence is 128×BW, and BW represents the number of channels occupied by the Ga sequence, that is, BW=1, 2, 3, . When BW is 1, it can be expressed as Ga128, when BW is 2, it can be expressed as Ga256, when BW is 3, it can be expressed as Ga384, and so on.

As shown in FIG. 4, the existing EDMG STF format includes a total of N+1 Ga sequences, specifically including N repeated Ga sequences, followed by an inverted Ga sequence (ie, the -Ga sequence in FIG. 4). . In order to simplify the design of the receiver and facilitate the frequency domain processing based on the single carrier block, the total length of the EDMG-STF and the EDMG-CEF is required to be an integer multiple of the single carrier block, and since the length of the EDMG-CEF is determined to be 2.25 single carrier blocks, Therefore, the length of EDMG-STF should be taken as (Z + 0.75) single carrier blocks, where Z is a positive integer. Thus, the value range of N is 6, 10, 14, 18, 22, 26, 30, .... In the existing practical application, as described above, the duration of the EDMG STF is 4.5 or 5.5 single carrier block lengths, that is, N=18 or 22. Although the EDMG STF actually contains a total of N+1 Ga, the prior art generally uses N to indicate the length of the EDMG STF for simplicity of representation. It is worth mentioning that the above Ga can also be replaced by other forms of sequences in the Golay code, such as Gb sequences, or with a certain sequence of frequency domains of OFDM modulation.

However, in the existing practical applications, the EDMG STF only needs 4-8 Ga sequences in length to complete the re-adjustment and set the AGC, even if the EDMG STF is used for further time-frequency synchronization, phase tracking, and receiver bandwidth switching. The time margin required for factors such as time, the effective length of EDMG STF generally only requires 10-14 Ga sequences. Therefore, the existing EDMG STF field is designed to be too long, and the redundant EDMG STF is only used to wait for demodulation and decoding of the L-Header, resulting in waste of time and bandwidth resources.

In order to solve the problem that the EDMG STF wastes time-frequency resources in the prior art, the embodiment of the present invention provides a coding and modulation method and a code modulation device of a physical layer protocol data unit, which is beneficial to avoid waste of time-frequency resources by the EDMG STF. Wherein, the method and the coded modulation are based on the same inventive concept. Since the principles of the method and the coded modulation solve the problem are similar, the implementation of the coded modulation and the method can be referred to each other, and the repetition will not be repeated.

The service scenario and system architecture that may be applied to the embodiments of the present invention are described below with reference to FIG.

Referring to FIG. 5, FIG. 5 is a system architecture that may be applied in an embodiment of the present invention. The system architecture is a communication system with an analog beamforming training process in the millimeter wave band. The system architecture may include a station (STA) and an access point (AP) or a personal basic service set control point (PCP) network element. It is worth mentioning that, in practical applications, the number of STAs may be greater than three, or less than three, and the number of APs or PCPs may be greater than one, which is not limited in the embodiment of the present invention. For ease of explanation, a schematic diagram of a system architecture illustrated in FIG. 5 is exemplified, and no limitation is imposed on this. The code modulation device according to the present invention is a wireless communication transceiver device, and may be, for example, the STA in FIG.

The specific flow of the coding and modulation method of the physical layer protocol data unit disclosed in the embodiment of the present invention is further described below.

The code layer modulation method of the physical layer protocol data unit (PPDU) disclosed in the embodiment of the present invention includes a part 601.

In Section 601, the coded modulation device encodes and modulates the EDMG Header A field of the PPDU. The PPDU may include a field as shown in FIG. 6. As shown in FIG. 6, the EDMG Header A field is a field between the L-Header and the EDMG-STF.

As shown in FIG. 6, the EDMG Header A field is encoded and modulated by the coded modulation device and has M single carrier blocks, which is the sum of 2 and X. The X is a positive integer not equal to zero, for example, the X may be 1, 2 or 3, and the like. That is to say, the EDMG Header A field has at least 3 single carrier blocks after being encoded and modulated by the coded modulation device.

It is worth mentioning that, in the process of encoding and modulating the EDMG Header A field by the code modulation device, after the code modulation device encodes the EDMG Header A field, the coded EDMG Header A field needs to be mapped, and the code modulation device is encoded. Then, the mapped EDMG Header A field is modulated, and finally, the modulated EDMG Header A field is subjected to symbol block and guard interval GI insertion.

In the existing practical application, the total length of the modulated EDMG Header A field and the EDMG STF is required to be not less than 6.5 or 7.5 single carrier blocks, and the length of the existing modulated EDMG Header A field is 2 single carriers. Block, therefore, the modulated EDMG STF has a duration of at least 4.5 or 5.5 Single carrier block. As shown in FIG. 6, after implementing the embodiment of the present invention, when the length of the modulated EDMG Header A field is greater than the length of two single carrier blocks, the duration of the modulated EDMG STF may be less than the existing 4.5 or 5.5. Single carrier block. In addition, the EDMG Header A field can increase the length of the modulated EDMG Header A field by carrying more useful information (ie, grow from two single carrier blocks to more than two single carrier blocks), or can be repeated by coding. The length of the modulated EDMG Header A field is increased, so that all the single carrier blocks obtained after the modulation carry at least two pieces of information of the EDMG Header A field, which improves the reliability of information transmission in the EDMG Header A field. Therefore, by implementing the code modulation method of the physical layer protocol data unit provided by the embodiment of the present invention, by increasing the length of the modulated EDMG Header A field, the EDMG Header A field can carry more useful information, or the EDMG Header can be improved. The reliability of information transmission in the A field can also reduce the redundant portion of the EDMG STF, thereby avoiding waste of time-frequency resources.

As an alternative embodiment, the coded modulation device can modulate the EDMG STF in addition to the 601 portion.

Optionally, the EDMG STF is modulated by the coded modulation device and has Y single carrier blocks, and the sum of X and Y is greater than or equal to 4.5 single carrier blocks. For example, the sum of X and Y can be equal to 4.5 or 5.5 single carrier blocks.

In the existing practical application, the EDMG STF has at least 4.5 or 5.5 single carrier blocks after being modulated, but by implementing the embodiment, the EDMG STF may have a single carrier block of less than 4.5 or 5.5 after being modulated by the code modulation device. It can be seen that this embodiment can reduce the redundant portion of the EDMG STF.

Optionally, the EDMG STF is modulated by the coded modulation device and has Z OFDM symbols, and the total duration of the X single carrier blocks and the Z OFDM symbols is greater than or equal to the duration of 4.5 single carrier blocks. For example, the total duration of the X single carrier blocks and the Z OFDM symbols is equal to the duration of 4.5 or 5.5 single carrier blocks.

In an existing practical application, the EDMG STF has at least 4.5 or 5.5 OFDM symbols after being modulated. However, by implementing the embodiment, the EDMG STF may have an OFDM symbol of less than 4.5 or 5.5 after being modulated by the coded modulation device. Embodiments can reduce redundant portions of the EDMG STF.

As an optional implementation manner, when X is equal to 1, and the EDMG Header A field includes 128 information bits, in 601, the code modulation device encodes the EDMG Header A field of the PPDU. A specific implementation may be part 601a.

In section 601a, the code modulation device encodes the EDMG Header A field by a 1/2 code rate low density parity check code LDPC.

As shown in FIG. 7, the code modulation device encodes the EDMG Header A field with a low-density parity check code LDPC of 1/2 code rate for the EDMG Header A field, performs mapping after the encoding is completed, performs modulation after the mapping ends, and then performs modulation. The modulated EDMG Header A field performs symbol block and guard interval GI insertion. The above steps are performed 3 times, and finally 3 single carrier blocks are obtained.

Optionally, it is assumed that the sequence after the EDMG Header A2 scrambling code is represented as d _s =(q ₁ , q ₂ , . . . , q _LH ), where LH=128, and d _{s is} cascaded by 504-LH 0s. After the corresponding 1/2 code rate LDPC encoding in the 802.11 standard, the output LDPC codeword is c=(q ₁ , q ₂ ,..., q _LH , 0 ₁ , 0 ₂ ,..., 0 _{336 -LH} , p ₁ , p ₂ ,..., p ₃₃₆ ), where p ₁ , p ₂ , . . . , p ₃₃₆ are parity bits generated according to Hc=0, where H is 1/2 code Rate the parity check matrix corresponding to LDPC. The mapping process of Part A and Part C may be: deleting the LH+1 to 336th, and the 657th to the 672th bits in the LDPC codeword c to generate a sequence cs1=(q ₁ , q ₂ ,. .., q _LH , p ₁ , p ₂ , . . . , p ₃₂₀ ); The mapping process of Part B may be: deleting the LH+1 to the 336th in the LDPC codeword c, and the 641th to 656th bit to generate sequence cs2=(q ₁ , q ₂ , . . . , q _LH , p ₁ , p ₂ , . . . , p ₃₀₄ , p ₃₂₁ , . . . , p ₃₃₆ ); An exclusive OR (XOR) operation is performed with a pseudo-random (PN) sequence generated by the LFSR for data field scrambling, wherein the LFSR is initialized by an all-one vector. Cs1 and cs2 are cascaded and arranged to form a new sequence cs=(cs1, cs2, cs1).

The obtained 1344 (448 × 3) bits are modulated using BPSK or -BPSK, and then three BLKs are formed for transmission. It can be seen from the above that PartA and Part B adopt different mapping operations, and Part A and Part C adopt the same code modulation strategy, but Part C can utilize multiplication by (-1), phase shift, and cyclic shift. Alternatively, the diversity gain in the time domain or the frequency domain is obtained. For example, by multiplying the portion corresponding to Part C by -1, cs=(cs1, cs2, -1×cs1) is obtained.

By implementing this embodiment, the EDMG Header A field is encoded by the 1/2 code rate low density parity check code LDPC, and 128 information bits of the EDMG Header A1 can be carried over a single carrier block. The EDMG Header A field is encoded by the low-density parity check code LDPC of 1/2 code rate three times, and then the encoded EDMG Header A field is mapped and modulated, and three pieces of information bits respectively carrying 128 information bits are obtained. Single carrier block (ie, Part A, Part B, and Part C in Figure 7 It carries 128 information bits and carries the same information). Therefore, by implementing this embodiment, the EDMG Header A field can be encoded by the same coding method, thereby obtaining three single carrier blocks. By encoding the EDMG Header A field by the same coding method, the receiver can obtain higher demodulation and decoding performance for the EDMG Header A, and can reduce the decoding complexity of the receiver for the entire EDMG Header A.

As an optional implementation manner, the EDMG Header A field includes an EDMG Header A1 and an EDMG Header A2 field, the EDMG Header A1 field may include 128 information bits or 64 information bits, and the 601 part may be a 601b part.

In section 601b, the code modulation device encodes and modulates the EDMG Header A1 field and the EDMG Header A2 field. The EDMG Header A1 field is encoded and modulated with two single carrier blocks. The EDMG Header A2 field is encoded and modulated with X singles. Carrier block.

As an optional implementation manner, when X is equal to 2, the EDMG Header A1 field includes 128 information bits, and the EDMG Header A2 field includes 128 information bits, the specific implementation of the 601b portion may be: code modulation device pair EDMG Header The A1 field and the EDMG Header A2 field are coded in the same coding mode and modulated in the same modulation mode.

As an optional implementation manner, when X=2, the EDMG Header A1 field includes 128 information bits and the 128 information bits included in the EDMG Header A2 field, the code modulation device pairs the EDMG Header A1 field and the EDMG Header A2. The fields are encoded by the same coding method and modulated by the same modulation method. The specific process can be as shown in FIG. 8.

As shown in FIG. 8, the code modulation device encodes and modulates the EDMG Header A1 field. The code modulation device may split the 128 information bits of the EDMG Header A1 into two 64-bit parts, and then use the same coding (LDPC coding), mapping, and modulation (BPSK modulation) for the two 64-bit parts, respectively. Coding, mapping and modulation are performed, and finally two different single carrier blocks are obtained, that is, one single carrier block corresponds to Part A1 in FIG. 8, and the other single carrier block corresponds to Part B1 in FIG.

Since the code modulation device encodes the EDMG Header A1 field and the EDMG Header A2 field in the same coding mode and the same modulation mode. Therefore, as shown in FIG. 8, the code modulation device encodes and modulates the EDMG Header A2 field in such a manner that the code modulation device splits the 128 information bits of the EDMG Header A2 field into two 64-bit portions, and then respectively The two 64-bit parts are coded, mapped, and modulated using the same coding (LDPC coding), mapping, and modulation (BPSK modulation), and finally two different single-carrier blocks are obtained, that is, one single-carrier block corresponds to the one in FIG. Part A2, another single carrier block corresponds to Part B2 in FIG. It is worth mentioning that the EDMG Header A1 and EDMG Header A2 fields can be modulated separately without BPSK modulation, but with some deformation based on BPSK, for example, using π/2-BPSK for the EDMG Header A2 field. The two 64-bit portions are separately modulated, wherein π/2-BPSK is the modulation scheme defined in the 802.11 standard.

By implementing the implementation, the EDMG Header A is repeatedly coded to obtain four single carrier blocks, and the two single carrier blocks corresponding to the EDMG Header A1 carry the same information as the two single carrier blocks corresponding to the EDMG Header A2. Therefore, the reliability of information transmission of the EDMG Header A can be improved. By encoding the EDMG Header A1 field and the EDMG Header A2 field in the same coding mode and modulating the same modulation mode, the receiver can obtain higher demodulation and decoding performance for the EDMG Header A, and Reduce the decoding complexity of the receiver for the entire EDMG Header A.

As an optional implementation, in the EDMG Header A, each of the single carrier blocks formed after the modulation has a payload portion other than the GI (for example, FIG. 8Part A1, Part B1, Part A2, and Part B2), In the step of symbol block and insertion guard interval, it is also possible to multiply (-1), phase rotation, cyclic shift, etc. for some or all of the modulated symbols in each single carrier block modulated by the EDMG Header A code. One or more transform methods of the transform method such that the repeated encoding employed further achieves a diversity gain in the time or frequency domain. For example, some or all of the symbols in any single carrier block after Header A modulation are multiplied by r before the guard interval GI is inserted, where r is equal to e ^jθ and θ is an arbitrary value located in the closed interval [0, 2π].

For example, as shown in FIG. 8, for each BPSK symbol in the Part A2 and Part B2 single carrier blocks corresponding to the EDMG Header A2, a conversion method such as multiplication by (-1), phase rotation, cyclic shift, or the like may be used. In order to make the repetition coding obtain the diversity gain in the time domain or the frequency domain. For example, in the final output Part A1, Part B1, Part A2, and Part B2 of the EDMG Header A shown in FIG. 8, it may become Part A1, Part B1, (-1) × Part A2, (-1) × Part B2. , or Part A, Part B, (e ^jπ/2 ) × Part A2, (e ^jπ/2 ) × Part B2, and the like.

As an optional implementation manner, when X=2, the DMG Header A1 field includes 128 information bits that are different from the 128 information bits included in the EDMG Header A2 field, the code modulation device pairs the EDMG Header A1 field and the EDMG Header. The A2 field is coded by the same coding mode and modulated by the same modulation mode. The specific process can be as shown in FIG.

As shown in FIG. 9, the principle that the code modulation device encodes and modulates the EDMG Header A1 field is the same as the principle that the code modulation device encodes and modulates the EDMG Header A1 field in FIG. 8, and the code modulation device encodes the EDMG Header A2 field. The principle of modulation and modulation is the same as that of the code modulation device of FIG. 8 for encoding and modulating the EDMG Header A2 field, and details are not described herein.

By encoding the EDMG Header A1 field and the EDMG Header A2 field in the same coding mode and modulating the same modulation mode, the receiver can obtain higher demodulation and decoding performance for the EDMG Header A, which can be reduced. The decoding complexity of the receiver for the entire EDMG Header A.

As an optional implementation manner, when X=2, the DMG Header A1 field includes 128 information bits that are different from the 128 information bits included in the EDMG Header A2 field, the EDMG Header A1 field may include a payload bit and a loop. The redundancy check CRC bits, the information bits of the EDMG Header A2 field may also include payload bits and CRC bits, as shown in FIG.

As an optional implementation manner, when the EDMG Header A2 field and the EDMG Header A1 field respectively include a CRC, the preceding field can be used to carry higher priority, high urgency, and demodulation and decoding delay requirements. High physical layer signaling. Assume that the EDMG Header A1 field and the EDMG Header A2 are EDMG Header AX in time, and the EDMG Header AY in time. The urgent information is included in the previous EDMG Header AX, and will not Urgent information is included in the back EDMG Header AY. Urgent information including PPDU The transmission format information of the data field includes at least one of the following information: Aggregation mode, bandwidth, guard interval/recurrence prefix length (GI/CP Length), beamforming (Beamformed), short/ Long LDPC (Short/Long LDPC), enhanced directed multi-gigabit modulation coding strategy (EDMG-MCS), physical layer service data unit length (PSDU Length), number of spatial streams (Number of SS), space-time grouping applied Code (STBC Applied), Primary Channel Number, Open Loop Precoding. The non-emergency information includes information about the AGC and TRN fields in the PPDU: for example, training length, packet type, enhanced directed multi-gigabit training length, and partial information in the L-Header, such as the last received signal strength indicator RSSI. Since the EDMG Header AX uses an independent CRC for verification, these time-critical signaling can be independently demodulated and decoded prior to the EDMG Header AY, reducing the demodulation and decoding of these urgent physical layer signaling. Delay.

As an optional implementation manner, when X=2, the 128 information bits included in the DMG Header A1 field are different from the 128 information bits included in the EDMG Header A2 field, the EDMG Header A may include only one CRC bit, such as Figure 10 shows.

As an optional implementation manner, when X is equal to 2, the EDMG Header A1 field includes 64 information bits, and the EDMG Header A2 field includes 64 information bits that are different from the EDMG Header A1 field, the specific implementation of the 601b portion may be The code modulation device encodes and modulates the EDMG Header A1 field by the same coding mode as the traditional header L-Header field and the same modulation mode; the code modulation device adopts the same coding mode as the traditional header L-Header field and The same modulation scheme encodes and modulates the EDMG Header A2 field. Specifically, the code modulation process can be as shown in FIG.

As shown in FIG. 11, the code modulation device encodes and modulates the EDMG Header A1 field by the same coding mode and the same modulation mode as the conventional header L-Header field, specifically: 64 coding and modulation devices for the EDMG Header A1 field. The information bits are repeatedly coded, and finally two single-carrier blocks are generated, that is, the 64 information bits of the EDMG Header A1 are encoded, mapped and modulated at one time, the single-carrier block generated after the modulation corresponds to Part A1, and the other is to the EDMG Header A1. 64 information bits are encoded, mapped and modulated, and the single carrier block generated after modulation corresponds to Part B1.

Similarly, the code modulation device encodes and modulates the EDMG Header A2 field by the same coding mode and the same modulation mode as the traditional header L-Header field, specifically: code modulation device The 64 information bits of the EDMG Header A2 field are repeatedly coded, and finally two single carrier blocks are generated, that is, 64 information bits of the EDMG Header A2 are encoded, mapped and modulated at one time, and the single carrier block generated after the modulation corresponds to Part A2. Another time, 64 information bits of EDMG Header A2 are encoded, mapped and modulated, and the single carrier block generated after modulation corresponds to Part B2.

The encoding and modulation of the EDMG Header A1 field and the EDMG Header A2 field by the same encoding method and the same modulation method as the L-Header field can increase the transmission reliability of the EDMG Header A1 field and the EDMG Header A2 field, and can enable reception. The machine achieves higher demodulation and decoding performance for the EDMG Header A, which reduces the decoding complexity of the receiver for the entire EDMG Header A.

As an optional implementation manner, when X is equal to 2, the EDMG Header A1 field includes 64 information bits, and the EDMG Header A2 field includes 64 information bits different from the EDMG Header A1 field, the EDMG Header A may include only one. The CRC bit is shown in Figure 11. Alternatively, the EDMG Header A1 field and the EDMG Header A2 field may each include a CRC bit. In this way, the urgently required signaling can be placed in the preceding fields in the EDMG Header A1 field and the EDMG Header A2 field, which facilitates demodulation and decoding of time-critical signaling priorities, reducing these urgent physical layers. Demodulation and decoding delay of signaling.

As an optional implementation manner, when X is equal to 2, the EDMG Header A1 field includes 128 information bits, and the EDMG Header A2 field includes 64 information bits, in the 601b portion, the code modulation device encodes the EDMG Header A2 field. Specific implementations of the modulation and modulation may include the code modulation device modulating the EDMG Header A2 field by encoding in the same encoding as the legacy header L-Header field and the same modulation scheme. Specifically, the code modulation process can be as shown in FIG.

As shown in FIG. 12, the modulation coding mode of the EDMG Header A1 is the same as that of the existing EDMG Header A, that is, the 128 information bits of the EDMG Header A1 are split into two 64-bit parts, and then two 64-bit parts. The bit part adopts the same coding, mapping and modulation method to perform coding, mapping and modulation, and finally obtains two different single carrier blocks, that is, one single carrier block corresponds to Part A1 in FIG. 12, and the other single carrier block corresponds to FIG. Part B1.

As shown in FIG. 12, the code modulation device modulates the EDMG Header A2 field by the same coding method as the conventional header L-Header field and the same modulation mode, that is, The 64 information bits of EDMG Header A2 are repeatedly coded, and finally two single carrier blocks are generated, that is, 64 information bits of EDMG Header A2 are encoded, mapped and modulated at one time, and the single carrier block generated after modulation corresponds to Part A2. Another time, 64 information bits of EDMG Header A2 are encoded, mapped and modulated, and the single carrier block generated after modulation corresponds to Part B2. Part A2 and Part B2 carry the same information bits. Repeat coding will achieve a 3dB coding gain, making the transmission of EDMG Header A2 more robust (ie reliability).

In this embodiment, the EDMG Header A1 field and the EDMG Header A2 field may each include a CRC bit as shown in FIG. 12; alternatively, the EDMG Header A may include only one CRC bit.

As an optional implementation manner, when X is equal to 1, the EDMG Header A1 field includes 128 information bits, and the EDMG Header A2 field includes 64 information bits, the specific implementation of the 601b portion may include: coding and modulation device pair EDMG Header The A1 field and the EDMG Header A2 field are encoded by the same coding method and modulated by the same modulation scheme. Specifically, the code modulation process can be as shown in FIG.

As shown in FIG. 13, the modulation coding mode of the EDMG Header A1 is the same as that of the existing EDMG Header A, that is, the 128 information bits of the EDMG Header A1 are split into two 64-bit parts, and then two 64-bit parts. The bit part adopts the same coding mode (ie LDPC coding), mapping mode and modulation mode (ie π/2-BPSK modulation), performs coding, mapping and modulation, and finally obtains two different single carrier blocks, ie one single carrier block. Corresponding to Part A1 in FIG. 12, another single carrier block corresponds to Part B1 in FIG. Similarly, the code modulation device also encodes, maps, and modulates the EDMG Header A2 field using the same coding scheme (ie, LDPC coding), mapping method, and modulation scheme (ie, π/2-BPSK modulation) as the EDMG Header A1. A different single carrier block is obtained, which corresponds to Part A2.

In this embodiment, the EDMG Header A1 field and the EDMG Header A2 field may each include a CRC bit, as shown in FIG. 13, so that emergency signaling is placed in the EDMG Header A1 field and the EDMG Header A2 field. The preceding field facilitates demodulation and decoding of the time-critical signaling priority, and reduces the demodulation and decoding delay of these urgent physical layer signaling. Alternatively, EDMG Header A may include only one CRC bit.

As an optional implementation manner, when X is equal to 1, the EDMG Header A1 field includes 128 information bits, and the EDMG Header A2 field includes 128 information bits, the specific implementation of the 601b portion may include: the code modulation device passes the binary phase The EDMG Header A1 field is modulated by a shift keyed BPSK or BPSK variant (eg π/2-BPSK); the code modulation device modulates the EDMG Header A2 field by quadrature phase shift keying QPSK or QPSK deformation. Specifically, the code modulation process can be as shown in FIG.

As shown in FIG. 14, the code modulation device uses the same LDPC coding and mapping as the EDMG Header A1 field for the EDMG Header A2 field. The code modulation device modulates the EDMG Header A1 field by BPSK or BPSK deformation, and two single carrier blocks obtained after modulation, one corresponding to Part A1 and the other corresponding to Part B1. The code modulation device modulates the EDMG Header A2 field by binary phase shift keying QPSK or QPSK deformation to obtain 1 single carrier block, which corresponds to Part A2. Modulation of EDMG Header A2 using QPSK yields only one single carrier block carrying 128 information bits of EDMG Header A1.

In this embodiment, the EDMG Header A2 field includes 128 information bits that may be the same or different than the 128 information bits included in the EDMG Header A1 field. When the EDMG Header A1 field includes 128 information bits and the 128 information bits included in the EDMG Header A2 field, that is, the EDMG Header A only includes 128 information bits, and the EDMG Header A1 field and the EDMG Header A2 field share the same. 128 information bits. FIG. 14 exemplifies a case where 128 information bits included in the EDMG Header A1 field are the same as 128 information bits included in the EDMG Header A2 field.

In this embodiment, when the EDMG Header A2 field includes 128 information bits that are different from the EDMG Header A1 field, the EDMG Header A may include only one CRC bit, or the EDMG Header A1 field and the EDMG Header A2 field may respectively include one CRC bit. The EDMG Header A1 field and the EDMG Header A2 field respectively include a CRC bit, which places the urgently required signaling in the EDMG Header A1 field and the EDMG Header A2 field. The field facilitates demodulation and decoding of the time-critical signaling, and reduces the demodulation and decoding delay of these urgent physical layer signaling.

As an optional implementation manner, when X is equal to 1, the EDMG Header A1 field includes 128 information bits, and the EDMG Header A2 field includes 128 information bits, in the 601b portion, the code modulation device encodes the EDMG Header A1 field. Then, before the EDMG Header A1 field is modulated, the code modulation device may also map the encoded EDMG Header A1 field by the first mapping manner. Correspondingly, in the 601b part, after the code modulation device encodes the EDMG Header A2 field, before the EDMG Header A2 field is modulated, the code modulation device may also map the encoded EDMG Header A2 field by using the second mapping manner. To obtain X single carrier blocks, the first mapping manner is different from the second mapping manner. Specifically, the code modulation process can be as shown in FIG.

As shown in Figure 15, the EDMG Header A2 uses exactly the same encoding and the same modulation as the EDMG Header A1, but uses different mapping methods. The mapping method adopted by the EDMG Header A1 is referred to as a first mapping mode, and the mapping method adopted by the EDMG Header A2 is referred to as a second mapping mode. Assume that the sequence of the EDMG Header A after scrambling is expressed as d _s =(q ₁ ,q ₂ ,...,q _LH ), where LH=128, and d _{s is} cascaded 504-LH 0s, after passing through with EDMG After the same 3/4 code rate LDPC encoding of Header A1, the output LDPC codeword is c=(q ₁ , q ₂ ,..., q _LH , 0 ₁ , 0 ₂ ,..., 0 _504-LH , p ₁ , p ₂ , . . . , p ₁₆₈ ), wherein p ₁ , p ₂ , . . . , p ₁₆₈ are parity bits generated according to Hc=0, where H is the parity used by EDMG Header A1 Check matrix. After the first step of LDPC coding, the second mapping mode can be expressed as: LDPC codeword c

Repeated once, the obtained sequence is cs1=(q ₁ ,q ₂ ,...,q _LH ,q _LH+1 ,q _LH+2 ,...,q _2LH ,0 ₁ ,...,0 ₂₄ , p ₁ , p ₂ , . . . , p ₁₆₈ ), a pseudo-random generated by a partial or all content of cs1 and a linear feedback shift register (LFSR) for data field scrambling The (PN) sequence performs an exclusive OR (XOR) operation in which the LFSR is initialized by an all 1 vector. If part of the content of cs1 is XORed with the PN sequence generated by the LFSR, the bit participating in the operation in cs1 includes at least a part of 0 bit (0 ₁ , . . . , 0 ₂₄ ), for example, a part of the bit of cs1 ( 0 ₁ ,...,0 ₂₄ ,p ₁ ,p ₂ ,...,p ₁₆₈ ) After XOR operation with the PN sequence, cs1 becomes cs2=(q ₁ , q ₂ ,...,q _LH , q _LH+1 , q _LH+2 , . . . , q _2LH , p ₁ , . . . , p ₂₄ , p ₂₅ , . . . , p ₁₉₂ ).

Finally, the fully mapped cs2 sequence is subjected to the same BPSK modulation as EDMG Header A1.

In this embodiment, the EDMG Header A2 field includes 128 information bits that may be the same or different than the 128 information bits included in the EDMG Header A1 field. FIG. 15 exemplifies a case where 128 information bits included in the EDMG Header A1 field are the same as 128 information bits included in the EDMG Header A2 field.

In this embodiment, when the EDMG Header A2 field includes 128 information bits that are different from the EDMG Header A1 field, the EDMG Header A may include only one CRC bit, or the EDMG Header A1 field and the EDMG Header A2 field may respectively include one CRC bit.

In the above embodiments, the EDMG Header A field is extended to 3 or 4 single carrier blocks by adopting a method similar to the repetition coding/repetition modulation, which increases the transmission reliability of the EDMG Header A field, so that EDMG Header A The coding and modulation scheme used is much more robust than the lowest order modulation method MCS1 that the data field may use. Further, this may be such that in 802.11ay, if the CRC check of the L-Header fails, and the L-CE field is measured, the reported signal-to-noise ratio SNR/error vector magnitude EVM is sufficient to demodulate the L-Header and the EDMG Header. At A, we may still be able to demodulate the EDMG Header A. In this case, the Clear Channel Assessment (CCA) can be maintained high by the length information of the PPDU in the EDMG Header A, that is, according to the length information of the PPDU. Set the network allocation vector NAV. Properly setting the network allocation vector NAV can avoid transmission collisions between different STAs. In addition, EDMG Header A also contains a number of important transport format information. The successful demodulation of EDMG Header A can bring many benefits. For example, even if the data field of the PPDU cannot be successfully demodulated, it can also be carried by EDMG Header A. The indication information related to the TRN field of the beamforming training sequence is used to continue the beamforming training using the TRN field. Alternatively, the receiving STA of the PPDU may estimate the RSSI according to the previous received signal strength carried in the EDMG Header A, and estimate a more accurate MCS for the next PPDU.

The embodiment of the present invention may divide the functional unit of the code modulation device according to the foregoing method example. For example, each functional unit may be divided according to each function, or two or more of the functional units may be divided. The functions are integrated in one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit. It should be noted that the division of the unit in the embodiment of the present invention is schematic, and is only a logical function division, and the actual implementation may have another division manner.

An embodiment of the present invention provides a code modulation device, where the code modulation device includes a processing module, and the processing module is configured to encode and modulate an enhanced directional multi-gigabit header EDMG Header A field included in a physical layer protocol data unit. The EDMG Header A field is encoded and modulated with M single carrier blocks, the M being the sum of 2 and X, which is a positive integer not equal to zero.

The processing module is used to perform the method in part 601 of the method embodiment of the present invention. For the implementation of the processing module, reference may be made to the description of the method part 601 of the present invention, and details are not described herein again.

As an optional implementation manner, the processing module may further perform other processes in the method embodiment of the present invention. For example, the processing module is further configured to modulate an EDMG STF, where the EDMG STF modulation has Y single carrier blocks or Z OFDM symbols, the sum of X and Y is greater than or equal to 4.5 single carrier blocks, or the total duration of the X single carrier blocks and Z OFDM symbols is greater than or equal to the duration of 4.5 single carrier blocks.

As an optional implementation manner, the processing module may also perform a specific implementation of part 601 in the method embodiment of the present invention, for example, X is equal to 1, the EDMG Header A field includes 128 information bits, and the processing module is EDMG Header. The manner in which the A field is encoded may be specifically: the processing module encodes the EDMG Header A field by using a 1/2 code rate low density parity check code LDPC.

For example, the EDMG Header A field includes an EDMG Header A1 and an EDMG Header A2 field, and the EDMG Header A1 field includes 128 information bits or 64 information bits. The processing module is specifically configured to: perform an EDMG Header A1 field and an EDMG Header A2 field. Encoding and Modulation, the EDMG Header A1 field is encoded and modulated with two single-carrier blocks, and the EDMG Header A2 field is encoded and modulated with X single-carrier blocks.

For example, X is equal to 2, the EDMG Header A1 field includes 128 information bits, and the EDMG Header A2 field includes 128 information bits. The processing module is specifically configured to: use the same coding mode for the EDMG Header A1 field and the EDMG Header A2 field. The coding and the same modulation method are used for modulation.

For another example, X is equal to 2, and the EDMG Header A1 field includes 64 information bits, EDMG Header The A2 field includes 64 information bits that are different from the EDMG Header A1 field, and the processing module is specifically configured to: encode and modulate the EDMG Header A1 field by the same coding mode as the traditional header L-Header field and the same modulation mode. The EDMG Header A2 field is encoded and modulated by the same encoding as the traditional header L-Header field and the same modulation scheme.

For another example, X is equal to 2, the EDMG Header A1 field includes 128 information bits, and the EDMG Header A2 field includes 64 information bits. The processing module encodes and modulates the EDMG Header A2 field by specifically: passing the EDMG Header A2 field. The same encoding method as the conventional header L-Header field is encoded and modulated in the same modulation scheme.

For example, X is equal to 1, the EDMG Header A1 field includes 128 information bits, and the EDMG Header A2 field includes 64 information bits. The processing module is specifically configured to: encode the EDMG Header A1 field and the EDMG Header A2 field by the same coding mode. And the same modulation method for modulation.

For example, X is equal to 1, the EDMG Header A1 field includes 128 information bits, and the EDMG Header A2 field includes 128 information bits. The processing module can modulate the EDMG Header A1 field and the EDMG Header A2 field by using a binary phase. The EDMG Header A1 field is modulated by the shifting of the keyed BPSK or BPSK; the EDMG Header A2 field is modulated by the quadrature phase shift keying of the QPSK or QPSK variant.

As an optional implementation manner, X is equal to 1, the EDMG Header A1 field includes 128 information bits, the EDMG Header A2 field includes 128 information bits, and the processing module is further used after the processing module encodes the EDMG Header A1 field. Before the processing module modulates the EDMG Header A1 field, the encoded EDMG Header A1 field is mapped by the first mapping manner; the processing module is further configured to: after the processing module encodes the EDMG Header A2 field, in the processing module Before the EDMG Header A2 field is modulated, the encoded EDMG Header A2 field is mapped by the second mapping manner to obtain X single carrier blocks, and the first mapping manner is different from the second mapping manner.

As an optional implementation manner, a previous one of the EDMG Header A2 field and the EDMG Header A1 field includes first information, where the first information includes at least one of the following information: information aggregation, bandwidth, guard interval/loop Length of prefix, beamforming, short/long low-density parity check code, enhanced directional multi-gigabit modulation coding strategy, physical layer service data unit length, number of spatial streams, space-time block coding applied, main Channel number, open loop precoding.

As an optional implementation manner, a field that is located in the EDMG Header A2 field and the EDMG Header A1 field includes second information, where the second information includes at least one of the following information: training length, packet type, and previous reception. The signal strength indicates the RSSI, the enhanced directional multi-gigabit training length, and the receiving training unit of each transmitting training unit.

As an optional implementation manner, the symbol of any single carrier block after EDMG Header A modulation is multiplied by r before inserting the guard interval GI, where r is equal to e ^jθ and θ is located in the closed interval [0, 2π] Any value.

For a specific implementation of the optional implementation of the processing module, reference may be made to the corresponding description of the method embodiment of the present invention, and details are not described herein again.

Based on the same inventive concept, the principle of the code modulation device provided in the embodiment of the present invention is similar to the code modulation method of the physical layer protocol data unit in the method embodiment of the present invention. Therefore, the implementation of the user terminal can refer to the implementation of the method. For the sake of brevity, it will not be repeated here.

Referring to FIG. 16, FIG. 16 is a schematic diagram of another possible structure of a code modulation device according to an embodiment of the present invention. As shown in FIG. 16, the code modulation device 1600 includes a processor 1601, a memory 1602, and a bus system 1603. Optionally, a transceiver 1604 can also be included. The processor 1601 and the memory 1602 are connected by a bus system 1603, and the transceiver 1604 and the memory 1602 are connected by a bus system 1603.

The processor 1601 may be a central processing unit (CPU), a general-purpose processor, a coprocessor, a digital signal processor (DSP), and an application-specific integrated circuit (ASIC). Field Programmable Gate Array (FPGA) or other programmable logic device, transistor logic device, hardware component, or any combination thereof. The processor 1601 can also be a combination of computing functions, such as one or more microprocessor combinations, a combination of a DSP and a microprocessor, and the like.

Among them, the bus system 1603 can be a Peripheral Component Interconnect (referred to as PCI) bus or Extended Industry Standard Architecture (EISA) bus. The bus system 1603 can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in Figure 16, but it does not mean that there is only one bus or one type of bus.

The transceiver 1604 is configured to implement communication with other network elements, such as demodulation and decoding devices. For example, the transceiver 1604 can transmit the single carrier block obtained by the coding and modulation device in the coding and modulation method of the physical layer protocol data unit to the demodulation decoding device.

The processor 1601 calls the program code stored in the memory 1602 for performing the operations performed by the processing module of the code modulation device in the above embodiment.

For a specific implementation of the optional implementation of the processor 1601, reference may be made to the corresponding description of the method embodiment of the present invention, and details are not described herein.

The embodiment of the invention further provides a demodulation and decoding method and a demodulation and decoding device for a physical layer protocol data unit. As such, this embodiment is applicable to the system architecture shown in FIG. The demodulation decoding device may be the STA in FIG. The demodulation and decoding device may demodulate and decode the EDMG Header A field or the single carrier block of the EDMG STF generated by the code modulation device in the above embodiment.

Correspondingly, the demodulation and decoding method of the physical layer protocol data unit may include: demodulating and decoding the device to demodulate and decode the EDMG Header A field of the physical layer protocol data unit, and demodulating and translating the EDMG Header A field There are M single carrier blocks in front of the code, and M is the sum of 2 and X, which is a positive integer not equal to zero.

That is to say, the EDMG Header A field has at least 3 single carrier blocks before demodulation and decoding. The format diagram of the physical layer protocol data unit can be seen in FIG. 6 and the corresponding description in FIG. 6.

It is worth mentioning that in the process of demodulating and decoding the EDMG Header A field by the code modulation device, after the code modulation device demodulates the EDMG Header A field, it needs to reflect the demodulated EDMG Header A field. The shot, coded modulation device then decodes the inverse mapped EDMG Header A field.

By implementing the demodulation and decoding method of the physical layer protocol data unit provided by the embodiment of the present invention, the demodulation and decoding device can demodulate and decode the EDMG Header A field having M single carrier blocks. Therefore, the code modulation device can The EDMG Header A field is encoded and modulated to a length greater than two single carrier blocks, such that the modulated EDMG STF can be less than the existing 4.5 or 5.5 single carrier blocks. The EDMG Header A field can increase the length of the modulated EDMG Header A field by carrying more useful information (ie, grow from two single carrier blocks to more than two single carrier blocks), or can increase modulation by repeating coding. The length of the EDMG Header A field is such that all the single carrier blocks obtained after the modulation carry at least two pieces of information of the EDMG Header A field, which improves the reliability of information transmission in the EDMG Header A field.

As an optional implementation manner, the physical layer protocol data unit further includes an EDMG STF, where the EDMG Header A field is located before the EDMG STF, and the demodulation and decoding device can also demodulate the EDMG STF.

Optionally, the EDMG STF has Y single-carrier blocks before demodulation, and the sum of X and Y is greater than or equal to 4.5 single-carrier blocks.

Optionally, the EDMG STF has Z OFDM symbols before demodulation, and the total duration of the Z OFDM symbols is greater than or equal to the duration of 4.5 single carrier blocks.

In existing practical applications, the EDMG STF has at least 4.5 or 5.5 OFDM symbols after modulation, however by implementing this embodiment, the demodulation decoding device can have a single carrier block with Z (Z less than 4.5 or 5.5). EDMG STF demodulation, and then the code modulation device can be used to convert EDMG STF Modulation to the length of the OFDM symbol, it is seen that by implementing this embodiment it is advantageous to reduce the redundant portion of the EDMG STF.

As an optional implementation manner, the demodulation and decoding apparatus may further perform a single carrier block of an EDMG Header A field obtained by an optional implementation in the embodiment of the code modulation method of the physical layer protocol data unit. Demodulation and decoding.

The embodiment of the present invention may divide a functional unit into a demodulation and decoding device according to the foregoing method. For example, each functional unit may be divided according to each function, or two or more functions may be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit. It should be noted that the division of the unit in the embodiment of the present invention is schematic, and is only a logical function division, and the actual implementation may have another division manner.

The embodiment of the present invention provides a demodulation and decoding device, where the demodulation and decoding device includes a processing module, and the processing module is configured to demodulate and decode an EDMG Header A field, and the EDMG Header A field is demodulated and There are M single carrier blocks before decoding, and M is the sum of 2 and X, which is a positive integer not equal to zero.

As an optional implementation manner, the processing module is further configured to perform demodulation on the EDMG STF, where the EDMG STF has Y single-carrier blocks or Z OFDM symbols, and the sum of X and Y is greater than or equal to 4.5. The single carrier block, or the total duration of the X single carrier blocks and the Z OFDM symbols is greater than or equal to the duration of 4.5 single carrier blocks.

For a specific implementation manner of the processing module, refer to the specific implementation manner of the demodulation and decoding method of the physical layer protocol data unit, which is not described herein.

Based on the same inventive concept, the principle of solving the problem in the demodulation and decoding device provided in the embodiment of the present invention is similar to the demodulation and decoding method of the physical layer protocol data unit in the method embodiment of the present invention. Therefore, the implementation of the user terminal can be seen. The implementation of the method is described briefly and will not be described here.

Referring to FIG. 17, FIG. 17 is a schematic diagram of another possible structure of a demodulation and decoding device according to an embodiment of the present invention. As shown in FIG. 17, the demodulation decoding apparatus 1700 includes a processor 1701, a memory 1702, and a bus system 1703. Optionally, the demodulation and decoding device may further include a transceiver 1704, wherein the processor 1701 and the memory 1702 are connected by a bus system 1703, and the transceiver 1704 and the memory 1702 pass through the bus. System 1703 is connected.

The processor 1701 may be a central processing unit (CPU), a general-purpose processor, a coprocessor, a digital signal processor (DSP), and an application-specific integrated circuit (ASIC). Field Programmable Gate Array (FPGA) or other programmable logic device, transistor logic device, hardware component, or any combination thereof. The processor 1701 can also be a combination of computing functions, such as one or more microprocessor combinations, a combination of a DSP and a microprocessor, and the like.

The bus system 1703 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The bus system 1703 can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in Figure 17, but it does not mean that there is only one bus or one type of bus.

The transceiver 1704 is configured to implement communication with other network elements, such as code modulation devices. For example, the transceiver 1704 can receive the single carrier block obtained by the coded modulation device transmitted by the code modulation device in the code modulation method of the physical layer protocol data unit.

The processor 1701 calls the program code stored in the memory 1702 to perform the following operations:

The EDMG Header A field is demodulated and decoded. The EDMG Header A field has M single-carrier blocks before demodulation and decoding. The M is the sum of 2 and X, and the X is a positive integer not equal to zero.

As an optional implementation manner, the processor 1701 further calls the program code stored in the memory 1702 to demodulate the EDMG STF. The EDMG STF has Y single-carrier blocks or Z OFDM symbols before demodulation. The sum of Y is greater than or equal to 4.5 single carrier blocks, or the total duration of the X single carrier blocks and Z OFDM symbols is greater than or equal to the duration of 4.5 single carrier blocks.

For a specific implementation manner of the processor 1701, refer to the specific implementation manner of the demodulation and decoding method of the physical layer protocol data unit, which is not described herein.

It should also be noted that in the embodiments of the present invention, such as the first, second, and pin numbers, etc. Relational terms such as those are used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order. Furthermore, the term "comprises," "comprises," or "includes" or "includes" or "includes" or "includes" or "includes" or "includes" or "includes" Or include elements inherent to such a process, method, article, or device. The elements defined by the terms "including", "comprising", and <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;

Those skilled in the art can understand that all or part of the steps of implementing the above embodiments may be completed by hardware, or may be instructed by a program to execute related hardware, and the program may be stored in a non-volatile computer readable storage. In the medium, the above-mentioned storage medium may be a read only memory, a magnetic disk or an optical disk or the like.

Those skilled in the art will appreciate that in one or more examples described above, the functions described herein can be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions may be stored in a computer readable medium or transmitted as one or more instructions or code on a computer readable medium. Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another. A storage medium may be any available media that can be accessed by a general purpose or special purpose computer.

The specific embodiments described above further explain the beneficial effects of the present invention and the technical solutions. It should be understood that different embodiments may be combined, and the above embodiments are further described. Any combination, modification, equivalent substitution, improvement, etc., made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.

The specific embodiments of the present invention have been described in detail with reference to the preferred embodiments of the present invention. The scope of the protection, any modifications, equivalent substitutions, improvements, etc., which are made on the basis of the technical solutions of the present invention, are included in the scope of the present invention.

Claims

A coded modulation method for a physical layer protocol data unit, wherein the physical layer protocol data unit includes an enhanced directional multi-gigabit header EDMG Header A field, the method comprising:

The EDMG Header A field is encoded and modulated. The EDMG Header A field is encoded and modulated with M single carrier blocks, the M being the sum of 2 and X, and the X being a positive integer not equal to zero.
The method of claim 1, wherein the physical layer protocol data unit further comprises an enhanced directional multi-gigabit short training sequence field EDMG STF, the EDMG Header A field being located before the EDMG STF, the method Also includes:

Encoding and modulating the EDMG STF, the EDMG STF encoding and modulating having Y single carrier blocks or Z OFDM symbols, the sum of the X and the Y being greater than or equal to 4.5 single carrier blocks, or The total duration of the X single carrier blocks and the Z OFDM symbols is greater than or equal to the duration of 4.5 single carrier blocks.
The method according to claim 1 or 2, wherein the X is equal to 1, and the EDMG Header A field includes 128 information bits, and the EDMG Header A field is encoded, including:

The EDMG Header A field is encoded by a 1/2 code rate low density parity check code LDPC.
The method according to claim 1 or 2, wherein the EDMG Header A field comprises an EDMG Header A1 and an EDMG Header A2 field, the EDMG Header A1 field comprising 128 information bits or 64 information bits, The EDMG Header A field is encoded and modulated, including:

Encoding and modulating the EDMG Header A1 field and the EDMG Header A2 field, the EDMG Header A1 field encoding and modulating having two single carrier blocks, the EDMG Header A2 field encoding and modulating the X Single carrier block.
The method according to claim 4, wherein said X is equal to 2, said EDMG Header A1 field comprises 128 information bits, and said EDMG Header A2 field comprises 128 information bits for said EDMG Header A1 field Encoding and modulating with the EDMG Header A2 field, including:

The EDMG Header A1 field and the EDMG Header A2 field are coded by the same coding method and modulated by the same modulation mode.
The method according to claim 4, wherein said X is equal to 2, said EDMG Header A1 field comprises 64 information bits, and said EDMG Header A2 field comprises 64 different from said EDMG Header A1 field. Information bits, encoding and modulating the EDMG Header A1 field and the EDMG Header A2 field, including:

Encoding and modulating the EDMG Header A1 field by the same coding mode as the traditional header L-Header field and the same modulation mode;

The EDMG Header A2 field is encoded and modulated by the same coding scheme as the conventional header L-Header field and the same modulation scheme.
The method according to claim 4, wherein said X is equal to 2, said EDMG Header A1 field comprises 128 information bits, said EDMG Header A2 field comprises 64 information bits, said EDMG Header A2 field Coding and modulation, including:

The EDMG Header A2 field is encoded by the same coding method as the conventional header L-Header field and modulated by the same modulation scheme.
The method according to claim 4, wherein said X is equal to 1, said EDMG Header A1 field comprises 128 information bits, and said EDMG Header A2 field comprises 64 information bits for said EDMG Header A1 field Encoding and modulating with the EDMG Header A2 field, including:

The EDMG Header A1 field and the EDMG Header A2 field are encoded by the same coding method and modulated by the same modulation scheme.
The method of claim 4 wherein said X is equal to 1, said EDMG The Header A1 field includes 128 information bits, and the EDMG Header A2 field includes 128 information bits, and the EDMG Header A1 field and the EDMG Header A2 field are modulated, including:

Modulating the EDMG Header A1 field by a binary phase shift keying BPSK or BPSK variant;

The EDMG Header A2 field is modulated by quadrature phase shift keying QPSK or QPSK deformation.
The method according to claim 4, wherein said X is equal to 1, said EDMG Header A1 field comprises 128 information bits, and said EDMG Header A2 field comprises 128 information bits for said EDMG Header A1 field After the encoding, before the EDMG Header A1 field is modulated, the method further includes:

Mapping the encoded EDMG Header A1 field by using a first mapping manner;

After the EDMG Header A2 field is encoded, before the EDMG Header A2 field is modulated, the method further includes:

The encoded EDMG Header A2 field is mapped by using a second mapping manner to obtain the X single carrier blocks, where the first mapping manner is different from the second mapping manner.
The method according to any one of claims 4 to 10, wherein the first one of the EDMG Header A2 field and the EDMG Header A1 field includes first information, and the first information includes the following information. At least one of: information aggregation, bandwidth, guard interval/cycle prefix length, beamforming, short/long low-density parity check code, enhanced directional multi-gigabit modulation coding strategy, physical layer service data unit length The number of spatial streams, space-time block coding, primary channel number, and open-loop precoding.
The method according to any one of claims 4 to 11, wherein a field located in the EDMG Header A2 field and the EDMG Header A1 field includes second information, and the second information includes the following information. At least one of: training length, packet type, last received signal strength indication RSSI, enhanced directed multi-gigabit training length, and each receiving training unit receiving training unit.
The method according to any one of claims 4 to 12, characterized in that the information bits of the EDMG Header A1 comprise a payload bit and a cyclic redundancy check CRC bit, the information bits of the EDMG Header A2 comprise a payload Bit and Cyclic Redundancy Check CRC bits.
The method according to any one of claims 1 to 12, wherein the EDMG Header A field includes only one cyclic redundancy check CRC bit.
The method according to any one of claims 1 to 14, wherein the symbol of any one of the single carrier blocks modulated by the EDMG Header A is multiplied by r before the guard interval GI is inserted, and the r is equal to e. Jθ , the θ is an arbitrary value belonging to the closed interval [0, 2π].
A code modulation device, characterized in that the code modulation device comprises:

And a processing module, configured to encode and modulate an enhanced directional multi-gigabit header EDMG Header A field included in the physical layer protocol data unit, where the EDMG Header A field is encoded and modulated with M single carrier blocks, where the M is The sum of 2 and X, the X being a positive integer not equal to zero.
The coded modulation device according to claim 16, wherein said physical layer protocol data unit further comprises an enhanced directional multi-gigbit short training sequence field EDMG STF, said EDMG Header A field being located before said EDMG STF,

The processing module is further configured to modulate the EDMG STF, where the EDMG STF is modulated with Y single carrier blocks or Z OFDM symbols, and the sum of the X and the Y is greater than or equal to 4.5 single carriers. The block, or the total duration of the X single carrier blocks and the Z OFDM symbols is greater than or equal to the duration of 4.5 single carrier blocks.
The coded modulation device according to claim 16 or 17, wherein said X is equal to 1, said EDMG Header A field comprises 128 information bits, and said processing module encodes said EDMG Header A field Specifically:

The processing module encodes the EDMG Header A field by a 1/2 code rate low density parity check code LDPC.
The code modulation device according to claim 16 or 17, wherein the EDMG Header A field includes an EDMG Header A1 and an EDMG Header A2 field, and the EDMG Header A1 field includes 128 information bits or 64 information bits. The processing module is specifically configured to:

Encoding and modulating the EDMG Header A1 field and the EDMG Header A2 field, the EDMG Header A1 field encoding and modulating having two single carrier blocks, the EDMG Header A2 field encoding and modulating the X Single carrier block.
The coded modulation device according to claim 19, wherein said X is equal to 2, said EDMG Header A1 field comprises 128 information bits, said EDMG Header A2 field comprises 128 information bits, said processing module being specific Used for:

The EDMG Header A1 field and the EDMG Header A2 field are coded by the same coding method and modulated by the same modulation mode.
The coded modulation device according to claim 19, wherein said X is equal to 2, said EDMG Header A1 field comprises 64 information bits, and said EDMG Header A2 field comprises a different from said EDMG Header A1 field. 64 information bits, the processing module is specifically used to:

Encoding and modulating the EDMG Header A1 field by the same coding mode as the traditional header L-Header field and the same modulation mode;

The EDMG Header A2 field is encoded and modulated by the same coding scheme as the conventional header L-Header field and the same modulation scheme.
The coded modulation device according to claim 19, wherein said X is equal to 2, said EDMG Header A1 field comprises 128 information bits, said EDMG Header A2 field comprises 64 information bits, said processing module pair The manner in which the EDMG Header A2 field is encoded and modulated is specifically as follows:

The EDMG Header A2 field is encoded by the same coding method as the conventional header L-Header field and modulated by the same modulation scheme.
The coded modulation device according to claim 19, wherein said X is equal to 1, said EDMG Header A1 field comprises 128 information bits, said EDMG Header A2 field comprises 64 information bits, said processing module being specific Used for:

The EDMG Header A1 field and the EDMG Header A2 field are encoded by the same coding method and modulated by the same modulation scheme.
The coded modulation device according to claim 19, wherein said X is equal to 1, said EDMG Header A1 field comprises 128 information bits, said EDMG Header A2 field comprises 128 information bits, said processing module pair The manner in which the EDMG Header A1 field and the EDMG Header A2 field are modulated is specifically:

Modulating the EDMG Header A1 field by a binary phase shift keying BPSK or BPSK variant;

The EDMG Header A2 field is modulated by quadrature phase shift keying QPSK or QPSK deformation.
The coded modulation device according to claim 19, wherein said X is equal to 1, said EDMG Header A1 field comprises 128 information bits, and said EDMG Header A2 field comprises 128 information bits.

The processing module is further configured to: after the processing module encodes the EDMG Header A1 field, before the processing module modulates the EDMG Header A1 field, the coded location is performed by using a first mapping manner The EDMG Header A1 field is mapped;

The processing module is further configured to: after the processing module encodes the EDMG Header A2 field, before the processing module modulates the EDMG Header A2 field, use the second mapping manner to the encoded device The EDMG Header A2 field is mapped to obtain the X single carrier blocks, and the first mapping manner is different from the second mapping manner.
The code modulation device according to any one of claims 19 to 25, wherein the first field among the EDMG Header A2 field and the EDMG Header A1 field includes first information, and the first information includes At least one of the following information: information aggregation, bandwidth, guard interval/cycle prefix length, beamforming, short/long low-density parity check, enhancement The directional multi-gigabit modulation coding strategy, the physical layer service data unit length, the number of spatial streams, the space-time block coding, the primary channel number, and the open-loop precoding are applied.
The code modulation device according to any one of claims 19 to 26, wherein a field located in the EDMG Header A2 field and the EDMG Header A1 field includes second information, and the second information includes At least one of the following information: training length, packet type, last received signal strength indication RSSI, enhanced directed multi-gigabit training length, and each receiving training unit receiving training unit.
The code modulation device according to any one of claims 19 to 27, wherein the information bits of the EDMG Header A1 include a payload bit and a cyclic redundancy check CRC bit, and the information bits of the EDMG Header A2 include Payload bits and cyclic redundancy check CRC bits.
The coded modulation device according to any one of claims 16 to 27, wherein said EDMG Header A field includes only one cyclic redundancy check CRC bit.
The code modulation device according to any one of claims 16 to 29, characterized in that the symbol of any one of the single carrier blocks modulated by the EDMG Header A is multiplied by r before the guard interval GI is inserted, the r Equal to e jθ , which is an arbitrary value belonging to the closed interval [0, 2π].
A code modulation device, characterized in that the code modulation device comprises a processor, a memory, a bus system and one or more programs, the processor and the memory being connected by the bus system, wherein the one Or a plurality of programs stored in said memory, said one or more programs comprising instructions that, when said instructions are executed by said coded modulation device, cause said coded modulation device to perform any one of claims 1 to Said method.
A method for demodulating and decoding a physical layer protocol data unit, wherein the physical layer protocol data unit includes an enhanced directional multi-gigabit header EDMG Header A field, the method comprising:

Demodulating and decoding the EDMG Header A field, which has M single-carrier blocks before demodulation and decoding, the M being the sum of 2 and X, and the X being unequal to zero A positive integer.
The method of claim 32, wherein the physical layer protocol data unit further comprises an enhanced directional multi-gigabit short training sequence field EDMG STF, the EDMG Header A field being located before the EDMG STF, the method Also includes:

Demodulating the EDMG STF, the EDMG STF demodulating before having Y single carrier blocks or Z OFDM symbols, the sum of the X and the Y being greater than or equal to 4.5 single carrier blocks, or the X The total duration of the single carrier block and the Z OFDM symbols is greater than or equal to the duration of 4.5 single carrier blocks.
A demodulation and decoding device, characterized in that the demodulation and decoding device comprises:

a processing module, configured to demodulate and decode the EDMG Header A field, where the EDMG Header A field has M single-carrier blocks before demodulation and decoding, and the M is a sum of 2 and X, X is a positive integer not equal to zero.
The method according to claim 34, wherein said physical layer protocol data unit further comprises an enhanced directed multi-gigabit short training sequence field EDMG STF, said EDMG Header A field being located before said EDMG STF,

The processing module is further configured to perform demodulation on the EDMG STF, where the EDMG STF has Y single-carrier blocks or Z OFDM symbols before demodulation, and the sum of the X and the Y is greater than or equal to 4.5 The single carrier block, or the total duration of the X single carrier blocks and the Z OFDM symbols is greater than or equal to the duration of 4.5 single carrier blocks.
A demodulation and decoding device, characterized in that the demodulation and decoding device comprises a processor, a memory, a bus system and one or more programs, and the processor and the memory are connected by the bus system, wherein The one or more programs are stored in the memory, the one or more programs including instructions that, when executed by the demodulation decoding device, cause the demodulation decoding device to perform The method of claim 32 or 33.