WO2018074607A1 - Thin-film transistor, production method therefor, and solution for forming gate insulation film for thin-film transistor - Google Patents

Thin-film transistor, production method therefor, and solution for forming gate insulation film for thin-film transistor Download PDF

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Publication number
WO2018074607A1
WO2018074607A1 PCT/JP2017/038086 JP2017038086W WO2018074607A1 WO 2018074607 A1 WO2018074607 A1 WO 2018074607A1 JP 2017038086 W JP2017038086 W JP 2017038086W WO 2018074607 A1 WO2018074607 A1 WO 2018074607A1
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gate insulating
zirconium
solution
insulating film
film forming
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PCT/JP2017/038086
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French (fr)
Japanese (ja)
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下田 達也
金望 李
浩晃 小山
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凸版印刷株式会社
国立大学法人北陸先端科学技術大学院大学
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Priority to JP2018545782A priority Critical patent/JP7100851B2/en
Publication of WO2018074607A1 publication Critical patent/WO2018074607A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present disclosure relates to a thin film transistor, a manufacturing method thereof, and a gate insulating film forming solution for a thin film transistor.
  • Patent Documents 1 and 2 disclose a thin film transistor including a gate insulating layer between a gate electrode and a channel.
  • a material for the gate insulating layer an oxide composed of lanthanum and zirconium is used. Further, the firing temperature is set to about 400 ° C. when forming the gate insulating layer.
  • the process temperature needs to be 200 ° C. or lower.
  • the thin film transistor when the thin film transistor is applied to, for example, a high-definition or large-area display, high field effect mobility is required for driving the thin film transistor.
  • An object of the present disclosure is to provide a thin film transistor having good transistor characteristics (particularly, high field effect mobility). Another object of the present invention is to provide a method for manufacturing a thin film transistor having a process temperature of 200 ° C. or lower. Furthermore, it is to provide a gate insulating film forming solution for a thin film transistor that can be used in the manufacturing method.
  • the thin film transistor of the present disclosure includes a gate electrode, a gate insulating layer, and an oxide semiconductor layer in this order, and the gate insulating layer includes cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), Europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), and yttrium (Y)
  • the method of manufacturing a thin film transistor according to the present disclosure includes a step of applying a gate insulating film forming solution on the gate electrode to form a gate insulating film, and an oxygen-containing environment on the surface of the gate insulating film.
  • a step of forming a film, and a step of baking the oxide semiconductor film at 180 to 200 ° C. while irradiating the surface of the oxide semiconductor film with ultraviolet rays to form an oxide semiconductor layer is a step of applying a gate insulating film forming solution on the gate electrode to form a gate insulating film, and an oxygen-containing environment on the surface of the gate insulating film.
  • the insulating film forming solution contains lanthanum (La), zirconium (Zr), and acetylacetonate, and the atomic ratio between lanthanum (La) and zirconium (Zr) is lanthanum (La).
  • the number of atoms is 1, it is a solution (i) in which the number of zirconium (Zr) atoms is 0.8 or more, cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm) , Europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), and yttrium (Y)
  • the gate insulating film forming solution for a thin film transistor of the present disclosure includes lanthanum (La), zirconium (Zr), and acetylacetonate, and the atomic ratio of lanthanum (La) and zirconium (Zr) is When the number of atoms of lanthanum (La) is 1, it is a solution (i) in which the number of zirconium (Zr) atoms is 0.8 or more, cerium (Ce), praseodymium (Pr), neodymium (Nd) , Samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu) And a metal element selected from the group consisting of yttrium (Y), zirconium (Zr), and acet
  • the thin film transistor of the present disclosure has good transistor characteristics (particularly high field effect mobility). Further, according to the method of the present disclosure, a thin film transistor can be manufactured at a process temperature of 200 ° C. or lower. For this reason, the thin film transistor and the manufacturing method thereof of the present disclosure can be applied to a wide range of uses such as a flexible display.
  • FIG. 1A is a step of forming a gate electrode on the substrate
  • FIG. (C) is a step of heating the gate insulating film formed in (b) while irradiating with ultraviolet rays to form a gate insulating layer
  • (d) is an oxide semiconductor film on the gate insulating layer
  • (E) is a step in which the oxide semiconductor film formed in (d) is heated while being irradiated with ultraviolet rays to form an oxide semiconductor layer
  • (f) is a step on the oxide semiconductor layer.
  • (G) is a step of forming a resist film over part of the oxide semiconductor layer, the source electrode, and the drain electrode
  • (h) is a step of forming (g).
  • Etching a laminated body having a resist film Ri indicates the step of obtaining a thin film transistor. It is a figure which shows the result of having measured the ultraviolet light absorbency of the gate insulating film formation solution. It is a diagram showing the V G -I D characteristic and V G -I G characteristics of the thin film transistor in Example 2.
  • V G -I D characteristic and V G -I G characteristics of the thin film transistor of Comparative Example 3 is a diagram showing a. It is a diagram showing the V G -I D characteristic and V G -I G characteristics of the thin film transistor of Comparative Example 4.
  • the thin film transistor of the present disclosure includes a gate electrode, a gate insulating layer, and an oxide semiconductor layer in this order.
  • the gate insulating layer includes lanthanum (La) and zirconium (Zr), and the atomic ratio of lanthanum (La) to zirconium (Zr) is set to 1 for the number of lanthanum (La) atoms.
  • zirconium (Zr) is formed from an oxide having 0.8 or more atoms.
  • the gate insulating layer is formed of cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho). ), Erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), and yttrium (Y), and zirconium (Zr).
  • Ce cerium
  • Pr praseodymium
  • Nd neodymium
  • Sm samarium
  • Eu europium
  • Gd gadolinium
  • Tb terbium
  • Dy dysprosium
  • Ho holmium
  • Er Er
  • Tm thulium
  • Yb lutetium
  • Lu yttrium
  • Y zirconium
  • the gate insulating layer is formed of an oxide containing at least one metal element selected from the group consisting of hafnium (Hf), zirconium (Zr), and aluminum (Al).
  • the oxide semiconductor layer includes an oxide containing indium (In), an oxide containing indium (In) and tin (Sn), an oxide containing indium (In) and zinc (Zn), and indium (In ), Zirconium (Zr) and zinc (Zn) -containing oxide, indium (In) and gallium (Ga) oxide, and indium (In), zinc (Zn) and gallium (Ga). It is formed from an oxide selected from the group of oxides.
  • FIG. 1 is a cross-sectional view schematically showing an example of the thin film transistor of this embodiment.
  • the thin film transistor 10 shown in the figure includes a gate electrode 14, a gate insulating layer 16, an oxide semiconductor layer 18, a source electrode 32, and a drain electrode 34 in this order on a substrate 12.
  • the thin film transistor 10 shown in FIG. 1 has a bottom gate structure, it is not limited to this structure.
  • other structures such as a top gate structure may be used.
  • the patterning of the extraction electrode from each electrode is not shown.
  • substrate 12 As the substrate 12, a substrate used in a known thin film transistor can be applied.
  • the substrate 12 examples include a high heat-resistant glass, a SiO 2 / Si substrate (a substrate in which a silicon oxide film is formed on a silicon substrate), an alumina (Al 2 O 3 ) substrate, an STO (SrTiO) substrate, and a Si substrate. Insulating substrates and semiconductor substrates (for example, Si substrates, SiC substrates, Ge substrates) in which an STO (SrTiO) layer is formed via an SiO 2 layer and a Ti layer are included. Further, a plastic substrate made of a resin such as polyethylene naphthalate (PEN), polycarbonate (PC), polyimide (PI), or a flexible substrate such as paper is also included.
  • PEN polyethylene naphthalate
  • PC polycarbonate
  • PI polyimide
  • Gate electrode 14 As the gate electrode 14, a gate electrode used in a known thin film transistor can be adopted.
  • the material of the gate electrode 14 include metal materials such as refractory metals such as platinum, gold, silver, copper, titanium, aluminum, molybdenum, palladium, ruthenium, iridium, and tungsten, or alloys thereof, or indium tin. Oxide (ITO) or ruthenium oxide (RuO 2 ) can be used.
  • the gate insulating layer 16 is formed from an oxide containing a specific metal element.
  • the oxide containing a specific metal element is an oxide containing lanthanum (La) and zirconium (Zr) (hereinafter also simply referred to as “oxide (i)”), cerium (Ce), praseodymium ( Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium ( Yb), lutetium (Lu), and a metal element selected from the group consisting of yttrium (Y) and an oxide containing zirconium (Zr) (hereinafter also simply referred to as “oxide (ii)”), At least one metal element selected from the group consisting of hafnium (Hf), zirconium (Zr), and aluminum (Al) Oxides containing (hereinafter, simply referred to as
  • the “oxide containing a specific metal element” typically means an oxide containing a specific metal element as a main component, but the oxide contains impurities (for example, impurities derived from raw materials). ) May be included.
  • the content of impurities other than carbon and hydrogen in the oxide is preferably 0.2% by mass or less.
  • the oxide containing a specific metal element is oxide (i)
  • the atomic ratio of lanthanum (La) and zirconium (Zr) is set to 1 as the number of atoms of lanthanum (La)
  • the number of zirconium (Zr) atoms is 0.8 or more, preferably 0.8 to 10, and more preferably 1.5 to 4.
  • the atomic ratio between the metal element selected from the specific group and zirconium (Zr) is from the viewpoint of obtaining good transistor performance.
  • the number of atoms of the metal element is 1, the number of zirconium (Zr) atoms is 1.5 or more, preferably 1.5 to 9, and more preferably 2.3 to 9.
  • the atomic ratio can be obtained by performing elemental analysis using Rutherford backscattering spectroscopy (RBS method).
  • the content of carbon (C) in the gate insulating layer 16 is not particularly limited, but is preferably 0.5 atom% to 20 atom% from the viewpoint of obtaining good transistor performance.
  • the thickness of the gate insulating layer 16 is not particularly limited, but is preferably 30 nm to 500 nm from the viewpoint of reducing the operating voltage while suppressing leakage.
  • the oxide semiconductor layer 18 includes an oxide containing indium (In), an oxide containing indium (In) and tin (Sn), an oxide containing indium (In) and zinc (Zn), and indium (In). , An oxide containing zirconium (Zr) and zinc (Zn), an oxide containing indium (In) and gallium (Ga), and an oxide containing indium (In), zinc (Zn) and gallium (Ga) Formed from an oxide selected from the group consisting of:
  • the “oxide containing indium (In)” typically means an oxide containing indium (In) as a main component, but the oxide contains impurities (for example, impurities derived from raw materials). ) May be included.
  • the content of impurities other than carbon and hydrogen in the oxide is preferably 0.2% by mass or less.
  • the content of carbon (C) in the oxide semiconductor layer 18 is preferably 0.2 atom% to 15.0 atom% from the viewpoint of obtaining good transistor performance.
  • the content of hydrogen (H) in the oxide semiconductor layer 18 is preferably 1 atom% to 20 atom%. The same applies to the other five oxides.
  • the atomic ratio of indium (In) to tin (Sn) in the oxide semiconductor layer 18 is set so that the number of atoms of indium (In) is 1.
  • the number of tin (Sn) atoms be 0.005 to 0.03.
  • the atomic ratio of indium (In) to zinc (Zn) in the oxide semiconductor layer 18 is such that the number of atoms of indium (In) is 1.
  • the number of zinc (Zn) atoms is preferably 0.1 to 1.0.
  • the atomic ratio of indium (In), zirconium (Zr), and zinc (Zn) in the oxide semiconductor layer 18 is
  • the number of atoms of indium (In) is 1, it is not particularly limited, but from the viewpoint of obtaining good transistor performance, the number of zirconium (Zr) atoms is 0.005 to 0.03, zinc ( The number of atoms of Zn) is preferably 0.1 to 1.0.
  • the atomic ratio of indium (In) to gallium (Ga) in the oxide semiconductor layer 18 is such that the number of atoms of indium (In) is 1.
  • gallium (Ga) is preferably 0.1 to 1.0 from the viewpoint of obtaining good transistor performance.
  • the atomic ratio of indium (In), zinc (Zn), and gallium (Ga) in the oxide semiconductor layer 18 is
  • the number of atoms of indium (In) is 1, it is not particularly limited, but from the viewpoint of obtaining good transistor performance, zinc (Zn) is 0.1 to 1.0 and gallium (Ga) is 0. 1 to 1.2 is preferable.
  • the thickness of the oxide semiconductor layer 18 is not particularly limited, but is preferably 10 nm to 100 nm from the viewpoint of securing a sufficient operating current and realizing a thin film.
  • Source electrode and drain electrode 34 As the source electrode 32 and the drain electrode 34, the source electrode 32 and the drain electrode 34 used in a known thin film transistor can be adopted.
  • the material of the source electrode 32 and the drain electrode 34 is not limited, but for example, indium tin oxide (ITO), ruthenium oxide (RuO 2 ), molybdenum (Mo), platinum (Pt), or the like is used. it can.
  • the thin film transistor 10 includes lanthanum (La) and zirconium (Zr), and the atomic ratio of lanthanum (La) and zirconium (Zr) is equal to 1 in the number of lanthanum (La) atoms.
  • the number of atoms of zirconium (Zr) is 0.8 or more, it is formed of an oxide or contains a specific rare earth metal element and zirconium (Zr), and the number of atoms of the rare earth metal element Is formed from an oxide having zirconium (Zr) atoms of 1.5 or more, or from the group consisting of hafnium (Hf), zirconium (Zr), and aluminum (Al)
  • a gate insulating layer 16 formed of an oxide containing at least one selected metal element is included.
  • the thin film transistor 10 includes an oxide semiconductor layer 18 formed from a specific oxide containing indium (In). Thereby, the thin film transistor 10 of the present disclosure has good electrical characteristics, in particular, high field effect mobility.
  • the method of manufacturing a thin film transistor of the present disclosure includes a step of applying a gate insulating film forming solution on a gate electrode to form a gate insulating film, and irradiating the surface of the gate insulating film with ultraviolet light in an environment containing oxygen.
  • the gate insulating film is baked at 180 to 200 ° C. to form the gate insulating layer, and the oxide semiconductor film forming solution is applied on the gate insulating layer to form the oxide semiconductor film.
  • FIG. 2A and 2B are cross-sectional views sequentially showing each step of the method of manufacturing the thin film transistor 10 shown in FIG. 1, wherein FIG. 2A is a step of forming the gate electrode 14 on the substrate 12, and FIG. (C) is a step of heating the gate insulating film 16 ′ formed in (b) while irradiating it with ultraviolet rays to form a gate insulating layer 16; (d) ) Is a step of forming the oxide semiconductor film 18 ′ on the gate insulating layer 16, and (e) is a step of heating the oxide semiconductor film 18 ′ formed in (d) while irradiating with ultraviolet rays, thereby
  • the step of forming the semiconductor layer 18, (f) is the step of forming the source electrode 32 and the drain electrode 34 on the oxide semiconductor layer 18, and (g) is the part of the oxide semiconductor layer 18, the source electrode 32.
  • the resist film 3 on the drain electrode 34 Forming a, (h) shows the step of obtaining a thin film transistor 10.
  • This step is a step of forming the gate electrode 14 on the substrate 12 (FIG. 2A).
  • a cleaned substrate 12 It is preferable to use a cleaned substrate 12, and any known method such as plasma ashing using oxygen gas can be adopted as the cleaning method.
  • any known method such as a vacuum deposition method (for example, a sputtering method) can be employed.
  • This step is a step of forming a gate insulating film 16 ′ by applying a gate insulating film forming solution on the gate electrode 14 (FIG. 2B).
  • the coating method of the gate insulating film forming solution is not limited, but for example, spin coating method, dip coating method, die coating method, bar coating method, blade coating method, roll coating method, spray coating method, capillary coating method
  • a known method such as a nozzle coating method, an ink jet method, a screen printing method, a gravure printing method, a flexographic printing method, a relief printing, or a reverse offset printing can be used.
  • the gate insulating film forming solution contains lanthanum (La), zirconium (Zr), and acetylacetonate, and the atomic ratio of lanthanum (La) and zirconium (Zr) is the number of atoms of lanthanum (La).
  • the irradiation temperature of about 400 ° C. which has been conventionally applied, is set to 200 ° C. or less by using ultraviolet irradiation together with heating.
  • the gate insulating film forming solution of the present disclosure contributes to reduction of the firing temperature of the gate insulating film and improvement of the transistor characteristics of the TFT.
  • the gate insulating film forming solution can be prepared as follows.
  • a predetermined metal compound is dissolved in a solvent to prepare a solution having a predetermined molar concentration (for example, 0.2 mol / kg). Can do.
  • a solution having a predetermined molar concentration for example, 0.2 mol / kg.
  • the gate insulating film forming solution can be prepared by mixing so that the atomic ratio is Alternatively, a gate insulating film forming solution may be prepared by adding and dissolving two or more kinds of metal compounds in a solvent so that the metal element has a predetermined atomic ratio.
  • a gate insulating film forming solution can be prepared by adding acetylacetonate to the solution.
  • purification for example, filtration with a filter suitably.
  • dissolving a metal compound in a solvent you may heat suitably.
  • a lanthanum compound and a zirconium compound can be used as the metal compound.
  • the lanthanum compound include lanthanum acetylacetonate, lanthanum alkoxide, and organic acid salt of lanthanum.
  • zirconium compounds include zirconium acetylacetonate, zirconium nitrate, zirconium chloride, or zirconium alkoxide (eg, zirconium isopropoxide, zirconium butoxide, zirconium ethoxide, zirconium methoxyethoxide).
  • examples of the metal compound include metal acetylacetonate and acetate.
  • the metal is cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho). , Erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), and a metal selected from the group consisting of yttrium (Y).
  • the zirconium compound include the same compounds as those used when preparing the solution (i).
  • zirconium, hafnium, and an aluminum compound can be used as the metal compound.
  • zirconium, hafnium, and aluminum compounds include the corresponding metal acetylacetonates, nitrates, chlorides, or alkoxides (eg, isopropoxide, butoxide, ethoxide, methoxyethoxide).
  • the solvent used at the time of preparing the gate insulating film forming solution is preferably a solvent that does not prevent acetylacetonate from coordinating to the metal-containing core.
  • solvents include, but are not limited to, alcohol solvents selected from the group of ethanol, propanol, butanol, 2-methoxyethanol, 2-ethoxyethanol, and 2-butoxyethanol. it can.
  • the gate insulating film forming solution described above it is preferable to subject the gate insulating film forming solution described above to heat treatment in a hermetically sealed container from the viewpoints of cluster formation, uniform structure, and ultraviolet absorption efficiency.
  • the heat treatment in the sealed container can be performed, for example, by transferring the gate insulating film forming solution to a pressure-resistant container such as an autoclave and at a temperature not lower than the boiling point of the solvent (for example, 150 to 200 ° C.).
  • zirconium can be replaced with tantalum.
  • This step is a step of forming the gate insulating layer 16 by heating the gate insulating film 16 ′ while irradiating the surface of the gate insulating film 16 ′ of the stacked body 20 ′ formed in the step (b) with ultraviolet rays. (FIG. 2 (c)).
  • the ultraviolet irradiation is preferably performed uniformly over the entire surface of the gate insulating film 16 ′ in order to form a uniform gate insulating layer 16 with little unevenness.
  • the illuminance of the ultraviolet rays to be irradiated is not particularly limited when the solution (i) is used as the gate insulating film forming solution, but can be 7.0 to 12.0 mW / cm 2 .
  • the solution (ii) or solution (iii) is used as the gate insulating film forming solution, it is preferably 5.0 to 15.0 mW / cm 2 , more preferably 7.0 to 12.0 mW / cm 2 . is there.
  • the illuminance of the ultraviolet rays irradiated in this step can be lowered to the same level as the illuminance used in a general surface cleaning UV apparatus. This is because a high illuminance is not required because the ultraviolet absorption of the gate insulating film 16 ′ is high.
  • the heating method of the laminated body 20 ′ is not particularly limited.
  • the laminated body 20 ′ can be installed so that the surface of the substrate 12 is in contact with the heating surface of the heater.
  • initial heating is first performed at 80 to 170 ° C. and then baking is performed at 180 to 200 ° C. in an environment containing oxygen such as the air.
  • the initial heating is mainly intended to evaporate the solvent contained in the gate insulating film 16 '.
  • the gate insulating layer 16 may be formed of a plurality of layers. In the case of forming a plurality of layers, the step of forming the gate insulating film 16 'in the step (b) and the above series of initial heating and baking operations may be repeated a plurality of times.
  • This step is a step of applying the oxide semiconductor film forming solution onto the gate insulating layer 16 to form the oxide semiconductor film 18 ′ (FIG. 2D).
  • the application method of the oxide semiconductor film forming solution is not limited, but spin coating, dip coating, die coating, bar coating, blade coating, roll coating, spray coating, capillary coating, Known methods such as a nozzle coating method, an inkjet method, a screen printing method, a gravure printing method, a flexographic printing method, a relief printing, and a reverse offset printing can be used.
  • the oxide semiconductor film formation solution includes indium (In), indium (In) and tin (Sn), indium (In) and zinc (Zn), indium (In), zirconium (Zr), zinc (Zn), indium ( A metal element selected from the group consisting of In), gallium (Ga), indium (In), zinc (Zn), and gallium (Ga), and an oxidizing agent.
  • the oxide semiconductor film forming solution can be prepared, for example, as follows.
  • an indium (In) compound and optionally an oxidizing agent are dissolved in a solvent to obtain a predetermined molar concentration (for example, 0.2 mol / kg).
  • An indium (In) solution is prepared.
  • an indium (In) compound and a tin (Sn) compound, and optionally an oxidizing agent are dissolved in a solvent
  • An indium (In) / tin (Sn) solution having a predetermined molar concentration (for example, 0.2 mol / kg) is prepared.
  • an indium (In) compound and a zinc (Zn) compound, and optionally an oxidizing agent are dissolved in a solvent
  • An indium (In) / zinc (Zn) solution having a predetermined molar concentration for example, 0.2 mol / kg is prepared.
  • the oxide semiconductor film 18 ′ containing indium (In), zirconium (Zr), and zinc (Zn), an indium (In) compound, a zirconium (Zr) compound, a zinc (Zn) compound, and a case
  • the oxidizing agent is dissolved in a solvent to prepare an indium (In) / zirconium (Zr) / zinc (Zn) solution having a predetermined molar concentration (for example, 0.2 mol / kg).
  • an indium (In) compound and a gallium (Ga) compound, and optionally an oxidizing agent are dissolved in a solvent
  • An indium (In) / gallium (Ga) solution having a predetermined molar concentration (for example, 0.2 mol / kg) is prepared.
  • an indium (In) compound, a zinc (Zn) compound, a gallium (Ga) compound, and an oxidizing agent is dissolved in a solvent to prepare an indium (In) / zinc (Zn) / gallium (Ga) solution having a predetermined molar concentration (for example, 0.2 mol / kg).
  • indium (In) compounds include indium nitrate, indium acetylacetonate, indium acetate, indium chloride, or indium alkoxide (eg, indium isopropoxide, indium butoxide, indium ethoxide, indium methoxyethoxide). Can do.
  • tin (Sn) compounds include tin chloride, tin nitrate, tin acetate, or tin alkoxide (eg, tin isopropoxide, tin butoxide, tin ethoxide, tin methoxyethoxide).
  • Examples of zinc (Zn) compounds include zinc chloride, zinc nitrate, zinc acetate, or zinc alkoxide (for example, zinc isopropoxide, zinc butoxide, zinc ethoxide, zinc methoxyethoxide).
  • zirconium compounds include zirconium nitrate, zirconium chloride, or zirconium alkoxide (eg, zirconium isopropoxide, zirconium butoxide, zirconium ethoxide, zirconium methoxyethoxide).
  • gallium (Ga) compounds include gallium nitrate, gallium chloride, gallium acetate, gallium acetylacetonate or gallium alkoxide (gallium methoxide, gallium ethoxide, gallium propoxide, gallium butoxide).
  • the solvent used for the oxide semiconductor film forming solution is not particularly limited.
  • an alcohol solvent selected from the group of 2-methoxyethanol, ethanol, propanol, butanol, 2-ethoxyethanol, 2-butoxyethanol
  • a solvent of carboxylic acid selected from the group of acetic acid, propionic acid and octylic acid, or water can be employed. From the viewpoint of improving the characteristics of the TFT, it is preferable to use water as the solvent.
  • oxidizing agent used in the oxide semiconductor film forming solution examples include, but are not limited to, nitric acid, nitrate, peroxide, or perchlorate.
  • nitric acid examples include, but are not limited to, nitric acid, nitrate, peroxide, or perchlorate.
  • indium nitrate is used as the indium (In) compound when preparing the oxide semiconductor film forming solution, it is not necessary to add an oxidizing agent separately because it is itself a nitrate.
  • the oxide semiconductor film forming solution may contain a co-firing agent in order to adjust the firing temperature and firing strength of the solution.
  • co-firing agents include, but are not limited to, acetylacetone, acetylacetonate, urea, or ammonium acetate.
  • a solute When preparing the oxide semiconductor film forming solution, a solute may be added to the solvent and heated appropriately.
  • the oxide semiconductor film 18 ′ is heated while irradiating the surface of the oxide semiconductor film 18 ′ of the stacked body 30 ′ formed in the step (d) with ultraviolet rays, so that the oxide semiconductor layer 18 is formed. (FIG. 2 (e)).
  • Irradiation with ultraviolet rays is preferably performed uniformly over the entire surface of the oxide semiconductor film 18 ′ in order to form a uniform oxide semiconductor layer 18 without unevenness.
  • the illuminance of the ultraviolet rays to be irradiated is not particularly limited, but can be 5.0 to 15.0 mW / cm 2 , preferably 7.0 to 12.0 mW / cm 2 . In this way, the illuminance of the ultraviolet rays irradiated in this step can be lowered to the same level as the illuminance used in a general surface cleaning UV apparatus.
  • the heating method of the stacked body 30 ′ is not particularly limited, but for example, the stacked body 30 ′ can be installed so that the surface of the substrate 12 is in contact with the heating surface of the heater.
  • initial heating is first performed at 80 to 170 ° C. and then baking is performed at 180 to 200 ° C. in an environment containing oxygen such as the air.
  • the initial heating is mainly intended to evaporate the solvent contained in the oxide semiconductor film 18 '.
  • This step is a step of forming the source electrode 32 and the drain electrode 34 on the oxide semiconductor layer 18 (FIG. 2F).
  • any known method such as a lift-off method can be employed.
  • a resist film patterned by a photolithography method is formed on the oxide semiconductor layer 18, and a metal layer is formed on the oxide semiconductor layer 18 and the resist film by a sputtering method or the like. Thereafter, the source film 32 and the drain electrode 34 can be formed over the oxide semiconductor layer 18 by removing the resist film.
  • a commonly used lift-off layer material such as LOL2000 manufactured by Rohm and Haas and TSMR8900 manufactured by Tokyo Ohka Kogyo Co., Ltd. can be used.
  • the metal layer is formed of indium tin oxide (ITO)
  • ITO containing 5% by mass of tin oxide (SnO 2 ) can be used as the ITO layer target material.
  • the metal layer is, for example, when it is formed by ruthenium oxide (RuO 2) as the target material, it is possible to use ruthenium oxide (RuO 2).
  • This step is a step of forming a resist film 36 on part of the oxide semiconductor layer 18, the source electrode 32, and the drain electrode 34 (FIG. 2G).
  • the resist film 36 can be formed by patterning by a known method such as a photolithography method.
  • a resist material that is usually used for example, OMR85 manufactured by Tokyo Ohka Kogyo Co., Ltd. can be used.
  • the stacked body 40 including the resist film 36 formed in the step (g) is etched to remove the oxide semiconductor layer 18 not covered with the resist film 36, thereby obtaining the thin film transistor 10 (FIG. 2 (h)).
  • etching for example, a wet etching method using an etchant such as an etchant for ITO (ITO series manufactured by Kanto Chemical Co., Ltd.) or a dry etching method using argon plasma can be used.
  • an etchant such as an etchant for ITO (ITO series manufactured by Kanto Chemical Co., Ltd.) or a dry etching method using argon plasma can be used.
  • the thin film transistor 10 is preferably post-annealed in order to improve adhesion between the source electrode 32 and the drain electrode 34 and the oxide semiconductor layer 18.
  • the post-annealing is not particularly limited, but can be performed by heat treatment at 100 to 200 ° C., preferably 180 to 200 ° C. for 10 minutes or more using a heating means such as a heater.
  • a heating means such as a heater.
  • ultraviolet irradiation may be performed.
  • the illuminance of the ultraviolet rays is not particularly limited, but can be 5.0 to 15.0 mW / cm 2 , preferably 7.0 to 12.0 mW / cm 2 .
  • a thin film transistor can be manufactured at a process temperature of 200 ° C. or less. Therefore, for example, a TFT can be manufactured on a plastic substrate.
  • the method of the present disclosure can be applied to a wide range of applications such as a flexible display manufacturing application. Therefore, the realization of cost reduction can be expected.
  • Example 1 Lanthanum acetylacetonate and zirconium butoxide were added to 2-methoxyethanol so that the atomic ratio of lanthanum and zirconium was 3: 7, and the mixture was heated and stirred at 110 ° C. for 30 minutes. Next, the obtained solution was transferred to a pressure vessel, heated to 160 ° C., held for 1 hour, and then returned to room temperature to prepare a 0.1 mol / kg lanthanum / zirconium mixed solution. Thereafter, filtration was performed with a 0.2 um PTFE filter to obtain a gate insulating film forming solution (Example 1).
  • the obtained gate insulating film forming solution was transferred to an autoclave and heated until the internal temperature reached 180 ° C. In this state, it was held for 5 hours, and the inside of the container was returned to room temperature to obtain an autoclaved gate insulating film forming solution (Comparative Example 2).
  • UV absorbance measurement The ultraviolet absorbance of the prepared gate insulating film forming solution was measured using an ultraviolet-visible spectrophotometer (V-630 UV-visible spectrophotometer manufactured by JASCO International Co., Ltd.). The result is shown in FIG.
  • the gate insulating film forming solution (Example 1) had higher absorbance values in the ultraviolet wavelength region than the gate insulating film forming solutions (Comparative Example 1) and (Comparative Example 2).
  • the gate insulating film forming solution (Example 1) absorbs ultraviolet rays more than the gate insulating film forming solutions (Comparative Example 1) and (Comparative Example 2).
  • Example 1 Comparative Example 1 and Comparative Example 2, only the anion and / or solvent of the compound is different, and therefore the type of anion and / or solvent coordinated to the La—O—Zr core is different from that of the solution. It is thought to affect the ultraviolet absorption.
  • Example 1 lanthanum acetylacetonate is used as the lanthanum compound.
  • Acetylacetonate is widely known as a bidentate ligand that coordinates to many metal ions, and it is considered that acetylacetonate is preferentially coordinated to the core even in this solution.
  • the gate insulating film forming solution does not contain acetylacetonate.
  • the gate insulating film forming solution of Example 1 absorbed ultraviolet rays more than Comparative Example 1 and Comparative Example 2 because it contained acetylacetonate.
  • Example 2 Using the gate insulating film forming solution prepared in Example 1, a thin film transistor was manufactured as follows.
  • a gate electrode made of a titanium / platinum (Ti / Pt) layer was formed on a cleaned Si wafer substrate by a sputtering method.
  • the substrate surface on which the titanium / platinum (Ti / Pt) layer was formed was subjected to ashing treatment with oxygen plasma (15 W for 180 seconds).
  • the gate insulating film forming solution prepared in Example 1 was applied onto the gate electrode layer by spin coating (rotation speed: 2000 rpm, rotation time: 25 seconds) to form a gate insulating film.
  • the stacked body on which the gate insulating film is formed is allowed to stand on a hot plate set at 150 ° C. for 5 minutes and heated, and then the temperature is increased to 200 ° C.
  • the whole surface of the gate insulating film was irradiated with ultraviolet rays of 10 mW / cm 2 for 60 minutes to form a gate insulating layer.
  • UV irradiation was performed using a UV ozone cleaner (Samco UV-300H-E).
  • an oxide semiconductor film forming solution was applied over the gate insulating layer by a spin coating method (rotation speed: 3000 rpm, rotation time: 30 seconds).
  • the obtained laminate was allowed to stand on a hot plate set at 150 ° C. for 5 minutes and heated, and then the temperature was increased to 200 ° C., and the illuminance was 10 mW / cm 2 while heating at the same temperature.
  • the entire surface of the oxide semiconductor film was irradiated with ultraviolet rays for 60 minutes to form an oxide semiconductor layer.
  • UV irradiation was performed using a UV ozone cleaner (Samco UV-300H-E).
  • the thickness of the oxide semiconductor layer was 20 nm.
  • indium nitrate and zinc nitrate were added to 2-methoxyethanol so that the atomic ratio of indium to zinc was 8: 1, and the temperature was 110 ° C. and the rotation speed was 1000 rpm for 30 minutes. , And an indium / zinc solution prepared at 0.2 mol / kg was used.
  • a source electrode and a drain electrode were formed on the obtained oxide semiconductor layer by a lift-off method.
  • a resist film is formed by photolithography for element isolation (patterning of the oxide semiconductor layer), and the obtained laminate is wet etched using ITO-07 (an ITO etchant manufactured by Kanto Chemical Co., Inc.). Etched.
  • the obtained laminate was heated on a hot plate at 200 ° C. for 10 minutes to produce a thin film transistor.
  • Comparative Example 3 A thin film transistor was produced in the same manner as in Example 2 except that the gate insulating film forming solution prepared in Comparative Example 1 was used instead of the gate insulating film forming solution prepared in Example 1.
  • Comparative Example 4 A thin film transistor was fabricated in the same manner as in Example 2, except that the gate insulating film forming solution prepared in Comparative Example 2 was used instead of the gate insulating film forming solution prepared in Example 1.
  • a gate insulating film forming solution containing lanthanum (La), zirconium (Zr), and acetylacetonate is used for manufacturing a TFT, so that a TFT having good electrical characteristics can be obtained at a process temperature of 200 ° C. It was confirmed that it could be manufactured.
  • TFTs were manufactured from the gate insulating film forming solution, and more detailed electrical characteristics were evaluated.
  • a gate insulating film forming solution was applied onto the gate electrode layer by spin coating (rotation speed: 2000 rpm, rotation time: 25 seconds) to form a gate insulating film.
  • the gate insulating film forming solution was prepared as follows. First, lanthanum acetylacetonate and zirconium butoxide were added to 2-methoxyethanol so that the atomic ratio of lanthanum and zirconium was 3: 7, and the mixture was heated and stirred at 110 ° C. for 30 minutes. Next, this solution was transferred to a pressure vessel, heated to 160 ° C., held for 1 hour, and then returned to room temperature to prepare a 0.1 mol / kg lanthanum / zirconium mixed solution. Thereafter, filtration was performed with a 0.2 um PTFE filter to obtain a gate insulating film forming solution.
  • the stacked body on which the gate insulating film is formed is allowed to stand on a hot plate set at 150 ° C. for 5 minutes and heated, and then the temperature is increased to 200 ° C.
  • the whole surface of the gate insulating film was irradiated with ultraviolet rays of 10 mW / cm 2 for 60 minutes to form a gate insulating layer.
  • an oxide semiconductor film forming solution was applied over the gate insulating layer by a spin coating method (rotation speed: 3000 rpm, rotation time: 30 seconds).
  • the obtained laminate was allowed to stand on a hot plate set at 100 ° C. for 5 minutes and heated, and then the temperature was increased to 200 ° C., and the illuminance was 10 mW / cm 2 while heating at the same temperature.
  • the entire surface of the oxide semiconductor film was irradiated with ultraviolet rays for 60 minutes to form an oxide semiconductor layer.
  • the thickness of the oxide semiconductor layer was 20 nm.
  • an indium solution prepared by adding indium nitrate to water and stirring at 110 ° C. and a rotation speed of 1000 rpm for 30 minutes to adjust to 0.1 mol / kg was used.
  • a source electrode and a drain electrode were formed on the obtained oxide semiconductor layer by a lift-off method.
  • a resist film is formed by photolithography for element isolation (patterning of the oxide semiconductor layer), and the obtained laminate is wet etched using ITO-07 (an ITO etchant manufactured by Kanto Chemical Co., Inc.). Etched.
  • the obtained laminate was allowed to stand on a hot plate at 200 ° C. and heated for 10 minutes while irradiating ultraviolet rays having an illuminance of 10 mW / cm 2 , thereby producing a thin film transistor.
  • the thin film transistor of Example 3 had good transistor characteristics.
  • the field effect mobility ( ⁇ ) was 2 cm 2 / Vs or more, and the gate leakage current was as good as 8.1 ⁇ 10 ⁇ 10 A.
  • the thin film transistor has good transistor characteristics. It was.
  • the electrical characteristics of the thin film transistor were measured when a solution (ii) and a solution (iii) containing other specific metal elements and acetylacetonate were used as the gate insulating film forming solution. First, the results when using the solution (ii) are shown below.
  • Example 4 First, a gate electrode made of a titanium / platinum (Ti / Pt) layer was formed on a cleaned Si wafer substrate by sputtering. Next, the substrate surface on which the titanium / platinum (Ti / Pt) layer was formed was subjected to ashing treatment with oxygen plasma (15 W for 180 seconds).
  • Ag paste was formed at the four corners of the substrate in order to form gate electrode contact regions.
  • a gate insulating film forming solution was applied onto the gate electrode layer by spin coating (rotation speed: 2000 rpm, rotation time: 25 seconds) to form a gate insulating film.
  • a gate insulating film forming solution was prepared as follows. First, samarium acetylacetonate and zirconium acetylacetonate were added to 2-methoxyethanol so that the atomic ratio of samarium and zirconium was 1: 9, and the mixture was stirred with heating at 110 ° C. for 30 minutes, 0.1 mol / wt. kg of samarium / zirconium solution was obtained.
  • the obtained solution was transferred to a pressure vessel, heated to 160 ° C., held for 1 hour, and then returned to room temperature to prepare a 0.1 mol / kg samarium / zirconium solution. Thereafter, filtration was performed with a 0.2 um PTFE filter to obtain a gate insulating film forming solution.
  • the stacked body on which the gate insulating film is formed is allowed to stand on a hot plate set at 150 ° C. for 5 minutes and heated, and then the temperature is increased to 200 ° C.
  • the entire surface of the gate insulating film was irradiated with ultraviolet rays of 10.0 mW / cm 2 for 60 minutes to form a gate insulating layer.
  • UV irradiation was performed using a UV ozone cleaner (Samco UV-300H-E).
  • an oxide semiconductor film forming solution is applied onto the gate insulating layer by a spin coating method (rotation speed: 3000 rpm, rotation time: 30 seconds), and the obtained stacked body is placed on a hot plate set at 150 ° C. After standing and heating for 5 minutes, the temperature was raised to 200 ° C., and the surface of the oxide semiconductor film was irradiated with ultraviolet rays having an illuminance of 10.0 mW / cm 2 for 60 minutes while heating at the same temperature. An oxide semiconductor layer (InZnO layer) was formed. Here, UV irradiation was performed using a UV ozone cleaner (Samco UV-300H-E). The thickness of the oxide semiconductor layer was 15 nm.
  • indium nitrate and zinc nitrate were added to 2-methoxyethanol so that the atomic ratio of indium to zinc was 8: 1, and the solution was 30 ° C. at 110 ° C. and 1000 rpm.
  • a mixture prepared by stirring for 0.2 minutes to 0.2 mol / kg was used.
  • a source electrode and a drain electrode were formed on the oxide semiconductor layer by a lift-off method.
  • a resist film is formed by photolithography, and the obtained laminate is wet-etched using ITO-02 (an ITO etchant manufactured by Kanto Chemical Co., Inc.). Etched.
  • the obtained laminate was allowed to stand on a hot plate at 200 ° C. and heated for 10 minutes while irradiating ultraviolet rays having an illuminance of 10.0 mW / cm 2 , thereby producing a thin film transistor.
  • UV irradiation was performed using a UV ozone cleaner (Samco UV-300H-E).
  • Example 5 A thin film transistor was prepared in the same manner as in Example 4 except that samarium acetylacetonate and zirconium acetylacetonate were added so that the atomic ratio of samarium to zirconium was 2: 8 when the gate insulating film forming solution was prepared. Was made.
  • Example 6 A thin film transistor was prepared in the same manner as in Example 4 except that samarium acetylacetonate and zirconium acetylacetonate were added so that the atomic ratio of samarium to zirconium was 3: 7 when the gate insulating film forming solution was prepared. Was made.
  • Example 7 Europium acetylacetonate is used instead of samarium acetylacetonate when preparing the gate insulating film forming solution, and zinc nitrate is not used when preparing the oxide semiconductor film forming solution, and water is used instead of 2-methoxyethanol.
  • a thin film transistor was fabricated in the same manner as in Example 4 except that it was used.
  • Example 8 When preparing the gate insulating film forming solution, europium acetylacetonate is used instead of samarium acetylacetonate, and europium acetylacetonate and zirconium acetylacetonate are mixed so that the atomic ratio of europium and zirconium is 2: 8.
  • a thin film transistor was produced in the same manner as in Example 4 except that zinc nitrate was not used in preparing the oxide semiconductor film forming solution and water was used instead of 2-methoxyethanol.
  • Example 9 When preparing the gate insulating film forming solution, europium acetylacetonate is used instead of samarium acetylacetonate, and europium acetylacetonate and zirconium acetylacetonate are mixed so that the atomic ratio of europium and zirconium is 3: 7.
  • a thin film transistor was produced in the same manner as in Example 4 except that zinc nitrate was not used in preparing the oxide semiconductor film forming solution and water was used instead of 2-methoxyethanol.
  • Example 10 When preparing the gate insulating film forming solution, yttrium acetate was used instead of samarium acetylacetonate, and yttrium acetate and zirconium acetylacetonate were added so that the atomic ratio of yttrium to zirconium was 1: 9.
  • a thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
  • Example 11 When preparing the gate insulating film forming solution, cerium acetate was used in place of samarium acetylacetonate, and cerium acetate and zirconium acetylacetonate were added so that the atomic ratio of cerium and zirconium was 1: 9.
  • a thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
  • Example 12 When preparing the gate insulating film forming solution, praseodymium acetate is used instead of samarium acetylacetonate, and praseodymium acetate and zirconium acetylacetonate are added so that the atomic ratio of praseodymium and zirconium is 1: 9, and oxidation is performed.
  • a thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
  • Example 13 When preparing the gate insulating film forming solution, neodymium acetate was used instead of samarium acetylacetonate, and neodymium acetate and zirconium acetylacetonate were added so that the atomic ratio of neodymium and zirconium was 1: 9.
  • a thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
  • Example 14 When preparing the gate insulating film forming solution, samarium acetate is used instead of samarium acetylacetonate, and samarium acetate and zirconium acetylacetonate are added so that the atomic ratio of samarium and zirconium is 1: 9.
  • a thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
  • Example 15 When preparing the gate insulating film forming solution, europium acetate is used instead of samarium acetylacetonate, and europium acetate and zirconium acetylacetonate are added so that the atomic ratio of europium and zirconium is 1: 9.
  • a thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
  • Example 16 When preparing the gate insulating film forming solution, gadolinium acetate was used instead of samarium acetylacetonate, gadolinium acetate and zirconium acetylacetonate were added so that the atomic ratio of gadolinium and zirconium was 1: 9, and oxidation was performed.
  • a thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
  • Example 17 When preparing the gate insulating film forming solution, terbium acetate was used instead of samarium acetylacetonate, terbium acetate and zirconium acetylacetonate were added so that the atomic ratio of terbium and zirconium was 1: 9, and oxidation was performed.
  • a thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
  • Example 18 When preparing the gate insulating film forming solution, dysprosium acetate was used instead of samarium acetylacetonate, and dysprosium acetate and zirconium acetylacetonate were added so that the atomic ratio of dysprosium and zirconium was 1: 9.
  • a thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
  • Example 19 When preparing the gate insulating film forming solution, holmium acetate was used instead of samarium acetylacetonate, and holmium acetate and zirconium acetylacetonate were added so that the atomic ratio of holmium and zirconium was 1: 9.
  • a thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
  • Example 20 When preparing the gate insulating film forming solution, erbium acetate was used instead of samarium acetylacetonate, and erbium acetate and zirconium acetylacetonate were added so that the atomic ratio of erbium and zirconium was 1: 9.
  • a thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
  • Example 21 When preparing the gate insulating film forming solution, thulium acetate is used instead of samarium acetylacetonate, and thulium acetate and zirconium acetylacetonate are added so that the atomic ratio of thulium and zirconium is 1: 9, and oxidation is performed.
  • a thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
  • Example 22 When preparing the gate insulating film forming solution, ytterbium acetate was used instead of samarium acetylacetonate, and ytterbium acetate and zirconium acetylacetonate were added so that the atomic ratio of ytterbium and zirconium was 1: 9.
  • a thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
  • Example 23 When preparing the gate insulating film forming solution, lutetium acetate was used instead of samarium acetylacetonate, and lutetium acetate and zirconium acetylacetonate were added so that the atomic ratio of lutetium and zirconium was 1: 9.
  • a thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
  • Example 24 When preparing the gate insulating film forming solution, europium acetylacetonate is used instead of samarium acetylacetonate, and europium acetylacetonate and zirconium acetylacetonate are mixed so that the atomic ratio of europium and zirconium is 4: 6.
  • a thin film transistor was fabricated in the same manner as in Example 4 except that the above was added.
  • Example 25 In preparing the oxide semiconductor film forming solution, gallium nitrate is used instead of zinc nitrate, indium nitrate and gallium nitrate are added so that the atomic ratio of indium to gallium is 8: 1, and 2-methoxy is added.
  • a thin film transistor was produced in the same manner as in Example 4 except that water was used instead of ethanol.
  • Example 26 When preparing the gate insulating film forming solution, samarium acetylacetonate and zirconium acetylacetonate are added so that the atomic ratio of samarium and zirconium is 1:99, and when preparing the oxide semiconductor film forming solution, zinc nitrate is added.
  • a thin film transistor was manufactured in the same manner as in Example 4 except that water was used instead of 2-methoxyethanol.
  • Example 27 When preparing the gate insulating film forming solution, samarium acetylacetonate and zirconium acetylacetonate are added so that the atomic ratio of samarium and zirconium is 4:96, and when preparing the oxide semiconductor film forming solution, zinc nitrate is added.
  • a thin film transistor was manufactured in the same manner as in Example 4 except that water was used instead of 2-methoxyethanol.
  • Example 28 During the preparation of the gate insulating film forming solution, samarium acetylacetonate and zirconium acetylacetonate are added so that the atomic ratio of samarium and zirconium is 8:92, and during the preparation of the oxide semiconductor film forming solution, zinc nitrate is added.
  • a thin film transistor was manufactured in the same manner as in Example 4 except that water was used instead of 2-methoxyethanol.
  • Example 5 A thin film transistor was prepared in the same manner as in Example 4 except that samarium acetylacetonate and zirconium acetylacetonate were added so that the atomic ratio of samarium to zirconium was 1: 1 when the gate insulating film forming solution was prepared. Was made.
  • the thin film transistors of Examples 4 to 28 having a ratio of 1: 1.5 to 1:99 had very good electrical characteristics.
  • a field effect mobility of approximately 50 cm 2 / vs or more is required for driving the thin film transistor. It met the requirements.
  • the thin film transistor of Comparative Example 5 was inferior in electrical characteristics as compared with Examples 4 to 28.
  • the oxide constituting the gate insulating layer when the atomic ratio of the metal element (Sm) and zirconium (Zr) is about 1: 1, the electrical characteristics are remarkably deteriorated.
  • the thin film transistors of Examples 4 to 28 had very good electrical characteristics even when manufactured at a process temperature of 200 ° C. From this, it is possible to apply the said thin-film transistor and its manufacturing method to wide uses, such as a flexible display use.
  • Example 29 a gate electrode made of a titanium / platinum (Ti / Pt) layer was formed on a cleaned Si wafer substrate by sputtering. Next, the substrate surface on which the titanium / platinum (Ti / Pt) layer was formed was subjected to ashing treatment with oxygen plasma (15 W for 180 seconds).
  • Ag paste was formed at the four corners of the substrate in order to form gate electrode contact regions.
  • a gate insulating film forming solution was applied onto the gate electrode layer by spin coating (rotation speed: 2000 rpm, rotation time: 25 seconds) to form a gate insulating film.
  • a gate insulating film forming solution was prepared as follows. First, zirconium acetylacetonate was added to 2-methoxyethanol, and the mixture was heated and stirred at 110 ° C. for 30 minutes to obtain a 0.4 mol / kg zirconium solution. Next, the obtained solution was transferred to a pressure vessel, heated to 160 ° C., held for 1 hour, and then returned to room temperature to prepare a 0.4 mol / kg zirconium solution. Thereafter, filtration was performed with a 0.2 um PTFE filter to obtain a gate insulating film forming solution.
  • the stacked body on which the gate insulating film is formed is allowed to stand on a hot plate set at 150 ° C. for 5 minutes and heated, and then the temperature is increased to 200 ° C.
  • the entire surface of the gate insulating film was irradiated with ultraviolet rays of 10.0 mW / cm 2 for 60 minutes to form a gate insulating layer.
  • UV irradiation was performed using a UV ozone cleaner (Samco UV-300H-E).
  • an oxide semiconductor film forming solution is applied onto the gate insulating layer by a spin coating method (rotation speed: 3000 rpm, rotation time: 30 seconds), and the obtained stacked body is placed on a hot plate set at 150 ° C. After standing and heating for 5 minutes, the temperature was raised to 200 ° C., and the surface of the oxide semiconductor film was irradiated with ultraviolet rays having an illuminance of 10.0 mW / cm 2 for 60 minutes while heating at the same temperature. An oxide semiconductor layer (InO layer) was formed. Here, UV irradiation was performed using a UV ozone cleaner (Samco UV-300H-E). The thickness of the oxide semiconductor layer was 15 nm. As the oxide semiconductor film forming solution, a solution prepared by adding indium nitrate to water and stirring at 110 ° C. and a rotation speed of 1000 rpm for 30 minutes to be 0.2 mol / kg was used.
  • a source electrode and a drain electrode were formed on the oxide semiconductor layer by a lift-off method.
  • a resist film is formed by photolithography, and the obtained laminate is wet-etched using ITO-02 (an ITO etchant manufactured by Kanto Chemical Co., Inc.). Etched.
  • the obtained laminate was allowed to stand on a hot plate at 200 ° C. and heated for 10 minutes while irradiating ultraviolet rays having an illuminance of 10.0 mW / cm 2 , thereby producing a thin film transistor.
  • UV irradiation was performed using a UV ozone cleaner (Samco UV-300H-E).
  • Example 30 A thin film transistor was fabricated in the same manner as in Example 29 except that hafnium acetylacetonate was used instead of zirconium acetylacetonate when preparing the gate insulating film forming solution.
  • Example 31 A thin film transistor was fabricated in the same manner as in Example 29 except that aluminum acetylacetonate was used instead of zirconium acetylacetonate when preparing the gate insulating film forming solution.
  • Example 32 A thin film transistor was fabricated in the same manner as in Example 29 except that in the preparation of the oxide semiconductor forming solution, indium nitrate and zinc nitrate were mixed so that the atomic ratio of indium to zinc was 8: 2.
  • Example 33 A thin film transistor was manufactured in the same manner as in Example 29 except that in the preparation of the oxide semiconductor forming solution, indium nitrate and gallium nitrate were mixed so that the atomic ratio of indium to gallium was 8: 2.
  • Example 34 Hafnium acetylacetonate is used in place of zirconium acetylacetonate when preparing the gate insulating film forming solution, and indium nitrate and zinc nitrate are used in the preparation of the oxide semiconductor forming solution, and the atomic ratio of indium and zinc is 8:
  • a thin film transistor was manufactured in the same manner as in Example 29 except that the mixing was performed so as to be 2.
  • Example 35 Hafnium acetylacetonate was used instead of zirconium acetylacetonate when preparing the gate insulating film forming solution, and when preparing the oxide semiconductor forming solution, the atomic ratio of indium and gallium was 8: A thin film transistor was manufactured in the same manner as in Example 29 except that the mixing was performed so as to be 2.
  • Example 36 A thin film transistor was prepared in the same manner as in Example 29 except that aluminum acetylacetonate and zirconium acetylacetonate were mixed so that the atomic ratio of aluminum to zirconium was 9: 1 when preparing the gate insulating film forming solution. was made.
  • Example 37 A thin film transistor was prepared in the same manner as in Example 29 except that aluminum acetylacetonate and zirconium acetylacetonate were mixed so that the atomic ratio of aluminum to zirconium was 7: 3 when preparing the gate insulating film forming solution. was made.
  • Example 38 A thin film transistor was prepared in the same manner as in Example 29 except that aluminum acetylacetonate and zirconium acetylacetonate were mixed so that the atomic ratio of aluminum to zirconium was 1: 1 at the time of preparing the gate insulating film forming solution. was made.
  • Example 39 A thin film transistor was prepared in the same manner as in Example 29 except that aluminum acetylacetonate and zirconium acetylacetonate were mixed so that the atomic ratio of aluminum to zirconium was 3: 7 when preparing the gate insulating film forming solution. was made.
  • Example 40 A thin film transistor was prepared in the same manner as in Example 29, except that aluminum acetylacetonate and zirconium acetylacetonate were mixed so that the atomic ratio of aluminum to zirconium was 1: 9 when the gate insulating film forming solution was prepared. Was made.
  • Example 41 A thin film transistor was prepared in the same manner as in Example 29 except that hafnium acetylacetonate and zirconium acetylacetonate were mixed so that the atomic ratio of hafnium and zirconium was 1: 1 at the time of preparing the gate insulating film forming solution. was made.
  • Example 42 A thin film transistor was obtained in the same manner as in Example 29 except that hafnium acetylacetonate and zirconium acetylacetonate were mixed so that the atomic ratio of hafnium and zirconium was 9: 1 at the time of preparing the gate insulating film forming solution. was made.
  • Example 43 Except for mixing the aluminum acetylacetonate, hafnium acetylacetonate, and zirconium acetylacetonate so that the atomic ratio of aluminum, hafnium, and zirconium was 1: 1: 1 during the preparation of the gate insulating film forming solution, A thin film transistor was fabricated in the same manner as in Example 29.
  • the thin film transistors of Examples 29 to 43 had very good electrical characteristics.
  • a field-effect mobility of approximately 50 cm 2 / vs or more is required for driving the thin film transistor. It met the requirements.
  • the thin film transistors of Examples 29 to 43 had very good electrical characteristics even when manufactured at a process temperature of 200 ° C. From this, it is possible to apply the said thin-film transistor and its manufacturing method to wide uses, such as a flexible display use.

Abstract

The purpose of the present invention is to provide: a thin-film transistor having excellent transistor characteristics; and a production method in which the process temperature is 200˚C or lower. This thin-film transistor is provided with: a gate insulation layer which is either formed from an oxide including Zr, and a metal element selected from the group consisting of Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and Y, the atomic ratio of the metal element to the zirconium being such that the number of atoms of Zr is 1.5 or higher when the number of atoms of the metal element is 1, or formed from an oxide including at least one metal element selected from the group consisting of Hf, Zr, and Al; and an oxide semiconductor layer which is formed from an oxide selected from the group consisting of oxides including In, oxides including In and Sn, oxides including In and Zn, oxides including In, Zr, and Zn, oxides including In and Ga, and oxides including In, Zn, and Ga.

Description

薄膜トランジスタおよびその製造方法、ならびに薄膜トランジスタ用ゲート絶縁膜形成溶液THIN FILM TRANSISTOR, ITS MANUFACTURING METHOD, AND GATE INSULATING FILM FORMING SOLUTION FOR THIN FILM TRANSISTOR
 本開示は、薄膜トランジスタおよびその製造方法、ならびに薄膜トランジスタ用ゲート絶縁膜形成溶液に関する。 The present disclosure relates to a thin film transistor, a manufacturing method thereof, and a gate insulating film forming solution for a thin film transistor.
 近年、ディスプレイ駆動用素子等に用いることを目的とした薄膜トランジスタ(以下、TFTとも称する)の研究が盛んに行われている。そのような研究として、酸化物TFTの開発も進められている。従来、酸化物TFTの製造方法としては、スパッタ法などの真空プロセスが主流であったが、高価な製造設備が必要になる等の問題が存在していた。これに対して、真空プロセスからスピンコート法などの溶液プロセスに転換して低コスト化を図る動きも高まりつつある。 In recent years, research on thin film transistors (hereinafter also referred to as TFTs) intended to be used for display driving elements has been actively conducted. As such research, the development of oxide TFTs is also in progress. Conventionally, vacuum processes such as sputtering have been the mainstream for manufacturing oxide TFTs, but there have been problems such as the need for expensive manufacturing equipment. On the other hand, there is an increasing trend to reduce costs by switching from vacuum processes to solution processes such as spin coating.
 例えば、特許文献1および2には、ゲート電極とチャネルとの間にゲート絶縁層を備える薄膜トランジスタが開示されている。ゲート絶縁層の材料としては、ランタンとジルコニウムとからなる酸化物が用いられている。また、ゲート絶縁層形成時において、焼成温度を400℃程度としている。 For example, Patent Documents 1 and 2 disclose a thin film transistor including a gate insulating layer between a gate electrode and a channel. As a material for the gate insulating layer, an oxide composed of lanthanum and zirconium is used. Further, the firing temperature is set to about 400 ° C. when forming the gate insulating layer.
特開2015-60962号公報JP2015-60962A 国際公開第2013/141197号International Publication No. 2013/141197
 ところで、近年、フレキシブルディスプレイの開発が加速している。フレキシブルディスプレイとして、例えばプラスチック基板上にデバイスを作製するには、プロセス温度を200℃以下とする必要がある。 By the way, in recent years, the development of flexible displays has accelerated. For example, in order to produce a device on a plastic substrate as a flexible display, the process temperature needs to be 200 ° C. or lower.
 また、薄膜トランジスタを、例えば高精細または大面積のディスプレイに適用する場合には、その駆動のために、高い電界効果移動度が求められる。 Further, when the thin film transistor is applied to, for example, a high-definition or large-area display, high field effect mobility is required for driving the thin film transistor.
 本開示の目的は、良好なトランジスタ特性(特に、高い電界効果移動度)を有する薄膜トランジスタを提供することである。また、プロセス温度を200℃以下とする薄膜トランジスタの製造方法を提供することである。さらに、当該製造方法においても使用可能な薄膜トランジスタ用ゲート絶縁膜形成溶液を提供することである。 An object of the present disclosure is to provide a thin film transistor having good transistor characteristics (particularly, high field effect mobility). Another object of the present invention is to provide a method for manufacturing a thin film transistor having a process temperature of 200 ° C. or lower. Furthermore, it is to provide a gate insulating film forming solution for a thin film transistor that can be used in the manufacturing method.
 本開示の薄膜トランジスタは、ゲート電極、ゲート絶縁層、および酸化物半導体層をこの順で備え、前記ゲート絶縁層は、セリウム(Ce)、プラセオジム(Pr)、ネオジム(Nd)、サマリウム(Sm)、ユウロピウム(Eu)、ガドリニウム(Gd)、テルビウム(Tb)、ジスプロシウム(Dy)、ホルミウム(Ho)、エルビウム(Er)、ツリウム(Tm)、イッテルビウム(Yb)、ルテチウム(Lu)、およびイットリウム(Y)からなる群から選択される金属元素と、ジルコニウム(Zr)とを含み、前記群から選択される金属元素と、ジルコニウム(Zr)との原子数比が、前記群から選択される金属元素の原子数を1としたときに、ジルコニウム(Zr)の原子数が1.5以上である、酸化物から形成されているか、または、ハフニウム(Hf)、ジルコニウム(Zr)、およびアルミニウム(Al)からなる群から選択される少なくとも1種類の金属元素を含む酸化物から形成されており、前記酸化物半導体層は、インジウム(In)を含む酸化物、インジウム(In)と錫(Sn)とを含む酸化物、インジウム(In)と亜鉛(Zn)とを含む酸化物、インジウム(In)とジルコニウム(Zr)と亜鉛(Zn)とを含む酸化物、インジウム(In)とガリウム(Ga)とを含む酸化物、およびインジウム(In)と亜鉛(Zn)とガリウム(Ga)とを含む酸化物の群から選択される酸化物から形成されていることを特徴とする。 The thin film transistor of the present disclosure includes a gate electrode, a gate insulating layer, and an oxide semiconductor layer in this order, and the gate insulating layer includes cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), Europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), and yttrium (Y) A metal element selected from the group consisting of zirconium and zirconium (Zr), wherein the atomic ratio of the metal element selected from the group and zirconium (Zr) is an atom of the metal element selected from the group Whether the number of zirconium (Zr) atoms is 1.5 or more and the oxide is formed when the number is 1 Alternatively, the oxide semiconductor layer is formed of an oxide containing at least one metal element selected from the group consisting of hafnium (Hf), zirconium (Zr), and aluminum (Al), and the oxide semiconductor layer includes indium (In ), Oxides containing indium (In) and tin (Sn), oxides containing indium (In) and zinc (Zn), indium (In), zirconium (Zr) and zinc (Zn) , An oxide containing indium (In) and gallium (Ga), and an oxide selected from the group consisting of oxides containing indium (In), zinc (Zn), and gallium (Ga). It is formed.
 また、上記の本開示の薄膜トランジスタの製造方法は、ゲート電極の上にゲート絶縁膜形成溶液を塗布して、ゲート絶縁膜を形成する工程と、酸素を含む環境下、前記ゲート絶縁膜の表面に紫外線を照射しながら、180~200℃で前記ゲート絶縁膜を焼成して、ゲート絶縁層を形成する工程と、前記ゲート絶縁層の上に酸化物半導体膜形成溶液を塗布して、酸化物半導体膜を形成する工程と、前記酸化物半導体膜の表面に紫外線を照射しながら、180~200℃で前記酸化物半導体膜を焼成して、酸化物半導体層を形成する工程とを含み、前記ゲート絶縁膜形成溶液は、ランタン(La)と、ジルコニウム(Zr)と、アセチルアセトナートとを含み、ランタン(La)と、ジルコニウム(Zr)との原子数比が、ランタン(La)の原子数を1としたときに、ジルコニウム(Zr)の原子数が0.8以上である溶液(i)であるか、セリウム(Ce)、プラセオジム(Pr)、ネオジム(Nd)、サマリウム(Sm)、ユウロピウム(Eu)、ガドリニウム(Gd)、テルビウム(Tb)、ジスプロシウム(Dy)、ホルミウム(Ho)、エルビウム(Er)、ツリウム(Tm)、イッテルビウム(Yb)、ルテチウム(Lu)、およびイットリウム(Y)からなる群から選択される金属元素と、ジルコニウム(Zr)と、アセチルアセトナートとを含み、前記群から選択される金属元素と、ジルコニウム(Zr)との原子数比が、前記群から選択される金属元素の原子数を1としたときに、ジルコニウム(Zr)の原子数が1.5以上である溶液(ii)であるか、または、ハフニウム(Hf)、ジルコニウム(Zr)、およびアルミニウム(Al)からなる群から選択される少なくとも1種類の金属元素と、アセチルアセトナートとを含む溶液(iii)であり、前記酸化物半導体膜形成溶液は、インジウム(In)、インジウム(In)と錫(Sn)、インジウム(In)と亜鉛(Zn)、インジウム(In)とジルコニウム(Zr)と亜鉛(Zn)、インジウム(In)とガリウム(Ga)、およびインジウム(In)と亜鉛(Zn)とガリウム(Ga)からなる群から選択される金属と、酸化剤とを含むことを特徴とする。 In addition, the method of manufacturing a thin film transistor according to the present disclosure includes a step of applying a gate insulating film forming solution on the gate electrode to form a gate insulating film, and an oxygen-containing environment on the surface of the gate insulating film. A step of baking the gate insulating film at 180 to 200 ° C. while irradiating ultraviolet rays to form a gate insulating layer, and applying an oxide semiconductor film forming solution on the gate insulating layer, A step of forming a film, and a step of baking the oxide semiconductor film at 180 to 200 ° C. while irradiating the surface of the oxide semiconductor film with ultraviolet rays to form an oxide semiconductor layer. The insulating film forming solution contains lanthanum (La), zirconium (Zr), and acetylacetonate, and the atomic ratio between lanthanum (La) and zirconium (Zr) is lanthanum (La). When the number of atoms is 1, it is a solution (i) in which the number of zirconium (Zr) atoms is 0.8 or more, cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm) , Europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), and yttrium (Y) A metal element selected from the group consisting of: zirconium (Zr), and acetylacetonate, wherein the atomic ratio of the metal element selected from the group and zirconium (Zr) is selected from the group Or a solution (ii) in which the number of atoms of zirconium (Zr) is 1.5 or more, where Is a solution (iii) containing at least one metal element selected from the group consisting of hafnium (Hf), zirconium (Zr), and aluminum (Al), and acetylacetonate, and the oxide semiconductor film The forming solutions are indium (In), indium (In) and tin (Sn), indium (In) and zinc (Zn), indium (In) and zirconium (Zr) and zinc (Zn), indium (In) and gallium. It contains (Ga), a metal selected from the group consisting of indium (In), zinc (Zn), and gallium (Ga), and an oxidizing agent.
 さらに、本開示の薄膜トランジスタ用ゲート絶縁膜形成溶液は、ランタン(La)と、ジルコニウム(Zr)と、アセチルアセトナートとを含み、ランタン(La)と、ジルコニウム(Zr)との原子数比が、ランタン(La)の原子数を1としたときに、ジルコニウム(Zr)の原子数が0.8以上である溶液(i)であるか、セリウム(Ce)、プラセオジム(Pr)、ネオジム(Nd)、サマリウム(Sm)、ユウロピウム(Eu)、ガドリニウム(Gd)、テルビウム(Tb)、ジスプロシウム(Dy)、ホルミウム(Ho)、エルビウム(Er)、ツリウム(Tm)、イッテルビウム(Yb)、ルテチウム(Lu)、およびイットリウム(Y)からなる群から選択される金属元素と、ジルコニウム(Zr)と、アセチルアセトナートとを含み、前記群から選択される金属元素と、ジルコニウム(Zr)との原子数比が、前記群から選択される金属元素の原子数を1としたときに、ジルコニウム(Zr)の原子数が1.5以上である溶液(ii)であるか、または、ハフニウム(Hf)、ジルコニウム(Zr)、およびアルミニウム(Al)からなる群から選択される少なくとも1種類の金属元素と、アセチルアセトナートとを含む溶液(iii)であることを特徴とする。 Furthermore, the gate insulating film forming solution for a thin film transistor of the present disclosure includes lanthanum (La), zirconium (Zr), and acetylacetonate, and the atomic ratio of lanthanum (La) and zirconium (Zr) is When the number of atoms of lanthanum (La) is 1, it is a solution (i) in which the number of zirconium (Zr) atoms is 0.8 or more, cerium (Ce), praseodymium (Pr), neodymium (Nd) , Samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu) And a metal element selected from the group consisting of yttrium (Y), zirconium (Zr), and acetylacetona When the atomic ratio of the metal element selected from the group and zirconium (Zr) is 1 when the atomic number of the metal element selected from the group is 1, the atom of zirconium (Zr) A solution (ii) having a number of 1.5 or more, or at least one metal element selected from the group consisting of hafnium (Hf), zirconium (Zr), and aluminum (Al), and acetylacetate It is a solution (iii) containing natto.
 本開示の薄膜トランジスタは、良好なトランジスタ特性(特に、高い電界効果移動度)を有している。また、本開示の方法によれば、200℃以下のプロセス温度で薄膜トランジスタを製造することが可能である。このため、本開示の薄膜トランジスタおよびその製造方法は、フレキシブルディスプレイの用途など幅広い用途に適用することができる。 The thin film transistor of the present disclosure has good transistor characteristics (particularly high field effect mobility). Further, according to the method of the present disclosure, a thin film transistor can be manufactured at a process temperature of 200 ° C. or lower. For this reason, the thin film transistor and the manufacturing method thereof of the present disclosure can be applied to a wide range of uses such as a flexible display.
本実施形態の薄膜トランジスタの一例を概略的に示す断面図である。It is sectional drawing which shows roughly an example of the thin-film transistor of this embodiment. 図1に示す薄膜トランジスタの製造方法の各工程を順次示す断面図であり、(a)は、基板の上にゲート電極を形成する工程、(b)は、ゲート電極の上にゲート絶縁膜を形成する工程、(c)は、(b)で形成したゲート絶縁膜を、紫外線照射しながら加熱して、ゲート絶縁層を形成する工程、(d)は、ゲート絶縁層の上に酸化物半導体膜を形成する工程、(e)は、(d)で形成した酸化物半導体膜を、紫外線照射しながら加熱して、酸化物半導体層を形成する工程、(f)は、酸化物半導体層の上にソース電極およびドレイン電極を形成する工程、(g)は、酸化物半導体層の一部、ソース電極、およびドレイン電極の上にレジスト膜を形成する工程、(h)は、(g)で作製したレジスト膜を備える積層体をエッチングすることにより薄膜トランジスタを得る工程を示す。2A and 2B are cross-sectional views sequentially showing each step of the method of manufacturing the thin film transistor shown in FIG. 1, wherein FIG. 1A is a step of forming a gate electrode on the substrate, and FIG. (C) is a step of heating the gate insulating film formed in (b) while irradiating with ultraviolet rays to form a gate insulating layer, and (d) is an oxide semiconductor film on the gate insulating layer. (E) is a step in which the oxide semiconductor film formed in (d) is heated while being irradiated with ultraviolet rays to form an oxide semiconductor layer, and (f) is a step on the oxide semiconductor layer. (G) is a step of forming a resist film over part of the oxide semiconductor layer, the source electrode, and the drain electrode, and (h) is a step of forming (g). Etching a laminated body having a resist film Ri indicates the step of obtaining a thin film transistor. ゲート絶縁膜形成溶液の紫外線吸光度を測定した結果を示す図である。It is a figure which shows the result of having measured the ultraviolet light absorbency of the gate insulating film formation solution. 実施例2の薄膜トランジスタのVG-ID特性およびVG-IG特性を示す図である。It is a diagram showing the V G -I D characteristic and V G -I G characteristics of the thin film transistor in Example 2. 比較例3の薄膜トランジスタのVG-ID特性およびVG-IG特性を示す図である。V G -I D characteristic and V G -I G characteristics of the thin film transistor of Comparative Example 3 is a diagram showing a. 比較例4の薄膜トランジスタのVG-ID特性およびVG-IG特性を示す図である。It is a diagram showing the V G -I D characteristic and V G -I G characteristics of the thin film transistor of Comparative Example 4.
 以下に、本発明の実施の形態について詳細に説明する。以下の説明において適宜図面を参照するが、図面に記載された態様は本発明の例示であり、本発明はこれらの図面に記載された態様に制限されない。なお、各図において、同様の、または類似した機能を発揮する構成要素には同一、または類似の参照符号を付し、重複する説明を省略することがある。また、図面の寸法比率は、説明の都合上誇張されており、実際の比率とは異なる場合がある。さらに、本明細書において、「~」とは、その前後に記載される数値を下限値および上限値として含む意味で使用される。 Hereinafter, embodiments of the present invention will be described in detail. In the following description, the drawings are referred to as appropriate, but the embodiments described in the drawings are examples of the present invention, and the present invention is not limited to the embodiments described in these drawings. In each figure, the same or similar reference numerals are given to components that exhibit the same or similar functions, and redundant description may be omitted. In addition, the dimensional ratios in the drawings are exaggerated for convenience of explanation, and may be different from the actual ratios. Further, in the present specification, “˜” is used to mean that the numerical values described before and after it are included as a lower limit value and an upper limit value.
<薄膜トランジスタ>
 本開示の薄膜トランジスタは、ゲート電極、ゲート絶縁層、および酸化物半導体層をこの順で備える。ここで、ゲート絶縁層は、ランタン(La)と、ジルコニウム(Zr)とを含み、ランタン(La)と、ジルコニウム(Zr)との原子数比が、ランタン(La)の原子数を1としたときに、ジルコニウム(Zr)の原子数が0.8以上である、酸化物から形成されている。或いは、ゲート絶縁層は、セリウム(Ce)、プラセオジム(Pr)、ネオジム(Nd)、サマリウム(Sm)、ユウロピウム(Eu)、ガドリニウム(Gd)、テルビウム(Tb)、ジスプロシウム(Dy)、ホルミウム(Ho)、エルビウム(Er)、ツリウム(Tm)、イッテルビウム(Yb)、ルテチウム(Lu)、およびイットリウム(Y)からなる群から選択される金属元素と、ジルコニウム(Zr)とを含み、前記群から選択される金属元素と、ジルコニウム(Zr)との原子数比が、前記群から選択される金属元素の原子数を1としたときに、ジルコニウム(Zr)の原子数が1.5以上である、酸化物から形成されている。或いは、ゲート絶縁層は、ハフニウム(Hf)、ジルコニウム(Zr)、およびアルミニウム(Al)からなる群から選択される少なくとも1種類の金属元素を含む酸化物から形成されている。また、酸化物半導体層は、インジウム(In)を含む酸化物、インジウム(In)と錫(Sn)とを含む酸化物、インジウム(In)と亜鉛(Zn)とを含む酸化物、インジウム(In)とジルコニウム(Zr)と亜鉛(Zn)とを含む酸化物、インジウム(In)とガリウム(Ga)とを含む酸化物、およびインジウム(In)と亜鉛(Zn)とガリウム(Ga)とを含む酸化物の群から選択される酸化物から形成されている。
<Thin film transistor>
The thin film transistor of the present disclosure includes a gate electrode, a gate insulating layer, and an oxide semiconductor layer in this order. Here, the gate insulating layer includes lanthanum (La) and zirconium (Zr), and the atomic ratio of lanthanum (La) to zirconium (Zr) is set to 1 for the number of lanthanum (La) atoms. Sometimes zirconium (Zr) is formed from an oxide having 0.8 or more atoms. Alternatively, the gate insulating layer is formed of cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho). ), Erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), and yttrium (Y), and zirconium (Zr). When the atomic ratio between the metal element and zirconium (Zr) is 1 when the number of atoms of the metal element selected from the group is 1, the number of atoms of zirconium (Zr) is 1.5 or more. It is formed from an oxide. Alternatively, the gate insulating layer is formed of an oxide containing at least one metal element selected from the group consisting of hafnium (Hf), zirconium (Zr), and aluminum (Al). The oxide semiconductor layer includes an oxide containing indium (In), an oxide containing indium (In) and tin (Sn), an oxide containing indium (In) and zinc (Zn), and indium (In ), Zirconium (Zr) and zinc (Zn) -containing oxide, indium (In) and gallium (Ga) oxide, and indium (In), zinc (Zn) and gallium (Ga). It is formed from an oxide selected from the group of oxides.
 図1は、本実施形態の薄膜トランジスタの一例を概略的に示す断面図である。同図に示す薄膜トランジスタ10は、基板12上に、ゲート電極14、ゲート絶縁層16、酸化物半導体層18、ならびにソース電極32およびドレイン電極34をこの順で備える。 FIG. 1 is a cross-sectional view schematically showing an example of the thin film transistor of this embodiment. The thin film transistor 10 shown in the figure includes a gate electrode 14, a gate insulating layer 16, an oxide semiconductor layer 18, a source electrode 32, and a drain electrode 34 in this order on a substrate 12.
 図1に示す薄膜トランジスタ10は、ボトムゲート構造で示されているが、この構造に限定されない。例えば、トップゲート構造などその他の構造であってもよい。また、図面を簡略化するため、各電極からの引き出し電極のパターニングについては図示していない。 Although the thin film transistor 10 shown in FIG. 1 has a bottom gate structure, it is not limited to this structure. For example, other structures such as a top gate structure may be used. Further, in order to simplify the drawing, the patterning of the extraction electrode from each electrode is not shown.
 以下、図1に示す薄膜トランジスタ10の構成要素について説明する。 Hereinafter, components of the thin film transistor 10 shown in FIG. 1 will be described.
(基板)
 基板12としては、公知の薄膜トランジスタにおいて用いられている基板を適用できる。
(substrate)
As the substrate 12, a substrate used in a known thin film transistor can be applied.
 基板12の例としては、高耐熱ガラス、SiO2/Si基板(シリコン基板上に酸化シリコン膜を形成した基板)、アルミナ(Al23)基板、STO(SrTiO)基板、Si基板の表面にSiO2層及びTi層を介してSTO(SrTiO)層を形成した絶縁性基板、半導体基板(例えば、Si基板、SiC基板、Ge基板)が含まれる。また、ポリエチレンナフタレート(PEN)、ポリカーボネート(PC)、ポリイミド(PI)などの樹脂からなるプラスチック基板、または紙を始めとするフレキシブル基板も含まれる。 Examples of the substrate 12 include a high heat-resistant glass, a SiO 2 / Si substrate (a substrate in which a silicon oxide film is formed on a silicon substrate), an alumina (Al 2 O 3 ) substrate, an STO (SrTiO) substrate, and a Si substrate. Insulating substrates and semiconductor substrates (for example, Si substrates, SiC substrates, Ge substrates) in which an STO (SrTiO) layer is formed via an SiO 2 layer and a Ti layer are included. Further, a plastic substrate made of a resin such as polyethylene naphthalate (PEN), polycarbonate (PC), polyimide (PI), or a flexible substrate such as paper is also included.
(ゲート電極)
 ゲート電極14は、公知の薄膜トランジスタに用いられているゲート電極を採用することができる。ゲート電極14の材料としては、例えば、白金、金、銀、銅、チタン、アルミニウム、モリブデン、パラジウム、ルテニウム、イリジウム、タングステン、などの高融点金属、又はその合金等の金属材料、あるいは、インジウム錫酸化物(ITO)又は酸化ルテニウム(RuO2)を用いることができる。
(Gate electrode)
As the gate electrode 14, a gate electrode used in a known thin film transistor can be adopted. Examples of the material of the gate electrode 14 include metal materials such as refractory metals such as platinum, gold, silver, copper, titanium, aluminum, molybdenum, palladium, ruthenium, iridium, and tungsten, or alloys thereof, or indium tin. Oxide (ITO) or ruthenium oxide (RuO 2 ) can be used.
(ゲート絶縁層)
 ゲート絶縁層16は、特定の金属元素を含む酸化物から形成されている。
(Gate insulation layer)
The gate insulating layer 16 is formed from an oxide containing a specific metal element.
 特定の金属元素を含む酸化物は、ランタン(La)と、ジルコニウム(Zr)とを含む酸化物(以下、単に「酸化物(i)」とも称する)であるか、セリウム(Ce)、プラセオジム(Pr)、ネオジム(Nd)、サマリウム(Sm)、ユウロピウム(Eu)、ガドリニウム(Gd)、テルビウム(Tb)、ジスプロシウム(Dy)、ホルミウム(Ho)、エルビウム(Er)、ツリウム(Tm)、イッテルビウム(Yb)、ルテチウム(Lu)、およびイットリウム(Y)からなる群から選択される金属元素と、ジルコニウム(Zr)と含む酸化物(以下、単に「酸化物(ii)」とも称する)であるか、ハフニウム(Hf)、ジルコニウム(Zr)、およびアルミニウム(Al)からなる群から選択される少なくとも1種類の金属元素を含む酸化物(以下、単に「酸化物(iii)」とも称する)である。酸化物(i)および酸化物(ii)において、ジルコニウム(Zr)を用いる代わりに、タンタル(Ta)を用いてもよい。 The oxide containing a specific metal element is an oxide containing lanthanum (La) and zirconium (Zr) (hereinafter also simply referred to as “oxide (i)”), cerium (Ce), praseodymium ( Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium ( Yb), lutetium (Lu), and a metal element selected from the group consisting of yttrium (Y) and an oxide containing zirconium (Zr) (hereinafter also simply referred to as “oxide (ii)”), At least one metal element selected from the group consisting of hafnium (Hf), zirconium (Zr), and aluminum (Al) Oxides containing (hereinafter, simply referred to as "oxide (iii)") it is. In the oxide (i) and the oxide (ii), tantalum (Ta) may be used instead of zirconium (Zr).
 「特定の金属元素を含む酸化物」とは、典型的には、特定の金属元素を主成分として含む酸化物を意図しているが、当該酸化物に、不純物(例えば、原料に由来する不純物)が含まれていてもよい。良好なトランジスタ性能を得るためには、酸化物中の炭素および水素以外の不純物の含有量は、0.2質量%以下であることが好ましい。 The “oxide containing a specific metal element” typically means an oxide containing a specific metal element as a main component, but the oxide contains impurities (for example, impurities derived from raw materials). ) May be included. In order to obtain good transistor performance, the content of impurities other than carbon and hydrogen in the oxide is preferably 0.2% by mass or less.
 特定の金属元素を含む酸化物が、酸化物(i)である場合、ランタン(La)と、ジルコニウム(Zr)との原子数比が、ランタン(La)の原子数を1としたときに、ジルコニウム(Zr)の原子数が0.8以上であり、好ましくは0.8~10であり、さらに好ましくは1.5~4である。特定の金属元素を含む酸化物が、酸化物(ii)である場合、特定の群から選択される金属元素と、ジルコニウム(Zr)との原子数比は、良好なトランジスタ性能を得る観点から、金属元素の原子数を1としたときに、ジルコニウム(Zr)の原子数は、1.5以上であり、好ましくは1.5~9であり、さらに好ましくは2.3~9である。本開示において、原子数比は、ラザフォード後方散乱分光法(RBS法)を用いて、元素分析を行うことにより求めることができる。 When the oxide containing a specific metal element is oxide (i), when the atomic ratio of lanthanum (La) and zirconium (Zr) is set to 1 as the number of atoms of lanthanum (La), The number of zirconium (Zr) atoms is 0.8 or more, preferably 0.8 to 10, and more preferably 1.5 to 4. When the oxide containing the specific metal element is the oxide (ii), the atomic ratio between the metal element selected from the specific group and zirconium (Zr) is from the viewpoint of obtaining good transistor performance. When the number of atoms of the metal element is 1, the number of zirconium (Zr) atoms is 1.5 or more, preferably 1.5 to 9, and more preferably 2.3 to 9. In the present disclosure, the atomic ratio can be obtained by performing elemental analysis using Rutherford backscattering spectroscopy (RBS method).
 ゲート絶縁層16における炭素(C)の含有率は、特に制限するわけではないが、良好なトランジスタ性能を得る観点から、0.5atom%~20atom%であることが好ましい。 The content of carbon (C) in the gate insulating layer 16 is not particularly limited, but is preferably 0.5 atom% to 20 atom% from the viewpoint of obtaining good transistor performance.
 炭素(C)と水素(H)の含有率については、National Electrostatics Corporation 製 Pelletron 3SDHを用いて、ラザフォード後方散乱分光法(Rutherford Backscattering Spectrometry:RBS分析法)、水素前方散乱分析法(Hydrogen Forward scattering Spectrometry:HFS分析法)、及び核反応解析法(Nuclear Reaction Analysis:NRA分析法)を用いて元素分析を行うことにより求めることができる。 Regarding the content of carbon (C) and hydrogen (H), Rutherford Backscattering Spectrometry (RBS analysis method), Hydrogen forward scattering analysis method (Hdr forward analysis method), using Pelletron 3SDH manufactured by National Electrostatics Corporation. : HFS analysis method) and nuclear reaction analysis method (Nuclear Reaction Analysis: NRA analysis method).
 ゲート絶縁層16の厚みは、特に制限するわけではないが、リークを抑えながら動作電圧を下げる観点から、30nm~500nmであることが好ましい。 The thickness of the gate insulating layer 16 is not particularly limited, but is preferably 30 nm to 500 nm from the viewpoint of reducing the operating voltage while suppressing leakage.
(酸化物半導体層)
 酸化物半導体層18は、インジウム(In)を含む酸化物、インジウム(In)と錫(Sn)とを含む酸化物、インジウム(In)と亜鉛(Zn)とを含む酸化物、インジウム(In)とジルコニウム(Zr)と亜鉛(Zn)とを含む酸化物、インジウム(In)とガリウム(Ga)とを含む酸化物、およびインジウム(In)と亜鉛(Zn)とガリウム(Ga)を含む酸化物の群から選択される酸化物から形成されている。
(Oxide semiconductor layer)
The oxide semiconductor layer 18 includes an oxide containing indium (In), an oxide containing indium (In) and tin (Sn), an oxide containing indium (In) and zinc (Zn), and indium (In). , An oxide containing zirconium (Zr) and zinc (Zn), an oxide containing indium (In) and gallium (Ga), and an oxide containing indium (In), zinc (Zn) and gallium (Ga) Formed from an oxide selected from the group consisting of:
 「インジウム(In)を含む酸化物」とは、典型的には、インジウム(In)を主成分として含む酸化物を意図しているが、当該酸化物に、不純物(例えば、原料に由来する不純物)が含まれていてもよい。良好なトランジスタ性能を得るためには、酸化物中の炭素および水素以外の不純物の含有量は、0.2質量%以下であることが好ましい。酸化物半導体層18における炭素(C)の含有率は、良好なトランジスタ性能を得る観点から、0.2atom%~15.0atom%であることが好ましい。また、酸化物半導体層18中の水素(H)の含有率は、1atom%~20atom%であることが好ましい。他の5種類の酸化物についても同様のことが当てはまる。 The “oxide containing indium (In)” typically means an oxide containing indium (In) as a main component, but the oxide contains impurities (for example, impurities derived from raw materials). ) May be included. In order to obtain good transistor performance, the content of impurities other than carbon and hydrogen in the oxide is preferably 0.2% by mass or less. The content of carbon (C) in the oxide semiconductor layer 18 is preferably 0.2 atom% to 15.0 atom% from the viewpoint of obtaining good transistor performance. In addition, the content of hydrogen (H) in the oxide semiconductor layer 18 is preferably 1 atom% to 20 atom%. The same applies to the other five oxides.
 インジウム(In)と錫(Sn)とを含む酸化物を用いる場合において、酸化物半導体層18におけるインジウム(In)と錫(Sn)との原子数比は、インジウム(In)の原子数を1としたときに、特に制限するわけではないが、良好なトランジスタ性能を得る観点から、錫(Sn)の原子数を0.005~0.03とすることが好ましい。 In the case of using an oxide containing indium (In) and tin (Sn), the atomic ratio of indium (In) to tin (Sn) in the oxide semiconductor layer 18 is set so that the number of atoms of indium (In) is 1. However, from the viewpoint of obtaining good transistor performance, it is preferable that the number of tin (Sn) atoms be 0.005 to 0.03.
 インジウム(In)と亜鉛(Zn)とを含む酸化物を用いる場合において、酸化物半導体層18におけるインジウム(In)と亜鉛(Zn)との原子数比は、インジウム(In)の原子数を1としたときに、特に制限するわけではないが、良好なトランジスタ性能を得る観点から、亜鉛(Zn)の原子数を0.1~1.0とすることが好ましい。 In the case of using an oxide containing indium (In) and zinc (Zn), the atomic ratio of indium (In) to zinc (Zn) in the oxide semiconductor layer 18 is such that the number of atoms of indium (In) is 1. However, from the viewpoint of obtaining good transistor performance, the number of zinc (Zn) atoms is preferably 0.1 to 1.0.
 インジウム(In)とジルコニウム(Zr)と亜鉛(Zn)とを含む酸化物を用いる場合において、酸化物半導体層18におけるインジウム(In)とジルコニウム(Zr)と亜鉛(Zn)との原子数比は、インジウム(In)の原子数を1としたときに、特に制限するわけではないが、良好なトランジスタ性能を得る観点から、ジルコニウム(Zr)の原子数を0.005~0.03、亜鉛(Zn)の原子数を0.1~1.0とすることが好ましい。 In the case of using an oxide containing indium (In), zirconium (Zr), and zinc (Zn), the atomic ratio of indium (In), zirconium (Zr), and zinc (Zn) in the oxide semiconductor layer 18 is When the number of atoms of indium (In) is 1, it is not particularly limited, but from the viewpoint of obtaining good transistor performance, the number of zirconium (Zr) atoms is 0.005 to 0.03, zinc ( The number of atoms of Zn) is preferably 0.1 to 1.0.
 インジウム(In)とガリウム(Ga)とを含む酸化物を用いる場合において、酸化物半導体層18におけるインジウム(In)とガリウム(Ga)との原子数比は、インジウム(In)の原子数を1としたときに、特に制限するわけではないが、良好なトランジスタ性能を得る観点から、ガリウム(Ga)を0.1~1.0とすることが好ましい。 In the case of using an oxide containing indium (In) and gallium (Ga), the atomic ratio of indium (In) to gallium (Ga) in the oxide semiconductor layer 18 is such that the number of atoms of indium (In) is 1. In this case, gallium (Ga) is preferably 0.1 to 1.0 from the viewpoint of obtaining good transistor performance.
 インジウム(In)と亜鉛(Zn)とガリウム(Ga)を含む酸化物を用いる場合において、酸化物半導体層18におけるインジウム(In)と亜鉛(Zn)とガリウム(Ga)との原子数比は、インジウム(In)の原子数を1としたときに、特に制限するわけではないが、良好なトランジスタ性能を得る観点から、亜鉛(Zn)を0.1~1.0、ガリウム(Ga)を0.1~1.2とすることが好ましい。 In the case of using an oxide containing indium (In), zinc (Zn), and gallium (Ga), the atomic ratio of indium (In), zinc (Zn), and gallium (Ga) in the oxide semiconductor layer 18 is When the number of atoms of indium (In) is 1, it is not particularly limited, but from the viewpoint of obtaining good transistor performance, zinc (Zn) is 0.1 to 1.0 and gallium (Ga) is 0. 1 to 1.2 is preferable.
 酸化物半導体層18の厚みは、特に制限するわけではないが、十分な動作電流を確保し、かつ、薄膜化を実現させる観点から、10nm~100nmであることが好ましい。 The thickness of the oxide semiconductor layer 18 is not particularly limited, but is preferably 10 nm to 100 nm from the viewpoint of securing a sufficient operating current and realizing a thin film.
(ソース電極およびドレイン電極)
 ソース電極32およびドレイン電極34は、公知の薄膜トランジスタに用いられているソース電極32およびドレイン電極34を採用することができる。ソース電極32およびドレイン電極34の材料としては、制限するわけではないが、例えば、インジウム錫酸化物(ITO)、酸化ルテニウム(RuO2)、モリブデン(Mo)、プラチナ(Pt)などを用いることができる。
(Source electrode and drain electrode)
As the source electrode 32 and the drain electrode 34, the source electrode 32 and the drain electrode 34 used in a known thin film transistor can be adopted. The material of the source electrode 32 and the drain electrode 34 is not limited, but for example, indium tin oxide (ITO), ruthenium oxide (RuO 2 ), molybdenum (Mo), platinum (Pt), or the like is used. it can.
 以上説明したように、薄膜トランジスタ10は、ランタン(La)と、ジルコニウム(Zr)とを含み、ランタン(La)と、ジルコニウム(Zr)との原子数比が、ランタン(La)の原子数を1としたときに、ジルコニウム(Zr)の原子数が0.8以上である、酸化物から形成されているか、特定の希土類金属元素と、ジルコニウム(Zr)とを含み、当該希土類金属元素の原子数を1としたときに、ジルコニウム(Zr)の原子数が1.5以上である酸化物から形成されているか、または、ハフニウム(Hf)、ジルコニウム(Zr)、およびアルミニウム(Al)からなる群から選択される少なくとも1種類の金属元素を含む酸化物から形成されているゲート絶縁層16を含む。また、薄膜トランジスタ10は、インジウム(In)を含む特定の酸化物から形成されている酸化物半導体層18を含む。これにより、本開示の薄膜トランジスタ10は、良好な電気特性、特に、高い電界効果移動度を備える。 As described above, the thin film transistor 10 includes lanthanum (La) and zirconium (Zr), and the atomic ratio of lanthanum (La) and zirconium (Zr) is equal to 1 in the number of lanthanum (La) atoms. When the number of atoms of zirconium (Zr) is 0.8 or more, it is formed of an oxide or contains a specific rare earth metal element and zirconium (Zr), and the number of atoms of the rare earth metal element Is formed from an oxide having zirconium (Zr) atoms of 1.5 or more, or from the group consisting of hafnium (Hf), zirconium (Zr), and aluminum (Al) A gate insulating layer 16 formed of an oxide containing at least one selected metal element is included. The thin film transistor 10 includes an oxide semiconductor layer 18 formed from a specific oxide containing indium (In). Thereby, the thin film transistor 10 of the present disclosure has good electrical characteristics, in particular, high field effect mobility.
 次に、本開示の薄膜トランジスタ10の製造方法を説明する。 Next, a method for manufacturing the thin film transistor 10 of the present disclosure will be described.
<薄膜トランジスタの製造方法>
 本開示の薄膜トランジスタの製造方法は、ゲート電極の上にゲート絶縁膜形成溶液を塗布して、ゲート絶縁膜を形成する工程と、酸素を含む環境下、当該ゲート絶縁膜の表面に紫外線を照射しながら、180~200℃で当該ゲート絶縁膜を焼成して、ゲート絶縁層を形成する工程と、当該ゲート絶縁層の上に酸化物半導体膜形成溶液を塗布して、酸化物半導体膜を形成する工程と、当該酸化物半導体膜の表面に紫外線を照射しながら、180~200℃で当該酸化物半導体膜を焼成して、酸化物半導体層を形成する工程とを含む。
<Method for Manufacturing Thin Film Transistor>
The method of manufacturing a thin film transistor of the present disclosure includes a step of applying a gate insulating film forming solution on a gate electrode to form a gate insulating film, and irradiating the surface of the gate insulating film with ultraviolet light in an environment containing oxygen. However, the gate insulating film is baked at 180 to 200 ° C. to form the gate insulating layer, and the oxide semiconductor film forming solution is applied on the gate insulating layer to form the oxide semiconductor film. And a step of baking the oxide semiconductor film at 180 to 200 ° C. while irradiating the surface of the oxide semiconductor film with ultraviolet rays to form an oxide semiconductor layer.
 図2は、図1に示す薄膜トランジスタ10の製造方法の各工程を順次示す断面図であり、(a)は、基板12の上にゲート電極14を形成する工程、(b)は、ゲート電極14の上にゲート絶縁膜16’を形成する工程、(c)は、(b)で形成したゲート絶縁膜16’を、紫外線照射しながら加熱して、ゲート絶縁層16を形成する工程、(d)は、ゲート絶縁層16の上に酸化物半導体膜18’を形成する工程、(e)は、(d)で形成した酸化物半導体膜18’を、紫外線照射しながら加熱して、酸化物半導体層18を形成する工程、(f)は、酸化物半導体層18の上にソース電極32およびドレイン電極34を形成する工程、(g)は、酸化物半導体層18の一部、ソース電極32、およびドレイン電極34の上にレジスト膜36を形成する工程、(h)は、薄膜トランジスタ10を得る工程を示す。以下に、図2(a)~(h)にそれぞれ対応している工程(a)~(h)について詳述する。 2A and 2B are cross-sectional views sequentially showing each step of the method of manufacturing the thin film transistor 10 shown in FIG. 1, wherein FIG. 2A is a step of forming the gate electrode 14 on the substrate 12, and FIG. (C) is a step of heating the gate insulating film 16 ′ formed in (b) while irradiating it with ultraviolet rays to form a gate insulating layer 16; (d) ) Is a step of forming the oxide semiconductor film 18 ′ on the gate insulating layer 16, and (e) is a step of heating the oxide semiconductor film 18 ′ formed in (d) while irradiating with ultraviolet rays, thereby The step of forming the semiconductor layer 18, (f) is the step of forming the source electrode 32 and the drain electrode 34 on the oxide semiconductor layer 18, and (g) is the part of the oxide semiconductor layer 18, the source electrode 32. And the resist film 3 on the drain electrode 34 Forming a, (h) shows the step of obtaining a thin film transistor 10. The steps (a) to (h) corresponding to FIGS. 2 (a) to (h) will be described in detail below.
(工程(a))
 本工程は、基板12の上にゲート電極14を形成する工程である(図2(a))。
(Process (a))
This step is a step of forming the gate electrode 14 on the substrate 12 (FIG. 2A).
 基板12は、洗浄したものを使用することが好ましく、その洗浄方法としては、酸素ガスを用いたプラズマアッシングなど既知のいかなる方法を採用することができる。 It is preferable to use a cleaned substrate 12, and any known method such as plasma ashing using oxygen gas can be adopted as the cleaning method.
 ゲート電極14の形成方法としては、真空蒸着法(例えば、スパッタリング法)など既知のいかなる方法を採用することができる。 As a method for forming the gate electrode 14, any known method such as a vacuum deposition method (for example, a sputtering method) can be employed.
(工程(b))
 本工程は、ゲート電極14の上にゲート絶縁膜形成溶液を塗布して、ゲート絶縁膜16’を形成する工程である(図2(b))。
(Process (b))
This step is a step of forming a gate insulating film 16 ′ by applying a gate insulating film forming solution on the gate electrode 14 (FIG. 2B).
 ゲート絶縁膜形成溶液の塗布方法としては、制限するわけではないが、例えば、スピンコート法、ディップコート法、ダイコート法、バーコート法、ブレードコート法、ロールコート法、スプレーコート法、キャピラリーコート法、ノズルコート法、インクジェット法、スクリーン印刷法、グラビア印刷法、フレキソ印刷法、凸版印刷、反転オフセット印刷など公知の方法を用いることができる。 The coating method of the gate insulating film forming solution is not limited, but for example, spin coating method, dip coating method, die coating method, bar coating method, blade coating method, roll coating method, spray coating method, capillary coating method A known method such as a nozzle coating method, an ink jet method, a screen printing method, a gravure printing method, a flexographic printing method, a relief printing, or a reverse offset printing can be used.
 ゲート絶縁膜形成溶液は、ランタン(La)と、ジルコニウム(Zr)と、アセチルアセトナートとを含み、ランタン(La)と、ジルコニウム(Zr)との原子数比が、ランタン(La)の原子数を1としたときに、ジルコニウム(Zr)の原子数が0.8以上である溶液(i)であるか、セリウム(Ce)、プラセオジム(Pr)、ネオジム(Nd)、サマリウム(Sm)、ユウロピウム(Eu)、ガドリニウム(Gd)、テルビウム(Tb)、ジスプロシウム(Dy)、ホルミウム(Ho)、エルビウム(Er)、ツリウム(Tm)、イッテルビウム(Yb)、ルテチウム(Lu)、およびイットリウム(Y)からなる群から選択される金属元素と、ジルコニウム(Zr)と、アセチルアセトナートとを含み、前記群から選択される金属元素と、ジルコニウム(Zr)との原子数比が、前記群から選択される金属元素の原子数を1としたときに、ジルコニウム(Zr)の原子数が1.5以上である溶液(ii)であるか、または、ハフニウム(Hf)、ジルコニウム(Zr)、およびアルミニウム(Al)からなる群から選択される少なくとも1種類の金属元素と、アセチルアセトナートとを含む溶液(iii)である。溶液(i)~溶液(iii)の各溶液中に含まれるアセチルアセトナートの割合は、各溶液中に含まれる上記に示した金属元素の総モル数に対して、20~400モル%とすることができる。 The gate insulating film forming solution contains lanthanum (La), zirconium (Zr), and acetylacetonate, and the atomic ratio of lanthanum (La) and zirconium (Zr) is the number of atoms of lanthanum (La). Is a solution (i) in which the number of zirconium (Zr) atoms is 0.8 or more, or cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), and yttrium (Y) A metal element selected from the group consisting of zirconium (Zr) and acetylacetonate, selected from the group When the atomic ratio between the genus element and zirconium (Zr) is 1, the number of atoms of zirconium (Zr) is 1.5 or more when the number of atoms of the metal element selected from the group is 1 (ii) Or a solution (iii) containing at least one metal element selected from the group consisting of hafnium (Hf), zirconium (Zr), and aluminum (Al) and acetylacetonate. The ratio of acetylacetonate contained in each of solutions (i) to (iii) is 20 to 400 mol% with respect to the total number of moles of the metal elements shown above contained in each solution. be able to.
 理論に拘束されるわけではないが、ゲート絶縁膜形成溶液中の分子構造に言及すると、金属を含むコアに、陰イオンまたは溶媒が配位して、クラスターを形成していると考えている。そして、本発明者らは、このコアにアセチルアセトナートが配位すると、紫外線の吸収が著しく高くなることを見出した。この特性を生かし、本開示では、後述する工程(c)において、紫外線照射を加熱と併用することにより、従来適用されていた400℃程度の焼成温度を200℃以下としている。さらに、特定の金属元素と、アセチルアセトナートとを含むゲート絶縁膜形成溶液をゲート絶縁層16の材料として用いると、最終的に作製されるTFTのトランジスタ特性が良好となることも実験にて確認している。 Without being bound by theory, when referring to the molecular structure in the gate insulating film forming solution, it is considered that an anion or a solvent is coordinated to the core containing the metal to form a cluster. The present inventors have found that the absorption of ultraviolet rays is remarkably increased when acetylacetonate is coordinated to this core. Taking advantage of this characteristic, in the present disclosure, in the step (c) described later, the irradiation temperature of about 400 ° C., which has been conventionally applied, is set to 200 ° C. or less by using ultraviolet irradiation together with heating. Furthermore, it has been confirmed by experiments that the transistor characteristics of the finally fabricated TFT are improved when a gate insulating film forming solution containing a specific metal element and acetylacetonate is used as the material of the gate insulating layer 16. is doing.
 このように、本開示のゲート絶縁膜形成溶液は、ゲート絶縁膜の焼成温度の低減およびTFTのトランジスタ特性の向上に寄与する。 As described above, the gate insulating film forming solution of the present disclosure contributes to reduction of the firing temperature of the gate insulating film and improvement of the transistor characteristics of the TFT.
 ゲート絶縁膜形成溶液は、以下のように調製することができる。 The gate insulating film forming solution can be prepared as follows.
 ゲート絶縁膜形成溶液中に含まれる金属元素が1種類の場合には、所定の金属化合物を、溶媒に溶解させて、所定のモル濃度(例えば、0.2mol/kg)の溶液を作製することができる。ゲート絶縁膜形成溶液中に含まれる金属元素が2種類以上の場合には、金属元素毎に、所定の金属化合物を溶媒に溶解させて溶液を調製した後、当該各溶液を、金属元素が所定の原子数比となるように混合して、ゲート絶縁膜形成溶液を調製することができる。或いは、金属元素が所定の原子数比となるように、2種以上の金属化合物を溶媒に加えて、溶解させて、ゲート絶縁膜形成溶液を調製してもよい。さらに、以上のように調製した溶液中に、所定量のアセチルアセトナートが含まれない場合、当該溶液にアセチルアセトナートを加えて、ゲート絶縁膜形成溶液を調製することもできる。なお、溶液を調製する際に、適宜、精製、例えば、フィルターによるろ過を行ってもよい。また、金属化合物を溶媒に溶解する際に、適宜加熱してもよい。 When the gate insulating film forming solution contains only one kind of metal element, a predetermined metal compound is dissolved in a solvent to prepare a solution having a predetermined molar concentration (for example, 0.2 mol / kg). Can do. When two or more kinds of metal elements are contained in the gate insulating film forming solution, after preparing a solution by dissolving a predetermined metal compound in a solvent for each metal element, The gate insulating film forming solution can be prepared by mixing so that the atomic ratio is Alternatively, a gate insulating film forming solution may be prepared by adding and dissolving two or more kinds of metal compounds in a solvent so that the metal element has a predetermined atomic ratio. Furthermore, when a predetermined amount of acetylacetonate is not contained in the solution prepared as described above, a gate insulating film forming solution can be prepared by adding acetylacetonate to the solution. In addition, when preparing a solution, you may perform refinement | purification, for example, filtration with a filter suitably. Moreover, when dissolving a metal compound in a solvent, you may heat suitably.
 溶液(i)を調製する場合には、金属化合物として、ランタン化合物およびジルコニウム化合物を用いることができる。ランタン化合物の例としては、ランタンアセチルアセトナート、ランタンアルコキシド、ランタンの有機酸塩を挙げることができる。ジルコニウム化合物の例としては、ジルコニウムアセチルアセトナート、硝酸ジルコニウム、塩化ジルコニウム、またはジルコニウムアルコキシド(例えば、ジルコニウムイソプロポキシド、ジルコニウムブトキシド、ジルコニウムエトキシド、ジルコニウムメトキシエトキシド)を挙げることができる。 In preparing the solution (i), a lanthanum compound and a zirconium compound can be used as the metal compound. Examples of the lanthanum compound include lanthanum acetylacetonate, lanthanum alkoxide, and organic acid salt of lanthanum. Examples of zirconium compounds include zirconium acetylacetonate, zirconium nitrate, zirconium chloride, or zirconium alkoxide (eg, zirconium isopropoxide, zirconium butoxide, zirconium ethoxide, zirconium methoxyethoxide).
 溶液(ii)を調製する場合には、金属化合物の例として、金属のアセチルアセトナート、アセテートを挙げることができる。ここで、金属は、セリウム(Ce)、プラセオジム(Pr)、ネオジム(Nd)、サマリウム(Sm)、ユウロピウム(Eu)、ガドリニウム(Gd)、テルビウム(Tb)、ジスプロシウム(Dy)、ホルミウム(Ho)、エルビウム(Er)、ツリウム(Tm)、イッテルビウム(Yb)、ルテチウム(Lu)、およびイットリウム(Y)からなる群から選択される金属である。ジルコニウム化合物の例としては、溶液(i)を調製する際に用いるものと同様の化合物を挙げることができる。 In preparing the solution (ii), examples of the metal compound include metal acetylacetonate and acetate. Here, the metal is cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho). , Erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), and a metal selected from the group consisting of yttrium (Y). Examples of the zirconium compound include the same compounds as those used when preparing the solution (i).
 溶液(iii)を調製する場合には、金属化合物として、ジルコニウム、ハフニウム、およびアルミニウム化合物を用いることができる。ジルコニウム、ハフニウム、およびアルミニウム化合物の例としては、対応する金属のアセチルアセトナート、硝酸化物、塩化物、またはアルコキシド(例えば、イソプロポキシド、ブトキシド、エトキシド、メトキシエトキシド)を挙げることができる。 When preparing the solution (iii), zirconium, hafnium, and an aluminum compound can be used as the metal compound. Examples of zirconium, hafnium, and aluminum compounds include the corresponding metal acetylacetonates, nitrates, chlorides, or alkoxides (eg, isopropoxide, butoxide, ethoxide, methoxyethoxide).
 ゲート絶縁膜形成溶液の調製時に使用する溶媒は、アセチルアセトナートが、金属を含むコアに配位することを妨げない溶媒であることが好ましい。このような溶媒の例としては、特に制限するわけではないが、エタノール、プロパノール、ブタノール、2-メトキシエタノール、2-エトキシエタノール、および2-ブトキシエタノールの群から選択されるアルコール溶媒を挙げることができる。 The solvent used at the time of preparing the gate insulating film forming solution is preferably a solvent that does not prevent acetylacetonate from coordinating to the metal-containing core. Examples of such solvents include, but are not limited to, alcohol solvents selected from the group of ethanol, propanol, butanol, 2-methoxyethanol, 2-ethoxyethanol, and 2-butoxyethanol. it can.
 さらに、クラスタ―の形成及びその構造の均一化並びに紫外線の吸収効率の観点から、以上に説明したゲート絶縁膜形成溶液を、密閉容器内で加熱処理に供することが好ましい。 Furthermore, it is preferable to subject the gate insulating film forming solution described above to heat treatment in a hermetically sealed container from the viewpoints of cluster formation, uniform structure, and ultraviolet absorption efficiency.
 密閉容器内での加熱処理は、例えば、ゲート絶縁膜形成溶液をオートクレーブなどの耐圧容器に移して、これを溶媒の沸点以上の温度(例えば、150~200℃)で行うことができる。 The heat treatment in the sealed container can be performed, for example, by transferring the gate insulating film forming solution to a pressure-resistant container such as an autoclave and at a temperature not lower than the boiling point of the solvent (for example, 150 to 200 ° C.).
 ゲート絶縁膜形成溶液として、溶液(i)または溶液(ii)を用いる場合であって、ジルコニウムの代わりにタンタルを用いる場合には、上記の説明において、ジルコニウムをタンタルに置き換えて読むことができるものとする。 When the solution (i) or the solution (ii) is used as the gate insulating film forming solution and tantalum is used instead of zirconium, in the above description, zirconium can be replaced with tantalum. And
(工程(c))
 本工程は、工程(b)で形成した積層体20’のゲート絶縁膜16’の表面に、紫外線を照射しながら、ゲート絶縁膜16’を加熱して、ゲート絶縁層16を形成する工程である(図2(c))。
(Process (c))
This step is a step of forming the gate insulating layer 16 by heating the gate insulating film 16 ′ while irradiating the surface of the gate insulating film 16 ′ of the stacked body 20 ′ formed in the step (b) with ultraviolet rays. (FIG. 2 (c)).
 紫外線の照射は、ムラの少ない均一なゲート絶縁層16を形成するために、ゲート絶縁膜16’の全面に均一に行うことが好ましい。この際、照射する紫外線の照度は、ゲート絶縁膜形成溶液として溶液(i)を用いる場合には、特に制限するわけではないが、7.0~12.0mW/cm2とすることができる。ゲート絶縁膜形成溶液として溶液(ii)または溶液(iii)を用いる場合には、好ましくは5.0~15.0mW/cm2であり、より好ましくは7.0~12.0mW/cm2である。このように、本工程で照射する紫外線の照度を、一般的な表面洗浄用UV装置に用いられている照度と同レベルに低くすることができる。これは、ゲート絶縁膜16’の紫外線吸収度が高いため、高い照度を必要としないことによる。 The ultraviolet irradiation is preferably performed uniformly over the entire surface of the gate insulating film 16 ′ in order to form a uniform gate insulating layer 16 with little unevenness. In this case, the illuminance of the ultraviolet rays to be irradiated is not particularly limited when the solution (i) is used as the gate insulating film forming solution, but can be 7.0 to 12.0 mW / cm 2 . When the solution (ii) or solution (iii) is used as the gate insulating film forming solution, it is preferably 5.0 to 15.0 mW / cm 2 , more preferably 7.0 to 12.0 mW / cm 2 . is there. In this way, the illuminance of the ultraviolet rays irradiated in this step can be lowered to the same level as the illuminance used in a general surface cleaning UV apparatus. This is because a high illuminance is not required because the ultraviolet absorption of the gate insulating film 16 ′ is high.
 積層体20’の加熱方法は、特に制限するわけではないが、例えば、ヒーターの加熱面に、基板12の面が接触するように積層体20’を設置して行うことができる。 The heating method of the laminated body 20 ′ is not particularly limited. For example, the laminated body 20 ′ can be installed so that the surface of the substrate 12 is in contact with the heating surface of the heater.
 積層体20’の加熱条件は、大気中など酸素を含む環境下、まず、80~170℃で初期加熱し、次いで、180~200℃で焼成することが好ましい。初期加熱は主に、ゲート絶縁膜16’に含まれる溶媒を蒸発させることを目的とする。 As for the heating condition of the laminate 20 ′, it is preferable that initial heating is first performed at 80 to 170 ° C. and then baking is performed at 180 to 200 ° C. in an environment containing oxygen such as the air. The initial heating is mainly intended to evaporate the solvent contained in the gate insulating film 16 '.
 ゲート絶縁層16は、複数の層から形成されていてもよい。複数の層を形成する場合には、工程(b)のゲート絶縁膜16’を形成する工程と、上記の初期加熱および焼成の一連の操作を複数回繰り返せばよい。 The gate insulating layer 16 may be formed of a plurality of layers. In the case of forming a plurality of layers, the step of forming the gate insulating film 16 'in the step (b) and the above series of initial heating and baking operations may be repeated a plurality of times.
(工程(d))
 本工程は、ゲート絶縁層16の上に酸化物半導体膜形成溶液を塗布して、酸化物半導体膜18’を形成する工程である(図2(d))。
(Process (d))
This step is a step of applying the oxide semiconductor film forming solution onto the gate insulating layer 16 to form the oxide semiconductor film 18 ′ (FIG. 2D).
 酸化物半導体膜形成溶液の塗布方法としては、制限するわけではないが、スピンコート法、ディップコート法、ダイコート法、バーコート法、ブレードコート法、ロールコート法、スプレーコート法、キャピラリーコート法、ノズルコート法、インクジェット法、スクリーン印刷法、グラビア印刷法、フレキソ印刷法、凸版印刷、反転オフセット印刷など公知の方法を用いることができる。 The application method of the oxide semiconductor film forming solution is not limited, but spin coating, dip coating, die coating, bar coating, blade coating, roll coating, spray coating, capillary coating, Known methods such as a nozzle coating method, an inkjet method, a screen printing method, a gravure printing method, a flexographic printing method, a relief printing, and a reverse offset printing can be used.
 酸化物半導体膜形成溶液は、インジウム(In)、インジウム(In)と錫(Sn)、インジウム(In)と亜鉛(Zn)、インジウム(In)とジルコニウム(Zr)と亜鉛(Zn)、インジウム(In)とガリウム(Ga)、およびインジウム(In)と亜鉛(Zn)とガリウム(Ga)からなる群から選択される金属元素と、酸化剤とを含む。酸化物半導体膜形成溶液は、例えば、以下のように調製することができる。 The oxide semiconductor film formation solution includes indium (In), indium (In) and tin (Sn), indium (In) and zinc (Zn), indium (In), zirconium (Zr), zinc (Zn), indium ( A metal element selected from the group consisting of In), gallium (Ga), indium (In), zinc (Zn), and gallium (Ga), and an oxidizing agent. The oxide semiconductor film forming solution can be prepared, for example, as follows.
 インジウム(In)を含む酸化物半導体膜18’を形成する場合には、インジウム(In)化合物および場合により酸化剤を、溶媒に溶解させて、所定のモル濃度(例えば、0.2mol/kg)のインジウム(In)溶液を作製する。 In the case of forming the oxide semiconductor film 18 ′ containing indium (In), an indium (In) compound and optionally an oxidizing agent are dissolved in a solvent to obtain a predetermined molar concentration (for example, 0.2 mol / kg). An indium (In) solution is prepared.
 インジウム(In)と錫(Sn)とを含む酸化物半導体膜18’を形成する場合には、インジウム(In)化合物および錫(Sn)化合物、ならびに場合により酸化剤を、溶媒に溶解させて、所定のモル濃度(例えば、0.2mol/kg)のインジウム(In)/錫(Sn)溶液を作製する。 When forming the oxide semiconductor film 18 ′ containing indium (In) and tin (Sn), an indium (In) compound and a tin (Sn) compound, and optionally an oxidizing agent are dissolved in a solvent, An indium (In) / tin (Sn) solution having a predetermined molar concentration (for example, 0.2 mol / kg) is prepared.
 インジウム(In)と亜鉛(Zn)とを含む酸化物半導体膜18’を形成する場合には、インジウム(In)化合物および亜鉛(Zn)化合物、ならびに場合により酸化剤を、溶媒に溶解させて、所定のモル濃度(例えば、0.2mol/kg)のインジウム(In)/亜鉛(Zn)溶液を作製する。 In the case of forming the oxide semiconductor film 18 ′ containing indium (In) and zinc (Zn), an indium (In) compound and a zinc (Zn) compound, and optionally an oxidizing agent are dissolved in a solvent, An indium (In) / zinc (Zn) solution having a predetermined molar concentration (for example, 0.2 mol / kg) is prepared.
 インジウム(In)とジルコニウム(Zr)と亜鉛(Zn)とを含む酸化物半導体膜18’を形成する場合には、インジウム(In)化合物、ジルコニウム(Zr)化合物および亜鉛(Zn)化合物、ならびに場合により酸化剤を、溶媒に溶解させて、所定のモル濃度(例えば、0.2mol/kg)のインジウム(In)/ジルコニウム(Zr)/亜鉛(Zn)溶液を作製する。 In the case of forming the oxide semiconductor film 18 ′ containing indium (In), zirconium (Zr), and zinc (Zn), an indium (In) compound, a zirconium (Zr) compound, a zinc (Zn) compound, and a case Thus, the oxidizing agent is dissolved in a solvent to prepare an indium (In) / zirconium (Zr) / zinc (Zn) solution having a predetermined molar concentration (for example, 0.2 mol / kg).
 インジウム(In)とガリウム(Ga)とを含む酸化物半導体膜18’を形成する場合には、インジウム(In)化合物およびガリウム(Ga)化合物、ならびに場合により酸化剤を、溶媒に溶解させて、所定のモル濃度(例えば、0.2mol/kg)のインジウム(In)/ガリウム(Ga)溶液を作製する。 In the case of forming the oxide semiconductor film 18 ′ containing indium (In) and gallium (Ga), an indium (In) compound and a gallium (Ga) compound, and optionally an oxidizing agent are dissolved in a solvent, An indium (In) / gallium (Ga) solution having a predetermined molar concentration (for example, 0.2 mol / kg) is prepared.
 インジウム(In)と亜鉛(Zn)とガリウム(Ga)とを含む酸化物半導体膜18’を形成する場合には、インジウム(In)化合物、亜鉛(Zn)化合物、およびガリウム(Ga)化合物、ならびに場合により酸化剤を、溶媒に溶解させて、所定のモル濃度(例えば、0.2mol/kg)のインジウム(In)/亜鉛(Zn)/ガリウム(Ga)溶液を作製する。 In the case of forming the oxide semiconductor film 18 ′ containing indium (In), zinc (Zn), and gallium (Ga), an indium (In) compound, a zinc (Zn) compound, a gallium (Ga) compound, and In some cases, an oxidizing agent is dissolved in a solvent to prepare an indium (In) / zinc (Zn) / gallium (Ga) solution having a predetermined molar concentration (for example, 0.2 mol / kg).
 インジウム(In)化合物の例としては、硝酸インジウム、インジウムアセチルアセトナート、酢酸インジウム、塩化インジウム、またはインジウムアルコキシド(例えば、インジウムイソプロポキシド、インジウムブトキシド、インジウムエトキシド、インジウムメトキシエトキシド)を挙げることができる。 Examples of indium (In) compounds include indium nitrate, indium acetylacetonate, indium acetate, indium chloride, or indium alkoxide (eg, indium isopropoxide, indium butoxide, indium ethoxide, indium methoxyethoxide). Can do.
 錫(Sn)化合物の例としては、塩化錫、硝酸錫、酢酸錫、または錫アルコキシド(例えば、錫イソプロポキシド、錫ブトキシド、錫エトキシド、錫メトキシエトキシド)を挙げることができる。 Examples of tin (Sn) compounds include tin chloride, tin nitrate, tin acetate, or tin alkoxide (eg, tin isopropoxide, tin butoxide, tin ethoxide, tin methoxyethoxide).
 亜鉛(Zn)化合物の例としては、塩化亜鉛、硝酸亜鉛、酢酸亜鉛、または亜鉛アルコキシド(例えば、亜鉛イソプロポキシド、亜鉛ブトキシド、亜鉛エトキシド、亜鉛メトキシエトキシド)を挙げることができる。 Examples of zinc (Zn) compounds include zinc chloride, zinc nitrate, zinc acetate, or zinc alkoxide (for example, zinc isopropoxide, zinc butoxide, zinc ethoxide, zinc methoxyethoxide).
 ジルコニウム化合物の例としては、硝酸ジルコニウム、塩化ジルコニウム、またはジルコニウムアルコキシド(例えば、ジルコニウムイソプロポキシド、ジルコニウムブトキシド、ジルコニウムエトキシド、ジルコニウムメトキシエトキシド)を挙げることができる。 Examples of zirconium compounds include zirconium nitrate, zirconium chloride, or zirconium alkoxide (eg, zirconium isopropoxide, zirconium butoxide, zirconium ethoxide, zirconium methoxyethoxide).
 ガリウム(Ga)化合物の例としては、硝酸ガリウム、塩化ガリウム、酢酸ガリウム、ガリウムアセチルアセトナートまたはガリウムアルコキシド(ガリウムメトキシド、ガリウムエトキシド、ガリウムプロポキシド、ガリウムブトキシド)を挙げることができる。 Examples of gallium (Ga) compounds include gallium nitrate, gallium chloride, gallium acetate, gallium acetylacetonate or gallium alkoxide (gallium methoxide, gallium ethoxide, gallium propoxide, gallium butoxide).
 酸化物半導体膜形成溶液に用いる溶媒は、特に制限するわけではないが、例えば、2-メトキシエタノール、エタノール、プロパノール、ブタノール、2-エトキシエタノール、2-ブトキシエタノールの群から選択されるアルコール溶媒、酢酸、プロピオン酸、オクチル酸の群から選択されるカルボン酸の溶媒、または、水を採用することができる。TFTの特性向上の観点から、溶媒として水を用いることが好ましい。 The solvent used for the oxide semiconductor film forming solution is not particularly limited. For example, an alcohol solvent selected from the group of 2-methoxyethanol, ethanol, propanol, butanol, 2-ethoxyethanol, 2-butoxyethanol, A solvent of carboxylic acid selected from the group of acetic acid, propionic acid and octylic acid, or water can be employed. From the viewpoint of improving the characteristics of the TFT, it is preferable to use water as the solvent.
 酸化物半導体膜形成溶液に用いる酸化剤の例としては、限定するわけではないが、硝酸、硝酸塩、過酸化物、または過塩素酸塩を挙げることができる。ここで、例えば、酸化物半導体膜形成溶液調製時に、インジウム(In)化合物として硝酸インジウムを用いる場合には、それ自体が硝酸塩であるため、別途、酸化剤を加える必要はない。 Examples of the oxidizing agent used in the oxide semiconductor film forming solution include, but are not limited to, nitric acid, nitrate, peroxide, or perchlorate. Here, for example, when indium nitrate is used as the indium (In) compound when preparing the oxide semiconductor film forming solution, it is not necessary to add an oxidizing agent separately because it is itself a nitrate.
 また、酸化物半導体膜形成溶液は、当該溶液の焼成温度および焼成の強さを調整するために助焼成剤を含んでいてもよい。助焼成剤の例としては、限定するわけではないが、アセチルアセトン、アセチルアセトネート、尿素、または酢酸アンモニウムを挙げることができる。 Further, the oxide semiconductor film forming solution may contain a co-firing agent in order to adjust the firing temperature and firing strength of the solution. Examples of co-firing agents include, but are not limited to, acetylacetone, acetylacetonate, urea, or ammonium acetate.
 酸化物半導体膜形成溶液の調製する際、溶媒に溶質を加えて、適宜加熱してもよい。 When preparing the oxide semiconductor film forming solution, a solute may be added to the solvent and heated appropriately.
(工程(e))
 本工程は、工程(d)で形成した積層体30’の酸化物半導体膜18’の表面に、紫外線を照射しながら、酸化物半導体膜18’を加熱して、酸化物半導体層18を形成する工程である(図2(e))。
(Process (e))
In this step, the oxide semiconductor film 18 ′ is heated while irradiating the surface of the oxide semiconductor film 18 ′ of the stacked body 30 ′ formed in the step (d) with ultraviolet rays, so that the oxide semiconductor layer 18 is formed. (FIG. 2 (e)).
 紫外線の照射は、ムラのない均一な酸化物半導体層18を形成するために、酸化物半導体膜18’の全面に均一に行うことが好ましい。この際、照射する紫外線の照度は、特に制限するわけではないが、5.0~15.0mW/cm2、好ましくは7.0~12.0mW/cm2とすることができる。このように、本工程で照射する紫外線の照度を、一般的な表面洗浄用UV装置に用いられている照度と同レベルに低くすることができる。 Irradiation with ultraviolet rays is preferably performed uniformly over the entire surface of the oxide semiconductor film 18 ′ in order to form a uniform oxide semiconductor layer 18 without unevenness. At this time, the illuminance of the ultraviolet rays to be irradiated is not particularly limited, but can be 5.0 to 15.0 mW / cm 2 , preferably 7.0 to 12.0 mW / cm 2 . In this way, the illuminance of the ultraviolet rays irradiated in this step can be lowered to the same level as the illuminance used in a general surface cleaning UV apparatus.
 積層体30’の加熱方法は、特に制限するわけではないが、例えば、ヒーターの加熱面に、基板12の面が接触するように積層体30’を設置して行うことができる。 The heating method of the stacked body 30 ′ is not particularly limited, but for example, the stacked body 30 ′ can be installed so that the surface of the substrate 12 is in contact with the heating surface of the heater.
 積層体30’の加熱条件は、大気中など酸素を含む環境下、まず、80~170℃で初期加熱し、次いで、180~200℃で焼成することが好ましい。初期加熱は主に、酸化物半導体膜18’に含まれる溶媒を蒸発させることを目的とする。 As for the heating condition of the laminate 30 ′, it is preferable that initial heating is first performed at 80 to 170 ° C. and then baking is performed at 180 to 200 ° C. in an environment containing oxygen such as the air. The initial heating is mainly intended to evaporate the solvent contained in the oxide semiconductor film 18 '.
(工程(f))
 本工程は、酸化物半導体層18の上にソース電極32およびドレイン電極34を形成する工程である(図2(f))。
(Process (f))
This step is a step of forming the source electrode 32 and the drain electrode 34 on the oxide semiconductor layer 18 (FIG. 2F).
 ソース電極32およびドレイン電極34の形成としては、リフトオフ法など既知のいかなる方法を採用することができる。 As the formation of the source electrode 32 and the drain electrode 34, any known method such as a lift-off method can be employed.
 リフトオフ法にて形成する場合、以下の手順で行うことができる。 When forming by lift-off method, it can be performed by the following procedure.
 酸化物半導体層18上に、フォトリソグラフィー法によってパターニングされたレジスト膜を形成し、酸化物半導体層18およびレジスト膜の上に、スパッタリング法などにより、金属層を形成する。その後、レジスト膜を除去することにより、酸化物半導体層18の上にソース電極32およびドレイン電極34を形成することができる。 A resist film patterned by a photolithography method is formed on the oxide semiconductor layer 18, and a metal layer is formed on the oxide semiconductor layer 18 and the resist film by a sputtering method or the like. Thereafter, the source film 32 and the drain electrode 34 can be formed over the oxide semiconductor layer 18 by removing the resist film.
 レジスト膜の材料としては、通常用いられているリフトオフ層の材料、例えば、ロームアンドハース社製LOL2000および東京応化工業社製TSMR8900を用いることができる。 As a material for the resist film, a commonly used lift-off layer material such as LOL2000 manufactured by Rohm and Haas and TSMR8900 manufactured by Tokyo Ohka Kogyo Co., Ltd. can be used.
 金属層が、例えば、インジウム錫酸化物(ITO)により形成されている場合には、ITO層ターゲット材として、5質量%の酸化錫(SnO2)を含有するITOを用いることができる。また、金属層が、例えば、酸化ルテニウム(RuO2)により形成されている場合には、ターゲット材として、酸化ルテニウム(RuO2)を用いることができる。 For example, when the metal layer is formed of indium tin oxide (ITO), ITO containing 5% by mass of tin oxide (SnO 2 ) can be used as the ITO layer target material. The metal layer is, for example, when it is formed by ruthenium oxide (RuO 2) as the target material, it is possible to use ruthenium oxide (RuO 2).
(工程(g))
 本工程は、酸化物半導体層18の一部、ソース電極32、およびドレイン電極34の上にレジスト膜36を形成する工程(図2(g))である。
(Process (g))
This step is a step of forming a resist film 36 on part of the oxide semiconductor layer 18, the source electrode 32, and the drain electrode 34 (FIG. 2G).
 レジスト膜36は、例えば、フォトリソグラフィー法などの公知の方法により、パターニングして形成することができる。 The resist film 36 can be formed by patterning by a known method such as a photolithography method.
 レジスト膜36の材料としては、通常用いられているレジスト材料、例えば、東京応化工業社製OMR85などを用いることができる。 As a material of the resist film 36, a resist material that is usually used, for example, OMR85 manufactured by Tokyo Ohka Kogyo Co., Ltd. can be used.
(工程(h))
 本工程は、工程(g)で形成したレジスト膜36を備える積層体40をエッチングすることにより、レジスト膜36で覆われていない酸化物半導体層18を除去して、薄膜トランジスタ10を得る工程(図2(h))である。
(Process (h))
In this step, the stacked body 40 including the resist film 36 formed in the step (g) is etched to remove the oxide semiconductor layer 18 not covered with the resist film 36, thereby obtaining the thin film transistor 10 (FIG. 2 (h)).
 エッチングとしては、例えば、ITO用エッチャント(関東化学株式会社製ITOシリーズ)などのエッチャントを用いるウェットエッチング法またはアルゴンプラズマによるドライエッチング法を用いることができる。 As the etching, for example, a wet etching method using an etchant such as an etchant for ITO (ITO series manufactured by Kanto Chemical Co., Ltd.) or a dry etching method using argon plasma can be used.
 酸化物半導体層の素子分離(工程(h))後には、ソース電極32およびドレイン電極34と酸化物半導体層18の密着性向上のため、薄膜トランジスタ10をポストアニール処理することが好ましい。ポストアニールは、特に制限するわけではないが、ヒーターなどの加熱手段を用いて、100~200℃、好ましくは180~200℃、10分以上の熱処理により実施することができる。熱処理に加えて、紫外線照射を実施してもよい。この場合、紫外線の照度は、特に制限するわけではないが、5.0~15.0mW/cm2、好ましくは7.0~12.0mW/cm2とすることができる。 After element separation of the oxide semiconductor layer (step (h)), the thin film transistor 10 is preferably post-annealed in order to improve adhesion between the source electrode 32 and the drain electrode 34 and the oxide semiconductor layer 18. The post-annealing is not particularly limited, but can be performed by heat treatment at 100 to 200 ° C., preferably 180 to 200 ° C. for 10 minutes or more using a heating means such as a heater. In addition to heat treatment, ultraviolet irradiation may be performed. In this case, the illuminance of the ultraviolet rays is not particularly limited, but can be 5.0 to 15.0 mW / cm 2 , preferably 7.0 to 12.0 mW / cm 2 .
 以上のとおり、本開示の方法によれば、200℃以下のプロセス温度で薄膜トランジスタを製造することが可能である。このため、例えば、プラスチック基板上にTFTを作製することができる。このように、本開示の方法は、フレキシブルディスプレイの製造用途など幅広い用途に適用することが可能である。したがって、低コスト化の実現も期待できる。 As described above, according to the method of the present disclosure, a thin film transistor can be manufactured at a process temperature of 200 ° C. or less. Therefore, for example, a TFT can be manufactured on a plastic substrate. As described above, the method of the present disclosure can be applied to a wide range of applications such as a flexible display manufacturing application. Therefore, the realization of cost reduction can be expected.
 以下、実施例を示して本発明を具体的に説明するが、本発明は、下記実施例に制限されるものではない。 Hereinafter, the present invention will be specifically described with reference to examples, but the present invention is not limited to the following examples.
<ゲート絶縁膜形成溶液の検討>
[ゲート絶縁膜形成溶液の調製]
(実施例1)
 2-メトキシエタノールに、ランタンアセチルアセトナートおよびジルコニウムブトキシドを、ランタンとジルコニウムとの原子数比が3:7となるように加え、110℃、30分加熱攪拌した。次いで、得られた溶液を耐圧容器に移し、160℃まで昇温し、1時間保持した後、常温に戻すことにより、0.1mol/kgのランタン/ジルコニウム混合溶液を調製した。その後0.2umのPTFEフィルターでろ過を行い、ゲート絶縁膜形成溶液(実施例1)を得た。
<Examination of gate insulating film forming solution>
[Preparation of gate insulating film forming solution]
Example 1
Lanthanum acetylacetonate and zirconium butoxide were added to 2-methoxyethanol so that the atomic ratio of lanthanum and zirconium was 3: 7, and the mixture was heated and stirred at 110 ° C. for 30 minutes. Next, the obtained solution was transferred to a pressure vessel, heated to 160 ° C., held for 1 hour, and then returned to room temperature to prepare a 0.1 mol / kg lanthanum / zirconium mixed solution. Thereafter, filtration was performed with a 0.2 um PTFE filter to obtain a gate insulating film forming solution (Example 1).
(比較例1)
 2-メトキシエタノールに、硝酸ランタンと硝酸ジルコニウムをランタンとジルコニウムとの原子数比が3:7となるように加え、110℃、30分加熱攪拌した。次いで、得られた溶液を耐圧容器に移し、120℃まで昇温し、1時間保持した後、常温に戻すことにより、0.1mol/kgのランタン/ジルコニウム混合溶液を調製した。その後0.2umのPTFEフィルターでろ過を行い、ゲート絶縁膜形成溶液(比較例1)を得た。
(Comparative Example 1)
To 2-methoxyethanol, lanthanum nitrate and zirconium nitrate were added so that the atomic ratio of lanthanum and zirconium was 3: 7, and the mixture was heated and stirred at 110 ° C. for 30 minutes. Next, the obtained solution was transferred to a pressure vessel, heated to 120 ° C., held for 1 hour, and then returned to room temperature to prepare a 0.1 mol / kg lanthanum / zirconium mixed solution. Thereafter, filtration was performed with a 0.2 um PTFE filter to obtain a gate insulating film forming solution (Comparative Example 1).
(比較例2)
 プロピオン酸に、ランタンアセテートを溶解し、これを、110℃、回転数1000rpmで30分間、撹拌して、0.2mol/kgのランタン溶液を調製した。次いで、プロピオン酸に、ジルコニウムブトキシドを溶解し、これを、110℃、回転数1000rpmで30分間、撹拌して、0.2mol/kgのジルコニウム溶液を調製した。調製したランタン溶液およびジルコニウム溶液の各溶液を、ランタンとジルコニウムとの原子数比が3:7となるように混合し、その後0.2umのPTFEフィルターでろ過を行い、ゲート絶縁膜形成溶液(比較例2)を得た。次いで、得られたゲート絶縁膜形成溶液を、オートクレーブに移し、内部温度が180℃になるまで加熱した。この状態で、5時間保持して、容器内を、常温に戻すことにより、オートクレーブ処理したゲート絶縁膜形成溶液(比較例2)を得た。
(Comparative Example 2)
Lanthanum acetate was dissolved in propionic acid, and this was stirred at 110 ° C. and a rotation speed of 1000 rpm for 30 minutes to prepare a 0.2 mol / kg lanthanum solution. Next, zirconium butoxide was dissolved in propionic acid, and this was stirred at 110 ° C. and a rotation speed of 1000 rpm for 30 minutes to prepare a 0.2 mol / kg zirconium solution. The prepared lanthanum solution and zirconium solution were mixed so that the atomic ratio of lanthanum and zirconium was 3: 7, then filtered through a 0.2 um PTFE filter, and a gate insulating film forming solution (comparison) Example 2) was obtained. Next, the obtained gate insulating film forming solution was transferred to an autoclave and heated until the internal temperature reached 180 ° C. In this state, it was held for 5 hours, and the inside of the container was returned to room temperature to obtain an autoclaved gate insulating film forming solution (Comparative Example 2).
[紫外線吸光度測定]
 調製したゲート絶縁膜形成溶液の紫外線吸光度を、紫外可視分光光度計(JASCO International Co., Ltd.社製のV-630紫外可視分光光度計)を用いて測定した。その結果を、図3に示す。
[UV absorbance measurement]
The ultraviolet absorbance of the prepared gate insulating film forming solution was measured using an ultraviolet-visible spectrophotometer (V-630 UV-visible spectrophotometer manufactured by JASCO International Co., Ltd.). The result is shown in FIG.
 図3に示すとおり、ゲート絶縁膜形成溶液(実施例1)は、ゲート絶縁膜形成溶液(比較例1)および(比較例2)と比較し、紫外線波長領域において、吸光度の数値が高かった。 As shown in FIG. 3, the gate insulating film forming solution (Example 1) had higher absorbance values in the ultraviolet wavelength region than the gate insulating film forming solutions (Comparative Example 1) and (Comparative Example 2).
 したがって、ゲート絶縁膜形成溶液(実施例1)は、ゲート絶縁膜形成溶液(比較例1)および(比較例2)と比較し、より紫外線を吸収するといえる。 Therefore, it can be said that the gate insulating film forming solution (Example 1) absorbs ultraviolet rays more than the gate insulating film forming solutions (Comparative Example 1) and (Comparative Example 2).
 この結果は、理論に拘束される訳ではないが、以下のような理由によると推測される。 This result is not bound by theory, but is presumed to be due to the following reasons.
 ランタン化合物とジルコニウム化合物を溶媒に溶解させると、ランタン(La)とジルコニウム(Zr)が酸素原子(O)を介して結合しているLa-O-Zrコアが生じ、その周りに、化合物の陰イオンまたは溶媒が配位して、クラスターを形成する。 When a lanthanum compound and a zirconium compound are dissolved in a solvent, a La—O—Zr core in which lanthanum (La) and zirconium (Zr) are bonded through an oxygen atom (O) is generated, and the compound is surrounded by the shadow of the compound. Ions or solvents coordinate to form clusters.
 実施例1、比較例1、および比較例2では、化合物の陰イオンおよび/または溶媒のみが相違するため、La-O-Zrコアに配位する陰イオンおよび/または溶媒の種類が、溶液の紫外線吸収度に影響を及ぼすと考えられる。 In Example 1, Comparative Example 1 and Comparative Example 2, only the anion and / or solvent of the compound is different, and therefore the type of anion and / or solvent coordinated to the La—O—Zr core is different from that of the solution. It is thought to affect the ultraviolet absorption.
 実施例1では、ランタン化合物としてランタンアセチルアセトナートを使用している。アセチルアセトナートは、多くの金属イオンに配位する2座配位子として広く知られており、本溶液中においても、アセチルアセトナートが優先的にコアに配位していると考えられる。他方、比較例1および2では、ゲート絶縁膜形成溶液中に、アセチルアセトナートを含んでいない。 In Example 1, lanthanum acetylacetonate is used as the lanthanum compound. Acetylacetonate is widely known as a bidentate ligand that coordinates to many metal ions, and it is considered that acetylacetonate is preferentially coordinated to the core even in this solution. On the other hand, in Comparative Examples 1 and 2, the gate insulating film forming solution does not contain acetylacetonate.
 したがって、実施例1のゲート絶縁膜形成溶液において、比較例1および比較例2よりも紫外線の吸収が大きかったのは、アセチルアセトナートを含んでいたからであるといえる。 Therefore, it can be said that the gate insulating film forming solution of Example 1 absorbed ultraviolet rays more than Comparative Example 1 and Comparative Example 2 because it contained acetylacetonate.
[薄膜トランジスタの製造]
(実施例2)
 実施例1で調製したゲート絶縁膜形成溶液を用いて、薄膜トランジスタを以下のように製造した。
[Manufacture of thin film transistors]
(Example 2)
Using the gate insulating film forming solution prepared in Example 1, a thin film transistor was manufactured as follows.
 まず、洗浄したSiウェハ基板上に、スパッタリング法により、チタン/白金(Ti/Pt)層からなるゲート電極を形成した。次いで、チタン/白金(Ti/Pt)層が成膜された基板表面に、酸素プラズマによるアッシング処理(15Wで180秒間)を施した。 First, a gate electrode made of a titanium / platinum (Ti / Pt) layer was formed on a cleaned Si wafer substrate by a sputtering method. Next, the substrate surface on which the titanium / platinum (Ti / Pt) layer was formed was subjected to ashing treatment with oxygen plasma (15 W for 180 seconds).
 その後、ゲート電極コンタクトのためにAgペーストを基板の四隅に形成した。 Thereafter, an Ag paste was formed at the four corners of the substrate for gate electrode contact.
 次に、ゲート電極層上に、スピンコート法(回転数2000rpm、回転時間25秒間)により、実施例1で調製したゲート絶縁膜形成溶液を塗布し、ゲート絶縁膜を形成した。 Next, the gate insulating film forming solution prepared in Example 1 was applied onto the gate electrode layer by spin coating (rotation speed: 2000 rpm, rotation time: 25 seconds) to form a gate insulating film.
 次いで、ゲート絶縁膜を形成した積層体を、150℃に設定されたホットプレート上に5分間静置、加熱した後、温度を上昇させて200℃とし、同温にて加熱しながら、照度が10mW/cm2の紫外線を60分間、ゲート絶縁膜の全面に照射して、ゲート絶縁層を形成した。ここで、紫外線の照射は、UVオゾンクリーナー(サムコ社製UV-300H-E)を用いて行った。以上に実施したスピンコート法によるゲート絶縁膜の形成、150℃での加熱および紫外線照射を伴う200℃での加熱の一連の操作を合計3回繰り返すことにより、ゲート絶縁層を3層積層した。ゲート絶縁層の厚みは合計で、50nmであった。 Next, the stacked body on which the gate insulating film is formed is allowed to stand on a hot plate set at 150 ° C. for 5 minutes and heated, and then the temperature is increased to 200 ° C. The whole surface of the gate insulating film was irradiated with ultraviolet rays of 10 mW / cm 2 for 60 minutes to form a gate insulating layer. Here, UV irradiation was performed using a UV ozone cleaner (Samco UV-300H-E). By repeating the above-described series of operations of forming a gate insulating film by spin coating, heating at 150 ° C., and heating at 200 ° C. accompanied by ultraviolet irradiation, a total of three gate insulating layers were laminated. The total thickness of the gate insulating layer was 50 nm.
 続いて、得られた積層体から、先に形成したAgペーストを除去して、測定用ゲート電極出しを行った。 Subsequently, the previously formed Ag paste was removed from the obtained laminate, and the gate electrode for measurement was taken out.
 その後、ゲート絶縁層上に、スピンコート法(回転数3000rpm、回転時間30秒間)により、酸化物半導体膜形成溶液を塗布した。得られた積層体を、150℃に設定されたホットプレート上に5分間静置、加熱した後、温度を上昇させて200℃とし、同温にて加熱しながら、照度が10mW/cm2の紫外線を60分間、酸化物半導体膜の全面に照射して、酸化物半導体層を形成した。ここで、紫外線の照射は、UVオゾンクリーナー(サムコ社製UV-300H-E)を用いて行った。酸化物半導体層の厚みは、20nmであった。なお、酸化物半導体膜形成溶液としては、2-メトキシエタノールに、硝酸インジウムおよび硝酸亜鉛を、インジウムと亜鉛の原子数比が8:1となるように加え、110℃、回転数1000rpmで30分間、撹拌して、0.2mol/kgに調製したインジウム/亜鉛溶液を使用した。 After that, an oxide semiconductor film forming solution was applied over the gate insulating layer by a spin coating method (rotation speed: 3000 rpm, rotation time: 30 seconds). The obtained laminate was allowed to stand on a hot plate set at 150 ° C. for 5 minutes and heated, and then the temperature was increased to 200 ° C., and the illuminance was 10 mW / cm 2 while heating at the same temperature. The entire surface of the oxide semiconductor film was irradiated with ultraviolet rays for 60 minutes to form an oxide semiconductor layer. Here, UV irradiation was performed using a UV ozone cleaner (Samco UV-300H-E). The thickness of the oxide semiconductor layer was 20 nm. As the oxide semiconductor film forming solution, indium nitrate and zinc nitrate were added to 2-methoxyethanol so that the atomic ratio of indium to zinc was 8: 1, and the temperature was 110 ° C. and the rotation speed was 1000 rpm for 30 minutes. , And an indium / zinc solution prepared at 0.2 mol / kg was used.
 続いて、得られた酸化物半導体層上に、リフトオフ法により、ソース電極およびドレイン電極を形成した。 Subsequently, a source electrode and a drain electrode were formed on the obtained oxide semiconductor layer by a lift-off method.
 その後、素子分離(酸化物半導体層のパターニング)のため、フォトリソグラフィーによってレジスト膜を形成し、得られた積層体を、ITO-07(関東化学株式会社製のITO用エッチャント)を用いたウェットエッチングによりエッチングした。 Thereafter, a resist film is formed by photolithography for element isolation (patterning of the oxide semiconductor layer), and the obtained laminate is wet etched using ITO-07 (an ITO etchant manufactured by Kanto Chemical Co., Inc.). Etched.
 次いで、得られた積層体を、200℃のホットプレート上で10分間加熱することにより、薄膜トランジスタを作製した。 Next, the obtained laminate was heated on a hot plate at 200 ° C. for 10 minutes to produce a thin film transistor.
(比較例3)
 実施例1で調製したゲート絶縁膜形成溶液の代わりに、比較例1で調製したゲート絶縁膜形成溶液を用いた以外は、実施例2と同様にして、薄膜トランジスタを作製した。
(Comparative Example 3)
A thin film transistor was produced in the same manner as in Example 2 except that the gate insulating film forming solution prepared in Comparative Example 1 was used instead of the gate insulating film forming solution prepared in Example 1.
(比較例4)
 実施例1で調製したゲート絶縁膜形成溶液の代わりに、比較例2で調製したゲート絶縁膜形成溶液を用いた以外は、実施例2と同様にして、薄膜トランジスタを作製した。
(Comparative Example 4)
A thin film transistor was fabricated in the same manner as in Example 2, except that the gate insulating film forming solution prepared in Comparative Example 2 was used instead of the gate insulating film forming solution prepared in Example 1.
[薄膜トランジスタの特性評価]
 実施例2および比較例3および4で作製した薄膜トランジスタの特性を評価した。具体的には、Semiconductor Parameter Analyzer(Agilent社製4155C)を用いて、ゲート電圧VG(V)-ドレイン電流ID(A)特性およびゲート電圧VG(V)-ゲート電流IG(A)特性を測定した。その結果を、図4Aから図4Cに示す。図4Aは、実施例2の薄膜トランジスタの特性を示しており、図4Bは、比較例3の薄膜トランジスタの特性を示しており、図4Cは、比較例4の薄膜トランジスタの特性を示している。なお、図4Aから図4Cに示す電圧VD=5Vは、薄膜トランジスタのソース電極とドレイン電極間に印加された電圧が5Vであることを示している。
[Characteristic evaluation of thin film transistor]
The characteristics of the thin film transistors fabricated in Example 2 and Comparative Examples 3 and 4 were evaluated. Specifically, using a Semiconductor Parameter Analyzer (manufactured by Agilent, 4155C), the gate voltage V G (V) -drain current I D (A) characteristics and the gate voltage V G (V) -gate current I G (A) Characteristics were measured. The results are shown in FIGS. 4A to 4C. 4A shows the characteristics of the thin film transistor of Example 2, FIG. 4B shows the characteristics of the thin film transistor of Comparative Example 3, and FIG. 4C shows the characteristics of the thin film transistor of Comparative Example 4. Note that the voltage V D = 5V shown in FIGS. 4A to 4C indicates that the voltage applied between the source electrode and the drain electrode of the thin film transistor is 5V.
 この結果によれば、実施例2の薄膜トランジスタのVG-ID特性およびVG-IG特性は、比較例3および4と比較し、良好であった。 According to this result, the V G -I D characteristic and the V G -I G characteristic of the thin film transistor of Example 2 were better than those of Comparative Examples 3 and 4.
 以上により、ランタン(La)と、ジルコニウム(Zr)と、アセチルアセトナートとを含むゲート絶縁膜形成溶液をTFTの製造に用いることで、プロセス温度を200℃として、良好な電気特性を有するTFTを製造することができることを確認した。 As described above, a gate insulating film forming solution containing lanthanum (La), zirconium (Zr), and acetylacetonate is used for manufacturing a TFT, so that a TFT having good electrical characteristics can be obtained at a process temperature of 200 ° C. It was confirmed that it could be manufactured.
 以下の実施例において、当該ゲート絶縁膜形成溶液からTFTを製造し、より詳細な電気特性を評価した。 In the following examples, TFTs were manufactured from the gate insulating film forming solution, and more detailed electrical characteristics were evaluated.
<薄膜トランジスタの製造およびトランジスタ特性評価>
[薄膜トランジスタの製造]
(実施例3)
 まず、洗浄したSiウェハ基板上に、スパッタリング法により、チタン/白金(Ti/Pt)層からなるゲート電極を形成した。次いで、チタン/白金(Ti/Pt)層が成膜された基板表面に、酸素プラズマによるアッシング処理(15Wで180秒間)を施した。
<Manufacture of thin film transistor and evaluation of transistor characteristics>
[Manufacture of thin film transistors]
(Example 3)
First, a gate electrode made of a titanium / platinum (Ti / Pt) layer was formed on a cleaned Si wafer substrate by sputtering. Next, the substrate surface on which the titanium / platinum (Ti / Pt) layer was formed was subjected to ashing treatment with oxygen plasma (15 W for 180 seconds).
 その後、ゲート電極コンタクトのためにAgペーストを基板の四隅に形成した。 Thereafter, an Ag paste was formed at the four corners of the substrate for gate electrode contact.
 次に、ゲート電極層上に、スピンコート法(回転数2000rpm、回転時間25秒間)により、ゲート絶縁膜形成溶液を塗布し、ゲート絶縁膜を形成した。なお、ゲート絶縁膜形成溶液は、以下のように調製した。まず、2-メトキシエタノールに、ランタンアセチルアセトナートとジルコニウムブトキシドをランタンとジルコニウムとの原子数比が3:7となるように加え、110℃、30分加熱攪拌した。次いで、この溶液を耐圧容器に移し、160℃まで昇温し、1時間保持した後、常温に戻すことにより0.1mol/kgのランタン/ジルコニウム混合溶液を調製した。その後0.2umのPTFEフィルターでろ過を行い、ゲート絶縁膜形成溶液を得た。 Next, a gate insulating film forming solution was applied onto the gate electrode layer by spin coating (rotation speed: 2000 rpm, rotation time: 25 seconds) to form a gate insulating film. The gate insulating film forming solution was prepared as follows. First, lanthanum acetylacetonate and zirconium butoxide were added to 2-methoxyethanol so that the atomic ratio of lanthanum and zirconium was 3: 7, and the mixture was heated and stirred at 110 ° C. for 30 minutes. Next, this solution was transferred to a pressure vessel, heated to 160 ° C., held for 1 hour, and then returned to room temperature to prepare a 0.1 mol / kg lanthanum / zirconium mixed solution. Thereafter, filtration was performed with a 0.2 um PTFE filter to obtain a gate insulating film forming solution.
 次いで、ゲート絶縁膜を形成した積層体を、150℃に設定されたホットプレート上に5分間静置、加熱した後、温度を上昇させて200℃とし、同温にて加熱しながら、照度が10mW/cm2の紫外線を60分間、ゲート絶縁膜の全面に照射して、ゲート絶縁層を形成した。以上に実施したスピンコート法によるゲート絶縁膜の形成、150℃での加熱および紫外線照射を伴う200℃での加熱の一連の操作を合計3回繰り返すことにより、ゲート絶縁層を3層積層した。ゲート絶縁層の厚みは合計で、50nmであった。 Next, the stacked body on which the gate insulating film is formed is allowed to stand on a hot plate set at 150 ° C. for 5 minutes and heated, and then the temperature is increased to 200 ° C. The whole surface of the gate insulating film was irradiated with ultraviolet rays of 10 mW / cm 2 for 60 minutes to form a gate insulating layer. By repeating the above-described series of operations of forming a gate insulating film by spin coating, heating at 150 ° C., and heating at 200 ° C. accompanied by ultraviolet irradiation, a total of three gate insulating layers were laminated. The total thickness of the gate insulating layer was 50 nm.
 続いて、得られた積層体から、先に形成したAgペーストを除去して、測定用ゲート電極出しを行った。 Subsequently, the previously formed Ag paste was removed from the obtained laminate, and the gate electrode for measurement was taken out.
 その後、ゲート絶縁層上に、スピンコート法(回転数3000rpm、回転時間30秒間)により、酸化物半導体膜形成溶液を塗布した。得られた積層体を、100℃に設定されたホットプレート上に5分間静置、加熱した後、温度を上昇させて200℃とし、同温にて加熱しながら、照度が10mW/cm2の紫外線を60分間、酸化物半導体膜の全面に照射して、酸化物半導体層を形成した。酸化物半導体層の厚みは、20nmであった。なお、酸化物半導体膜形成溶液としては、水に、硝酸インジウムを加え、110℃、回転数1000rpmで30分間撹拌して、0.1mol/kgに調製したインジウム溶液を使用した。 After that, an oxide semiconductor film forming solution was applied over the gate insulating layer by a spin coating method (rotation speed: 3000 rpm, rotation time: 30 seconds). The obtained laminate was allowed to stand on a hot plate set at 100 ° C. for 5 minutes and heated, and then the temperature was increased to 200 ° C., and the illuminance was 10 mW / cm 2 while heating at the same temperature. The entire surface of the oxide semiconductor film was irradiated with ultraviolet rays for 60 minutes to form an oxide semiconductor layer. The thickness of the oxide semiconductor layer was 20 nm. As the oxide semiconductor film formation solution, an indium solution prepared by adding indium nitrate to water and stirring at 110 ° C. and a rotation speed of 1000 rpm for 30 minutes to adjust to 0.1 mol / kg was used.
 続いて、得られた酸化物半導体層上に、リフトオフ法により、ソース電極およびドレイン電極を形成した。 Subsequently, a source electrode and a drain electrode were formed on the obtained oxide semiconductor layer by a lift-off method.
 その後、素子分離(酸化物半導体層のパターニング)のため、フォトリソグラフィーによってレジスト膜を形成し、得られた積層体を、ITO-07(関東化学株式会社製のITO用エッチャント)を用いたウェットエッチングによりエッチングした。 Thereafter, a resist film is formed by photolithography for element isolation (patterning of the oxide semiconductor layer), and the obtained laminate is wet etched using ITO-07 (an ITO etchant manufactured by Kanto Chemical Co., Inc.). Etched.
 次いで、得られた積層体を、200℃のホットプレート上に静置し、照度が10mW/cm2の紫外線を照射しながら、10分間加熱することにより、薄膜トランジスタを作製した。 Next, the obtained laminate was allowed to stand on a hot plate at 200 ° C. and heated for 10 minutes while irradiating ultraviolet rays having an illuminance of 10 mW / cm 2 , thereby producing a thin film transistor.
[トランジスタの特性評価]
 実施例3で製造した薄膜トランジスタに関し、on/off比、閾値電圧(Vth)、サブスレッショルド特性(SS)、電界効果移動度(μsat)、ヒステリシス(Hys)、およびゲートリーク電流(A)を測定して、そのトランジスタ特性を評価した。なお、これらのトランジスタ特性は、Semiconductor Parameter Analyzer(Agilent社製4155C)を用いて測定した。その測定結果を表1に示す。
[Evaluation of transistor characteristics]
Regarding the thin film transistor manufactured in Example 3, the on / off ratio, threshold voltage (Vth), subthreshold characteristic (SS), field effect mobility (μ sat ), hysteresis (Hys), and gate leakage current (A) are measured. Then, the transistor characteristics were evaluated. Note that these transistor characteristics were measured using a Semiconductor Parameter Analyzer (Agilent 4155C). The measurement results are shown in Table 1.
表1 トランジスタ特性の測定結果
Figure JPOXMLDOC01-appb-I000001
Table 1 Measurement results of transistor characteristics
Figure JPOXMLDOC01-appb-I000001
 表1に示すとおり、実施例3の薄膜トランジスタは、良好なトランジスタ特性を有していた。特に、電界効果移動度(μ)が2cm2/Vs以上であり、ゲートリーク電流が8.1×10-10Aと良好であった。 As shown in Table 1, the thin film transistor of Example 3 had good transistor characteristics. In particular, the field effect mobility (μ) was 2 cm 2 / Vs or more, and the gate leakage current was as good as 8.1 × 10 −10 A.
 以上のとおり、ゲート絶縁膜形成溶液として、ランタン(La)と、ジルコニウム(Zr)と、アセチルアセトナートとを含む溶液(i)を用いた場合に、薄膜トランジスタは、良好なトランジスタ特性を有していた。次に、ゲート絶縁膜形成溶液として、その他の特定の金属元素と、アセチルアセトナートとを含む溶液(ii)および溶液(iii)を用いた場合の薄膜トランジスタの電気特性を測定した。先ず、溶液(ii)を用いた場合の結果を以下に示す。 As described above, when the solution (i) containing lanthanum (La), zirconium (Zr), and acetylacetonate is used as the gate insulating film forming solution, the thin film transistor has good transistor characteristics. It was. Next, the electrical characteristics of the thin film transistor were measured when a solution (ii) and a solution (iii) containing other specific metal elements and acetylacetonate were used as the gate insulating film forming solution. First, the results when using the solution (ii) are shown below.
<薄膜トランジスタの製造>
(実施例4)
 まず、洗浄したSiウェハ基板上に、スパッタリング法により、チタン/白金(Ti/Pt)層からなるゲート電極を形成した。次いで、チタン/白金(Ti/Pt)層が成膜された基板表面に、酸素プラズマによるアッシング処理(15Wで180秒間)を施した。
<Manufacture of thin film transistor>
Example 4
First, a gate electrode made of a titanium / platinum (Ti / Pt) layer was formed on a cleaned Si wafer substrate by sputtering. Next, the substrate surface on which the titanium / platinum (Ti / Pt) layer was formed was subjected to ashing treatment with oxygen plasma (15 W for 180 seconds).
 その後、ゲート電極コンタクト領域を形成するためにAgペーストを基板の四隅に形成した。 Thereafter, Ag paste was formed at the four corners of the substrate in order to form gate electrode contact regions.
 次に、ゲート電極層上に、スピンコート法(回転数2000rpm、回転時間25秒間)により、ゲート絶縁膜形成溶液を塗布し、ゲート絶縁膜を形成した。なお、ゲート絶縁膜形成溶液を、以下のように調製した。まず、2-メトキシエタノールに、サマリウムアセチルアセトナートおよびジルコニウムアセチルアセトナートを、サマリウムとジルコニウムとの原子数比が1:9となるように加え、110℃、30分加熱攪拌し、0.1mol/kgのサマリウム/ジルコニウム溶液を得た。次いで、得られた溶液を耐圧容器に移し、160℃まで昇温し、1時間保持した後、常温に戻すことにより、0.1mol/kgのサマリウム/ジルコニウム溶液を調製した。その後0.2umのPTFEフィルターでろ過を行い、ゲート絶縁膜形成溶液を得た。 Next, a gate insulating film forming solution was applied onto the gate electrode layer by spin coating (rotation speed: 2000 rpm, rotation time: 25 seconds) to form a gate insulating film. A gate insulating film forming solution was prepared as follows. First, samarium acetylacetonate and zirconium acetylacetonate were added to 2-methoxyethanol so that the atomic ratio of samarium and zirconium was 1: 9, and the mixture was stirred with heating at 110 ° C. for 30 minutes, 0.1 mol / wt. kg of samarium / zirconium solution was obtained. Next, the obtained solution was transferred to a pressure vessel, heated to 160 ° C., held for 1 hour, and then returned to room temperature to prepare a 0.1 mol / kg samarium / zirconium solution. Thereafter, filtration was performed with a 0.2 um PTFE filter to obtain a gate insulating film forming solution.
 次いで、ゲート絶縁膜を形成した積層体を、150℃に設定されたホットプレート上に5分間静置、加熱した後、温度を上昇させて200℃とし、同温にて加熱しながら、照度が10.0mW/cm2の紫外線を60分間、ゲート絶縁膜の全面に照射して、ゲート絶縁層を形成した。ここで、紫外線の照射は、UVオゾンクリーナー(サムコ社製UV-300H-E)を用いて行った。以上に実施したスピンコート法によるゲート絶縁膜の形成、150℃での加熱および紫外線照射を伴う200℃での加熱の一連の操作を合計3回繰り返すことにより、ゲート絶縁層を3層積層した。ゲート絶縁層の厚みは合計で50nmであった。 Next, the stacked body on which the gate insulating film is formed is allowed to stand on a hot plate set at 150 ° C. for 5 minutes and heated, and then the temperature is increased to 200 ° C. The entire surface of the gate insulating film was irradiated with ultraviolet rays of 10.0 mW / cm 2 for 60 minutes to form a gate insulating layer. Here, UV irradiation was performed using a UV ozone cleaner (Samco UV-300H-E). By repeating the above-described series of operations of forming a gate insulating film by spin coating, heating at 150 ° C., and heating at 200 ° C. accompanied by ultraviolet irradiation, a total of three gate insulating layers were laminated. The total thickness of the gate insulating layer was 50 nm.
 続いて、得られた積層体から、先に形成したAgペーストを除去して、測定用ゲート電極出しを行った。 Subsequently, the previously formed Ag paste was removed from the obtained laminate, and the gate electrode for measurement was taken out.
 その後、ゲート絶縁層上に、スピンコート法(回転数3000rpm、回転時間30秒間)により、酸化物半導体膜形成溶液を塗布し、得られた積層体を、150℃に設定されたホットプレート上に5分間静置、加熱した後、温度を上昇させて200℃とし、同温にて加熱しながら、照度が10.0mW/cm2の紫外線を60分間、酸化物半導体膜の全面に照射して、酸化物半導体層(InZnO層)を形成した。ここで、紫外線の照射は、UVオゾンクリーナー(サムコ社製UV-300H-E)を用いて行った。酸化物半導体層の厚みは、15nmであった。なお、酸化物半導体膜形成溶液としては、2-メトキシエタノールに、硝酸インジウムおよび硝酸亜鉛を、インジウムと亜鉛との原子数比が8:1になるように加え、110℃、回転数1000rpmで30分間、撹拌して、0.2mol/kgに調製したものを使用した。 Thereafter, an oxide semiconductor film forming solution is applied onto the gate insulating layer by a spin coating method (rotation speed: 3000 rpm, rotation time: 30 seconds), and the obtained stacked body is placed on a hot plate set at 150 ° C. After standing and heating for 5 minutes, the temperature was raised to 200 ° C., and the surface of the oxide semiconductor film was irradiated with ultraviolet rays having an illuminance of 10.0 mW / cm 2 for 60 minutes while heating at the same temperature. An oxide semiconductor layer (InZnO layer) was formed. Here, UV irradiation was performed using a UV ozone cleaner (Samco UV-300H-E). The thickness of the oxide semiconductor layer was 15 nm. As the oxide semiconductor film forming solution, indium nitrate and zinc nitrate were added to 2-methoxyethanol so that the atomic ratio of indium to zinc was 8: 1, and the solution was 30 ° C. at 110 ° C. and 1000 rpm. A mixture prepared by stirring for 0.2 minutes to 0.2 mol / kg was used.
 続いて、酸化物半導体層上に、リフトオフ法により、ソース電極およびドレイン電極を形成した。 Subsequently, a source electrode and a drain electrode were formed on the oxide semiconductor layer by a lift-off method.
 その後、素子分離(酸化物半導体層のパターニング)のため、フォトリソグラフィーによってレジスト膜を形成し、得られた積層体を、ITO-02(関東化学株式会社製のITO用エッチャント)を用いたウェットエッチングによりエッチングした。 Then, for element isolation (patterning of the oxide semiconductor layer), a resist film is formed by photolithography, and the obtained laminate is wet-etched using ITO-02 (an ITO etchant manufactured by Kanto Chemical Co., Inc.). Etched.
 次いで、得られた積層体を、200℃のホットプレート上に静置し、照度が10.0mW/cm2の紫外線を照射しながら、10分間加熱することにより、薄膜トランジスタを作製した。ここで、紫外線の照射は、UVオゾンクリーナー(サムコ社製UV-300H-E)を用いて行った。 Next, the obtained laminate was allowed to stand on a hot plate at 200 ° C. and heated for 10 minutes while irradiating ultraviolet rays having an illuminance of 10.0 mW / cm 2 , thereby producing a thin film transistor. Here, UV irradiation was performed using a UV ozone cleaner (Samco UV-300H-E).
(実施例5)
 ゲート絶縁膜形成溶液の調製時に、サマリウムとジルコニウムとの原子数比が2:8となるようにサマリウムアセチルアセトナートとジルコニウムアセチルアセトナートとを加えた以外は、実施例4と同様にして、薄膜トランジスタを作製した。
(Example 5)
A thin film transistor was prepared in the same manner as in Example 4 except that samarium acetylacetonate and zirconium acetylacetonate were added so that the atomic ratio of samarium to zirconium was 2: 8 when the gate insulating film forming solution was prepared. Was made.
(実施例6)
 ゲート絶縁膜形成溶液の調製時に、サマリウムとジルコニウムとの原子数比が3:7となるようにサマリウムアセチルアセトナートとジルコニウムアセチルアセトナートとを加えた以外は、実施例4と同様にして、薄膜トランジスタを作製した。
(Example 6)
A thin film transistor was prepared in the same manner as in Example 4 except that samarium acetylacetonate and zirconium acetylacetonate were added so that the atomic ratio of samarium to zirconium was 3: 7 when the gate insulating film forming solution was prepared. Was made.
(実施例7)
 ゲート絶縁膜形成溶液の調製時に、サマリウムアセチルアセトナートの代わりに、ユウロピウムアセチルアセトナートを用い、酸化物半導体膜形成溶液の調製時に、硝酸亜鉛を用いず、また2-メトキシエタノールの代わりに水を用いた以外は、実施例4と同様にして、薄膜トランジスタを作製した。
(Example 7)
Europium acetylacetonate is used instead of samarium acetylacetonate when preparing the gate insulating film forming solution, and zinc nitrate is not used when preparing the oxide semiconductor film forming solution, and water is used instead of 2-methoxyethanol. A thin film transistor was fabricated in the same manner as in Example 4 except that it was used.
(実施例8)
 ゲート絶縁膜形成溶液の調製時に、サマリウムアセチルアセトナートの代わりに、ユウロピウムアセチルアセトナートを用い、ユウロピウムとジルコニウムとの原子数比が2:8となるようにユウロピウムアセチルアセトナートとジルコニウムアセチルアセトナートとを加え、酸化物半導体膜形成溶液の調製時に硝酸亜鉛を用いず、2-メトキシエタノールの代わりに水を用いた以外は、実施例4と同様にして、薄膜トランジスタを作製した。
(Example 8)
When preparing the gate insulating film forming solution, europium acetylacetonate is used instead of samarium acetylacetonate, and europium acetylacetonate and zirconium acetylacetonate are mixed so that the atomic ratio of europium and zirconium is 2: 8. A thin film transistor was produced in the same manner as in Example 4 except that zinc nitrate was not used in preparing the oxide semiconductor film forming solution and water was used instead of 2-methoxyethanol.
(実施例9)
 ゲート絶縁膜形成溶液の調製時に、サマリウムアセチルアセトナートの代わりに、ユウロピウムアセチルアセトナートを用い、ユウロピウムとジルコニウムとの原子数比が3:7となるようにユウロピウムアセチルアセトナートとジルコニウムアセチルアセトナートとを加え、酸化物半導体膜形成溶液の調製時に硝酸亜鉛を用いず、2-メトキシエタノールの代わりに水を用いた以外は、実施例4と同様にして、薄膜トランジスタを作製した。
Example 9
When preparing the gate insulating film forming solution, europium acetylacetonate is used instead of samarium acetylacetonate, and europium acetylacetonate and zirconium acetylacetonate are mixed so that the atomic ratio of europium and zirconium is 3: 7. A thin film transistor was produced in the same manner as in Example 4 except that zinc nitrate was not used in preparing the oxide semiconductor film forming solution and water was used instead of 2-methoxyethanol.
(実施例10)
 ゲート絶縁膜形成溶液の調製時に、サマリウムアセチルアセトナートの代わりに、イットリウムアセテートを用い、イットリウムとジルコニウムとの原子数比が1:9となるようにイットリウムアセテートとジルコニウムアセチルアセトナートとを加え、酸化物半導体膜形成溶液の調製時に硝酸亜鉛を用いず、2-メトキシエタノールの代わりに水を用いた以外は、実施例4と同様にして、薄膜トランジスタを作製した。
(Example 10)
When preparing the gate insulating film forming solution, yttrium acetate was used instead of samarium acetylacetonate, and yttrium acetate and zirconium acetylacetonate were added so that the atomic ratio of yttrium to zirconium was 1: 9. A thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
(実施例11)
 ゲート絶縁膜形成溶液の調製時に、サマリウムアセチルアセトナートの代わりに、セリウムアセテートを用い、セリウムとジルコニウムとの原子数比が1:9となるようにセリウムアセテートとジルコニウムアセチルアセトナートとを加え、酸化物半導体膜形成溶液の調製時に硝酸亜鉛を用いず、2-メトキシエタノールの代わりに水を用いた以外は、実施例4と同様にして、薄膜トランジスタを作製した。
(Example 11)
When preparing the gate insulating film forming solution, cerium acetate was used in place of samarium acetylacetonate, and cerium acetate and zirconium acetylacetonate were added so that the atomic ratio of cerium and zirconium was 1: 9. A thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
(実施例12)
 ゲート絶縁膜形成溶液の調製時に、サマリウムアセチルアセトナートの代わりに、プラセオジムアセテートを用い、プラセオジムとジルコニウムとの原子数比が1:9となるようにプラセオジムアセテートとジルコニウムアセチルアセトナートとを加え、酸化物半導体膜形成溶液の調製時に硝酸亜鉛を用いず、2-メトキシエタノールの代わりに水を用いた以外は、実施例4と同様にして、薄膜トランジスタを作製した。
(Example 12)
When preparing the gate insulating film forming solution, praseodymium acetate is used instead of samarium acetylacetonate, and praseodymium acetate and zirconium acetylacetonate are added so that the atomic ratio of praseodymium and zirconium is 1: 9, and oxidation is performed. A thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
(実施例13)
 ゲート絶縁膜形成溶液の調製時に、サマリウムアセチルアセトナートの代わりに、ネオジムアセテートを用い、ネオジムとジルコニウムとの原子数比が1:9となるようにネオジムアセテートとジルコニウムアセチルアセトナートとを加え、酸化物半導体膜形成溶液の調製時に硝酸亜鉛を用いず、2-メトキシエタノールの代わりに水を用いた以外は、実施例4と同様にして、薄膜トランジスタを作製した。
(Example 13)
When preparing the gate insulating film forming solution, neodymium acetate was used instead of samarium acetylacetonate, and neodymium acetate and zirconium acetylacetonate were added so that the atomic ratio of neodymium and zirconium was 1: 9. A thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
(実施例14)
 ゲート絶縁膜形成溶液の調製時に、サマリウムアセチルアセトナートの代わりに、サマリウムアセテートを用い、サマリウムとジルコニウムとの原子数比が1:9となるようにサマリウムアセテートとジルコニウムアセチルアセトナートとを加え、酸化物半導体膜形成溶液の調製時に硝酸亜鉛を用いず、2-メトキシエタノールの代わりに水を用いた以外は、実施例4と同様にして、薄膜トランジスタを作製した。
(Example 14)
When preparing the gate insulating film forming solution, samarium acetate is used instead of samarium acetylacetonate, and samarium acetate and zirconium acetylacetonate are added so that the atomic ratio of samarium and zirconium is 1: 9. A thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
(実施例15)
 ゲート絶縁膜形成溶液の調製時に、サマリウムアセチルアセトナートの代わりに、ユウロピウムアセテートを用い、ユウロピウムとジルコニウムとの原子数比が1:9となるようにユウロピウムアセテートとジルコニウムアセチルアセトナートとを加え、酸化物半導体膜形成溶液の調製時に硝酸亜鉛を用いず、2-メトキシエタノールの代わりに水を用いた以外は、実施例4と同様にして、薄膜トランジスタを作製した。
(Example 15)
When preparing the gate insulating film forming solution, europium acetate is used instead of samarium acetylacetonate, and europium acetate and zirconium acetylacetonate are added so that the atomic ratio of europium and zirconium is 1: 9. A thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
(実施例16)
 ゲート絶縁膜形成溶液の調製時に、サマリウムアセチルアセトナートの代わりに、ガドリニウムアセテートを用い、ガドリニウムとジルコニウムとの原子数比が1:9となるようにガドリニウムアセテートとジルコニウムアセチルアセトナートとを加え、酸化物半導体膜形成溶液の調製時に硝酸亜鉛を用いず、2-メトキシエタノールの代わりに水を用いた以外は、実施例4と同様にして、薄膜トランジスタを作製した。
(Example 16)
When preparing the gate insulating film forming solution, gadolinium acetate was used instead of samarium acetylacetonate, gadolinium acetate and zirconium acetylacetonate were added so that the atomic ratio of gadolinium and zirconium was 1: 9, and oxidation was performed. A thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
(実施例17)
 ゲート絶縁膜形成溶液の調製時に、サマリウムアセチルアセトナートの代わりに、テルビウムアセテートを用い、テルビウムとジルコニウムとの原子数比が1:9となるようにテルビウムアセテートとジルコニウムアセチルアセトナートとを加え、酸化物半導体膜形成溶液の調製時に硝酸亜鉛を用いず、2-メトキシエタノールの代わりに水を用いた以外は、実施例4と同様にして、薄膜トランジスタを作製した。
(Example 17)
When preparing the gate insulating film forming solution, terbium acetate was used instead of samarium acetylacetonate, terbium acetate and zirconium acetylacetonate were added so that the atomic ratio of terbium and zirconium was 1: 9, and oxidation was performed. A thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
(実施例18)
 ゲート絶縁膜形成溶液の調製時に、サマリウムアセチルアセトナートの代わりに、ジスプロシウムアセテートを用い、ジスプロシウムとジルコニウムとの原子数比が1:9となるようにジスプロシウムアセテートとジルコニウムアセチルアセトナートとを加え、酸化物半導体膜形成溶液の調製時に硝酸亜鉛を用いず、2-メトキシエタノールの代わりに水を用いた以外は、実施例4と同様にして、薄膜トランジスタを作製した。
(Example 18)
When preparing the gate insulating film forming solution, dysprosium acetate was used instead of samarium acetylacetonate, and dysprosium acetate and zirconium acetylacetonate were added so that the atomic ratio of dysprosium and zirconium was 1: 9. A thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
(実施例19)
 ゲート絶縁膜形成溶液の調製時に、サマリウムアセチルアセトナートの代わりに、ホルミウムアセテートを用い、ホルミウムとジルコニウムとの原子数比が1:9となるようにホルミウムアセテートとジルコニウムアセチルアセトナートとを加え、酸化物半導体膜形成溶液の調製時に硝酸亜鉛を用いず、2-メトキシエタノールの代わりに水を用いた以外は、実施例4と同様にして、薄膜トランジスタを作製した。
(Example 19)
When preparing the gate insulating film forming solution, holmium acetate was used instead of samarium acetylacetonate, and holmium acetate and zirconium acetylacetonate were added so that the atomic ratio of holmium and zirconium was 1: 9. A thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
(実施例20)
 ゲート絶縁膜形成溶液の調製時に、サマリウムアセチルアセトナートの代わりに、エルビウムアセテートを用い、エルビウムとジルコニウムとの原子数比が1:9となるようにエルビウムアセテートとジルコニウムアセチルアセトナートとを加え、酸化物半導体膜形成溶液の調製時に硝酸亜鉛を用いず、2-メトキシエタノールの代わりに水を用いた以外は、実施例4と同様にして、薄膜トランジスタを作製した。
(Example 20)
When preparing the gate insulating film forming solution, erbium acetate was used instead of samarium acetylacetonate, and erbium acetate and zirconium acetylacetonate were added so that the atomic ratio of erbium and zirconium was 1: 9. A thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
(実施例21)
 ゲート絶縁膜形成溶液の調製時に、サマリウムアセチルアセトナートの代わりに、ツリウムアセテートを用い、ツリウムとジルコニウムとの原子数比が1:9となるようにツリウムアセテートとジルコニウムアセチルアセトナートとを加え、酸化物半導体膜形成溶液の調製時に硝酸亜鉛を用いず、2-メトキシエタノールの代わりに水を用いた以外は、実施例4と同様にして、薄膜トランジスタを作製した。
(Example 21)
When preparing the gate insulating film forming solution, thulium acetate is used instead of samarium acetylacetonate, and thulium acetate and zirconium acetylacetonate are added so that the atomic ratio of thulium and zirconium is 1: 9, and oxidation is performed. A thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
(実施例22)
 ゲート絶縁膜形成溶液の調製時に、サマリウムアセチルアセトナートの代わりに、イッテルビウムアセテートを用い、イッテルビウムとジルコニウムとの原子数比が1:9となるようにイッテルビウムアセテートとジルコニウムアセチルアセトナートとを加え、酸化物半導体膜形成溶液の調製時に硝酸亜鉛を用いず、2-メトキシエタノールの代わりに水を用いた以外は、実施例4と同様にして、薄膜トランジスタを作製した。
(Example 22)
When preparing the gate insulating film forming solution, ytterbium acetate was used instead of samarium acetylacetonate, and ytterbium acetate and zirconium acetylacetonate were added so that the atomic ratio of ytterbium and zirconium was 1: 9. A thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
(実施例23)
 ゲート絶縁膜形成溶液の調製時に、サマリウムアセチルアセトナートの代わりに、ルテチウムアセテートを用い、ルテチウムとジルコニウムとの原子数比が1:9となるようにルテチウムアセテートとジルコニウムアセチルアセトナートとを加え、酸化物半導体膜形成溶液の調製時に硝酸亜鉛を用いず、2-メトキシエタノールの代わりに水を用いた以外は、実施例4と同様にして、薄膜トランジスタを作製した。
(Example 23)
When preparing the gate insulating film forming solution, lutetium acetate was used instead of samarium acetylacetonate, and lutetium acetate and zirconium acetylacetonate were added so that the atomic ratio of lutetium and zirconium was 1: 9. A thin film transistor was fabricated in the same manner as in Example 4 except that zinc nitrate was not used in the preparation of the physical semiconductor film forming solution and water was used instead of 2-methoxyethanol.
(実施例24)
 ゲート絶縁膜形成溶液の調製時に、サマリウムアセチルアセトナートの代わりに、ユウロピウムアセチルアセトナートを用い、ユウロピウムとジルコニウムとの原子数比が4:6となるようにユウロピウムアセチルアセトナートとジルコニウムアセチルアセトナートとを加えた以外は、実施例4と同様にして、薄膜トランジスタを作製した。
(Example 24)
When preparing the gate insulating film forming solution, europium acetylacetonate is used instead of samarium acetylacetonate, and europium acetylacetonate and zirconium acetylacetonate are mixed so that the atomic ratio of europium and zirconium is 4: 6. A thin film transistor was fabricated in the same manner as in Example 4 except that the above was added.
(実施例25)
 酸化物半導体膜形成溶液の調製時に、硝酸亜鉛の代わりに、硝酸ガリウムを用い、インジウムとガリウムとの原子数比が8:1となるように硝酸インジウムと硝酸ガリウムとを加え、また2-メトキシエタノールの代わりに水を用いた以外は、実施例4と同様にして、薄膜トランジスタを作製した。
(Example 25)
In preparing the oxide semiconductor film forming solution, gallium nitrate is used instead of zinc nitrate, indium nitrate and gallium nitrate are added so that the atomic ratio of indium to gallium is 8: 1, and 2-methoxy is added. A thin film transistor was produced in the same manner as in Example 4 except that water was used instead of ethanol.
(実施例26)
 ゲート絶縁膜形成溶液の調製時に、サマリウムとジルコニウムとの原子数比が1:99となるようにサマリウムアセチルアセトナートとジルコニウムアセチルアセトナートとを加え、酸化物半導体膜形成溶液の調製時に、硝酸亜鉛を用いず、また2-メトキシエタノールの代わりに水を用いた以外は、実施例4と同様にして、薄膜トランジスタを作製した。
(Example 26)
When preparing the gate insulating film forming solution, samarium acetylacetonate and zirconium acetylacetonate are added so that the atomic ratio of samarium and zirconium is 1:99, and when preparing the oxide semiconductor film forming solution, zinc nitrate is added. A thin film transistor was manufactured in the same manner as in Example 4 except that water was used instead of 2-methoxyethanol.
(実施例27)
 ゲート絶縁膜形成溶液の調製時に、サマリウムとジルコニウムとの原子数比が4:96となるようにサマリウムアセチルアセトナートとジルコニウムアセチルアセトナートとを加え、酸化物半導体膜形成溶液の調製時に、硝酸亜鉛を用いず、また2-メトキシエタノールの代わりに水を用いた以外は、実施例4と同様にして、薄膜トランジスタを作製した。
(Example 27)
When preparing the gate insulating film forming solution, samarium acetylacetonate and zirconium acetylacetonate are added so that the atomic ratio of samarium and zirconium is 4:96, and when preparing the oxide semiconductor film forming solution, zinc nitrate is added. A thin film transistor was manufactured in the same manner as in Example 4 except that water was used instead of 2-methoxyethanol.
(実施例28)
 ゲート絶縁膜形成溶液の調製時に、サマリウムとジルコニウムとの原子数比が8:92となるようにサマリウムアセチルアセトナートとジルコニウムアセチルアセトナートとを加え、酸化物半導体膜形成溶液の調製時に、硝酸亜鉛を用いず、また2-メトキシエタノールの代わりに水を用いた以外は、実施例4と同様にして、薄膜トランジスタを作製した。
(Example 28)
During the preparation of the gate insulating film forming solution, samarium acetylacetonate and zirconium acetylacetonate are added so that the atomic ratio of samarium and zirconium is 8:92, and during the preparation of the oxide semiconductor film forming solution, zinc nitrate is added. A thin film transistor was manufactured in the same manner as in Example 4 except that water was used instead of 2-methoxyethanol.
(比較例5)
 ゲート絶縁膜形成溶液の調製時に、サマリウムとジルコニウムとの原子数比が1:1となるようにサマリウムアセチルアセトナートとジルコニウムアセチルアセトナートとを加えた以外は、実施例4と同様にして、薄膜トランジスタを作製した。
(Comparative Example 5)
A thin film transistor was prepared in the same manner as in Example 4 except that samarium acetylacetonate and zirconium acetylacetonate were added so that the atomic ratio of samarium to zirconium was 1: 1 when the gate insulating film forming solution was prepared. Was made.
<トランジスタの特性評価>
 上記実施例および比較例で製造した薄膜トランジスタに関し、on/off比、閾値電圧(Vth)、サブスレッショルド特性(SS)、電界効果移動度(μsat)、ヒステリシス(Hys)、およびゲートリーク電流(A)を測定して、そのトランジスタ特性を評価した。なお、これらのトランジスタ特性は、Semiconductor Parameter Analyzer(Agilent社製4155C)を用いて測定した。その測定結果を表2に示す。

<Evaluation of transistor characteristics>
Regarding the thin film transistors manufactured in the above examples and comparative examples, the on / off ratio, threshold voltage (Vth), subthreshold characteristic (SS), field effect mobility (μ sat ), hysteresis (Hys), and gate leakage current (A ) Was measured to evaluate the transistor characteristics. Note that these transistor characteristics were measured using a Semiconductor Parameter Analyzer (Agilent 4155C). The measurement results are shown in Table 2.

 (表2-1)
表2 トランジスタ特性の測定結果
Figure JPOXMLDOC01-appb-I000002








(Table 2-1)
Table 2 Measurement results of transistor characteristics
Figure JPOXMLDOC01-appb-I000002








 (表2-2)
(表2の続き)
Figure JPOXMLDOC01-appb-I000003
(Table 2-2)
(Continued from Table 2)
Figure JPOXMLDOC01-appb-I000003
 表2に示すとおり、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu、およびYからなる群から選択される金属元素とZrとの原子数比が1:1.5~1:99である実施例4~28の薄膜トランジスタは、非常に良好な電気特性を有していた。薄膜トランジスタを、例えば高精細または大面積のディスプレイに適用する場合には、その駆動のために、概ね50cm2/vs以上の電界効果移動度が求められるところ、実施例4~28の薄膜トランジスタは、その要求を満たすものであった。 As shown in Table 2, the atomic ratio of Zr to a metal element selected from the group consisting of Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and Y The thin film transistors of Examples 4 to 28 having a ratio of 1: 1.5 to 1:99 had very good electrical characteristics. When the thin film transistor is applied to, for example, a high-definition or large-area display, a field effect mobility of approximately 50 cm 2 / vs or more is required for driving the thin film transistor. It met the requirements.
 他方、比較例5の薄膜トランジスタは、実施例4~28と比較し、その電気特性は非常に劣るものであった。このように、ゲート絶縁層を構成する酸化物において、金属元素(Sm)とジルコニウム(Zr)との原子数比が1:1程度であると電気特性の悪化が顕著であった。 On the other hand, the thin film transistor of Comparative Example 5 was inferior in electrical characteristics as compared with Examples 4 to 28. As described above, in the oxide constituting the gate insulating layer, when the atomic ratio of the metal element (Sm) and zirconium (Zr) is about 1: 1, the electrical characteristics are remarkably deteriorated.
 以上のとおり、実施例4~28の薄膜トランジスタは、プロセス温度を200℃として製造した場合であっても、非常に良好な電気特性を有していた。このことから、当該薄膜トランジスタおよびその製造方法を、フレキシブルディスプレイ用途など幅広い用途に適用することが可能である。 As described above, the thin film transistors of Examples 4 to 28 had very good electrical characteristics even when manufactured at a process temperature of 200 ° C. From this, it is possible to apply the said thin-film transistor and its manufacturing method to wide uses, such as a flexible display use.
 次に、ゲート絶縁膜形成溶液として溶液(iii)を用いた場合の結果を以下に示す。 Next, the results when the solution (iii) is used as the gate insulating film forming solution are shown below.
<薄膜トランジスタの製造>
(実施例29)
 まず、洗浄したSiウェハ基板上に、スパッタリング法により、チタン/白金(Ti/Pt)層からなるゲート電極を形成した。次いで、チタン/白金(Ti/Pt)層が成膜された基板表面に、酸素プラズマによるアッシング処理(15Wで180秒間)を施した。
<Manufacture of thin film transistor>
(Example 29)
First, a gate electrode made of a titanium / platinum (Ti / Pt) layer was formed on a cleaned Si wafer substrate by sputtering. Next, the substrate surface on which the titanium / platinum (Ti / Pt) layer was formed was subjected to ashing treatment with oxygen plasma (15 W for 180 seconds).
 その後、ゲート電極コンタクト領域を形成するためにAgペーストを基板の四隅に形成した。 Thereafter, Ag paste was formed at the four corners of the substrate in order to form gate electrode contact regions.
 次に、ゲート電極層上に、スピンコート法(回転数2000rpm、回転時間25秒間)により、ゲート絶縁膜形成溶液を塗布し、ゲート絶縁膜を形成した。なお、ゲート絶縁膜形成溶液を、以下のように調製した。まず、2-メトキシエタノールに、ジルコニウムアセチルアセトナートを加え、110℃、30分加熱攪拌し、0.4mol/kgのジルコニウム溶液を得た。次いで、得られた溶液を耐圧容器に移し、160℃まで昇温し、1時間保持した後、常温に戻すことにより、0.4mol/kgのジルコニウム溶液を調製した。その後0.2umのPTFEフィルターでろ過を行い、ゲート絶縁膜形成溶液を得た。 Next, a gate insulating film forming solution was applied onto the gate electrode layer by spin coating (rotation speed: 2000 rpm, rotation time: 25 seconds) to form a gate insulating film. A gate insulating film forming solution was prepared as follows. First, zirconium acetylacetonate was added to 2-methoxyethanol, and the mixture was heated and stirred at 110 ° C. for 30 minutes to obtain a 0.4 mol / kg zirconium solution. Next, the obtained solution was transferred to a pressure vessel, heated to 160 ° C., held for 1 hour, and then returned to room temperature to prepare a 0.4 mol / kg zirconium solution. Thereafter, filtration was performed with a 0.2 um PTFE filter to obtain a gate insulating film forming solution.
 次いで、ゲート絶縁膜を形成した積層体を、150℃に設定されたホットプレート上に5分間静置、加熱した後、温度を上昇させて200℃とし、同温にて加熱しながら、照度が10.0mW/cm2の紫外線を60分間、ゲート絶縁膜の全面に照射して、ゲート絶縁層を形成した。ここで、紫外線の照射は、UVオゾンクリーナー(サムコ社製UV-300H-E)を用いて行った。以上に実施したスピンコート法によるゲート絶縁膜の形成、150℃での加熱および紫外線照射を伴う200℃での加熱の一連の操作を合計3回繰り返すことにより、ゲート絶縁層を3層積層した。ゲート絶縁層の厚みは合計で50nmであった。 Next, the stacked body on which the gate insulating film is formed is allowed to stand on a hot plate set at 150 ° C. for 5 minutes and heated, and then the temperature is increased to 200 ° C. The entire surface of the gate insulating film was irradiated with ultraviolet rays of 10.0 mW / cm 2 for 60 minutes to form a gate insulating layer. Here, UV irradiation was performed using a UV ozone cleaner (Samco UV-300H-E). By repeating the above-described series of operations of forming a gate insulating film by spin coating, heating at 150 ° C., and heating at 200 ° C. accompanied by ultraviolet irradiation, a total of three gate insulating layers were laminated. The total thickness of the gate insulating layer was 50 nm.
 続いて、得られた積層体から、先に形成したAgペーストを除去して、測定用ゲート電極出しを行った。 Subsequently, the previously formed Ag paste was removed from the obtained laminate, and the gate electrode for measurement was taken out.
 その後、ゲート絶縁層上に、スピンコート法(回転数3000rpm、回転時間30秒間)により、酸化物半導体膜形成溶液を塗布し、得られた積層体を、150℃に設定されたホットプレート上に5分間静置、加熱した後、温度を上昇させて200℃とし、同温にて加熱しながら、照度が10.0mW/cm2の紫外線を60分間、酸化物半導体膜の全面に照射して、酸化物半導体層(InO層)を形成した。ここで、紫外線の照射は、UVオゾンクリーナー(サムコ社製UV-300H-E)を用いて行った。酸化物半導体層の厚みは、15nmであった。なお、酸化物半導体膜形成溶液としては、水に、硝酸インジウムを加え、110℃、回転数1000rpmで30分間、撹拌して、0.2mol/kgに調製したものを使用した。 Thereafter, an oxide semiconductor film forming solution is applied onto the gate insulating layer by a spin coating method (rotation speed: 3000 rpm, rotation time: 30 seconds), and the obtained stacked body is placed on a hot plate set at 150 ° C. After standing and heating for 5 minutes, the temperature was raised to 200 ° C., and the surface of the oxide semiconductor film was irradiated with ultraviolet rays having an illuminance of 10.0 mW / cm 2 for 60 minutes while heating at the same temperature. An oxide semiconductor layer (InO layer) was formed. Here, UV irradiation was performed using a UV ozone cleaner (Samco UV-300H-E). The thickness of the oxide semiconductor layer was 15 nm. As the oxide semiconductor film forming solution, a solution prepared by adding indium nitrate to water and stirring at 110 ° C. and a rotation speed of 1000 rpm for 30 minutes to be 0.2 mol / kg was used.
 続いて、酸化物半導体層上に、リフトオフ法により、ソース電極およびドレイン電極を形成した。 Subsequently, a source electrode and a drain electrode were formed on the oxide semiconductor layer by a lift-off method.
 その後、素子分離(酸化物半導体層のパターニング)のため、フォトリソグラフィーによってレジスト膜を形成し、得られた積層体を、ITO-02(関東化学株式会社製のITO用エッチャント)を用いたウェットエッチングによりエッチングした。 Then, for element isolation (patterning of the oxide semiconductor layer), a resist film is formed by photolithography, and the obtained laminate is wet-etched using ITO-02 (an ITO etchant manufactured by Kanto Chemical Co., Inc.). Etched.
 次いで、得られた積層体を、200℃のホットプレート上に静置し、照度が10.0mW/cm2の紫外線を照射しながら、10分間加熱することにより、薄膜トランジスタを作製した。ここで、紫外線の照射は、UVオゾンクリーナー(サムコ社製UV-300H-E)を用いて行った。 Next, the obtained laminate was allowed to stand on a hot plate at 200 ° C. and heated for 10 minutes while irradiating ultraviolet rays having an illuminance of 10.0 mW / cm 2 , thereby producing a thin film transistor. Here, UV irradiation was performed using a UV ozone cleaner (Samco UV-300H-E).
(実施例30)
 ゲート絶縁膜形成溶液の調製時に、ジルコニウムアセチルアセトナートの代わりにハフニウムアセチルアセトナートを用いた以外は、実施例29と同様にして、薄膜トランジスタを作製した。
(Example 30)
A thin film transistor was fabricated in the same manner as in Example 29 except that hafnium acetylacetonate was used instead of zirconium acetylacetonate when preparing the gate insulating film forming solution.
(実施例31)
 ゲート絶縁膜形成溶液の調製時に、ジルコニウムアセチルアセトナートの代わりにアルミニウムアセチルアセトナートを用いた以外は、実施例29と同様にして、薄膜トランジスタを作製した。
(Example 31)
A thin film transistor was fabricated in the same manner as in Example 29 except that aluminum acetylacetonate was used instead of zirconium acetylacetonate when preparing the gate insulating film forming solution.
(実施例32)
 酸化物半導体形成溶液の調製時に、硝酸インジウムと硝酸亜鉛を、インジウムと亜鉛との原子数比が8:2となるように混合した以外は、実施例29と同様にして、薄膜トランジスタを作製した。
(Example 32)
A thin film transistor was fabricated in the same manner as in Example 29 except that in the preparation of the oxide semiconductor forming solution, indium nitrate and zinc nitrate were mixed so that the atomic ratio of indium to zinc was 8: 2.
(実施例33)
 酸化物半導体形成溶液の調製時に、硝酸インジウムと硝酸ガリウムを、インジウムとガリウムとの原子数比が8:2となるように混合した以外は、実施例29と同様にして、薄膜トランジスタを作製した。
(Example 33)
A thin film transistor was manufactured in the same manner as in Example 29 except that in the preparation of the oxide semiconductor forming solution, indium nitrate and gallium nitrate were mixed so that the atomic ratio of indium to gallium was 8: 2.
(実施例34)
 ゲート絶縁膜形成溶液の調製時に、ジルコニウムアセチルアセトナートの代わりにハフニウムアセチルアセトナートを用い、酸化物半導体形成溶液の調製時に、硝酸インジウムと硝酸亜鉛を、インジウムと亜鉛との原子数比が8:2となるように混合した以外は、実施例29と同様にして、薄膜トランジスタを作製した。
(Example 34)
Hafnium acetylacetonate is used in place of zirconium acetylacetonate when preparing the gate insulating film forming solution, and indium nitrate and zinc nitrate are used in the preparation of the oxide semiconductor forming solution, and the atomic ratio of indium and zinc is 8: A thin film transistor was manufactured in the same manner as in Example 29 except that the mixing was performed so as to be 2.
(実施例35)
 ゲート絶縁膜形成溶液の調製時に、ジルコニウムアセチルアセトナートの代わりにハフニウムアセチルアセトナートを用い、酸化物半導体形成溶液の調製時に、硝酸インジウムと硝酸ガリウムを、インジウムとガリウムとの原子数比が8:2となるように混合した以外は、実施例29と同様にして、薄膜トランジスタを作製した。
(Example 35)
Hafnium acetylacetonate was used instead of zirconium acetylacetonate when preparing the gate insulating film forming solution, and when preparing the oxide semiconductor forming solution, the atomic ratio of indium and gallium was 8: A thin film transistor was manufactured in the same manner as in Example 29 except that the mixing was performed so as to be 2.
(実施例36)
 ゲート絶縁膜形成溶液の調製時に、アルミニウムアセチルアセトナートとジルコニウムアセチルアセトナートを、アルミニウムとジルコニウムとの原子数比が9:1になるように混合した以外は、実施例29と同様にして、薄膜トランジスタを作製した。
(Example 36)
A thin film transistor was prepared in the same manner as in Example 29 except that aluminum acetylacetonate and zirconium acetylacetonate were mixed so that the atomic ratio of aluminum to zirconium was 9: 1 when preparing the gate insulating film forming solution. Was made.
(実施例37)
 ゲート絶縁膜形成溶液の調製時に、アルミニウムアセチルアセトナートとジルコニウムアセチルアセトナートを、アルミニウムとジルコニウムとの原子数比が7:3になるように混合した以外は、実施例29と同様にして、薄膜トランジスタを作製した。
(Example 37)
A thin film transistor was prepared in the same manner as in Example 29 except that aluminum acetylacetonate and zirconium acetylacetonate were mixed so that the atomic ratio of aluminum to zirconium was 7: 3 when preparing the gate insulating film forming solution. Was made.
(実施例38)
 ゲート絶縁膜形成溶液の調製時に、アルミニウムアセチルアセトナートとジルコニウムアセチルアセトナートを、アルミニウムとジルコニウムとの原子数比が1:1になるように混合した以外は、実施例29と同様にして、薄膜トランジスタを作製した。
(Example 38)
A thin film transistor was prepared in the same manner as in Example 29 except that aluminum acetylacetonate and zirconium acetylacetonate were mixed so that the atomic ratio of aluminum to zirconium was 1: 1 at the time of preparing the gate insulating film forming solution. Was made.
(実施例39)
 ゲート絶縁膜形成溶液の調製時に、アルミニウムアセチルアセトナートとジルコニウムアセチルアセトナートを、アルミニウムとジルコニウムとの原子数比が3:7になるように混合した以外は、実施例29と同様にして、薄膜トランジスタを作製した。
(Example 39)
A thin film transistor was prepared in the same manner as in Example 29 except that aluminum acetylacetonate and zirconium acetylacetonate were mixed so that the atomic ratio of aluminum to zirconium was 3: 7 when preparing the gate insulating film forming solution. Was made.
(実施例40)
 ゲート絶縁膜形成溶液の調製時に、アルミニウムアセチルアセトナートとジルコニウムアセチルアセトナートを、アルミニウムとジルコニウムとの原子数比が1:9になるように混合した以外は、実施例29と同様にして、薄膜トランジスタを作製した。
(Example 40)
A thin film transistor was prepared in the same manner as in Example 29, except that aluminum acetylacetonate and zirconium acetylacetonate were mixed so that the atomic ratio of aluminum to zirconium was 1: 9 when the gate insulating film forming solution was prepared. Was made.
(実施例41)
 ゲート絶縁膜形成溶液の調製時に、ハフニウムアセチルアセトナートとジルコニウムアセチルアセトナートを、ハフニウムとジルコニウムとの原子数比が1:1になるように混合した以外は、実施例29と同様にして、薄膜トランジスタを作製した。
(Example 41)
A thin film transistor was prepared in the same manner as in Example 29 except that hafnium acetylacetonate and zirconium acetylacetonate were mixed so that the atomic ratio of hafnium and zirconium was 1: 1 at the time of preparing the gate insulating film forming solution. Was made.
(実施例42)
 ゲート絶縁膜形成溶液の調製時に、ハフニウムアセチルアセトナートとジルコニウムアセチルアセトナートを、ハフニウムとジルコニウムとの原子数比が9:1になるように混合した以外は、実施例29と同様にして、薄膜トランジスタを作製した。
(Example 42)
A thin film transistor was obtained in the same manner as in Example 29 except that hafnium acetylacetonate and zirconium acetylacetonate were mixed so that the atomic ratio of hafnium and zirconium was 9: 1 at the time of preparing the gate insulating film forming solution. Was made.
(実施例43)
 ゲート絶縁膜形成溶液の調製時に、アルミニウムアセチルアセトナートとハフニウムアセチルアセトナートとジルコニウムアセチルアセトナートを、アルミニウムとハフニウムとジルコニウムとの原子数比が1:1:1になるように混合した以外は、実施例29と同様にして、薄膜トランジスタを作製した。
(Example 43)
Except for mixing the aluminum acetylacetonate, hafnium acetylacetonate, and zirconium acetylacetonate so that the atomic ratio of aluminum, hafnium, and zirconium was 1: 1: 1 during the preparation of the gate insulating film forming solution, A thin film transistor was fabricated in the same manner as in Example 29.
<トランジスタの特性評価>
 製造した薄膜トランジスタに関し、on/off比、閾値電圧(Vth)、サブスレッショルド特性(SS)、電界効果移動度(μsat)、ヒステリシス(Hys)、およびゲートリーク電流(A)を測定して、そのトランジスタ特性を評価した。なお、これらのトランジスタ特性は、Semiconductor Parameter Analyzer(Agilent社製4155C)を用いて測定した。その測定結果を表3に示す。

<Evaluation of transistor characteristics>
Regarding the manufactured thin film transistor, the on / off ratio, threshold voltage (Vth), subthreshold characteristic (SS), field effect mobility (μ sat ), hysteresis (Hys), and gate leakage current (A) were measured, Transistor characteristics were evaluated. Note that these transistor characteristics were measured using a Semiconductor Parameter Analyzer (Agilent 4155C). The measurement results are shown in Table 3.

表3 トランジスタ特性の測定結果
Figure JPOXMLDOC01-appb-I000004
Table 3 Measurement results of transistor characteristics
Figure JPOXMLDOC01-appb-I000004
 表3に示すとおり、実施例29~43の薄膜トランジスタは、非常に良好な電気特性を有していた。薄膜トランジスタを、例えば高精細または大面積のディスプレイに適用する場合には、その駆動のために、概ね50cm2/vs以上の電界効果移動度が求められるところ、実施例29~43の薄膜トランジスタは、その要求を満たすものであった。 As shown in Table 3, the thin film transistors of Examples 29 to 43 had very good electrical characteristics. When the thin film transistor is applied to, for example, a high-definition or large-area display, a field-effect mobility of approximately 50 cm 2 / vs or more is required for driving the thin film transistor. It met the requirements.
 以上のとおり、実施例29~43の薄膜トランジスタは、プロセス温度を200℃として製造した場合であっても、非常に良好な電気特性を有していた。このことから、当該薄膜トランジスタおよびその製造方法を、フレキシブルディスプレイ用途など幅広い用途に適用することが可能である。 As described above, the thin film transistors of Examples 29 to 43 had very good electrical characteristics even when manufactured at a process temperature of 200 ° C. From this, it is possible to apply the said thin-film transistor and its manufacturing method to wide uses, such as a flexible display use.
 10   薄膜トランジスタ
 12   基板
 14   ゲート電極
 16   ゲート絶縁層
 16’  ゲート絶縁膜
 18   酸化物半導体層
 18’  酸化物半導体膜
 32   ソース電極
 34   ドレイン電極
DESCRIPTION OF SYMBOLS 10 Thin-film transistor 12 Substrate 14 Gate electrode 16 Gate insulating layer 16 'Gate insulating film 18 Oxide semiconductor layer 18' Oxide semiconductor film 32 Source electrode 34 Drain electrode

Claims (12)

  1.  ゲート電極、ゲート絶縁層、および酸化物半導体層をこの順で備える、薄膜トランジスタであって、
     前記ゲート絶縁層は、
     セリウム(Ce)、プラセオジム(Pr)、ネオジム(Nd)、サマリウム(Sm)、ユウロピウム(Eu)、ガドリニウム(Gd)、テルビウム(Tb)、ジスプロシウム(Dy)、ホルミウム(Ho)、エルビウム(Er)、ツリウム(Tm)、イッテルビウム(Yb)、ルテチウム(Lu)、およびイットリウム(Y)からなる群から選択される金属元素と、ジルコニウム(Zr)とを含み、前記群から選択される金属元素と、ジルコニウム(Zr)との原子数比が、前記群から選択される金属元素の原子数を1としたときに、ジルコニウム(Zr)の原子数が1.5以上である、酸化物から形成されているか、または、
     ハフニウム(Hf)、ジルコニウム(Zr)、およびアルミニウム(Al)からなる群から選択される少なくとも1種類の金属元素を含む酸化物から形成されており、
     前記酸化物半導体層は、インジウム(In)を含む酸化物、インジウム(In)と錫(Sn)とを含む酸化物、インジウム(In)と亜鉛(Zn)とを含む酸化物、インジウム(In)とジルコニウム(Zr)と亜鉛(Zn)とを含む酸化物、インジウム(In)とガリウム(Ga)とを含む酸化物、およびインジウム(In)と亜鉛(Zn)とガリウム(Ga)とを含む酸化物の群から選択される酸化物から形成されていることを特徴とする、薄膜トランジスタ。
    A thin film transistor comprising a gate electrode, a gate insulating layer, and an oxide semiconductor layer in this order,
    The gate insulating layer is
    Cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), A metal element selected from the group consisting of thulium (Tm), ytterbium (Yb), lutetium (Lu), and yttrium (Y), and zirconium (Zr), and a metal element selected from the group, zirconium Whether the atomic ratio with respect to (Zr) is made of an oxide having an atomic number of zirconium (Zr) of 1.5 or more when the atomic number of a metal element selected from the group is 1 Or
    Formed of an oxide containing at least one metal element selected from the group consisting of hafnium (Hf), zirconium (Zr), and aluminum (Al);
    The oxide semiconductor layer includes an oxide containing indium (In), an oxide containing indium (In) and tin (Sn), an oxide containing indium (In) and zinc (Zn), and indium (In). , An oxide containing zirconium (Zr) and zinc (Zn), an oxide containing indium (In) and gallium (Ga), and an oxide containing indium (In), zinc (Zn) and gallium (Ga) A thin film transistor, characterized in that it is made of an oxide selected from the group of objects.
  2.  ゲート電極、ゲート絶縁層、および酸化物半導体層をこの順で備える、薄膜トランジスタの製造方法であって、
     ゲート電極の上にゲート絶縁膜形成溶液を塗布して、ゲート絶縁膜を形成する工程と、
     酸素を含む環境下、前記ゲート絶縁膜の表面に紫外線を照射しながら、180~200℃で前記ゲート絶縁膜を焼成して、ゲート絶縁層を形成する工程と、
     前記ゲート絶縁層の上に酸化物半導体膜形成溶液を塗布して、酸化物半導体膜を形成する工程と、
     前記酸化物半導体膜の表面に紫外線を照射しながら、180~200℃で前記酸化物半導体膜を焼成して、酸化物半導体層を形成する工程と、
    を含み、
     前記ゲート絶縁膜形成溶液は、
     ランタン(La)と、ジルコニウム(Zr)と、アセチルアセトナートとを含み、ランタン(La)と、ジルコニウム(Zr)との原子数比が、ランタン(La)の原子数を1としたときに、ジルコニウム(Zr)の原子数が0.8以上である溶液(i)であるか、
     セリウム(Ce)、プラセオジム(Pr)、ネオジム(Nd)、サマリウム(Sm)、ユウロピウム(Eu)、ガドリニウム(Gd)、テルビウム(Tb)、ジスプロシウム(Dy)、ホルミウム(Ho)、エルビウム(Er)、ツリウム(Tm)、イッテルビウム(Yb)、ルテチウム(Lu)、およびイットリウム(Y)からなる群から選択される金属元素と、ジルコニウム(Zr)と、アセチルアセトナートとを含み、前記群から選択される金属元素と、ジルコニウム(Zr)との原子数比が、前記群から選択される金属元素の原子数を1としたときに、ジルコニウム(Zr)の原子数が1.5以上である溶液(ii)であるか、または、
     ハフニウム(Hf)、ジルコニウム(Zr)、およびアルミニウム(Al)からなる群から選択される少なくとも1種類の金属元素と、アセチルアセトナートとを含む溶液(iii)であり、
     前記酸化物半導体膜形成溶液は、インジウム(In)、インジウム(In)と錫(Sn)、インジウム(In)と亜鉛(Zn)、インジウム(In)とジルコニウム(Zr)と亜鉛(Zn)、インジウム(In)とガリウム(Ga)、およびインジウム(In)と亜鉛(Zn)とガリウム(Ga)からなる群から選択される金属元素と、酸化剤とを含むことを特徴とする、製造方法。
    A method of manufacturing a thin film transistor comprising a gate electrode, a gate insulating layer, and an oxide semiconductor layer in this order,
    Applying a gate insulating film forming solution on the gate electrode to form a gate insulating film;
    Baking the gate insulating film at 180 to 200 ° C. while irradiating the surface of the gate insulating film with ultraviolet rays in an oxygen-containing environment to form a gate insulating layer;
    Applying an oxide semiconductor film forming solution on the gate insulating layer to form an oxide semiconductor film;
    Firing the oxide semiconductor film at 180 to 200 ° C. while irradiating the surface of the oxide semiconductor film with ultraviolet rays to form an oxide semiconductor layer;
    Including
    The gate insulating film forming solution is
    When lanthanum (La), zirconium (Zr), and acetylacetonate are included, and the atomic ratio of lanthanum (La) and zirconium (Zr) is 1, the number of lanthanum (La) atoms is 1, A solution (i) in which the number of atoms of zirconium (Zr) is 0.8 or more,
    Cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), Comprising a metal element selected from the group consisting of thulium (Tm), ytterbium (Yb), lutetium (Lu), and yttrium (Y), zirconium (Zr), and acetylacetonate, and selected from the group When the atomic ratio between the metal element and zirconium (Zr) is 1 when the number of atoms of the metal element selected from the above group is 1, a solution having a zirconium (Zr) atom number of 1.5 or more (ii) ) Or
    A solution (iii) containing at least one metal element selected from the group consisting of hafnium (Hf), zirconium (Zr), and aluminum (Al), and acetylacetonate;
    The oxide semiconductor film forming solution includes indium (In), indium (In) and tin (Sn), indium (In) and zinc (Zn), indium (In), zirconium (Zr), zinc (Zn), and indium. A manufacturing method comprising a metal element selected from the group consisting of (In), gallium (Ga), indium (In), zinc (Zn), and gallium (Ga), and an oxidizing agent.
  3.  前記ゲート絶縁層を形成する工程において、前記ゲート絶縁膜形成溶液が前記溶液(i)である場合に、照射される紫外線の照度が7~12mW/cm2であることを特徴とする、請求項2に記載の製造方法。 The illuminance of ultraviolet rays irradiated in the step of forming the gate insulating layer when the gate insulating film forming solution is the solution (i) is 7 to 12 mW / cm 2. 2. The production method according to 2.
  4.  前記ゲート絶縁層を形成する工程において、前記ゲート絶縁膜形成溶液が前記溶液(ii)または溶液(iii)である場合に、照射される紫外線の照度が5~15mW/cm2であることを特徴とする、請求項2に記載の製造方法。 In the step of forming the gate insulating layer, when the gate insulating film forming solution is the solution (ii) or the solution (iii), the illuminance of the irradiated ultraviolet rays is 5 to 15 mW / cm 2. The manufacturing method according to claim 2.
  5.  前記酸化物半導体層を形成する工程において、前記ゲート絶縁膜形成溶液が前記溶液(i)である場合に、照射される紫外線の照度が7~12mW/cm2であることを特徴とする、請求項2に記載の製造方法。 In the step of forming the oxide semiconductor layer, when the gate insulating film forming solution is the solution (i), the illuminance of ultraviolet rays to be irradiated is 7 to 12 mW / cm 2. Item 3. The manufacturing method according to Item 2.
  6.  前記酸化物半導体層を形成する工程において、前記ゲート絶縁膜形成溶液が前記溶液(ii)または溶液(iii)である場合に、照射される紫外線の照度が5~15mW/cm2であることを特徴とする、請求項2に記載の製造方法。 In the step of forming the oxide semiconductor layer, when the gate insulating film forming solution is the solution (ii) or the solution (iii), the illuminance of the irradiated ultraviolet ray is 5 to 15 mW / cm 2. The manufacturing method according to claim 2, wherein the manufacturing method is characterized.
  7.  前記ゲート絶縁膜形成溶液は、前記ゲート電極の上に塗布する前に、密閉容器内で、150~200℃で加熱処理されていることを特徴とする、請求項2から6のいずれかに記載の製造方法。 7. The gate insulating film forming solution according to claim 2, wherein the gate insulating film forming solution is heat-treated at 150 to 200 ° C. in a sealed container before being applied on the gate electrode. Manufacturing method.
  8.  前記ゲート絶縁膜形成溶液の溶媒が、アルコール溶媒であることを特徴とする、請求項2から7のいずれかに記載の製造方法。 The manufacturing method according to any one of claims 2 to 7, wherein a solvent of the gate insulating film forming solution is an alcohol solvent.
  9.  前記酸化剤が、硝酸、硝酸塩、過酸化物、および過塩素酸塩からなる群から選択されることを特徴とする、請求項2から8のいずれかに記載の製造方法。 The method according to any one of claims 2 to 8, wherein the oxidizing agent is selected from the group consisting of nitric acid, nitrate, peroxide, and perchlorate.
  10.  薄膜トランジスタ用ゲート絶縁膜形成溶液であって、
     前記ゲート絶縁膜形成溶液は、
     ランタン(La)と、ジルコニウム(Zr)と、アセチルアセトナートとを含み、ランタン(La)と、ジルコニウム(Zr)との原子数比が、ランタン(La)の原子数を1としたときに、ジルコニウム(Zr)の原子数が0.8以上である溶液(i)であるか、
     セリウム(Ce)、プラセオジム(Pr)、ネオジム(Nd)、サマリウム(Sm)、ユウロピウム(Eu)、ガドリニウム(Gd)、テルビウム(Tb)、ジスプロシウム(Dy)、ホルミウム(Ho)、エルビウム(Er)、ツリウム(Tm)、イッテルビウム(Yb)、ルテチウム(Lu)、およびイットリウム(Y)からなる群から選択される金属元素と、ジルコニウム(Zr)と、アセチルアセトナートとを含み、前記群から選択される金属元素と、ジルコニウム(Zr)との原子数比が、前記群から選択される金属元素の原子数を1としたときに、ジルコニウム(Zr)の原子数が1.5以上である溶液(ii)であるか、または、
     ハフニウム(Hf)、ジルコニウム(Zr)、およびアルミニウム(Al)からなる群から選択される少なくとも1種類の金属元素と、アセチルアセトナートとを含む溶液(iii)であることを特徴とする、薄膜トランジスタ用ゲート絶縁膜形成溶液。
    A solution for forming a gate insulating film for a thin film transistor,
    The gate insulating film forming solution is
    When lanthanum (La), zirconium (Zr), and acetylacetonate are included, and the atomic ratio of lanthanum (La) and zirconium (Zr) is 1, the number of lanthanum (La) atoms is 1, A solution (i) in which the number of atoms of zirconium (Zr) is 0.8 or more,
    Cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), Comprising a metal element selected from the group consisting of thulium (Tm), ytterbium (Yb), lutetium (Lu), and yttrium (Y), zirconium (Zr), and acetylacetonate, and selected from the group When the atomic ratio between the metal element and zirconium (Zr) is 1 when the number of atoms of the metal element selected from the above group is 1, a solution having a zirconium (Zr) atom number of 1.5 or more (ii) ) Or
    It is a solution (iii) containing at least one metal element selected from the group consisting of hafnium (Hf), zirconium (Zr), and aluminum (Al), and acetylacetonate, for a thin film transistor Gate insulating film forming solution.
  11.  密閉容器内で、150~200℃で加熱処理されていることを特徴とする、請求項10に記載の薄膜トランジスタ用ゲート絶縁膜形成溶液。 11. The gate insulating film forming solution for a thin film transistor according to claim 10, wherein the solution is heat-treated at 150 to 200 ° C. in a sealed container.
  12.  前記ゲート絶縁膜形成溶液の溶媒が、アルコール溶媒であることを特徴とする、請求項10または11に記載の薄膜トランジスタ用ゲート絶縁膜形成溶液。 12. The gate insulating film forming solution for a thin film transistor according to claim 10 or 11, wherein the solvent of the gate insulating film forming solution is an alcohol solvent.
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