WO2018066547A1 - Oxide sintered body and sputtering target - Google Patents

Oxide sintered body and sputtering target Download PDF

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Publication number
WO2018066547A1
WO2018066547A1 PCT/JP2017/035939 JP2017035939W WO2018066547A1 WO 2018066547 A1 WO2018066547 A1 WO 2018066547A1 JP 2017035939 W JP2017035939 W JP 2017035939W WO 2018066547 A1 WO2018066547 A1 WO 2018066547A1
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Prior art keywords
sintered body
thin film
less
oxide
sputtering
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PCT/JP2017/035939
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French (fr)
Japanese (ja)
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井上 一吉
雅敏 柴田
重和 笘井
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出光興産株式会社
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Priority to JP2017562795A priority Critical patent/JP6326560B1/en
Publication of WO2018066547A1 publication Critical patent/WO2018066547A1/en

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    • CCHEMISTRY; METALLURGY
    • C04CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04BLIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B35/00Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products
    • C04B35/01Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/08Oxides
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34Sputtering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present invention relates to an oxide sintered body and a sputtering target produced using the same.
  • Amorphous (amorphous) oxide semiconductors used for thin film transistors (TFTs) have higher carrier mobility than general-purpose amorphous silicon (a-Si), a large optical band gap, and can be formed at low temperatures. It is expected to be applied to next-generation displays that require large size, high resolution, and high-speed driving, and resin substrates with low heat resistance.
  • a sputtering method of sputtering a sputtering target is preferably used. This is because the thin film formed by the sputtering method has a component composition, film thickness, etc. in the film surface direction (in the film surface) as compared with the thin film formed by the ion plating method, vacuum evaporation method, or electron beam evaporation method. This is because the internal uniformity is excellent and a thin film having the same component composition as the sputtering target can be formed.
  • Patent Document 1 describes a method for producing a garnet compound represented by A 3 B 2 C 3 O 12 as a compound of aluminum oxide and samarium oxide.
  • Sm 3 Al 2 Al 3 O 12 compounds are exemplified.
  • Patent Document 2 describes a sputtering target containing a compound having an A 3 B 5 O 12 garnet structure obtained by sintering a raw material containing indium oxide, yttrium oxide, and aluminum oxide or gallium oxide. . Since this target includes a garnet structure, electrical resistance is reduced, abnormal discharge during sputtering is small, and there is a description regarding application to a TFT element with high mobility.
  • Patent Document 3 describes an ⁇ -Al 2 O 3 ceramic composite material containing a compound of SmAlO 3 and NdAlO 3 type perovskite structure obtained by sintering a raw material containing samarium oxide and aluminum oxide. Yes.
  • JP 2008-7340 A International Publication No. 2015/098060 Japanese Patent Laid-Open No. 9-67194
  • An object of the present invention is to provide a novel oxide sintered body and a sputtering target.
  • the present inventors have eagerly searched for a new substance based on indium oxide containing a lanthanoid metal element that can be used as a target material.
  • a novel oxide sintered body containing a perovskite phase and a bixbite phase represented by In 2 O 3 has been found.
  • the sputtering target using this oxide sintered compact had advantageous characteristics as target materials, such as high sintering density, low bulk resistance, few warpage of a target, and high bonding rate. Due to these target characteristics, abnormal discharge hardly occurs even when sputtering is performed with high power, and stable sputtering is possible. Further, the thin film obtained by sputtering this sputtering target has been found to exhibit excellent TFT performance (CVD resistance) when used in a TFT, and the present invention has been completed.
  • the following oxide sintered body, sputtering target, oxide semiconductor thin film manufacturing method, thin film transistor manufacturing method, and electronic device manufacturing method are provided.
  • the perovskite phase is a compound represented by the following general formula (I).
  • LnAlO 3 (I) (In the formula, Ln represents one or more metal elements selected from La, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.) 3.
  • In / (In + Al + Ln) is 0.64 or more and 0.98 or less
  • Al / (In + Al + Ln) is 0.01 or more and 0.18 or less
  • Ln / (In + Al + Ln) is 0.01 or more and 0.18 or less 5.1 to 4
  • the manufacturing method of the oxide semiconductor thin film characterized by forming into a film using the sputtering target of 6.5.
  • the manufacturing method of the thin-film transistor characterized by including the process of forming an oxide semiconductor thin film using the sputtering target of 7.5.
  • a step of forming an oxide semiconductor thin film using the sputtering target according to 8.5 The manufacturing method of the electronic device characterized by including the process of manufacturing the thin-film transistor containing the said oxide semiconductor thin film, and the process of mounting the said thin-film transistor in an electronic device.
  • Ln is one or more metal elements selected from La, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu;
  • the oxide semiconductor thin film whose atomic ratio of said In, said Al, and said Ln is the following range.
  • a thin film transistor including a semiconductor thin film is 0.64 or more and 0.98 or less Al / (In + Al + Ln) is 0.01 or more and 0.18 or less Ln / (In + Al + Ln) is 0.01 or more and 0.18 or less 10.9
  • a thin film transistor including a semiconductor thin film is 0.64 or more and 0.98 or less
  • Al / (In + Al + Ln) is 0.01 or more and 0.18 or less
  • Ln / (In + Al + Ln) is 0.01 or more and 0.18 or less 10.9
  • a thin film transistor including a semiconductor thin film is 0.01 or more and 0.18 or less 10.9
  • a novel oxide sintered body and sputtering target can be provided.
  • FIG. 1A is a top view of a display device including a TFT of the present invention
  • FIG. 1B is used when a liquid crystal element including the TFT of the present invention is applied to a pixel portion of the display device.
  • FIG. 1C is a circuit diagram of a pixel portion that can be used when an organic EL element including a TFT of the present invention is applied to the pixel portion of the display device. is there.
  • An example of a circuit structure of a CMOS image sensor is shown.
  • 2 is an X-ray diffraction pattern of the oxide sintered body of Example 1.
  • FIG. 2 is an X-ray diffraction pattern of an oxide sintered body of Example 2.
  • FIG. 4 is an X-ray diffraction pattern of an oxide sintered body of Example 3.
  • FIG. 1A is a top view of a display device including a TFT of the present invention
  • FIG. 1B is used when a liquid crystal element including the TFT of the present invention is applied to a
  • FIG. 4 is an X-ray diffraction pattern of an oxide sintered body of Example 4.
  • 6 is an X-ray diffraction pattern of an oxide sintered body of Example 5.
  • FIG. 7 is an X-ray diffraction pattern of an oxide sintered body of Example 7.
  • FIG. 7 is an X-ray diffraction pattern of an oxide sintered body of Example 8.
  • FIG. 10 is an X-ray diffraction pattern of an oxide sintered body of Example 9.
  • 3 is an X-ray diffraction pattern of an oxide sintered body of Example 10.
  • FIG. 3 is an X-ray diffraction pattern of an oxide sintered body of Example 11.
  • FIG. 3 is an X-ray diffraction pattern of an oxide sintered body of Example 12.
  • An oxide sintered body according to an embodiment of the present invention includes a perovskite phase and a bixbite phase represented by In 2 O 3 .
  • the perovskite phase and the bixbite phase represented by In 2 O 3 in the sintered body of the present invention can be detected from the XRD chart by, for example, the X-ray diffraction (XRD) method.
  • XRD X-ray diffraction
  • the perovskite phase in the sintered body of the present invention is preferably a compound represented by the following general formula (I).
  • LnAlO 3 (I) (In the formula, Ln represents one or more metal elements selected from La, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.) Ln is particularly preferably one or both of Sm and Nd.
  • the compound represented by the general formula (I) has a perovskite structure, and by including this, a high-density sintered body can be obtained.
  • the perovskite compound represented by the general formula (I) may have a single crystal structure or a polycrystalline structure.
  • the sintered body of the present invention includes a perovskite phase represented by the above general formula (I) and a bixbite phase represented by In 2 O 3 , whereby a sintered density (relative density) and a volume resistivity are included. (Bulk resistance) can be improved. Also, the expansion coefficient can be reduced and the thermal conductivity can be increased. In addition, a sintered body having a low volume resistivity and a high sintering density should be used even when fired by a simple method such as in an atmosphere of oxygen using an atmosphere firing furnace or in the atmosphere. Can do.
  • the sintered body of the present invention having the above characteristics is preferable as a target material.
  • the sintered body of the present invention As a target material, the generation of stress is suppressed, the strength and thermal conductivity of the target are increased, the linear expansion coefficient is suppressed, the occurrence of microcracks and chipping of the target is suppressed, nodules and Generation of abnormal discharge can be suppressed, and a sputtering target capable of sputtering with high power can be obtained.
  • the sintered body of the present invention as a target material, it is possible to obtain a high-performance TFT with high mobility and small deterioration of semiconductor characteristics due to chemical vapor deposition (CVD) or the like.
  • a sputtering target according to an embodiment of the present invention (hereinafter referred to as a target of the present invention) is produced using the sintered body of the present invention.
  • the target of the present invention is a target material obtained by grinding the sintered body of the present invention, and this is bonded to a metal support such as a copper plate (hereinafter also referred to as a backing plate or target support) with metal indium or the like. Manufactured. The method for producing the oxide sintered body of the present invention and the target of the present invention will be described later.
  • the atomic ratio of In, Al, and Ln in the sintered body used for the target of the present invention is preferably in the following range.
  • In / (In + Al + Ln) is 0.64 or more and 0.98 or less
  • Al / (In + Al + Ln) is 0.01 or more and 0.18 or less
  • Ln / (In + Al + Ln) is 0.01 or more and 0.18 or less
  • In / (In + Al + Ln) is 0.70 or more and 0.96 or less
  • Al / (In + Al + Ln) is 0.02 or more and 0.15 or less Ln / (In + Al + Ln) is 0.02 or more and 0.15 or less
  • In / (In + Al + Ln) is less than 0.64, the movement of the TFT including the oxide semiconductor thin film to be formed may be reduced. If it exceeds 0.98, the stability of the TFT may not be obtained, or it may be difficult to become a semiconductor by conducting it.
  • the perovskite phase represented by the general formula (I) is not formed, and the stability of the TFT may not be obtained, or it may be difficult to become conductive and become a semiconductor. Or stable sputtering may not be possible. On the other hand, if it exceeds 0.18, the movement of the TFT including the oxide semiconductor thin film to be formed may be small.
  • the perovskite phase represented by the general formula (I) may not be formed, and the stability of the TFT may not be obtained, or it may become difficult to become a semiconductor by conducting. Or stable sputtering may not be possible. On the other hand, if it exceeds 0.18, the movement of the TFT including the oxide semiconductor thin film to be formed may be small.
  • the sintered body of the present invention may further contain a positive tetravalent metal element. Thereby, sputtering can be performed more stably.
  • Examples of the positive tetravalent metal element include Sn, Ti, Zr, Hf, Ce, and Ge.
  • the sintered body of the present invention can contain one or more of these. Sn is preferred. Bulk resistance decreases due to the Sn doping effect, and sputtering can be performed more stably.
  • the positive tetravalent metal element is preferably dissolved in the bixbite phase represented by In 2 O 3 or the perovskite phase represented by the general formula (I), and the bixbite represented by In 2 O 3 More preferably, it is in solid solution in the phase.
  • the solid solution is preferably a substitutional solid solution. Thereby, sputtering can be performed more stably.
  • Ln and Al may be dissolved in a bixbite phase represented by In 2 O 3 .
  • the solid solution of the positive tetravalent metal element, Ln and Al can be identified from, for example, the lattice constant of XRD measurement.
  • the content of the positive tetravalent metal element is preferably 100 ppm or more and 10,000 ppm or less, more preferably 500 ppm or more and 8000 ppm or less, more preferably, with respect to all metal elements in the oxide sintered body of the present invention. It is 800 ppm or more and 6000 ppm or less. If it is less than 100 ppm, the bulk resistance may increase. On the other hand, if it exceeds 10,000 ppm, the TFT including the oxide semiconductor thin film to be formed may become conductive, and the on / off value may be reduced.
  • the abundance ratio of the bixbite phase represented by In 2 O 3 is preferably 1 to 99 wt%, and more preferably 10 to 98 wt%. If the abundance ratio of the bixbite phase represented by In 2 O 3 is in the above range, the perovskite phase is dispersed in the In 2 O 3 crystal, and the fluorescent material other than the target material is doped with a rare earth element. Application to the above is also conceivable.
  • the abundance ratio of the bixbite phase represented by In 2 O 3 can be measured by the method described in the examples.
  • the bixbite phase represented by In 2 O 3 is preferably the main component. If a crystal structure other than the bixbite structure is precipitated as a main component, the mobility may be lowered.
  • the bixbite phase represented by In 2 O 3 is a main component means that the existence ratio of the bixbite phase represented by In 2 O 3 is more than 50 wt%, preferably 70 wt%. As mentioned above, More preferably, it is 80 wt% or more, More preferably, it is 85 wt% or more.
  • the sintered density is preferably in the range of 6.5 to 7.1 g / cm 3 , more preferably in the range of 6.6 to 7.1 g / cm 3. preferable.
  • the sintered density is in the range of 6.5 to 7.1 g / cm 3 , voids that cause abnormal discharge and start nodules can be reduced when used as a target.
  • the sintered density can be measured by, for example, the Archimedes method.
  • the bulk resistance is preferably 50 m ⁇ ⁇ cm or less, more preferably 30 m ⁇ ⁇ cm or less, and further preferably 20 m ⁇ ⁇ cm or less.
  • the bulk resistance is preferably 50 m ⁇ ⁇ cm or less, more preferably 30 m ⁇ ⁇ cm or less, and further preferably 20 m ⁇ ⁇ cm or less.
  • it is 1 mohm * cm or more, or 5 mohm * cm or more.
  • 50 m ⁇ ⁇ cm or less during DC sputtering film formation with high power, abnormal discharge due to target charging is less likely to occur, and the plasma state is stabilized and spark is less likely to occur.
  • the bulk resistance can be measured based on, for example, a four-probe method. Specifically, it can be measured based on the four-probe method (JIS R 1637) using a known resistivity meter. There are about five measurement points, and the average value is preferably the bulk resistance value.
  • the measurement locations are preferably a total of five locations, that is, the center, four corners, and a midpoint between the centers.
  • the oxide sintered body has a total of five points: a center of a square inscribed in the circle, and four points of the four corners of the square and an intermediate point of the center.
  • the three-point bending strength is preferably 120 MPa or more, more preferably 140 MPa or more, and further preferably 150 MPa or more.
  • the pressure is less than 120 MPa, when sputtering film formation is performed with high power, the strength of the target is weak, the target is cracked or chipping occurs, and the chipped fragments may be scattered on the target and cause abnormal discharge. .
  • the three-point bending strength can be tested in accordance with, for example, JIS R 1601 “Room temperature bending strength test of fine ceramics”. Specifically, using a standard test piece having a width of 4 mm, a thickness of 3 mm, and a length of 40 mm, the test piece is placed on two fulcrums arranged at a fixed distance (30 mm), and the crosshead speed is 0 from the center between the fulcrums. The bending strength can be calculated from the maximum load when the test piece is broken by applying a load of 0.5 mm / min.
  • the linear expansion coefficient is preferably 8.0 ⁇ 10 ⁇ 6 K ⁇ 1 or less, more preferably 7.5 ⁇ 10 ⁇ 6 K ⁇ 1 or less, and 7.0 ⁇ 10 It is more preferably ⁇ 6 K ⁇ 1 or less.
  • the lower limit is not particularly limited, but is usually 5.0 ⁇ 10 ⁇ 6 K ⁇ 1 or more. If it exceeds 8.0 ⁇ 10 ⁇ 6 K ⁇ 1 , it is heated with high power during sputtering, the target expands, deformation occurs between the bonded copper plates, and microcracks are generated in the target due to stress. There is a risk of causing abnormal discharge due to cracking or chipping.
  • the linear expansion coefficient is, for example, a standard test piece having a width of 5 mm, a thickness of 5 mm, and a length of 10 mm.
  • the temperature increase rate is set to 5 ° C./min. It can be obtained by detecting with a detector.
  • the thermal conductivity is preferably 5.0 W / m ⁇ K or more, more preferably 5.5 W / m ⁇ K or more, and even more preferably 6.0 W / m ⁇ K or more. 6.5 W / m ⁇ K or more is most preferable.
  • the upper limit is not particularly limited, but is usually 10 W / m ⁇ K or less. In the case of less than 5.0 W / m ⁇ K, when sputtering film formation is performed with high power, the temperature of the sputtered surface and the bonded surface is different, and microcracks, cracks, and chipping may occur in the target due to internal stress. .
  • the thermal conductivity can be calculated by, for example, obtaining a specific heat capacity and a thermal diffusivity by a laser flash method using a standard test piece having a diameter of 10 mm and a thickness of 1 mm, and multiplying this by the density of the test piece.
  • the metal element of the sintered body of the present invention is essentially composed of In, Al, Ln, and optionally a positive tetravalent metal element, and contains other inevitable impurities as long as the effects of the present invention are not impaired. But you can. For example, 90 atomic% or more, 95 atomic% or more, 98 atomic% or more, 99 atomic% or more, or 100 atomic% of the metal element of the sintered body of the present invention is In, Al and Ln, or In, Al, Ln. And a positive tetravalent metal element.
  • the sintered body of the present invention includes a step of preparing a mixed powder of a raw material powder containing In, a raw material powder containing Al, and a raw material powder containing Ln, a step of forming a mixed powder to produce a molded body, and a molded body Can be produced by a step of baking.
  • the mixed powder may include a raw material powder containing a positive tetravalent metal element.
  • the raw material powder is preferably an oxide powder.
  • the mixing ratio of the raw material powder corresponds to, for example, the atomic ratio of the sintered body to be obtained.
  • the average particle diameter of the raw material powder is preferably 0.1 to 1.2 ⁇ m, more preferably 0.5 to 1.0 ⁇ m or less.
  • the average particle diameter of the raw material powder can be measured with a laser diffraction type particle size distribution apparatus or the like.
  • the method for mixing and forming the raw materials is not particularly limited, and can be performed using a known method.
  • a binder may be added when mixing.
  • the mixing of the raw materials can be performed using a known device such as a ball mill, a bead mill, a jet mill, or an ultrasonic device.
  • the mixing time may be appropriately adjusted, but is preferably about 6 to 100 hours.
  • the molding method may be, for example, pressing a mixed powder into a molded body. By this process, it can be formed into a product shape (for example, a shape suitable as a sputtering target).
  • the mixed powder raw material is filled in a mold, and molded by a mold press or cold isostatic press (CIP) at a pressure of 1000 kg / cm 2 or more, for example, to obtain a molded body.
  • molding aids such as polyvinyl alcohol, polyethylene glycol, methylcellulose, polywax, oleic acid, and stearic acid may be used.
  • the obtained molded body can be sintered at a sintering temperature of 1200 to 1650 ° C. for 10 hours or more, for example, to obtain a sintered body.
  • the sintering temperature is preferably 1350 to 1600 ° C, more preferably 1400 to 1600 ° C, still more preferably 1450 to 1600 ° C.
  • the sintering time is preferably 10 to 50 hours, more preferably 12 to 40 hours, still more preferably 13 to 30 hours.
  • the sintering temperature is less than 1200 ° C. or the sintering time is less than 10 hours, the sintering does not proceed sufficiently, and the electrical resistance of the target is not sufficiently lowered, which may cause abnormal discharge.
  • the firing temperature exceeds 1650 ° C. or the firing time exceeds 50 hours, the average crystal grain size increases due to remarkable crystal grain growth, and coarse pores are generated, and the sintered body strength is reduced. May cause abnormal discharge.
  • the compact is usually sintered in an air atmosphere or an oxygen gas atmosphere.
  • the oxygen gas atmosphere is preferably an atmosphere having an oxygen concentration of, for example, 10 to 50% by volume.
  • the sintered body density can be increased by performing the temperature raising process in an air atmosphere.
  • the heating rate during sintering is from 50 ° C. to 150 ° C./hour from 800 ° C. to the sintering temperature (1200 to 1650 ° C.).
  • the temperature range above 800 ° C. is the range where the sintering proceeds most.
  • the rate of temperature rise in this temperature range is slower than 50 ° C./hour, crystal grain growth becomes significant, and there is a possibility that densification cannot be achieved.
  • the rate of temperature increase is higher than 150 ° C./hour, a temperature distribution is generated in the molded body, and the sintered body may be warped or cracked.
  • the rate of temperature increase from 800 ° C. to the sintering temperature is preferably 60 to 140 ° C./hour, more preferably 70 to 130 ° C./hour.
  • the sputtering target of the present invention can be produced using the above-described sintered body of the present invention. Thereby, an oxide semiconductor thin film can be manufactured by vacuum processes, such as sputtering method.
  • the sputtering target can be produced, for example, by cutting or polishing the sintered body and bonding it to a backing plate. For example, by cutting, a sintered part in a highly oxidized state and an uneven surface on the surface of the sintered body can be removed. Also, it can be specified size.
  • the surface may be polished with # 200, # 400, or # 800. Thereby, abnormal discharge and generation of particles during sputtering can be suppressed.
  • the bonding rate is preferably 90% or more, more preferably 95% or more, and even more preferably 99% or more.
  • the bonding rate here refers to the area ratio of the surface where the target material and the target support material are bonded via the bonding layer with respect to the area of the overlapping surface of the target material and the target support.
  • the bonding rate can usually be measured with an ultrasonic flaw detector or the like.
  • a method for joining the target material and the target support will be described.
  • Surface treatment is performed on the joint surface with the target support in the target material processed into a predetermined shape.
  • a device used for the surface treatment a commercially available blasting device can be used.
  • the product name “Pneuma Blaster SGF-5-B” manufactured by Fuji Seisakusho can be mentioned.
  • Glass, alumina, zirconia, SiC, or the like can be used as the powder used in the blasting method, and these are appropriately selected according to the composition, hardness, etc. of the target material.
  • a bonding material such as metal indium solder is applied to the bonding surface.
  • a bonding material such as metal indium solder is applied to the bonding surface of the backing plate that has been subjected to a cleaning treatment if necessary.
  • a thin film layer such as copper or nickel having excellent wettability with the bonding material is previously formed on the bonding surface of the target material by a sputtering method. After forming by plating, etc., apply the bonding material by heating it above the melting point of the bonding material using the target material, or apply the bonding material directly to the bonding surface of the target material using ultrasonic waves. Also good.
  • the target support to which the bonding material is applied is heated to a temperature equal to or higher than the melting point of the used bonding material to melt the bonding material layer on the surface, and then the above-mentioned powder is placed on the surface to back the target material and the backing material. After joining the plates, the target can be obtained by cooling to room temperature.
  • the sputtering target of the present invention can be applied to a direct current (DC) sputtering method, a radio frequency (RF) sputtering method, an alternating current (AC) sputtering method, a pulsed DC sputtering method, and the like.
  • DC direct current
  • RF radio frequency
  • AC alternating current
  • DC pulsed DC
  • An oxide semiconductor thin film can be obtained by forming a film using the sputtering target of the present invention. Thereby, a thin film that exhibits excellent TFT performance when used in a TFT can be formed.
  • Film formation can be performed by a vapor deposition method, a sputtering method, an ion plating method, a pulse laser vapor deposition method, or the like.
  • Sputtering is preferably performed in an oxidizing argon atmosphere into which an oxygen atom-containing gas (oxidizing gas) such as O 2 or H 2 O is introduced. It is possible to suppress the generation of impurities that are an impediment to light transmission necessary for semiconductor characteristics and light stability obtained by performing sputtering in an oxidizing atmosphere.
  • the concentration of the oxidizing gas may be appropriately adjusted depending on the desired semiconductor characteristics of the film, particularly the carrier concentration. This adjustment can also be performed by, for example, the substrate temperature, the sputtering pressure, or the like.
  • a sputtering gas from the viewpoint of easily controlling the composition of the gas, preferably with Ar-O 2 based gas or Ar-H 2 O-based gas, more preferably at Ar-O 2 based gas control is excellent particularly .
  • Ar—O 2 -based gas a semiconductor film having semiconductor characteristics with excellent light stability can be obtained.
  • the O 2 concentration is preferably 0.2 to 50% by volume. If the O 2 concentration is less than 0.2% by volume, the resulting film may be colored yellow and the light stability may be poor. On the other hand, when the O 2 concentration is more than 50% by volume, the deposition cost of the thin film at the time of sputtering becomes slow, which may increase the production cost. Further, when the O 2 concentration is about 10% by volume, the obtained film has a carrier concentration of 10 15 to 10 18 cm ⁇ 3 by heat treatment, and can be used as an excellent semiconductor film.
  • the pressure before film formation in the sputtering apparatus (the pressure in the chamber) is preferably 10 ⁇ 6 to 10 ⁇ 3 Pa.
  • the pressure in the chamber exceeds 10 ⁇ 3 Pa, it is affected by residual moisture remaining in the vacuum, so that resistance control may be difficult.
  • the pressure in the chamber is less than 10 ⁇ 6 Pa, it takes time for evacuation, which may deteriorate productivity.
  • the current density during sputtering (the value obtained by dividing the input power by the area of the target surface) is preferably 1 to 10 W / cm 2 .
  • the current density is less than 1 W / cm 2 , the discharge may not be stable.
  • the current density exceeds 10 W / cm 2 , there is a possibility that the target may break due to the heat generated.
  • the pressure during sputtering is preferably 0.01 to 20 Pa. If the sputtering pressure is less than 0.01 Pa, the discharge may not be stable. On the other hand, when the sputtering pressure is higher than 20 Pa, the sputtering discharge may not be stable, and the sputtering gas itself may be taken into the conductive film to deteriorate the film characteristics.
  • the pressure is preferably 0.05 to 5 Pa, more preferably 0.1 to 1 Pa.
  • the substrate on which the oxide semiconductor thin film of the present invention is formed examples include glass, ceramics, plastics, and metals.
  • the substrate temperature during film formation is not particularly limited, but is preferably 300 ° C. or less from the viewpoint of easily obtaining an amorphous film.
  • the substrate temperature may be about room temperature when no intentional heating is performed. Although it can be used as a semiconductor element as an amorphous thin film, immediately after film formation, it was formed as an amorphous film, and after forming an island-shaped semiconductor portion by patterning, it was crystallized by heat treatment. Later, a source / drain electrode or the like may be connected to form a thin film semiconductor element.
  • the substrate may be post-heated (heat treatment).
  • This heat treatment is preferably performed at 150 to 400 ° C., preferably 200 to 350 ° C. in the air, nitrogen or vacuum.
  • heat treatment it is possible to prevent deterioration of the semiconductor film by crystallization, suppress changes in the carrier concentration of the semiconductor film, increase the band gap with excellent light stability, and improve the light transmittance. It becomes. Whether or not it is crystallized is determined by whether or not a peak is observed in the XRD measurement.
  • the heat treatment is less than 150 ° C., oxygen in the thin film is gradually exhausted and the semiconductor film may be deteriorated.
  • the heat treatment exceeds 350 ° C., the carrier concentration of the semiconductor film may be lowered.
  • An oxide semiconductor thin film according to an embodiment of the present invention (hereinafter referred to as an oxide semiconductor thin film of the present invention) is manufactured using the sputtering target of the present invention.
  • the oxide semiconductor thin film of the present invention contains In, Al, and Ln, and the Ln is one or more selected from La, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.
  • the atomic ratio of In, Al, and Ln is in the following range. In / (In + Al + Ln) is 0.64 or more and 0.98 or less Al / (In + Al + Ln) is 0.01 or more and 0.18 or less Ln / (In + Al + Ln) is 0.01 or more and 0.18 or less
  • the atomic ratio of In, Al, and Ln in the oxide semiconductor thin film of the present invention is preferably in the following range.
  • In / (In + Al + Ln) is 0.64 or more and 0.98 or less
  • Al / (In + Al + Ln) is 0.01 or more and 0.18 or less
  • Ln / (In + Al + Ln) is 0.01 or more and 0.18 or less More preferably, in the following range is there.
  • In / (In + Al + Ln) is 0.70 or more and 0.96 or less Al / (In + Al + Ln) is 0.02 or more and 0.15 or less Ln / (In + Al + Ln) is 0.02 or more and 0.15 or less Atomic ratio of the oxide semiconductor thin film
  • the specific ground for the upper and lower limits in is the same as the specific ground for the upper and lower limits in the atomic ratio of the oxide sintered body of the present invention.
  • the content (atomic ratio) of each metal element in the oxide semiconductor thin film can be obtained by measuring the abundance of each element by ICP (Inductive Coupled Plasma) measurement or XRF (X-ray Fluorescence) measurement.
  • ICP Inductive Coupled Plasma
  • XRF X-ray Fluorescence
  • ICP measurement an induction plasma emission analyzer can be used.
  • XRF measurement a thin film X-ray fluorescence analyzer (AZX400, manufactured by Rigaku Corporation) can be used.
  • the content (atomic ratio) of each metal element in the oxide semiconductor thin film can be analyzed with the same accuracy as the induction plasma emission analysis even when using the sector type dynamic secondary ion mass spectrometer SIMS analysis.
  • a material in which the source and drain electrodes are formed with the same channel length as the TFT element on the upper surface of a standard oxide thin film with a known atomic ratio of metal elements measured by an induction plasma emission spectrometer or thin film fluorescent X-ray analyzer Analyze the oxide semiconductor layer by using a sector-type dynamic secondary ion mass spectrometer SIMS (IMS-7f-Auto, manufactured by AMETEK) as a standard material, obtain the mass spectrum intensity of each element, and obtain the known element concentration and mass spectrum intensity.
  • SIMS IMS-7f-Auto, manufactured by AMETEK
  • the calculated atomic ratio is Separately, it can be confirmed that it is within 2 atomic% of the atomic ratio of the oxide semiconductor film measured by the thin film fluorescent X-ray analyzer or the induction plasma emission analyzer.
  • a thin film transistor (TFT) according to an embodiment of the present invention includes the above-described oxide semiconductor thin film.
  • the oxide semiconductor thin film can be suitably used as a channel layer, for example.
  • the TFT of the present invention preferably has the following characteristics.
  • Saturation mobility of the TFT is 1.0cm 2 / V ⁇ s or more, preferably not more than 50.0cm 2 / V ⁇ s.
  • Saturation mobility of the TFT is 1.0 cm 2 / V ⁇ s or more, it is possible to drive the transfer transistor, cancel transistor, liquid crystal display, and organic EL display of the CMOS image sensor.
  • the saturation mobility of the TFT By setting the saturation mobility of the TFT to 50.0 cm 2 / V ⁇ s or less, the off current can be made 10 ⁇ 12 A or less, and the on / off ratio can be made 10 8 or more.
  • the saturation mobility of the TFT can be obtained from the transfer characteristics when a drain voltage of 20 V is applied. Specifically, a graph of the transfer characteristic Id-Vg is created, the transconductance (Gm) of each Vg is calculated, and the saturation mobility is obtained by the equation of the saturation region.
  • Id is a current between the source and drain electrodes
  • Vg is a gate voltage when a voltage Vd is applied between the source and drain electrodes.
  • the threshold voltage (Vth) is preferably ⁇ 3.0 V or more and +3.0 or less, more preferably ⁇ 2.5 or more and +2.5 V or less.
  • the on-off ratio is preferably 10 6 or more and 10 12 or less, more preferably 10 7 or more and 10 11 or less, and even more preferably 10 8 or more and 10 11 or less.
  • the on-off ratio is 10 6 or more, the liquid crystal display can be driven.
  • the on-off ratio is 10 12 or less, it becomes possible to drive an organic EL panel with a large contrast, and the off current can be 10 ⁇ 12 A or less, which is used for a transfer transistor or a cancel transistor of a CMOS image sensor. In this case, it is possible to lengthen the image holding time and improve the sensitivity.
  • the Off current value is preferably 10 ⁇ 11 A or less, and more preferably 10 ⁇ 12 A or less.
  • the off-current is 10 ⁇ 11 A or less, it is possible to drive an organic EL panel with a large contrast, and when used for a transfer transistor or a cancel transistor of a CMOS image sensor, Sensitivity can be improved.
  • the defect density of the oxide semiconductor thin film used for the channel layer of the TFT of the present invention is preferably 5.0 ⁇ 10 16 cm ⁇ 3 or less, and more preferably 1.0 ⁇ 10 16 cm ⁇ 3 or less.
  • the element configuration of the TFT is not particularly limited, and various known element configurations can be employed.
  • the TFT of the present invention can be applied to various integrated circuits such as a field effect transistor, a logic circuit, a memory circuit, and a differential amplifier circuit. Further, in addition to the field effect transistor, the present invention can also be applied to an electrostatic induction transistor, a Schottky barrier transistor, a Schottky diode, and a resistance element. Moreover, it can use for electronic devices, such as display apparatuses, such as a liquid crystal display and an organic electroluminescent display, for example.
  • FIG. 1A is a top view of a display device including a TFT of the present invention
  • FIG. 1B is used when a liquid crystal element using the TFT of the present invention is applied to a pixel portion of the display device
  • 1C is a circuit diagram of a pixel portion that can be used when an organic EL element using a TFT of the present invention is applied to the pixel portion of the display device. is there.
  • the TFT of the present invention disposed in the pixel portion can be formed as already described.
  • the TFT of the present invention can easily be an n-channel type, a part of the driver circuit that can be formed using an n-channel transistor is formed over the same substrate as the transistor in the pixel portion. In this manner, a highly reliable display device can be provided by using the transistor described in any of the above embodiments for the transistor and the driver circuit in the pixel portion.
  • the display device in FIG. 1A is an active matrix display device.
  • the display device includes a pixel portion 11, a first scanning line driving circuit 12, a second scanning line driving circuit 13, and a signal line driving circuit 14 on a substrate 10.
  • a plurality of signal lines are extended from the signal line driving circuit 14, and a plurality of scanning lines are extended from the first scanning line driving circuit 12 and the second scanning line driving circuit 13.
  • Pixels each having a display element are provided in a matrix in the intersecting regions between the scanning lines and the signal lines.
  • the substrate 10 of the display device is connected to a timing control circuit (also referred to as a controller or a control IC) via a connecting portion such as an FPC (Flexible Printed Circuit).
  • a timing control circuit also referred to as a controller or a control IC
  • FPC Flexible Printed Circuit
  • the first scanning line driving circuit 12, the second scanning line driving circuit 13, and the signal line driving circuit 14 are formed on the same substrate 10 as the pixel portion 11. For this reason, the number of components such as a drive circuit provided outside is reduced, so that cost can be reduced. Further, when the drive circuit is provided outside the substrate 10, it is necessary to extend the wiring, and the number of connections between the wirings increases. In the case where a driver circuit is provided over the same substrate 10, the number of connections between the wirings can be reduced, and reliability or yield can be improved.
  • FIG. 1 An example of the circuit configuration of the pixel portion is shown in FIG. This example is a circuit of a pixel portion that can be applied to a pixel portion of a VA liquid crystal display device.
  • This circuit of the pixel portion can be applied to a configuration having a plurality of pixel electrodes in one pixel. Each pixel electrode is connected to a different transistor, and each transistor is configured to be driven by a different gate signal. As a result, signals applied to the individual pixel electrodes of the multi-domain designed pixel can be controlled independently.
  • the gate wiring 21 of the transistor 24 and the gate wiring 22 of the transistor 25 are separated so that different gate signals can be given.
  • the source or drain electrode 23 functioning as a data line is used in common for the transistor 24 and the transistor 25.
  • the TFT of the present invention can be used as appropriate. Thereby, a highly reliable liquid crystal display device can be provided.
  • the first pixel electrode is electrically connected to the transistor 24, and the second pixel electrode is electrically connected to the transistor 25.
  • the first pixel electrode and the second pixel electrode are separated.
  • the shape of the first pixel electrode and the second pixel electrode is not particularly limited.
  • the first pixel electrode may be V-shaped.
  • the gate electrode of the transistor 24 is connected to the gate wiring 21, and the gate electrode of the transistor 25 is connected to the gate wiring 22.
  • Different gate signals are given to the gate wiring 21 and the gate wiring 22 to change the operation timing of the transistors 24 and 25, thereby controlling the alignment of the liquid crystal.
  • a storage capacitor may be formed by the capacitor wiring 20, the gate insulating film functioning as a dielectric, and the capacitor electrode electrically connected to the first pixel electrode or the second pixel electrode.
  • the multi-domain structure includes a first liquid crystal element 26 and a second liquid crystal element 27 in one pixel.
  • the first liquid crystal element 26 is composed of a first pixel electrode, a counter electrode, and a liquid crystal layer therebetween
  • the second liquid crystal element 27 is composed of a second pixel electrode, a counter electrode, and a liquid crystal layer therebetween.
  • the circuit of the pixel portion shown in FIG. 1B is not limited to this.
  • a switch, a resistor, a capacitor, a transistor, a sensor, a logic circuit, or the like may be newly added to the pixel illustrated in FIG.
  • FIG. 1 shows a pixel structure of a display device using an organic EL element, and shows an example in which two n-channel transistors are used for one pixel.
  • the oxide semiconductor thin film of the present invention can be used for a channel formation region of an n-channel transistor.
  • Digital time gray scale driving can be applied to the circuit of this pixel portion.
  • the TFT of the present invention can be used as appropriate. Thereby, an organic EL display device with high reliability can be provided.
  • the circuit configuration of the pixel portion is not limited to the pixel configuration shown in FIG.
  • a switch, a resistor, a capacitor, a sensor, a transistor, a logic circuit, or the like may be added to the circuit of the pixel portion illustrated in FIG.
  • a CMOS (Complementary Metal Oxide Semiconductor) image sensor is a solid-state imaging device that holds a potential in a signal charge storage unit and outputs the potential to a vertical output line via an amplification transistor. If there is a leak current in the reset transistor and / or the transfer transistor included in the CMOS image sensor, charging or discharging occurs due to the leak current, and the potential of the signal charge storage portion changes. When the potential of the signal charge storage portion changes, the potential of the amplification transistor also changes, resulting in a value that deviates from the original potential, and the captured image deteriorates.
  • CMOS Complementary Metal Oxide Semiconductor
  • the amplifying transistor may be either a thin film transistor or a bulk transistor.
  • FIG. 2 is a diagram illustrating an example of a pixel configuration of a CMOS image sensor.
  • the pixel includes a photodiode 40 which is a photoelectric conversion element, a transfer transistor 41, a reset transistor 42, an amplification transistor 43, and various wirings.
  • a plurality of pixels are arranged in a matrix to form a sensor.
  • a selection transistor electrically connected to the amplification transistor 43 may be provided.
  • “OS” written in a transistor symbol represents an oxide semiconductor
  • Si represents silicon, which represents a preferable material when applied to each transistor.
  • the photodiode 40 is connected to the source side of the transfer transistor 41, and a signal charge storage unit 44 (FD: also referred to as floating diffusion) is formed on the drain side of the transfer transistor 41.
  • the signal charge storage unit 44 is connected to the source of the reset transistor 42 and the gate of the amplification transistor 43.
  • the reset power supply line 46 may be deleted. For example, there is a method of connecting the drain of the reset transistor 42 to the power supply line 45 or the vertical output line 47 instead of the reset power supply line 46.
  • Examples 1 to 4 Samarium oxide powder, indium oxide powder, and aluminum oxide powder were weighed so as to have the ratio shown in Table 1 below, placed in a polyethylene pot, and mixed and ground for 72 hours by a dry ball mill to prepare a mixed powder.
  • This mixed powder was put into a mold and formed into a press-molded body at a pressure of 500 kg / cm 2 .
  • This molded body was densified by CIP at a pressure of 2000 kg / cm 2 .
  • this molded body was placed in a normal pressure firing furnace, held at 350 ° C. for 3 hours in an air atmosphere, then heated at 50 ° C./hour, and sintered at 1350 ° C. for 40 hours. Thereafter, the mixture was left to cool to obtain an oxide sintered body.
  • ⁇ Apparatus Smartlab (manufactured by Rigaku Corporation) ⁇ X-ray: Cu-K ⁇ ray (wavelength 1.5418mm) ⁇ 2 ⁇ - ⁇ reflection method, continuous scan (2.0 ° / min) ⁇ Sampling interval: 0.02 ° ⁇ Slit DS (divergence slit), SS (scattering slit), RS (light receiving slit): 1 mm
  • FIGS. 1 to 4 XRD charts of the sintered bodies obtained in Examples 1 to 4 are shown in FIGS. 1 to 4, respectively. 1 to 4, it was found that the sintered body obtained in each example had the perovskite phase and the bixbite phase shown in Table 1.
  • Example 5 Samarium oxide powder, indium oxide powder, and aluminum oxide powder were weighed so as to have the ratio shown in Table 2 below, placed in a polyethylene pot, and mixed and ground for 72 hours by a dry ball mill to prepare a mixed powder.
  • This mixed powder was put into a mold and formed into a press-molded body at a pressure of 500 kg / cm 2 .
  • This molded body was densified by CIP at a pressure of 2000 kg / cm 2 .
  • this molded body was placed in a normal pressure firing furnace, held at 350 ° C. for 10 hours in an air atmosphere, then heated at 50 ° C./hour, and sintered at 1450 ° C. for 40 hours. Thereafter, the mixture was left to cool to obtain an oxide sintered body.
  • the characteristics of the sintered body were evaluated in the same manner as in Examples 1 to 4. The results are shown in Table 2.
  • the obtained oxide sintered body was ground and polished to produce a 4 inch ⁇ ⁇ 5 mmt oxide sintered body disc.
  • This disk was bonded to a copper backing plate having a thickness of 8 mm using molten metal indium.
  • Target bonding rate (%) The bonding rate (%) of the obtained target was measured by the following method. The results are shown in Table 2. The bonding rate was determined by measuring the void part that was not bonded by an ultrasonic flaw detector and calculating the ratio of the bonded part based on the target area.
  • Example 6 Using the sputtering target obtained in Example 5, an oxide semiconductor layer (channel layer) was formed by sputtering on a silicon substrate with a thermal oxide film using a channel-shaped metal mask.
  • a titanium electrode was formed to a thickness of 50 nm using a source / drain shaped metal mask.
  • annealing was performed in air at 300 ° C.
  • the TFT element was mounted on a CVD apparatus, and a SiO 2 film having a thickness of 100 nm was formed as a passivation film at 350 ° C., and then TFT characteristics after annealing in the atmosphere at 300 ° C. for 1 hour were evaluated.
  • the mobility was 12 cm 2 / V ⁇ sec
  • the S value (Swing Factor) 0.78. I was able to reproduce it.
  • the off current was 10 ⁇ 12 A or less. From these results, it can be used for a transistor of a display device of a display or a cancel transistor or a transfer transistor of a CMOS image sensor.
  • Examples 7-9 Neodymium oxide powder, indium oxide powder, and aluminum oxide powder were weighed so as to have the ratio shown in Table 3 below, placed in a polyethylene pot, and mixed and ground for 72 hours by a dry ball mill to prepare a mixed powder.
  • This mixed powder was put into a mold and formed into a press-molded body at a pressure of 500 kg / cm 2 .
  • This molded body was densified by CIP at a pressure of 2000 kg / cm 2 .
  • this molded body was placed in a normal pressure firing furnace, held at 350 ° C. for 3 hours in an air atmosphere, then heated at 50 ° C./hour, and sintered at 1350 ° C. for 40 hours. Thereafter, the mixture was left to cool to obtain an oxide sintered body.
  • Examples 10-12 Samarium oxide powder, indium oxide powder, and aluminum oxide powder were weighed so as to have the ratio shown in Table 4 below, placed in a polyethylene pot, and mixed and ground for 72 hours by a dry ball mill to prepare a mixed powder.
  • This mixed powder was put into a mold and formed into a press-molded body at a pressure of 500 kg / cm 2 .
  • This molded body was densified by CIP at a pressure of 1000 kg / cm 2 .
  • this molded body was placed in a normal pressure sintering furnace, left in an air atmosphere at 350 ° C. for 3 hours, heated at 50 ° C./hour, and sintered at 1420 ° C. for 28 hours.
  • the obtained oxide sintered body was ground and polished to produce a 4 inch ⁇ ⁇ 5 mmt oxide sintered body disc.
  • This disk was bonded to a copper backing plate having a thickness of 8 mm using a molten metal indium.
  • Example 13 Using the sputtering target obtained in Example 11, an oxide semiconductor layer (channel layer) was formed by sputtering on a silicon substrate with a thermal oxide film using a channel-shaped metal mask.
  • a titanium electrode was formed to a thickness of 50 nm using a source / drain shaped metal mask.
  • annealing was performed in air at 350 ° C.
  • This TFT element was mounted on a CVD apparatus, and a SiO 2 film having a thickness of 100 nm was formed as a passivation film at 300 ° C., and then TFT characteristics were evaluated after annealing at 350 ° C. in the air for 1 hour.
  • the mobility was 21 cm 2 / V ⁇ sec
  • the current value exceeding 10 ⁇ 8 A
  • the S value (Swing Factor) 0.26. I was able to reproduce it.
  • the off current was 10 ⁇ 12 A or less. From these results, it can be used for a transistor of a display device of a display or a cancel transistor or a transfer transistor of a CMOS image sensor.
  • the oxide sintered body of the present invention can be used as a sputtering target, and is useful for producing an oxide semiconductor thin film of a thin film transistor (TFT) used for a display device such as a liquid crystal display or an organic EL display.
  • TFT thin film transistor

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Abstract

An oxide sintered body which contains a perovskite phase and a bixbyite phase represented by In2O3.

Description

酸化物焼結体及びスパッタリングターゲットOxide sintered body and sputtering target
 本発明は、酸化物焼結体、及びそれを用いて作製されたスパッタリングターゲットに関する。 The present invention relates to an oxide sintered body and a sputtering target produced using the same.
 薄膜トランジスタ(TFT)に用いられるアモルファス(非晶質)酸化物半導体は、汎用のアモルファスシリコン(a-Si)に比べて高いキャリヤー移動度を有し、光学バンドギャップが大きく、低温で成膜できるため、大型・高解像度・高速駆動が要求される次世代ディスプレイや、耐熱性の低い樹脂基板等への適用が期待されている。 Amorphous (amorphous) oxide semiconductors used for thin film transistors (TFTs) have higher carrier mobility than general-purpose amorphous silicon (a-Si), a large optical band gap, and can be formed at low temperatures. It is expected to be applied to next-generation displays that require large size, high resolution, and high-speed driving, and resin substrates with low heat resistance.
 上記酸化物半導体(膜)の形成に当たっては、スパッタリングターゲットをスパッタリングするスパッタリング法が好適に用いられている。これは、スパッタリング法で形成された薄膜が、イオンプレーティング法や真空蒸着法、電子ビーム蒸着法で形成された薄膜に比べ、膜面方向(膜面内)における成分組成や膜厚等の面内均一性に優れており、スパッタリングターゲットと同じ成分組成の薄膜を形成できるためである。 In forming the oxide semiconductor (film), a sputtering method of sputtering a sputtering target is preferably used. This is because the thin film formed by the sputtering method has a component composition, film thickness, etc. in the film surface direction (in the film surface) as compared with the thin film formed by the ion plating method, vacuum evaporation method, or electron beam evaporation method. This is because the internal uniformity is excellent and a thin film having the same component composition as the sputtering target can be formed.
 特許文献1には、酸化アルミニウム、酸化サマリウムの化合物として、A12で表されるガーネット化合物の製造方法が記載されている。
 中には、SmAlAl12化合物が例示されている。
Patent Document 1 describes a method for producing a garnet compound represented by A 3 B 2 C 3 O 12 as a compound of aluminum oxide and samarium oxide.
In the examples, Sm 3 Al 2 Al 3 O 12 compounds are exemplified.
 特許文献2には、酸化インジウム、酸化イットリウム、及び酸化アルミニウム又は酸化ガリウムを含む原料を焼結して得られる、A12型ガーネット構造の化合物を含有するスパッタリングターゲットが記載されている。このターゲットは、ガーネット構造を含むことにより、電気抵抗が小さくなり、スパッタリング中の異常放電も少なく、高移動度のTFT素子への適用に関する記載がある。 Patent Document 2 describes a sputtering target containing a compound having an A 3 B 5 O 12 garnet structure obtained by sintering a raw material containing indium oxide, yttrium oxide, and aluminum oxide or gallium oxide. . Since this target includes a garnet structure, electrical resistance is reduced, abnormal discharge during sputtering is small, and there is a description regarding application to a TFT element with high mobility.
 特許文献3には、酸化サマリウム、及び酸化アルミニウムを含む原料を焼結して得られる、SmAlO3、NdAlO型ぺロブスカイト構造の化合物を含有するα-Alセラミックス複合材料が記載されている。 Patent Document 3 describes an α-Al 2 O 3 ceramic composite material containing a compound of SmAlO 3 and NdAlO 3 type perovskite structure obtained by sintering a raw material containing samarium oxide and aluminum oxide. Yes.
特開2008-7340号公報JP 2008-7340 A 国際公開2015/098060号公報International Publication No. 2015/098060 特開平9-67194号公報Japanese Patent Laid-Open No. 9-67194
 しかし一方で、さらなる高性能なTFTへの要求が強くあり、高移動度で、CVD等での半導体特性の劣化が小さい材料への要望は大きい。 However, on the other hand, there is a strong demand for higher performance TFTs, and there is a great demand for materials with high mobility and small deterioration of semiconductor characteristics due to CVD or the like.
 本発明の目的は、新規な酸化物焼結体及びスパッタリングターゲットを提供することである。 An object of the present invention is to provide a novel oxide sintered body and a sputtering target.
 酸化インジウムをベースとするターゲット材に、ランタノイド系金属の様な原子半径の大きな元素を添加すると、酸化インジウムの格子定数が変化したり、焼結密度が上がらずターゲット材の強度が低下したり、大パワーでのスパッタリング中に熱応力によりマイクロクラックを発生したり、チッピングを起こし異常放電が発生したりする場合がある。これらの現象は得られる薄膜に欠陥を発生させTFT性能の劣化を引き起こす。 When an element with a large atomic radius such as a lanthanoid metal is added to a target material based on indium oxide, the lattice constant of indium oxide changes, the sintered density does not increase, and the strength of the target material decreases. During sputtering at high power, microcracks may be generated due to thermal stress, or abnormal discharge may occur due to chipping. These phenomena cause defects in the obtained thin film and cause deterioration of TFT performance.
 本発明者らは、上記問題点を解決するため、ターゲット材として用いることができるランタノイド系金属元素を含む、酸化インジウムをベースとする新たな物質を見出すべく鋭意探索を行い、ランタノイド系金属元素を含むペロブスカイト相及びInで表されるビックスバイト相を含む新規な酸化物焼結体を見出した。そして、この酸化物焼結体を用いたスパッタリングターゲットは焼結密度が高い、バルク抵抗が低い、ターゲットの反りが少ない、ボンディング率が高い等のターゲット材として有利な特性を有することを見出した。これらのターゲット特性により、大パワーでのスパッタリングでも異常放電が生じ難く安定したスパッタリングが可能となる。また、このスパッタリングターゲットをスパッタして得られる薄膜は、TFTに用いたときに優れたTFT性能(耐CVD性)を発揮することを見出し、本発明を完成させた。 In order to solve the above-mentioned problems, the present inventors have eagerly searched for a new substance based on indium oxide containing a lanthanoid metal element that can be used as a target material. A novel oxide sintered body containing a perovskite phase and a bixbite phase represented by In 2 O 3 has been found. And it discovered that the sputtering target using this oxide sintered compact had advantageous characteristics as target materials, such as high sintering density, low bulk resistance, few warpage of a target, and high bonding rate. Due to these target characteristics, abnormal discharge hardly occurs even when sputtering is performed with high power, and stable sputtering is possible. Further, the thin film obtained by sputtering this sputtering target has been found to exhibit excellent TFT performance (CVD resistance) when used in a TFT, and the present invention has been completed.
 本発明によれば、以下の酸化物焼結体、スパッタリングターゲット、酸化物半導体薄膜の製造方法、薄膜トランジスタの製造方法及び電子機器の製造方法が提供される。
1.ペロブスカイト相及びInで表されるビックスバイト相を含む酸化物焼結体。
2.前記ペロブスカイト相が、下記一般式(I)で表される化合物である、1に記載の酸化物焼結体。
  LnAlO     (I)
(式中、Lnは、La、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb及びLuから選ばれた一種以上の金属元素を表す。)
3.前記Lnが、Sm及びNdのいずれか一方又は両方である、1又は2のいずれかに記載の酸化物焼結体。
4.前記酸化物焼結体中のIn、Al及びLnの原子比が、下記の範囲である2又は3に記載の酸化物焼結体。
    In/(In+Al+Ln)が0.64以上0.98以下
    Al/(In+Al+Ln)が0.01以上0.18以下
    Ln/(In+Al+Ln)が0.01以上0.18以下
5.1~4のいずれかに記載の酸化物焼結体を用いて作製されたスパッタリングターゲット。
6.5に記載のスパッタリングターゲットを用いて製膜することを特徴とする酸化物半導体薄膜の製造方法。
7.5に記載のスパッタリングターゲットを用いて酸化物半導体薄膜を製膜する工程を含むことを特徴とする薄膜トランジスタの製造方法。
8.5に記載のスパッタリングターゲットを用いて酸化物半導体薄膜を製膜する工程、
 前記酸化物半導体薄膜を含む薄膜トランジスタを製造する工程、及び
 前記薄膜トランジスタを電子機器に搭載する工程
を含むことを特徴とする電子機器の製造方法。
9.In、Al及びLnを含み、
 前記Lnは、La、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb及びLuから選ばれた一種以上の金属元素であり、
 前記In、前記Al及び前記Lnの原子比が、下記の範囲である、酸化物半導体薄膜。
    In/(In+Al+Ln)が0.64以上0.98以下
    Al/(In+Al+Ln)が0.01以上0.18以下
    Ln/(In+Al+Ln)が0.01以上0.18以下
10.9に記載の酸化物半導体薄膜を含む薄膜トランジスタ。
11.9に記載の薄膜トランジスタを含む電子機器。
According to the present invention, the following oxide sintered body, sputtering target, oxide semiconductor thin film manufacturing method, thin film transistor manufacturing method, and electronic device manufacturing method are provided.
1. An oxide sintered body containing a perovskite phase and a bixbite phase represented by In 2 O 3 .
2. 2. The oxide sintered body according to 1, wherein the perovskite phase is a compound represented by the following general formula (I).
LnAlO 3 (I)
(In the formula, Ln represents one or more metal elements selected from La, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.)
3. The oxide sintered body according to any one of 1 and 2, wherein the Ln is one or both of Sm and Nd.
4). The oxide sintered body according to 2 or 3, wherein an atomic ratio of In, Al, and Ln in the oxide sintered body is in the following range.
In / (In + Al + Ln) is 0.64 or more and 0.98 or less Al / (In + Al + Ln) is 0.01 or more and 0.18 or less Ln / (In + Al + Ln) is 0.01 or more and 0.18 or less 5.1 to 4 A sputtering target produced using the oxide sintered body described in 1.
The manufacturing method of the oxide semiconductor thin film characterized by forming into a film using the sputtering target of 6.5.
The manufacturing method of the thin-film transistor characterized by including the process of forming an oxide semiconductor thin film using the sputtering target of 7.5.
A step of forming an oxide semiconductor thin film using the sputtering target according to 8.5,
The manufacturing method of the electronic device characterized by including the process of manufacturing the thin-film transistor containing the said oxide semiconductor thin film, and the process of mounting the said thin-film transistor in an electronic device.
9. Including In, Al and Ln,
Ln is one or more metal elements selected from La, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu;
The oxide semiconductor thin film whose atomic ratio of said In, said Al, and said Ln is the following range.
In / (In + Al + Ln) is 0.64 or more and 0.98 or less Al / (In + Al + Ln) is 0.01 or more and 0.18 or less Ln / (In + Al + Ln) is 0.01 or more and 0.18 or less 10.9 A thin film transistor including a semiconductor thin film.
An electronic device including the thin film transistor according to 11.9.
 本発明によれば、新規な酸化物焼結体及びスパッタリングターゲットが提供できる。 According to the present invention, a novel oxide sintered body and sputtering target can be provided.
図1(A)は、本発明のTFTを含む表示装置の上面図であり、図1(B)は、表示装置の画素部に、本発明のTFTを含む液晶素子を適用する場合に用いることができる画素部の回路の図であり、図1(C)は、表示装置の画素部に、本発明のTFTを含む有機EL素子を適用する場合に用いることができる画素部の回路の図である。1A is a top view of a display device including a TFT of the present invention, and FIG. 1B is used when a liquid crystal element including the TFT of the present invention is applied to a pixel portion of the display device. FIG. 1C is a circuit diagram of a pixel portion that can be used when an organic EL element including a TFT of the present invention is applied to the pixel portion of the display device. is there. CMOSイメージセンサーの回路構成の一例を示す。An example of a circuit structure of a CMOS image sensor is shown. 実施例1の酸化物焼結体のX線回折パターンである。2 is an X-ray diffraction pattern of the oxide sintered body of Example 1. FIG. 実施例2の酸化物焼結体のX線回折パターンである。2 is an X-ray diffraction pattern of an oxide sintered body of Example 2. FIG. 実施例3の酸化物焼結体のX線回折パターンである。4 is an X-ray diffraction pattern of an oxide sintered body of Example 3. FIG. 実施例4の酸化物焼結体のX線回折パターンである。4 is an X-ray diffraction pattern of an oxide sintered body of Example 4. 実施例5の酸化物焼結体のX線回折パターンである。6 is an X-ray diffraction pattern of an oxide sintered body of Example 5. FIG. 実施例7の酸化物焼結体のX線回折パターンである。7 is an X-ray diffraction pattern of an oxide sintered body of Example 7. FIG. 実施例8の酸化物焼結体のX線回折パターンである。7 is an X-ray diffraction pattern of an oxide sintered body of Example 8. FIG. 実施例9の酸化物焼結体のX線回折パターンである。10 is an X-ray diffraction pattern of an oxide sintered body of Example 9. 実施例10の酸化物焼結体のX線回折パターンである。3 is an X-ray diffraction pattern of an oxide sintered body of Example 10. FIG. 実施例11の酸化物焼結体のX線回折パターンである。3 is an X-ray diffraction pattern of an oxide sintered body of Example 11. FIG. 実施例12の酸化物焼結体のX線回折パターンである。3 is an X-ray diffraction pattern of an oxide sintered body of Example 12. FIG.
 本発明の一実施形態の酸化物焼結体(以下、本発明の焼結体という)は、ペロブスカイト相及びInで表されるビックスバイト相を含むことを特徴とする。 An oxide sintered body according to an embodiment of the present invention (hereinafter referred to as a sintered body of the present invention) includes a perovskite phase and a bixbite phase represented by In 2 O 3 .
 本発明の焼結体中のペロブスカイト相及びInで表されるビックスバイト相は、例えば、X線回折(XRD)法により、XRDチャートから検出することができる。 The perovskite phase and the bixbite phase represented by In 2 O 3 in the sintered body of the present invention can be detected from the XRD chart by, for example, the X-ray diffraction (XRD) method.
 本発明の焼結体における、前記ペロブスカイト相は、下記一般式(I)で表される化合物であることが好ましい。
  LnAlO     (I)
(式中、Lnは、La、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb及びLuから選ばれた一種以上の金属元素を表す。)
 Lnは、Sm及びNdのいずれか一方又は両方であることが特に好ましい。
The perovskite phase in the sintered body of the present invention is preferably a compound represented by the following general formula (I).
LnAlO 3 (I)
(In the formula, Ln represents one or more metal elements selected from La, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.)
Ln is particularly preferably one or both of Sm and Nd.
 前記一般式(I)で表される化合物は、ペロブスカイト型構造を有しており、これを含むことで高密度の焼結体となり得る。 The compound represented by the general formula (I) has a perovskite structure, and by including this, a high-density sintered body can be obtained.
 一般式(I)で表されるペロブスカイト化合物は、単結晶構造でも多結晶構造でもよい。 The perovskite compound represented by the general formula (I) may have a single crystal structure or a polycrystalline structure.
 本発明の焼結体は、前記一般式(I)で表されるペロブスカイト相、及び、Inで表されるビックスバイト相を含むことにより、焼結密度(相対密度)及び体積抵抗率(バルク抵抗)を向上させることができる。また、膨張係数を小さく、熱伝導度を大きくすることができる。また、雰囲気焼成炉を用いて酸素雰囲気下という特殊な条件下や、大気下等で行うような簡便な方法で焼成した場合でも、体積抵抗率も低く焼結密度も高い焼結体とすることができる。上記特性を有する本発明の焼結体は、ターゲット材として好ましい。 The sintered body of the present invention includes a perovskite phase represented by the above general formula (I) and a bixbite phase represented by In 2 O 3 , whereby a sintered density (relative density) and a volume resistivity are included. (Bulk resistance) can be improved. Also, the expansion coefficient can be reduced and the thermal conductivity can be increased. In addition, a sintered body having a low volume resistivity and a high sintering density should be used even when fired by a simple method such as in an atmosphere of oxygen using an atmosphere firing furnace or in the atmosphere. Can do. The sintered body of the present invention having the above characteristics is preferable as a target material.
 本発明の焼結体をターゲット材として用いることにより、応力の発生を抑え、ターゲットの強度や熱伝導度を高め、線膨張係数を抑え、ターゲットのマイクロクラックやチッピングの発生を抑制し、ノジュールや異常放電の発生を抑制することができ、大パワーでのスパッタリングが可能なスパッタリングターゲットを得ることができる。
 加えて、本発明の焼結体をターゲット材として用いることにより、高移動度で、化学気相成長(CVD)等での半導体特性の劣化が小さい、高性能のTFTを得ることができる。
By using the sintered body of the present invention as a target material, the generation of stress is suppressed, the strength and thermal conductivity of the target are increased, the linear expansion coefficient is suppressed, the occurrence of microcracks and chipping of the target is suppressed, nodules and Generation of abnormal discharge can be suppressed, and a sputtering target capable of sputtering with high power can be obtained.
In addition, by using the sintered body of the present invention as a target material, it is possible to obtain a high-performance TFT with high mobility and small deterioration of semiconductor characteristics due to chemical vapor deposition (CVD) or the like.
 本発明の一実施形態に係るスパッタリングターゲット(以下、本発明のターゲットという)は、上記本発明の焼結体を用いて作製されることを特徴とする。
 本発明のターゲットは、上記本発明の焼結体を研削加工してターゲット材とし、これを銅板等の金属サポート(以下、バッキングプレート、又は、ターゲット支持体ともいう)に金属インジウム等で貼り合わせて製造される。
 本発明の酸化物焼結体及び本発明のターゲットの製造方法は後述する。
A sputtering target according to an embodiment of the present invention (hereinafter referred to as a target of the present invention) is produced using the sintered body of the present invention.
The target of the present invention is a target material obtained by grinding the sintered body of the present invention, and this is bonded to a metal support such as a copper plate (hereinafter also referred to as a backing plate or target support) with metal indium or the like. Manufactured.
The method for producing the oxide sintered body of the present invention and the target of the present invention will be described later.
 本発明のターゲットに用いる焼結体におけるIn、Al及びLnの原子比は、下記の範囲であることが好ましい。
    In/(In+Al+Ln)が0.64以上0.98以下
    Al/(In+Al+Ln)が0.01以上0.18以下
    Ln/(In+Al+Ln)が0.01以上0.18以下
 より好ましくは、下記の範囲である。
    In/(In+Al+Ln)が0.70以上0.96以下
    Al/(In+Al+Ln)が0.02以上0.15以下
    Ln/(In+Al+Ln)が0.02以上0.15以下
The atomic ratio of In, Al, and Ln in the sintered body used for the target of the present invention is preferably in the following range.
In / (In + Al + Ln) is 0.64 or more and 0.98 or less Al / (In + Al + Ln) is 0.01 or more and 0.18 or less Ln / (In + Al + Ln) is 0.01 or more and 0.18 or less More preferably, in the following range is there.
In / (In + Al + Ln) is 0.70 or more and 0.96 or less Al / (In + Al + Ln) is 0.02 or more and 0.15 or less Ln / (In + Al + Ln) is 0.02 or more and 0.15 or less
 In/(In+Al+Ln)が0.64未満の場合、形成する酸化物半導体薄膜を含むTFTの移動動が小さくなるおそれがある。0.98超の場合、TFTの安定性が得られないおそれや、導電化して半導体になりにくいおそれがある。 When In / (In + Al + Ln) is less than 0.64, the movement of the TFT including the oxide semiconductor thin film to be formed may be reduced. If it exceeds 0.98, the stability of the TFT may not be obtained, or it may be difficult to become a semiconductor by conducting it.
 Al/(In+Al+Ln)が、0.01未満の場合、一般式(I)で表されるペロブスカイト相が形成されず、TFTの安定性が得られないおそれや、導電化して半導体になりにくいおそれがあったり、安定したスパッタリングができなくなるおそれがある。一方、0.18超の場合、形成する酸化物半導体薄膜を含むTFTの移動動が小さくなるおそれがある。 When Al / (In + Al + Ln) is less than 0.01, the perovskite phase represented by the general formula (I) is not formed, and the stability of the TFT may not be obtained, or it may be difficult to become conductive and become a semiconductor. Or stable sputtering may not be possible. On the other hand, if it exceeds 0.18, the movement of the TFT including the oxide semiconductor thin film to be formed may be small.
 Ln/(In+Al+Ln)が、0.01未満の場合、一般式(I)で表されるペロブスカイト相が形成されず、TFTの安定性が得られないおそれや、導電化して半導体になりにくいおそれがあったり、安定したスパッタリングができなくなるおそれがある。一方、0.18超の場合、形成する酸化物半導体薄膜を含むTFTの移動動が小さくなるおそれがある。 If Ln / (In + Al + Ln) is less than 0.01, the perovskite phase represented by the general formula (I) may not be formed, and the stability of the TFT may not be obtained, or it may become difficult to become a semiconductor by conducting. Or stable sputtering may not be possible. On the other hand, if it exceeds 0.18, the movement of the TFT including the oxide semiconductor thin film to be formed may be small.
 本発明の焼結体は、さらに、正四価の金属元素を含んでもよい。
 これにより、より安定的にスパッタリングを行うことができる。
The sintered body of the present invention may further contain a positive tetravalent metal element.
Thereby, sputtering can be performed more stably.
 正四価の金属元素としては、Sn、Ti、Zr、Hf、Ce、Ge等が挙げられる。本発明の焼結体は、これらのうち一種又は二種以上を含むことができる。
 Snが好ましい。Snのドーピング効果によりバルク抵抗が低下し、より安定的にスパッタリングを行うことができる。
Examples of the positive tetravalent metal element include Sn, Ti, Zr, Hf, Ce, and Ge. The sintered body of the present invention can contain one or more of these.
Sn is preferred. Bulk resistance decreases due to the Sn doping effect, and sputtering can be performed more stably.
 正四価の金属元素は、Inで表されるビックスバイト相又は一般式(I)で表されるペロブスカイト相に固溶していることが好ましく、Inで表されるビックスバイト相に固溶していることがより好ましい。固溶は、置換型固溶が好ましい。
 これにより、より安定的にスパッタリングを行うことができる。
 また、Ln及びAlはInで表されるビックスバイト相に固溶してもよい。
The positive tetravalent metal element is preferably dissolved in the bixbite phase represented by In 2 O 3 or the perovskite phase represented by the general formula (I), and the bixbite represented by In 2 O 3 More preferably, it is in solid solution in the phase. The solid solution is preferably a substitutional solid solution.
Thereby, sputtering can be performed more stably.
Ln and Al may be dissolved in a bixbite phase represented by In 2 O 3 .
 正四価の金属元素、Ln及びAlの固溶については、例えばXRD測定の格子定数から同定することができる。 The solid solution of the positive tetravalent metal element, Ln and Al can be identified from, for example, the lattice constant of XRD measurement.
 正四価の金属元素の含有量は、本発明の酸化物焼結体中の全金属元素に対して、原子濃度で100ppm以上10000ppm以下が好ましく、より好ましくは500ppm以上8000ppm以下であり、さらに好ましくは800ppm以上6000ppm以下である。
 100ppm未満の場合、バルク抵抗が上昇するおそれがある。一方、10000ppm超の場合、形成する酸化物半導体薄膜を含むTFTが導通するおそれや、オン/オフ値が小さくなるおそれがある。
The content of the positive tetravalent metal element is preferably 100 ppm or more and 10,000 ppm or less, more preferably 500 ppm or more and 8000 ppm or less, more preferably, with respect to all metal elements in the oxide sintered body of the present invention. It is 800 ppm or more and 6000 ppm or less.
If it is less than 100 ppm, the bulk resistance may increase. On the other hand, if it exceeds 10,000 ppm, the TFT including the oxide semiconductor thin film to be formed may become conductive, and the on / off value may be reduced.
 本発明の焼結体における、Inで表されるビックスバイト相の存在比率は、1~99wt%であることが好ましく、10~98wt%であることがより好ましい。Inで表されるビックスバイト相の存在比率が上記範囲であれば、ペロブスカイト相がIn結晶中に分散しており、希土類元素をドーピングする等により、ターゲット素材以外の蛍光材料等への応用も考えられる。
 Inで表されるビックスバイト相の存在比率は、実施例に記載の方法により測定することができる。
In the sintered body of the present invention, the abundance ratio of the bixbite phase represented by In 2 O 3 is preferably 1 to 99 wt%, and more preferably 10 to 98 wt%. If the abundance ratio of the bixbite phase represented by In 2 O 3 is in the above range, the perovskite phase is dispersed in the In 2 O 3 crystal, and the fluorescent material other than the target material is doped with a rare earth element. Application to the above is also conceivable.
The abundance ratio of the bixbite phase represented by In 2 O 3 can be measured by the method described in the examples.
 本発明の焼結体においては、Inで表されるビックスバイト相が主成分であることが好ましい。ビックスバイト構造以外の結晶構造が主成分として析出すると、移動度の低下を招くおそれがある。「Inで表されるビックスバイト相が主成分である」とは、Inで表されるビックスバイト相の存在比率が50wt%超であることを意味し、好ましくは70wt%以上、より好ましくは80wt%以上、さらに好ましくは85wt%以上である。 In the sintered body of the present invention, the bixbite phase represented by In 2 O 3 is preferably the main component. If a crystal structure other than the bixbite structure is precipitated as a main component, the mobility may be lowered. “The bixbite phase represented by In 2 O 3 is a main component” means that the existence ratio of the bixbite phase represented by In 2 O 3 is more than 50 wt%, preferably 70 wt%. As mentioned above, More preferably, it is 80 wt% or more, More preferably, it is 85 wt% or more.
 本発明の焼結体においては、焼結密度が6.5~7.1g/cmの範囲内であることが好ましく、6.6~7.1g/cmの範囲内であることがより好ましい。焼結密度が6.5~7.1g/cmの範囲内であれば、ターゲットとして用いた際に、異常放電の原因やノジュール発生の起点となる空隙を減少させることができる。
 焼結密度は、例えば、アルキメデス法で測定することができる。
In the sintered body of the present invention, the sintered density is preferably in the range of 6.5 to 7.1 g / cm 3 , more preferably in the range of 6.6 to 7.1 g / cm 3. preferable. When the sintered density is in the range of 6.5 to 7.1 g / cm 3 , voids that cause abnormal discharge and start nodules can be reduced when used as a target.
The sintered density can be measured by, for example, the Archimedes method.
 本発明の焼結体においては、バルク抵抗が、好ましくは50mΩ・cm以下であり、より好ましくは30mΩ・cm以下であり、さらに好ましくは20mΩ・cm以下である。下限値に、特に制限はないが、通常1mΩ・cm以上、又は5mΩ・cm以上である。
 50mΩ・cm以下の場合、大パワーでのDCスパッタ成膜時に、ターゲットの帯電による異常放電が発生しにくく、また、プラズマ状態が安定し、スパークが発生しにくくなる。また、パルスDCスパッタ装置やRFスパッタ装置、RF+DCスパッタ装置を用いる場合、さらにプラズマが安定し、異常放電等の問題もなく、安定してスパッタできるようになる。
 バルク抵抗は、例えば、四探針法に基づき測定することができる。具体的には公知の抵抗率計を使用して四探針法(JIS R 1637)に基づき測定できる。測定箇所は5箇所程度であり、平均値をバルク抵抗値とするのが好ましい。
 測定箇所は、酸化物焼結体の平面形状が四角形の場合には、中心及び四隅と中心の中間点の4点の計5箇所とするのが好ましい。
 なお、酸化物焼結体の平面形状が円形の場合は、円に内接する正方形の中心及び正方形の四隅と中心の中間点の4点の計5箇所とするのが好ましい。
In the sintered body of the present invention, the bulk resistance is preferably 50 mΩ · cm or less, more preferably 30 mΩ · cm or less, and further preferably 20 mΩ · cm or less. Although there is no restriction | limiting in particular in a lower limit, Usually, it is 1 mohm * cm or more, or 5 mohm * cm or more.
In the case of 50 mΩ · cm or less, during DC sputtering film formation with high power, abnormal discharge due to target charging is less likely to occur, and the plasma state is stabilized and spark is less likely to occur. Further, when a pulse DC sputtering apparatus, an RF sputtering apparatus, or an RF + DC sputtering apparatus is used, the plasma is further stabilized and the sputtering can be performed stably without problems such as abnormal discharge.
The bulk resistance can be measured based on, for example, a four-probe method. Specifically, it can be measured based on the four-probe method (JIS R 1637) using a known resistivity meter. There are about five measurement points, and the average value is preferably the bulk resistance value.
When the planar shape of the oxide sintered body is a quadrangle, the measurement locations are preferably a total of five locations, that is, the center, four corners, and a midpoint between the centers.
When the planar shape of the oxide sintered body is a circle, it is preferable that the oxide sintered body has a total of five points: a center of a square inscribed in the circle, and four points of the four corners of the square and an intermediate point of the center.
 本発明の焼結体においては、3点曲げ強度が、120MPa以上であることが好ましく、140MPa以上がより好ましく、150MPa以上がさらに好ましい。
 120MPa未満の場合、大パワーでスパッタ成膜した際に、ターゲットの強度が弱く、ターゲットが割れたり、チッピングを起こして、チッピングした破片がターゲット上に飛散し、異常放電の原因となるおそれがある。
In the sintered body of the present invention, the three-point bending strength is preferably 120 MPa or more, more preferably 140 MPa or more, and further preferably 150 MPa or more.
When the pressure is less than 120 MPa, when sputtering film formation is performed with high power, the strength of the target is weak, the target is cracked or chipping occurs, and the chipped fragments may be scattered on the target and cause abnormal discharge. .
 3点曲げ強度は、例えばJIS R 1601「ファインセラミックスの室温曲げ強さ試験」に準じて、試験することができる。
 具体的には、幅4mm、厚さ3mm、長さ40mmの標準試験片を用いて、一定距離(30mm)に配置された2支点上に試験片を置き、支点間の中央からクロスヘッド速度0.5mm/分の荷重を加え、試験片が破壊した時の最大荷重より、曲げ強さを算出することができる。
The three-point bending strength can be tested in accordance with, for example, JIS R 1601 “Room temperature bending strength test of fine ceramics”.
Specifically, using a standard test piece having a width of 4 mm, a thickness of 3 mm, and a length of 40 mm, the test piece is placed on two fulcrums arranged at a fixed distance (30 mm), and the crosshead speed is 0 from the center between the fulcrums. The bending strength can be calculated from the maximum load when the test piece is broken by applying a load of 0.5 mm / min.
 本発明の焼結体においては、線膨張係数が8.0×10-6-1以下であることが好ましく、7.5×10-6-1以下がより好ましく、7.0×10-6-1以下がさらに好ましい。下限値に、特に制限はないが、通常5.0×10-6-1以上である。
 8.0×10-6-1を超える場合、大パワーでスパッタリング中に加熱され、ターゲットが膨張し、ボンディングされている銅版との間で変形が起こり、応力によりターゲットにマイクロクラックが入ったり、割れやチッピングにより、異常放電の原因となるおそれがある。
 線膨張係数は、例えば幅5mm、厚さ5mm、長さ10mmの標準試験片を用いて、昇温速度を5℃/分にセットし、300℃に到達した時の熱膨張による変位を、位置検出機で検出することにより求めることができる。
In the sintered body of the present invention, the linear expansion coefficient is preferably 8.0 × 10 −6 K −1 or less, more preferably 7.5 × 10 −6 K −1 or less, and 7.0 × 10 It is more preferably −6 K −1 or less. The lower limit is not particularly limited, but is usually 5.0 × 10 −6 K −1 or more.
If it exceeds 8.0 × 10 −6 K −1 , it is heated with high power during sputtering, the target expands, deformation occurs between the bonded copper plates, and microcracks are generated in the target due to stress. There is a risk of causing abnormal discharge due to cracking or chipping.
The linear expansion coefficient is, for example, a standard test piece having a width of 5 mm, a thickness of 5 mm, and a length of 10 mm. The temperature increase rate is set to 5 ° C./min. It can be obtained by detecting with a detector.
 本発明の焼結体においては、熱伝導率が5.0W/m・K以上であることが好ましく、5.5W/m・K以上がより好ましく、6.0W/m・K以上がさらに好ましく、6.5W/m・K以上が最も好ましい。
 上限値は、特に制限はないが、通常10W/m・K以下である。
 5.0W/m・K未満の場合、大パワーでスパッタリング成膜した際に、スパッタ面とボンディングされた面の温度が異なり、内部応力によりターゲットにマイクロクラックや割れ、チッピングが発生するおそれがある。
 熱伝導率は、例えば直径10mm、厚さ1mmの標準試験片を用いて、レーザーフラッシュ法により比熱容量と熱拡散率を求め、これに試験片の密度を乗算することにより算出できる。
In the sintered body of the present invention, the thermal conductivity is preferably 5.0 W / m · K or more, more preferably 5.5 W / m · K or more, and even more preferably 6.0 W / m · K or more. 6.5 W / m · K or more is most preferable.
The upper limit is not particularly limited, but is usually 10 W / m · K or less.
In the case of less than 5.0 W / m · K, when sputtering film formation is performed with high power, the temperature of the sputtered surface and the bonded surface is different, and microcracks, cracks, and chipping may occur in the target due to internal stress. .
The thermal conductivity can be calculated by, for example, obtaining a specific heat capacity and a thermal diffusivity by a laser flash method using a standard test piece having a diameter of 10 mm and a thickness of 1 mm, and multiplying this by the density of the test piece.
 本発明の焼結体の金属元素は、本質的に、In、Al、Ln、及び任意に、正四価の金属元素からなっており、本発明の効果を損なわない範囲で他に不可避不純物を含んでもよい。
 本発明の焼結体の金属元素の、例えば、90原子%以上、95原子%以上、98原子%以上、99原子%以上又は100原子%が、In、Al及びLn、又はIn、Al、Ln及び正四価の金属元素からなっていてもよい。
The metal element of the sintered body of the present invention is essentially composed of In, Al, Ln, and optionally a positive tetravalent metal element, and contains other inevitable impurities as long as the effects of the present invention are not impaired. But you can.
For example, 90 atomic% or more, 95 atomic% or more, 98 atomic% or more, 99 atomic% or more, or 100 atomic% of the metal element of the sintered body of the present invention is In, Al and Ln, or In, Al, Ln. And a positive tetravalent metal element.
 本発明の焼結体は、Inを含む原料粉末、Alを含む原料粉末、及びLnを含む原料粉末の混合粉末を調製する工程、混合粉末を成形して成形体を製造する工程、及び成形体を焼成する工程により、製造できる。
 混合粉末は、正四価の金属元素を含む原料粉末を含んでもよい。
 原料粉末は、酸化物粉末が好ましい。
The sintered body of the present invention includes a step of preparing a mixed powder of a raw material powder containing In, a raw material powder containing Al, and a raw material powder containing Ln, a step of forming a mixed powder to produce a molded body, and a molded body Can be produced by a step of baking.
The mixed powder may include a raw material powder containing a positive tetravalent metal element.
The raw material powder is preferably an oxide powder.
 原料粉末の混合比は、例えば得ようとする焼結体の原子比に対応させる。 The mixing ratio of the raw material powder corresponds to, for example, the atomic ratio of the sintered body to be obtained.
 原料粉末の平均粒径は、好ましくは0.1~1.2μmであり、より好ましくは0.5~1.0μm以下である。原料粉末の平均粒径はレーザー回折式粒度分布装置等で測定することができる。 The average particle diameter of the raw material powder is preferably 0.1 to 1.2 μm, more preferably 0.5 to 1.0 μm or less. The average particle diameter of the raw material powder can be measured with a laser diffraction type particle size distribution apparatus or the like.
 原料の混合、成形方法は特に限定されず、公知の方法を用いて行うことができる。また、混合する際にはバインダーを添加してもよい。
 原料の混合は、例えば、ボールミル、ビーズミル、ジェットミル又は超音波装置等の公知の装置を用いて行うことができる。混合時間は、適宜調整すればよいが、6~100時間程度が好ましい。
The method for mixing and forming the raw materials is not particularly limited, and can be performed using a known method. In addition, a binder may be added when mixing.
The mixing of the raw materials can be performed using a known device such as a ball mill, a bead mill, a jet mill, or an ultrasonic device. The mixing time may be appropriately adjusted, but is preferably about 6 to 100 hours.
 成形方法は、例えば、混合粉末を加圧成形して成形体とすることができる。この工程により、製品の形状(例えば、スパッタリングターゲットとして好適な形状)に成形することができる。 The molding method may be, for example, pressing a mixed powder into a molded body. By this process, it can be formed into a product shape (for example, a shape suitable as a sputtering target).
 混合粉末原料を成形型に充填し、通常、金型プレス又は冷間静水圧プレス(CIP)により、例えば1000kg/cm以上の圧力で成形を施して、成形体を得ることができる。
 尚、成形処理に際しては、ポリビニルアルコールやポリエチレングリコール、メチルセルロース、ポリワックス、オレイン酸、ステアリン酸等の成形助剤を用いてもよい。
The mixed powder raw material is filled in a mold, and molded by a mold press or cold isostatic press (CIP) at a pressure of 1000 kg / cm 2 or more, for example, to obtain a molded body.
In the molding process, molding aids such as polyvinyl alcohol, polyethylene glycol, methylcellulose, polywax, oleic acid, and stearic acid may be used.
 得られた成形体を、例えば1200~1650℃の焼結温度で10時間以上焼結して焼結体を得ることができる。
 焼結温度は、好ましくは1350~1600℃、より好ましくは1400~1600℃、さらに好ましくは1450~1600℃である。焼結時間は好ましくは10~50時間、より好ましくは12~40時間、さらに好ましくは13~30時間である。
The obtained molded body can be sintered at a sintering temperature of 1200 to 1650 ° C. for 10 hours or more, for example, to obtain a sintered body.
The sintering temperature is preferably 1350 to 1600 ° C, more preferably 1400 to 1600 ° C, still more preferably 1450 to 1600 ° C. The sintering time is preferably 10 to 50 hours, more preferably 12 to 40 hours, still more preferably 13 to 30 hours.
 焼結温度が1200℃未満又は焼結時間が10時間未満であると、焼結が十分進行しないため、ターゲットの電気抵抗が十分下がらず、異常放電の原因となるおそれがある。一方、焼成温度が1650℃を超えるか、又は、焼成時間が50時間を超えると、著しい結晶粒成長により平均結晶粒径の増大や、粗大空孔の発生を来たし、焼結体強度の低下や異常放電の原因となるおそれがある。 If the sintering temperature is less than 1200 ° C. or the sintering time is less than 10 hours, the sintering does not proceed sufficiently, and the electrical resistance of the target is not sufficiently lowered, which may cause abnormal discharge. On the other hand, when the firing temperature exceeds 1650 ° C. or the firing time exceeds 50 hours, the average crystal grain size increases due to remarkable crystal grain growth, and coarse pores are generated, and the sintered body strength is reduced. May cause abnormal discharge.
 常圧焼結法では、通常、成形体を大気雰囲気、又は酸素ガス雰囲気にて焼結する。酸素ガス雰囲気は、酸素濃度が、例えば10~50体積%の雰囲気であることが好ましい。昇温過程を大気雰囲気下ですることで、焼結体密度を高くすることができる。 In the normal pressure sintering method, the compact is usually sintered in an air atmosphere or an oxygen gas atmosphere. The oxygen gas atmosphere is preferably an atmosphere having an oxygen concentration of, for example, 10 to 50% by volume. The sintered body density can be increased by performing the temperature raising process in an air atmosphere.
 さらに、焼結に際しての昇温速度は、800℃から焼結温度(1200~1650℃)までを50~150℃/時間とすることが好ましい。
 本発明の焼結体において800℃から上の温度範囲は、焼結が最も進行する範囲である。この温度範囲での昇温速度が50℃/時間より遅くなると、結晶粒成長が著しくなって、高密度化を達成することができないおそれがある。一方、昇温速度が150℃/時間より速くなると、成形体に温度分布が生じ、焼結体が反ったり割れたりするおそれがある。
 800℃から焼結温度における昇温速度は、好ましくは60~140℃/時間、より好ましくは70~130℃/時間である。
Furthermore, it is preferable that the heating rate during sintering is from 50 ° C. to 150 ° C./hour from 800 ° C. to the sintering temperature (1200 to 1650 ° C.).
In the sintered body of the present invention, the temperature range above 800 ° C. is the range where the sintering proceeds most. When the rate of temperature rise in this temperature range is slower than 50 ° C./hour, crystal grain growth becomes significant, and there is a possibility that densification cannot be achieved. On the other hand, when the rate of temperature increase is higher than 150 ° C./hour, a temperature distribution is generated in the molded body, and the sintered body may be warped or cracked.
The rate of temperature increase from 800 ° C. to the sintering temperature is preferably 60 to 140 ° C./hour, more preferably 70 to 130 ° C./hour.
 本発明のスパッタリングターゲットは、上述の本発明の焼結体を用いて作製することができる。これにより、酸化物半導体薄膜を、スパッタリング法等の真空プロセスで製造することができる。 The sputtering target of the present invention can be produced using the above-described sintered body of the present invention. Thereby, an oxide semiconductor thin film can be manufactured by vacuum processes, such as sputtering method.
 スパッタリングターゲットは、例えば、焼結体を切削又は研磨加工し、バッキングプレートにボンディングすることにより作製することができる。
 例えば、切削加工することで、焼結体表面の、高酸化状態の焼結部や、凸凹した面を除くことができる。また、指定の大きさにすることができる。
 表面を#200番、もしくは#400番、さらには#800番の研磨を行ってもよい。これにより、スパッタリング中の異常放電やパーティクルの発生を抑えることができる。
The sputtering target can be produced, for example, by cutting or polishing the sintered body and bonding it to a backing plate.
For example, by cutting, a sintered part in a highly oxidized state and an uneven surface on the surface of the sintered body can be removed. Also, it can be specified size.
The surface may be polished with # 200, # 400, or # 800. Thereby, abnormal discharge and generation of particles during sputtering can be suppressed.
 スパッタリング時の冷却効率を保つ上でボンディング率は、90%以上とすることが好ましく、95%以上がより好ましく、99%以上がさらに好ましい。ここでいうボンディング率とは、ターゲット材とターゲット支持体との重なり合った面の面積に対して、ターゲット材とターゲット支持体材とが接合層を介して接合されている面の面積割合を示す。ボンディング率は、通常、超音波探傷装置等により測定することができる。 In order to maintain the cooling efficiency during sputtering, the bonding rate is preferably 90% or more, more preferably 95% or more, and even more preferably 99% or more. The bonding rate here refers to the area ratio of the surface where the target material and the target support material are bonded via the bonding layer with respect to the area of the overlapping surface of the target material and the target support. The bonding rate can usually be measured with an ultrasonic flaw detector or the like.
 ターゲット材とターゲット支持体との接合方法について説明する。
 所定の形状に加工したターゲット材における、ターゲット支持体との接合面に対して、表面処理を行う。表面処理に使用される装置は、一般に市販されているブラスト装置を使用することができる。例えば、不二製作所製、商品名「ニューマブラスター・SGF-5-B」を挙げることができる。ブラスト法に用いられる粉末としては、ガラス、アルミナ、ジルコニア、SiC、等が使用できるが、これらはターゲット材の組成、硬度等に併せて適宜選択される。
A method for joining the target material and the target support will be described.
Surface treatment is performed on the joint surface with the target support in the target material processed into a predetermined shape. As a device used for the surface treatment, a commercially available blasting device can be used. For example, the product name “Pneuma Blaster SGF-5-B” manufactured by Fuji Seisakusho can be mentioned. Glass, alumina, zirconia, SiC, or the like can be used as the powder used in the blasting method, and these are appropriately selected according to the composition, hardness, etc. of the target material.
 得られた表面処理済みのターゲット材表面を、必要に応じて洗浄した後、接合面に金属インジウム半田等の接合材料を塗布する。同じく必要に応じて洗浄処理を施したバッキングプレートの接合面に、金属インジウム半田等の接合材料を塗布する。この際に、ターゲット材が直接接合材料に溶着しない材料で構成されている場合には、予めターゲット材の接合面に接合材料との濡れ性に優れた銅、ニッケル等の薄膜層を、スパッタリング法、メッキ法等により形成した後、このターゲット材を使用する接合材料の融点以上に加熱して接合材料を塗布するか、あるいは超音波を用いてターゲット材の接合面に直接接合材料を塗布してもよい。 After cleaning the surface of the target material that has been subjected to surface treatment as necessary, a bonding material such as metal indium solder is applied to the bonding surface. Similarly, a bonding material such as metal indium solder is applied to the bonding surface of the backing plate that has been subjected to a cleaning treatment if necessary. At this time, when the target material is composed of a material that is not directly welded to the bonding material, a thin film layer such as copper or nickel having excellent wettability with the bonding material is previously formed on the bonding surface of the target material by a sputtering method. After forming by plating, etc., apply the bonding material by heating it above the melting point of the bonding material using the target material, or apply the bonding material directly to the bonding surface of the target material using ultrasonic waves. Also good.
 次に、接合材料を塗布したターゲット支持体を、使用された接合材料の融点以上に加熱して表面の接合材料層を融解させた後、上述の粉末をその表面に配置し、ターゲット材とバッキングプレートを接合した後、室温まで冷却してターゲットを得ることができる。 Next, the target support to which the bonding material is applied is heated to a temperature equal to or higher than the melting point of the used bonding material to melt the bonding material layer on the surface, and then the above-mentioned powder is placed on the surface to back the target material and the backing material. After joining the plates, the target can be obtained by cooling to room temperature.
 本発明のスパッタリングターゲットは、直流(DC)スパッタリング法、高周波(RF)スパッタリング法、交流(AC)スパッタリング法、パルスDCスパッタリング法等に適用することができる。 The sputtering target of the present invention can be applied to a direct current (DC) sputtering method, a radio frequency (RF) sputtering method, an alternating current (AC) sputtering method, a pulsed DC sputtering method, and the like.
 上記本発明のスパッタリングターゲットを用いて製膜することにより、酸化物半導体薄膜を得ることができる。これにより、TFTに用いたときに優れたTFT性能が発揮される薄膜を形成できる。 An oxide semiconductor thin film can be obtained by forming a film using the sputtering target of the present invention. Thereby, a thin film that exhibits excellent TFT performance when used in a TFT can be formed.
 製膜は、蒸着法、スパッタリング法、イオンプレーティング法、パルスレーザー蒸着法等により行うことができる。
 スパッタリングは、O、HO、等の酸素原子含有ガス(酸化性ガス)を導入した酸化性アルゴン雰囲気下で行うとよい。スパッタリングを酸化性雰囲気下で行うことにより得られる半導体特性及び光安定性に必要な光透過性の阻害要因となる不純物の生成を抑制することができる。
 上記酸化性ガスの濃度は、所望する膜の半導体特性、特にキャリヤー濃度により適宜調整するとよい。この調整は、例えば基板温度、スパッタリング圧力等により行うこともできる。
Film formation can be performed by a vapor deposition method, a sputtering method, an ion plating method, a pulse laser vapor deposition method, or the like.
Sputtering is preferably performed in an oxidizing argon atmosphere into which an oxygen atom-containing gas (oxidizing gas) such as O 2 or H 2 O is introduced. It is possible to suppress the generation of impurities that are an impediment to light transmission necessary for semiconductor characteristics and light stability obtained by performing sputtering in an oxidizing atmosphere.
The concentration of the oxidizing gas may be appropriately adjusted depending on the desired semiconductor characteristics of the film, particularly the carrier concentration. This adjustment can also be performed by, for example, the substrate temperature, the sputtering pressure, or the like.
 スパッタリングガスとしては、ガスの組成を制御しやすい観点から、好ましくはAr-O系ガス又はAr-HO系ガスを用い、より好ましくは制御性が特に優れるAr-O系ガスである。
 Ar-O系ガスを用いることにより、光安定性に優れた半導体特性を有する半導体膜が得られる。O濃度は、好ましくは0.2~50体積%である。
 O濃度が0.2体積%未満の場合、得られる膜が黄色く着色し、光安定性が劣るおそれがある。一方、O濃度が50体積%超の場合、スパッタリング時の薄膜の堆積速度が遅くなるため生産コストが高くなるおそれがある。
 また、O濃度を10体積%程度にした場合に、得られた膜が熱処理によりキャリヤー濃度が1015~1018cm-3台となり、優れた半導体膜として使用可能である。
As a sputtering gas, from the viewpoint of easily controlling the composition of the gas, preferably with Ar-O 2 based gas or Ar-H 2 O-based gas, more preferably at Ar-O 2 based gas control is excellent particularly .
By using Ar—O 2 -based gas, a semiconductor film having semiconductor characteristics with excellent light stability can be obtained. The O 2 concentration is preferably 0.2 to 50% by volume.
If the O 2 concentration is less than 0.2% by volume, the resulting film may be colored yellow and the light stability may be poor. On the other hand, when the O 2 concentration is more than 50% by volume, the deposition cost of the thin film at the time of sputtering becomes slow, which may increase the production cost.
Further, when the O 2 concentration is about 10% by volume, the obtained film has a carrier concentration of 10 15 to 10 18 cm −3 by heat treatment, and can be used as an excellent semiconductor film.
 スパッタリング装置内の成膜前の圧力(チャンバ内の圧力は)は、好ましくは10-6~10-3Paである。
 チャンバ内の圧力が10-3Pa超の場合、真空中に残った残留水分の影響を受けるので、抵抗制御がしにくくなるおそれがある。一方、チャンバ内の圧力が10-6Pa未満の場合、真空引きに時間を要するため、生産性が悪くなるおそれがある。
The pressure before film formation in the sputtering apparatus (the pressure in the chamber) is preferably 10 −6 to 10 −3 Pa.
When the pressure in the chamber exceeds 10 −3 Pa, it is affected by residual moisture remaining in the vacuum, so that resistance control may be difficult. On the other hand, when the pressure in the chamber is less than 10 −6 Pa, it takes time for evacuation, which may deteriorate productivity.
 スパッタリング時の電流密度(投入電力をターゲット面の面積で割った値)は、好ましくは1~10W/cmである。
 電流密度が1W/cm未満の場合、放電が安定しないおそれがある。一方、電流密度が10W/cm超の場合、ターゲットが発生した熱で割れるおそれがある。
The current density during sputtering (the value obtained by dividing the input power by the area of the target surface) is preferably 1 to 10 W / cm 2 .
When the current density is less than 1 W / cm 2 , the discharge may not be stable. On the other hand, when the current density exceeds 10 W / cm 2 , there is a possibility that the target may break due to the heat generated.
 スパッタリング中の圧力は、好ましくは0.01~20Paである。
 スパッタリング圧力が0.01Pa未満の場合、放電が安定しないおそれがある。一方、スパッタリング圧力が20Pa超の場合、スパッタ放電が安定しないおそれがあるうえ、スパッタリングガス自身が導電膜中に取り込まれ、膜の特性を下げるおそれがある。好ましくは、0.05~5Pa、より好ましくは、0.1~1Paである。
The pressure during sputtering is preferably 0.01 to 20 Pa.
If the sputtering pressure is less than 0.01 Pa, the discharge may not be stable. On the other hand, when the sputtering pressure is higher than 20 Pa, the sputtering discharge may not be stable, and the sputtering gas itself may be taken into the conductive film to deteriorate the film characteristics. The pressure is preferably 0.05 to 5 Pa, more preferably 0.1 to 1 Pa.
 本発明の酸化物半導体薄膜を成膜する基体としては、ガラス、セラミックス、プラスチックス、金属等が挙げられる。
 成膜中の基体温度は特に制限されないが、非晶質膜を得られやすい観点から、好ましくは300℃以下である。基体温度は、特に意図的な加熱をしない場合、即ち室温程度でもよい。非晶質薄膜のまま半導体素子として使用することもできるが、成膜直後は、非晶質膜として成膜し、パターン二ングにより島状の半導体部分を形成した後、熱処理により結晶化させた後に、ソース・ドレイン電極などを接続し、薄膜半導体素子とすることもできる。
Examples of the substrate on which the oxide semiconductor thin film of the present invention is formed include glass, ceramics, plastics, and metals.
The substrate temperature during film formation is not particularly limited, but is preferably 300 ° C. or less from the viewpoint of easily obtaining an amorphous film. The substrate temperature may be about room temperature when no intentional heating is performed. Although it can be used as a semiconductor element as an amorphous thin film, immediately after film formation, it was formed as an amorphous film, and after forming an island-shaped semiconductor portion by patterning, it was crystallized by heat treatment. Later, a source / drain electrode or the like may be connected to form a thin film semiconductor element.
 成膜後、スパッタリング中に導入した酸素は膜中に固定されていないため、基体を後加熱(熱処理)するとよい。この熱処理は、好ましく大気中、窒素中又は真空中で150~400℃で行い、好ましくは200℃~350℃で行う。200℃~350℃で熱処理を行うことにより、結晶化させることにより半導体膜の劣化を防ぎ、半導体膜のキャリヤー濃度の変化を抑えたり、光安定に優れるバンドギャップが広がり光透過率の向上が可能となる。結晶化したか否かは、XRD測定において、ピークが観察されるかで判断される。
 熱処理が150℃未満の場合、薄膜中の酸素が徐々に排出され半導体膜の劣化がおきるおそれがある。一方、熱処理が350℃超の場合、半導体膜のキャリヤー濃度が低くなるおそれがある。
After the film formation, oxygen introduced during sputtering is not fixed in the film, and thus the substrate may be post-heated (heat treatment). This heat treatment is preferably performed at 150 to 400 ° C., preferably 200 to 350 ° C. in the air, nitrogen or vacuum. By performing heat treatment at 200 ° C to 350 ° C, it is possible to prevent deterioration of the semiconductor film by crystallization, suppress changes in the carrier concentration of the semiconductor film, increase the band gap with excellent light stability, and improve the light transmittance. It becomes. Whether or not it is crystallized is determined by whether or not a peak is observed in the XRD measurement.
When the heat treatment is less than 150 ° C., oxygen in the thin film is gradually exhausted and the semiconductor film may be deteriorated. On the other hand, when the heat treatment exceeds 350 ° C., the carrier concentration of the semiconductor film may be lowered.
 本発明の一実施形態の酸化物半導体薄膜(以下、本発明の酸化物半導体薄膜という)は、上記本発明のスパッタリングターゲットにより製造されたものである。
 本発明の酸化物半導体薄膜は、In、Al及びLnを含み、前記Lnは、La、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb及びLuから選ばれた一種以上の金属元素であり、前記In、前記Al及び前記Lnの原子比が、下記の範囲であることを特徴とする。
    In/(In+Al+Ln)が0.64以上0.98以下
    Al/(In+Al+Ln)が0.01以上0.18以下
    Ln/(In+Al+Ln)が0.01以上0.18以下
An oxide semiconductor thin film according to an embodiment of the present invention (hereinafter referred to as an oxide semiconductor thin film of the present invention) is manufactured using the sputtering target of the present invention.
The oxide semiconductor thin film of the present invention contains In, Al, and Ln, and the Ln is one or more selected from La, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. The atomic ratio of In, Al, and Ln is in the following range.
In / (In + Al + Ln) is 0.64 or more and 0.98 or less Al / (In + Al + Ln) is 0.01 or more and 0.18 or less Ln / (In + Al + Ln) is 0.01 or more and 0.18 or less
 本発明の酸化物半導体薄膜におけるIn、Al及びLnの原子比は、下記の範囲であることが好ましい。
    In/(In+Al+Ln)が0.64以上0.98以下
    Al/(In+Al+Ln)が0.01以上0.18以下
    Ln/(In+Al+Ln)が0.01以上0.18以下
 より好ましくは、下記の範囲である。
    In/(In+Al+Ln)が0.70以上0.96以下
    Al/(In+Al+Ln)が0.02以上0.15以下
    Ln/(In+Al+Ln)が0.02以上0.15以下
 上記酸化物半導体薄膜の原子比における上下限の具体的な根拠は、本発明の酸化物焼結体の原子比における上下限の具体的な根拠と同じである。
The atomic ratio of In, Al, and Ln in the oxide semiconductor thin film of the present invention is preferably in the following range.
In / (In + Al + Ln) is 0.64 or more and 0.98 or less Al / (In + Al + Ln) is 0.01 or more and 0.18 or less Ln / (In + Al + Ln) is 0.01 or more and 0.18 or less More preferably, in the following range is there.
In / (In + Al + Ln) is 0.70 or more and 0.96 or less Al / (In + Al + Ln) is 0.02 or more and 0.15 or less Ln / (In + Al + Ln) is 0.02 or more and 0.15 or less Atomic ratio of the oxide semiconductor thin film The specific ground for the upper and lower limits in is the same as the specific ground for the upper and lower limits in the atomic ratio of the oxide sintered body of the present invention.
 酸化物半導体薄膜中の各金属元素の含有量(原子比)は、ICP(Inductive Coupled Plasma)測定又はXRF(X-ray Fluorescence)測定により、各元素の存在量を測定することで求めることができる。ICP測定は誘導プラズマ発光分析装置を用いることができる。XRF測定は薄膜蛍光X線分析装置(AZX400、リガク社製)を用いることができる。 The content (atomic ratio) of each metal element in the oxide semiconductor thin film can be obtained by measuring the abundance of each element by ICP (Inductive Coupled Plasma) measurement or XRF (X-ray Fluorescence) measurement. . For the ICP measurement, an induction plasma emission analyzer can be used. For XRF measurement, a thin film X-ray fluorescence analyzer (AZX400, manufactured by Rigaku Corporation) can be used.
 また、セクタ型ダイナミック二次イオン質量分析計SIMS分析を用いても誘導プラズマ発光分析と同等の精度で酸化物半導体薄膜中の各金属元素の含有量(原子比)を分析できる。誘導プラズマ発光分析装置又は薄膜蛍光X線分析装置で測定した金属元素の原子比が既知の標準酸化物薄膜の上面に、ソース・ドレイン電極をTFT素子と同様の材料をチャネル長で形成したものを標準材料とし、セクタ型ダイナミック二次イオン質量分析計SIMS(IMS 7f-Auto、AMETEK社製)により酸化物半導体層の分析に行い各元素の質量スペクトル強度を得、既知の元素濃度と質量スペクトル強度の検量線を作製する。次に、実TFT素子の酸化物半導体膜部分を、セクタ型ダイナミック二次イオン質量分析計SIMS分析によるスペクトル強度から、前述の検量線を用いて、原子比を算出すると、算出された原子比は、別途、薄膜蛍光X線分析装置又は誘導プラズマ発光分析装置で測定された酸化物半導体膜の原子比の2原子%以内であることが確認できる。 In addition, the content (atomic ratio) of each metal element in the oxide semiconductor thin film can be analyzed with the same accuracy as the induction plasma emission analysis even when using the sector type dynamic secondary ion mass spectrometer SIMS analysis. A material in which the source and drain electrodes are formed with the same channel length as the TFT element on the upper surface of a standard oxide thin film with a known atomic ratio of metal elements measured by an induction plasma emission spectrometer or thin film fluorescent X-ray analyzer Analyze the oxide semiconductor layer by using a sector-type dynamic secondary ion mass spectrometer SIMS (IMS-7f-Auto, manufactured by AMETEK) as a standard material, obtain the mass spectrum intensity of each element, and obtain the known element concentration and mass spectrum intensity. A calibration curve is prepared. Next, when calculating the atomic ratio of the oxide semiconductor film portion of the actual TFT element from the spectrum intensity obtained by the SIMS analysis of the sector type dynamic secondary ion mass spectrometer, using the calibration curve described above, the calculated atomic ratio is Separately, it can be confirmed that it is within 2 atomic% of the atomic ratio of the oxide semiconductor film measured by the thin film fluorescent X-ray analyzer or the induction plasma emission analyzer.
 本発明の一実施形態に係る薄膜トランジスタ(TFT)(以下、本発明のTFTという)は、上述の酸化物半導体薄膜を含む。酸化物半導体薄膜は、例えばチャネル層として好適に使用できる。 A thin film transistor (TFT) according to an embodiment of the present invention (hereinafter referred to as a TFT of the present invention) includes the above-described oxide semiconductor thin film. The oxide semiconductor thin film can be suitably used as a channel layer, for example.
 本発明のTFTは、以下の特性を有することが好ましい。
 TFTの飽和移動度は1.0cm/V・s以上、50.0cm/V・s以下が好ましい。TFTの飽和移動度を1.0cm/V・s以上とすることにより、CMOSイメージセンサーの転送トランジスタやキャンセルトランジスタ、液晶ディスプレイや有機ELディスプレイを駆動できる。TFTの飽和移動度を50.0cm/V・s以下とすることにより、オフ電流を10-12A以下にでき、オンオフ比を10以上にできる。
The TFT of the present invention preferably has the following characteristics.
Saturation mobility of the TFT is 1.0cm 2 / V · s or more, preferably not more than 50.0cm 2 / V · s. By setting the saturation mobility of the TFT to 1.0 cm 2 / V · s or more, it is possible to drive the transfer transistor, cancel transistor, liquid crystal display, and organic EL display of the CMOS image sensor. By setting the saturation mobility of the TFT to 50.0 cm 2 / V · s or less, the off current can be made 10 −12 A or less, and the on / off ratio can be made 10 8 or more.
 TFTの飽和移動度は、ドレイン電圧を20V印加した場合の伝達特性から求められる。具体的には、伝達特性Id-Vgのグラフを作成し、各Vgのトランスコンダクタンス(Gm)を算出し、飽和領域の式により飽和移動度を求める。Idはソース・ドレイン電極間の電流、Vgはソース・ドレイン電極間に電圧Vdを印加したときのゲート電圧である。 The saturation mobility of the TFT can be obtained from the transfer characteristics when a drain voltage of 20 V is applied. Specifically, a graph of the transfer characteristic Id-Vg is created, the transconductance (Gm) of each Vg is calculated, and the saturation mobility is obtained by the equation of the saturation region. Id is a current between the source and drain electrodes, and Vg is a gate voltage when a voltage Vd is applied between the source and drain electrodes.
 閾値電圧(Vth)は、-3.0V以上、+3.0以下が好ましく、-2.5以上、+2.5V以下がより好ましい。閾値電圧が-3.0V以上、+3.0以下であると、オフ電流が小さく、オンオフ比の大きな薄膜トランジスタができ、バルクのシリコンウェハで構成された回路と組み合わせて駆動することができる。
 本発明において、閾値電圧(Vth)は、伝達特性のグラフよりId=10-9AでのVgと定義する。
The threshold voltage (Vth) is preferably −3.0 V or more and +3.0 or less, more preferably −2.5 or more and +2.5 V or less. When the threshold voltage is −3.0 V or higher and +3.0 or lower, a thin film transistor having a small off-current and a large on-off ratio can be formed, and can be driven in combination with a circuit formed of a bulk silicon wafer.
In the present invention, the threshold voltage (Vth) is defined as Vg at Id = 10 −9 A from the transfer characteristic graph.
 on-off比は10以上、1012以下が好ましく、10以上、1011以下がより好ましく、10以上、1011以下がさらに好ましい。on-off比が10以上であると、液晶ディスプレイを駆動することができる。on-off比が1012以下であると、コントラストの大きな有機ELパネルの駆動が可能になり、また、オフ電流を10-12A以下にでき、CMOSイメージセンサーの転送トランジスタやキャンセルトランジスタに用いた場合、画像の保持時間を長くしたり、感度を向上させたりすることができる。
 本発明において、on-off比は、Vg=-10VのIdの値をOff電流値とし、Vg=20VのIdの値をOn電流値として、比[On/Off]を算出した。
The on-off ratio is preferably 10 6 or more and 10 12 or less, more preferably 10 7 or more and 10 11 or less, and even more preferably 10 8 or more and 10 11 or less. When the on-off ratio is 10 6 or more, the liquid crystal display can be driven. When the on-off ratio is 10 12 or less, it becomes possible to drive an organic EL panel with a large contrast, and the off current can be 10 −12 A or less, which is used for a transfer transistor or a cancel transistor of a CMOS image sensor. In this case, it is possible to lengthen the image holding time and improve the sensitivity.
In the present invention, for the on-off ratio, the ratio [On / Off] was calculated using the Id value of Vg = −10 V as the Off current value and the Id value of Vg = 20 V as the On current value.
 Off電流値は、10-11A以下が好ましく、10-12A以下がより好ましい。オフ電流を10-11A以下であると、コントラストの大きな有機ELパネルの駆動が可能であり、また、CMOSイメージセンサーの転送トランジスタやキャンセルトランジスタに用いた場合、画像の保持時間を長くしたり、感度を向上させたりすることができる。 The Off current value is preferably 10 −11 A or less, and more preferably 10 −12 A or less. When the off-current is 10 −11 A or less, it is possible to drive an organic EL panel with a large contrast, and when used for a transfer transistor or a cancel transistor of a CMOS image sensor, Sensitivity can be improved.
 本発明のTFTのチャネル層に用いられる酸化物半導体薄膜の欠陥密度は、5.0×1016cm-3以下が好ましく、1.0×1016cm-3以下がより好ましい。欠陥密度を上記のように低くすることにより、薄膜トランジスタの移動度がさらに高くなり、光照射時の安定性、熱に対する安定性が高くなり、TFTが安定して作動するようになる。 The defect density of the oxide semiconductor thin film used for the channel layer of the TFT of the present invention is preferably 5.0 × 10 16 cm −3 or less, and more preferably 1.0 × 10 16 cm −3 or less. By reducing the defect density as described above, the mobility of the thin film transistor is further increased, the stability during light irradiation and the stability against heat are increased, and the TFT operates stably.
 TFTの素子構成は特に限定されず、公知の各種の素子構成を採用することができる。本発明のTFTは、電界効果型トランジスタ、論理回路、メモリ回路、差動増幅回路等、各種の集積回路にも適用できる。さらに、電界効果型トランジスタ以外にも、静電誘起型トランジスタ、ショットキー障壁型トランジスタ、ショットキーダイオード、抵抗素子にも適用できる。また、例えば液晶ディスプレイや有機エレクトロルミネッセンスディスプレイ等の表示装置等の電子機器に用いることができる。 The element configuration of the TFT is not particularly limited, and various known element configurations can be employed. The TFT of the present invention can be applied to various integrated circuits such as a field effect transistor, a logic circuit, a memory circuit, and a differential amplifier circuit. Further, in addition to the field effect transistor, the present invention can also be applied to an electrostatic induction transistor, a Schottky barrier transistor, a Schottky diode, and a resistance element. Moreover, it can use for electronic devices, such as display apparatuses, such as a liquid crystal display and an organic electroluminescent display, for example.
 本発明のTFTを表示装置に用いる場合について説明する。 The case where the TFT of the present invention is used for a display device will be described.
 図1(A)は、本発明のTFTを含む表示装置の上面図であり、図1(B)は、表示装置の画素部に、本発明のTFTを用いる液晶素子を適用する場合に用いることができる画素部の回路の図であり、図1(C)は、表示装置の画素部に、本発明のTFTを用いる有機EL素子を適用する場合に用いることができる画素部の回路の図である。 1A is a top view of a display device including a TFT of the present invention, and FIG. 1B is used when a liquid crystal element using the TFT of the present invention is applied to a pixel portion of the display device. 1C is a circuit diagram of a pixel portion that can be used when an organic EL element using a TFT of the present invention is applied to the pixel portion of the display device. is there.
 画素部に配置する本発明のTFTは、既に説明したとおりに形成することができる。また、本発明のTFTはnチャネル型とすることが容易なので、駆動回路のうち、nチャネル型トランジスタで構成することができる駆動回路の一部を画素部のトランジスタと同一基板上に形成する。このように、画素部のトランジスタや駆動回路に上記実施の形態に示すトランジスタを用いることにより、信頼性の高い表示装置を提供することができる。 The TFT of the present invention disposed in the pixel portion can be formed as already described. In addition, since the TFT of the present invention can easily be an n-channel type, a part of the driver circuit that can be formed using an n-channel transistor is formed over the same substrate as the transistor in the pixel portion. In this manner, a highly reliable display device can be provided by using the transistor described in any of the above embodiments for the transistor and the driver circuit in the pixel portion.
 図1(A)の表示装置は、アクティブマトリクス型表示装置である。表示装置は、基板10上に、画素部11、第1の走査線駆動回路12、第2の走査線駆動回路13、信号線駆動回路14を有する。画素部11には、複数の信号線が信号線駆動回路14から延伸して配置され、複数の走査線が第1の走査線駆動回路12及び第2の走査線駆動回路13から延伸して配置されている。走査線と信号線との交差領域には、各々、表示素子を有する画素がマトリクス状に設けられている。表示装置の基板10はFPC(Flexible Printed Circuit)等の接続部を介して、タイミング制御回路(コントローラ、制御ICともいう)に接続されている。 The display device in FIG. 1A is an active matrix display device. The display device includes a pixel portion 11, a first scanning line driving circuit 12, a second scanning line driving circuit 13, and a signal line driving circuit 14 on a substrate 10. In the pixel portion 11, a plurality of signal lines are extended from the signal line driving circuit 14, and a plurality of scanning lines are extended from the first scanning line driving circuit 12 and the second scanning line driving circuit 13. Has been. Pixels each having a display element are provided in a matrix in the intersecting regions between the scanning lines and the signal lines. The substrate 10 of the display device is connected to a timing control circuit (also referred to as a controller or a control IC) via a connecting portion such as an FPC (Flexible Printed Circuit).
 図1(A)では、第1の走査線駆動回路12、第2の走査線駆動回路13、信号線駆動回路14は、画素部11と同じ基板10上に形成される。そのため、外部に設ける駆動回路等の部品の数が減るので、コストの低減を図ることができる。また、基板10外部に駆動回路を設けた場合、配線を延伸させる必要が生じ、配線間の接続数が増える。同じ基板10上に駆動回路を設けた場合、その配線間の接続数を減らすことができ、信頼性の向上、又は歩留まりの向上を図ることができる。 In FIG. 1A, the first scanning line driving circuit 12, the second scanning line driving circuit 13, and the signal line driving circuit 14 are formed on the same substrate 10 as the pixel portion 11. For this reason, the number of components such as a drive circuit provided outside is reduced, so that cost can be reduced. Further, when the drive circuit is provided outside the substrate 10, it is necessary to extend the wiring, and the number of connections between the wirings increases. In the case where a driver circuit is provided over the same substrate 10, the number of connections between the wirings can be reduced, and reliability or yield can be improved.
 画素部の回路構成の一例を図1(B)に示す。この例は、VA型液晶表示装置の画素部に適用することができる画素部の回路である。 An example of the circuit configuration of the pixel portion is shown in FIG. This example is a circuit of a pixel portion that can be applied to a pixel portion of a VA liquid crystal display device.
 この画素部の回路は、一つの画素に複数の画素電極を有する構成に適用できる。それぞれの画素電極は異なるトランジスタに接続され、各トランジスタは異なるゲート信号で駆動できるように構成されている。これにより、マルチドメイン設計された画素の個々の画素電極に印加する信号を、独立して制御できる。 This circuit of the pixel portion can be applied to a configuration having a plurality of pixel electrodes in one pixel. Each pixel electrode is connected to a different transistor, and each transistor is configured to be driven by a different gate signal. As a result, signals applied to the individual pixel electrodes of the multi-domain designed pixel can be controlled independently.
 トランジスタ24のゲート配線21と、トランジスタ25のゲート配線22には、異なるゲート信号を与えることができるように分離されている。一方、データ線として機能するソース電極又はドレイン電極23は、トランジスタ24とトランジスタ25で共通に用いられている。トランジスタ24とトランジスタ25は本発明のTFTを適宜用いることができる。これにより、信頼性の高い液晶表示装置を提供することができる。 The gate wiring 21 of the transistor 24 and the gate wiring 22 of the transistor 25 are separated so that different gate signals can be given. On the other hand, the source or drain electrode 23 functioning as a data line is used in common for the transistor 24 and the transistor 25. As the transistor 24 and the transistor 25, the TFT of the present invention can be used as appropriate. Thereby, a highly reliable liquid crystal display device can be provided.
 トランジスタ24には、第1の画素電極が電気的に接続され、トランジスタ25には、第2の画素電極が電気的に接続される。第1の画素電極と第2の画素電極とは分離されている。第1の画素電極と第2の画素電極の形状としては、特に限定はない。例えば、第1の画素電極は、V字状とすればよい。 The first pixel electrode is electrically connected to the transistor 24, and the second pixel electrode is electrically connected to the transistor 25. The first pixel electrode and the second pixel electrode are separated. The shape of the first pixel electrode and the second pixel electrode is not particularly limited. For example, the first pixel electrode may be V-shaped.
 トランジスタ24のゲート電極はゲート配線21と接続され、トランジスタ25のゲート電極はゲート配線22と接続されている。ゲート配線21とゲート配線22に異なるゲート信号を与えてトランジスタ24とトランジスタ25の動作タイミングを異ならせ、液晶の配向を制御できる。 The gate electrode of the transistor 24 is connected to the gate wiring 21, and the gate electrode of the transistor 25 is connected to the gate wiring 22. Different gate signals are given to the gate wiring 21 and the gate wiring 22 to change the operation timing of the transistors 24 and 25, thereby controlling the alignment of the liquid crystal.
 容量配線20と、誘電体として機能するゲート絶縁膜と、第1の画素電極又は第2の画素電極と電気的に接続する容量電極とで保持容量を形成してもよい。 A storage capacitor may be formed by the capacitor wiring 20, the gate insulating film functioning as a dielectric, and the capacitor electrode electrically connected to the first pixel electrode or the second pixel electrode.
 マルチドメイン構造は、一画素に第1の液晶素子26と第2の液晶素子27を備える。第1の液晶素子26は第1の画素電極と対向電極とその間の液晶層とで構成され、第2の液晶素子27は第2の画素電極と対向電極とその間の液晶層とで構成される。 The multi-domain structure includes a first liquid crystal element 26 and a second liquid crystal element 27 in one pixel. The first liquid crystal element 26 is composed of a first pixel electrode, a counter electrode, and a liquid crystal layer therebetween, and the second liquid crystal element 27 is composed of a second pixel electrode, a counter electrode, and a liquid crystal layer therebetween. .
 図1(B)に示す画素部の回路は、これに限定されない。例えば、図1(B)に示す画素に新たにスイッチ、抵抗素子、容量素子、トランジスタ、センサー、又は論理回路等を追加してもよい。 The circuit of the pixel portion shown in FIG. 1B is not limited to this. For example, a switch, a resistor, a capacitor, a transistor, a sensor, a logic circuit, or the like may be newly added to the pixel illustrated in FIG.
 画素の回路構成の他の一例を図1(C)に示す。この例は、有機EL素子を用いた表示装置の画素構造であり、nチャネル型のトランジスタを1つの画素に2つ用いる例を示す。本発明の酸化物半導体薄膜は、nチャネル型のトランジスタのチャネル形成領域に用いることができる。この画素部の回路は、デジタル時間階調駆動を適用することができる。 Another example of the circuit configuration of the pixel is shown in FIG. This example shows a pixel structure of a display device using an organic EL element, and shows an example in which two n-channel transistors are used for one pixel. The oxide semiconductor thin film of the present invention can be used for a channel formation region of an n-channel transistor. Digital time gray scale driving can be applied to the circuit of this pixel portion.
 スイッチング用トランジスタ31及び駆動用トランジスタ32は本発明のTFTを適宜用いることができる。これにより、信頼性の高い有機EL表示装置を提供することができる。 As the switching transistor 31 and the driving transistor 32, the TFT of the present invention can be used as appropriate. Thereby, an organic EL display device with high reliability can be provided.
 画素部の回路の構成は、図1(C)に示す画素構成に限定されない。例えば、図1(C)に示す画素部の回路にスイッチ、抵抗素子、容量素子、センサー、トランジスタ又は論理回路等を追加してもよい。 The circuit configuration of the pixel portion is not limited to the pixel configuration shown in FIG. For example, a switch, a resistor, a capacitor, a sensor, a transistor, a logic circuit, or the like may be added to the circuit of the pixel portion illustrated in FIG.
 本発明のTFTを含む固体撮像素子の動作について、以下に説明する。 The operation of the solid-state imaging device including the TFT of the present invention will be described below.
 CMOS(Complementary Metal Oxide Semiconductor)イメージセンサーは、信号電荷蓄積部に電位を保持し、その電位を増幅トランジスタを介して垂直出力線に出力する固体撮像素子である。CMOSイメージセンサーに含まれるリセットトランジスタ及び/又は転送トランジスタにリーク電流があると、そのリーク電流によって充電又は放電が起こり、信号電荷蓄積部の電位が変化する。信号電荷蓄積部の電位が変わると増幅トランジスタの電位も変わってしまい、本来の電位からずれた値となり、撮像された映像が劣化してしまう。 A CMOS (Complementary Metal Oxide Semiconductor) image sensor is a solid-state imaging device that holds a potential in a signal charge storage unit and outputs the potential to a vertical output line via an amplification transistor. If there is a leak current in the reset transistor and / or the transfer transistor included in the CMOS image sensor, charging or discharging occurs due to the leak current, and the potential of the signal charge storage portion changes. When the potential of the signal charge storage portion changes, the potential of the amplification transistor also changes, resulting in a value that deviates from the original potential, and the captured image deteriorates.
 本発明のTFTをCMOSイメージセンサーのリセットトランジスタ及び転送トランジスタに適用した場合の動作の効果を説明する。尚、増幅トランジスタは、薄膜トランジスタ又はバルクトランジスタのどちらを適用してもよい。 The effect of operation when the TFT of the present invention is applied to a reset transistor and a transfer transistor of a CMOS image sensor will be described. Note that the amplifying transistor may be either a thin film transistor or a bulk transistor.
 図2は、CMOSイメージセンサーの画素構成の一例を示す図である。画素は光電変換素子であるフォトダイオード40、転送トランジスタ41、リセットトランジスタ42、増幅トランジスタ43及び各種配線で構成されており、マトリクス状に複数が配置されてセンサーを構成している。また、増幅トランジスタ43と電気的に接続される選択トランジスタを設けてもよい。トランジスタ記号に記してある「OS」は酸化物半導体(Oxide Semiconductor)を示し、「Si」はシリコンを示しており、それぞれのトランジスタに適用すると好ましい材料を表している。 FIG. 2 is a diagram illustrating an example of a pixel configuration of a CMOS image sensor. The pixel includes a photodiode 40 which is a photoelectric conversion element, a transfer transistor 41, a reset transistor 42, an amplification transistor 43, and various wirings. A plurality of pixels are arranged in a matrix to form a sensor. A selection transistor electrically connected to the amplification transistor 43 may be provided. “OS” written in a transistor symbol represents an oxide semiconductor, and “Si” represents silicon, which represents a preferable material when applied to each transistor.
 フォトダイオード40は、転送トランジスタ41のソース側に接続されており、転送トランジスタ41のドレイン側には信号電荷蓄積部44(FD:フローティングディフュージョンともいう)が形成される。信号電荷蓄積部44にはリセットトランジスタ42のソース及び増幅トランジスタ43のゲートが接続されている。別の構成として、リセット電源線46を削除することもできる。例えば、リセットトランジスタ42のドレインをリセット電源線46ではなく、電源線45又は垂直出力線47につなぐ方法がある。 The photodiode 40 is connected to the source side of the transfer transistor 41, and a signal charge storage unit 44 (FD: also referred to as floating diffusion) is formed on the drain side of the transfer transistor 41. The signal charge storage unit 44 is connected to the source of the reset transistor 42 and the gate of the amplification transistor 43. As another configuration, the reset power supply line 46 may be deleted. For example, there is a method of connecting the drain of the reset transistor 42 to the power supply line 45 or the vertical output line 47 instead of the reset power supply line 46.
 以下、実施例を挙げて本発明をより具体的に説明するが、本発明は、下記実施例に限定されず、本発明の趣旨に適合し得る範囲で適切に変更を加えて実施することも可能であり、それらはいずれも本発明の技術的範囲に含まれる。 EXAMPLES Hereinafter, the present invention will be described more specifically with reference to examples. However, the present invention is not limited to the following examples, and may be implemented with appropriate modifications within a scope that can meet the gist of the present invention. These are all possible and are within the scope of the present invention.
[酸化物焼結体の製造]
実施例1~4
 下記表1に示す割合となるように酸化サマリウム粉末、酸化インジウム粉末、酸化アルミニウム粉末を秤量し、ポリエチレン製のポットに入れて、乾式ボールミルにより72時間混合粉砕し、混合粉末を作製した。
 この混合粉末を金型に入れ、500kg/cmの圧力でプレス成型体とした。この成型体を2000kg/cmの圧力でCIPにより緻密化を行った。次に、この成型体を常圧焼成炉に設置して、大気雰囲気下で、350℃で3時間保持した後に、50℃/時間にて昇温し、1350℃にて、40時間焼結し、その後、放置して冷却し、酸化物焼結体を得た。
[Production of sintered oxide]
Examples 1 to 4
Samarium oxide powder, indium oxide powder, and aluminum oxide powder were weighed so as to have the ratio shown in Table 1 below, placed in a polyethylene pot, and mixed and ground for 72 hours by a dry ball mill to prepare a mixed powder.
This mixed powder was put into a mold and formed into a press-molded body at a pressure of 500 kg / cm 2 . This molded body was densified by CIP at a pressure of 2000 kg / cm 2 . Next, this molded body was placed in a normal pressure firing furnace, held at 350 ° C. for 3 hours in an air atmosphere, then heated at 50 ° C./hour, and sintered at 1350 ° C. for 40 hours. Thereafter, the mixture was left to cool to obtain an oxide sintered body.
[酸化物焼結体の特性評価]
(1)XRDの測定
 得られた焼結体について、X線回折測定装置Smartlabにより、以下の条件で、焼結体のX線回折(XRD)を測定した。得られたXRDチャートを粉末X線回折パターン総合回析ソフトウェアJADE6(株式会社リガク)により分析し、焼結体中の結晶相を求めた。結果を表1に示す。
[Characteristic evaluation of oxide sintered body]
(1) Measurement of XRD About the obtained sintered compact, X-ray diffraction (XRD) of the sintered compact was measured with the X-ray-diffraction measuring apparatus Smartlab on the following conditions. The obtained XRD chart was analyzed by powder X-ray diffraction pattern comprehensive diffraction software JADE6 (Rigaku Corporation) to obtain the crystal phase in the sintered body. The results are shown in Table 1.
・装置:Smartlab(株式会社リガク製)
・X線:Cu-Kα線(波長1.5418Å)
・2θ-θ反射法、連続スキャン(2.0°/分)
・サンプリング間隔:0.02°
・スリットDS(発散スリット)、SS(散乱スリット)、RS(受光スリット):1mm
・ Apparatus: Smartlab (manufactured by Rigaku Corporation)
・ X-ray: Cu-Kα ray (wavelength 1.5418mm)
・ 2θ-θ reflection method, continuous scan (2.0 ° / min)
・ Sampling interval: 0.02 °
・ Slit DS (divergence slit), SS (scattering slit), RS (light receiving slit): 1 mm
 また、実施例1~4で得た焼結体のXRDチャートをそれぞれ図1~4に示す。
 図1~4から、各実施例で得た焼結体が表1に示したペロブスカイト相及びビックスバイト相を有することがわかった。
In addition, XRD charts of the sintered bodies obtained in Examples 1 to 4 are shown in FIGS. 1 to 4, respectively.
1 to 4, it was found that the sintered body obtained in each example had the perovskite phase and the bixbite phase shown in Table 1.
(2)Inの存在比率(wt%)
 得られた焼結体中のInの存在比率(wt%)は、通常の方法で求めた。即ち、X線回折のプロファイルから、JADE6により分析し、全パターンフィッティング(WPF)により焼結体の結晶構造を求めた。さらに、ピーク強度比から、Inの存在比として求めた。結果を表1に示す。
(2) In 2 O 3 abundance ratio (wt%)
The abundance ratio (wt%) of In 2 O 3 in the obtained sintered body was determined by a usual method. That is, from the X-ray diffraction profile, it was analyzed by JADE6, and the crystal structure of the sintered body was obtained by all pattern fitting (WPF). Further, the peak intensity ratio was determined as a presence ratio of In 2 O 3. The results are shown in Table 1.
(3)焼結密度(g/cm
 得られた焼結体の焼結密度(g/cm)を、アルキメデス法で測定した。結果を表1に示す。
(3) Sintered density (g / cm 3 )
The sintered density (g / cm 3 ) of the obtained sintered body was measured by the Archimedes method. The results are shown in Table 1.
(4)バルク抵抗(mΩ・cm)
 得られた焼結体のバルク抵抗(mΩ・cm)を、抵抗率計ロレスタAX MCP-T370(三菱化学株式会社製)を使用して、四探針法(JISR1637)に基づき測定した。結果を表1に示す。
(4) Bulk resistance (mΩ · cm)
The bulk resistance (mΩ · cm) of the obtained sintered body was measured based on the four-probe method (JISR1637) using a resistivity meter Loresta AX MCP-T370 (manufactured by Mitsubishi Chemical Corporation). The results are shown in Table 1.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
[スパッタリングターゲットの製造]
実施例5
 下記表2に示す割合となるように酸化サマリウム粉末、酸化インジウム粉末、酸化アルミニウム粉末を秤量し、ポリエチレン製のポットに入れて、乾式ボールミルにより72時間混合粉砕し、混合粉末を作製した。
 この混合粉末を金型に入れ、500kg/cmの圧力でプレス成型体とした。この成型体を2000kg/cmの圧力でCIPにより緻密化を行った。次に、この成型体を常圧焼成炉に設置して、大気雰囲気下で、350℃で10時間保持した後に、50℃/時間にて昇温し、1450℃にて、40時間焼結し、その後、放置して冷却し、酸化物焼結体を得た。実施例1~4と同様に焼結体の特性評価を行った。結果を表2に示す。
[Manufacture of sputtering target]
Example 5
Samarium oxide powder, indium oxide powder, and aluminum oxide powder were weighed so as to have the ratio shown in Table 2 below, placed in a polyethylene pot, and mixed and ground for 72 hours by a dry ball mill to prepare a mixed powder.
This mixed powder was put into a mold and formed into a press-molded body at a pressure of 500 kg / cm 2 . This molded body was densified by CIP at a pressure of 2000 kg / cm 2 . Next, this molded body was placed in a normal pressure firing furnace, held at 350 ° C. for 10 hours in an air atmosphere, then heated at 50 ° C./hour, and sintered at 1450 ° C. for 40 hours. Thereafter, the mixture was left to cool to obtain an oxide sintered body. The characteristics of the sintered body were evaluated in the same manner as in Examples 1 to 4. The results are shown in Table 2.
 得られた酸化物焼結体を研削研磨して、4インチφ×5mmtの酸化物焼結体の円板を製造した。この円板を、溶融させた金属インジウムを用いて、銅製の8mm厚みのバッキングプレートにボンディングした。 The obtained oxide sintered body was ground and polished to produce a 4 inch φ × 5 mmt oxide sintered body disc. This disk was bonded to a copper backing plate having a thickness of 8 mm using molten metal indium.
[スパッタリングターゲットの特性評価]
(1)ターゲットの反り(mm)
 得られたターゲットの反り(mm)を下記方法により測定した。結果を表2に示す。
 定盤上にターゲットを静置し、隙間ゲージにて隙間を計測し、反り量(mm)とした。
[Characteristic evaluation of sputtering target]
(1) Warpage of target (mm)
The warpage (mm) of the obtained target was measured by the following method. The results are shown in Table 2.
The target was allowed to stand on the surface plate, and the gap was measured with a gap gauge to obtain the amount of warpage (mm).
(2)ターゲットのボンディング率(%)
 得られたターゲットのボンディング率(%)を下記方法により測定した。結果を表2に示す。
 ボンディング率は、超音波探傷機によりボンディングされていないボイド部分を計測し、ターゲット面積基準にボンディングされている部分の比率を算出した。
(2) Target bonding rate (%)
The bonding rate (%) of the obtained target was measured by the following method. The results are shown in Table 2.
The bonding rate was determined by measuring the void part that was not bonded by an ultrasonic flaw detector and calculating the ratio of the bonded part based on the target area.
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
[酸化物半導体薄膜の製造]
実施例6
 実施例5で得られたスパッタリングターゲットを用いて、熱酸化膜付きシリコン基板上にチャネル形状のメタルマスクを用い、酸化物半導体層(チャネル層)をスパッタリングにより成膜した。スパッタリング条件は、スパッタ圧=0.5Pa、酸素分圧=5%、基板温度=室温で行い、膜厚は50nmに設定した。次に、ソース・ドレイン形状のメタルマスクを用い、チタン電極を50nm成膜した。最後に、空気中300℃、1時間の条件でアニールすることで、チャネル長200μm、チャネル幅1000μmのボトムゲート、トップコンタクトの簡易型TFTを得た。アニール条件としては、250℃~450℃、0.5時間~10時間の範囲でチャネル部のキャリヤー濃度を見ながら適宜選択した。
 得られたTFTの特性を評価した結果、移動度=14cm/V・sec、電流値が10-8Aを超えるゲート電圧の値Vth>0.45V、S値(Swing Factor)=0.72であった。
[Manufacture of oxide semiconductor thin films]
Example 6
Using the sputtering target obtained in Example 5, an oxide semiconductor layer (channel layer) was formed by sputtering on a silicon substrate with a thermal oxide film using a channel-shaped metal mask. The sputtering conditions were as follows: sputtering pressure = 0.5 Pa, oxygen partial pressure = 5%, substrate temperature = room temperature, and the film thickness was set to 50 nm. Next, a titanium electrode was formed to a thickness of 50 nm using a source / drain shaped metal mask. Finally, annealing was performed in air at 300 ° C. for 1 hour to obtain a simple TFT having a bottom gate and top contact with a channel length of 200 μm and a channel width of 1000 μm. The annealing conditions were appropriately selected while observing the carrier concentration in the channel portion in the range of 250 to 450 ° C. and 0.5 to 10 hours.
As a result of evaluating the characteristics of the obtained TFT, mobility = 14 cm 2 / V · sec, gate voltage value Vth> 0.45 V, current value exceeding 10 −8 A, S value (Swing Factor) = 0.72. Met.
 このTFT素子を、CVD装置に装着し、350℃にて、パッシベーション膜としてSiOを100nmの厚みに成膜し、その後、300℃、大気中で1時間アニールした後のTFT特性を評価した。結果、移動度=12cm/V・sec、電流値が10-8Aを超えるゲート電圧の値Vth>0.32V、S値(Swing Factor)=0.78となり、ほぼ、CVD前の特性を再現することができた。
 また、オフ電流は、10-12A以下であった。これらの結果から、ディスプレイの表示装置のトランジスタ、又は、CMOSイメージセンサーのキャンセルトランジスタや転送トランジスタにも使用可能である。
The TFT element was mounted on a CVD apparatus, and a SiO 2 film having a thickness of 100 nm was formed as a passivation film at 350 ° C., and then TFT characteristics after annealing in the atmosphere at 300 ° C. for 1 hour were evaluated. As a result, the mobility was 12 cm 2 / V · sec, the gate voltage value Vth> 0.32 V exceeding 10 −8 A, and the S value (Swing Factor) = 0.78. I was able to reproduce it.
The off current was 10 −12 A or less. From these results, it can be used for a transistor of a display device of a display or a cancel transistor or a transfer transistor of a CMOS image sensor.
実施例7~9
 下記表3に示す割合となるように酸化ネオジム粉末、酸化インジウム粉末、酸化アルミニウム粉末を秤量し、ポリエチレン製のポットに入れて、乾式ボールミルにより72時間混合粉砕し、混合粉末を作製した。
 この混合粉末を金型に入れ、500kg/cmの圧力でプレス成型体とした。この成型体を2000kg/cmの圧力でCIPにより緻密化を行った。次に、この成型体を常圧焼成炉に設置して、大気雰囲気下で、350℃で3時間保持した後に、50℃/時間にて昇温し、1350℃にて、40時間焼結し、その後、放置して冷却し、酸化物焼結体を得た。
Examples 7-9
Neodymium oxide powder, indium oxide powder, and aluminum oxide powder were weighed so as to have the ratio shown in Table 3 below, placed in a polyethylene pot, and mixed and ground for 72 hours by a dry ball mill to prepare a mixed powder.
This mixed powder was put into a mold and formed into a press-molded body at a pressure of 500 kg / cm 2 . This molded body was densified by CIP at a pressure of 2000 kg / cm 2 . Next, this molded body was placed in a normal pressure firing furnace, held at 350 ° C. for 3 hours in an air atmosphere, then heated at 50 ° C./hour, and sintered at 1350 ° C. for 40 hours. Thereafter, the mixture was left to cool to obtain an oxide sintered body.
 得られた酸化物焼結体について、実施例1~4と同様に酸化物焼結体の特性を評価した。結果を表3に示す。 For the obtained oxide sintered body, the characteristics of the oxide sintered body were evaluated in the same manner as in Examples 1 to 4. The results are shown in Table 3.
Figure JPOXMLDOC01-appb-T000003
Figure JPOXMLDOC01-appb-T000003
 [スパッタリングターゲットの製造]
実施例10~12
 下記表4に示す割合となるように酸化サマリウム粉末、酸化インジウム粉末、酸化アルミニウム粉末を秤量し、ポリエチレン製のポットに入れて、乾式ボールミルにより72時間混合粉砕し、混合粉末を作製した。
 この混合粉末を金型に入れて、500kg/cmの圧力でプレス成型体とした。この成型体を1000kg/cmの圧力でCIPにより緻密化を行った。次に、この成型体を常圧焼結炉に設置して、大気雰囲気下で、350℃で3時間放置した後に、50℃/時間にて昇温し、1420℃にて、28時間焼結し、その後、放置して冷却し、酸化物焼結体を得た。
 得られた酸化物焼結体について、実施例1~4と同様に酸化物焼結体の特性を評価した。結果を表4に示す。
 また、実施例10~12で得た焼結体のXRDチャートをそれぞれ図9~11に示す。
 図9~11から、各実施例で得た焼結体が表4に示したペロブスカイト相及びビックスバイト相を有することがわかった。
[Manufacture of sputtering target]
Examples 10-12
Samarium oxide powder, indium oxide powder, and aluminum oxide powder were weighed so as to have the ratio shown in Table 4 below, placed in a polyethylene pot, and mixed and ground for 72 hours by a dry ball mill to prepare a mixed powder.
This mixed powder was put into a mold and formed into a press-molded body at a pressure of 500 kg / cm 2 . This molded body was densified by CIP at a pressure of 1000 kg / cm 2 . Next, this molded body was placed in a normal pressure sintering furnace, left in an air atmosphere at 350 ° C. for 3 hours, heated at 50 ° C./hour, and sintered at 1420 ° C. for 28 hours. After that, it was left to cool to obtain an oxide sintered body.
With respect to the obtained oxide sintered body, the characteristics of the oxide sintered body were evaluated in the same manner as in Examples 1 to 4. The results are shown in Table 4.
Further, XRD charts of the sintered bodies obtained in Examples 10 to 12 are shown in FIGS. 9 to 11, respectively.
9 to 11, it was found that the sintered bodies obtained in the respective examples had the perovskite phase and the bixbite phase shown in Table 4.
 得られた酸化物焼結体を研削研磨して、4インチφ×5mmtの酸化物焼結体の円板を製造した。この円板を、溶融させた金属インジウムを用いて、銅製の8mmt厚みのバッキングプレートにボンディングした。 The obtained oxide sintered body was ground and polished to produce a 4 inch φ × 5 mmt oxide sintered body disc. This disk was bonded to a copper backing plate having a thickness of 8 mm using a molten metal indium.
[スパッタリングターゲットの評価]
(1)ターゲットの反り(mm)
 得られたターゲットの反り(mm)は、下記方法により測定した。結果を表4に示す。
 定盤上にターゲットを静置し、隙間ゲージにて隙間を計測し、反り量(mm)とした。
(2)ターゲットのボンディング率(%)
 得られたターゲットのボンディング率(%)を下記方法により測定した。結果を表4に示す。
 ボンディング率は、超音波探傷機によりボンディングされていない部分を計測し、ターゲット面積基準にボンディングされている部分の比率を算出した。
[Evaluation of sputtering target]
(1) Warpage of target (mm)
The warpage (mm) of the obtained target was measured by the following method. The results are shown in Table 4.
The target was allowed to stand on the surface plate, and the gap was measured with a gap gauge to obtain the amount of warpage (mm).
(2) Target bonding rate (%)
The bonding rate (%) of the obtained target was measured by the following method. The results are shown in Table 4.
The bonding rate was determined by measuring the portion that was not bonded by the ultrasonic flaw detector and calculating the ratio of the portion bonded based on the target area.
Figure JPOXMLDOC01-appb-T000004
Figure JPOXMLDOC01-appb-T000004
[酸化物半導体薄膜の製造]
実施例13
 実施例11で得られたスパッタリングターゲットを用いて、熱酸化膜付きシリコン基板上にチャネル形状のメタルマスクを用い、酸化物半導体層(チャネル層)をスパッタリングにより成膜した。スパッタリング条件は、スパッタ圧=0.5Pa、酸素分圧=1%、基板温度=室温で行い、膜厚は50nmに設定した。次に、ソース・ドレイン形状のメタルマスクを用い、チタン電極を50nm成膜した。最後に、空気中350℃、1時間の条件でアニールすることで、チャネル長200μm、チャネル幅2000μmのボトムゲート、トップコンタクトの簡易型TFTを得た。アニール条件としては、250℃~450℃、0.5時間~10時間の範囲でチャネル部のキャリヤー濃度を見ながら適宜選択した。350℃で1時間熱処理した薄膜のXRDを測定した結果、Inで表されるビックスバイト構造のチャートが得られ、結晶化していることが確認された。
[Manufacture of oxide semiconductor thin films]
Example 13
Using the sputtering target obtained in Example 11, an oxide semiconductor layer (channel layer) was formed by sputtering on a silicon substrate with a thermal oxide film using a channel-shaped metal mask. The sputtering conditions were as follows: sputtering pressure = 0.5 Pa, oxygen partial pressure = 1%, substrate temperature = room temperature, and the film thickness was set to 50 nm. Next, a titanium electrode was formed to a thickness of 50 nm using a source / drain shaped metal mask. Finally, annealing was performed in air at 350 ° C. for 1 hour to obtain a simple TFT having a bottom gate and top contact with a channel length of 200 μm and a channel width of 2000 μm. The annealing conditions were appropriately selected while observing the carrier concentration in the channel portion in the range of 250 to 450 ° C. and 0.5 to 10 hours. As a result of measuring the XRD of the thin film heat-treated at 350 ° C. for 1 hour, a bixbite structure chart represented by In 2 O 3 was obtained and confirmed to be crystallized.
 得られたTFTの特性を評価した結果、移動度=17cm/V・sec、電流値が10-8Aを超えるゲート電圧の値Vth>0.15V、S値(Swing Factor)=0.22であった。 As a result of evaluating the characteristics of the obtained TFT, the mobility was 17 cm 2 / V · sec, the gate voltage value Vth> 0.15 V, where the current value exceeded 10 −8 A, and the S value (Swing Factor) = 0.22. Met.
 このTFT素子を、CVD装置に装着し、300℃にて、パッシベーション膜としてSiOを100nmの厚みに成膜し、その後、350℃、大気中で1時間アニールした後のTFT特性を評価した。結果、移動度=21cm/V・sec、電流値が10-8Aを超えるゲート電圧の値Vth>0.24V、S値(Swing Factor)=0.26となり、ほぼ、CVD前の特性を再現することができた。また、オフ電流は、10-12A以下であった。これらの結果から、ディスプレイの表示装置のトランジスタ、又は、CMOSイメージセンサーのキャンセルトランジスタや転送トランジスタにも使用可能である。 This TFT element was mounted on a CVD apparatus, and a SiO 2 film having a thickness of 100 nm was formed as a passivation film at 300 ° C., and then TFT characteristics were evaluated after annealing at 350 ° C. in the air for 1 hour. As a result, the mobility was 21 cm 2 / V · sec, the gate voltage value Vth> 0.24 V, the current value exceeding 10 −8 A, and the S value (Swing Factor) = 0.26. I was able to reproduce it. The off current was 10 −12 A or less. From these results, it can be used for a transistor of a display device of a display or a cancel transistor or a transfer transistor of a CMOS image sensor.
 本発明の酸化物焼結体はスパッタリングターゲットに利用でき、液晶ディスプレイや有機ELディスプレイ等の表示装置等に用いられる薄膜トランジスタ(TFT)の酸化物半導体薄膜等の製造に有用である。 The oxide sintered body of the present invention can be used as a sputtering target, and is useful for producing an oxide semiconductor thin film of a thin film transistor (TFT) used for a display device such as a liquid crystal display or an organic EL display.
 上記に本発明の実施形態及び/又は実施例を幾つか詳細に説明したが、当業者は、本発明の新規な教示及び効果から実質的に離れることなく、これら例示である実施形態及び/又は実施例に多くの変更を加えることが容易である。従って、これらの多くの変更は本発明の範囲に含まれる。
 本願のパリ優先の基礎となる日本出願明細書の内容を全てここに援用する。
Although several embodiments and / or examples of the present invention have been described in detail above, those skilled in the art will appreciate that these exemplary embodiments and / or embodiments are substantially without departing from the novel teachings and advantages of the present invention. It is easy to make many changes to the embodiment. Accordingly, many of these modifications are within the scope of the present invention.
All the contents of the Japanese application specification that is the basis of the priority of Paris in this application are incorporated herein.

Claims (11)

  1.  ペロブスカイト相及びInで表されるビックスバイト相を含む酸化物焼結体。 An oxide sintered body containing a perovskite phase and a bixbite phase represented by In 2 O 3 .
  2.  前記ペロブスカイト相が、下記一般式(I)で表される化合物である、請求項1に記載の酸化物焼結体。
      LnAlO     (I)
    (式中、Lnは、La、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb及びLuから選ばれた一種以上の金属元素を表す。)
    The oxide sintered body according to claim 1, wherein the perovskite phase is a compound represented by the following general formula (I).
    LnAlO 3 (I)
    (In the formula, Ln represents one or more metal elements selected from La, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.)
  3.  前記Lnが、Sm及びNdのいずれか一方又は両方である、請求項1又は2のいずれかに記載の酸化物焼結体。 The oxide sintered body according to any one of claims 1 and 2, wherein the Ln is one or both of Sm and Nd.
  4.  前記酸化物焼結体中のIn、Al及びLnの原子比が、下記の範囲である請求項2又は3に記載の酸化物焼結体。
        In/(In+Al+Ln)が0.64以上0.98以下
        Al/(In+Al+Ln)が0.01以上0.18以下
        Ln/(In+Al+Ln)が0.01以上0.18以下
    The oxide sintered body according to claim 2 or 3, wherein an atomic ratio of In, Al, and Ln in the oxide sintered body is in the following range.
    In / (In + Al + Ln) is 0.64 or more and 0.98 or less Al / (In + Al + Ln) is 0.01 or more and 0.18 or less Ln / (In + Al + Ln) is 0.01 or more and 0.18 or less
  5.  請求項1~4のいずれかに記載の酸化物焼結体を用いて作製されたスパッタリングターゲット。 A sputtering target produced using the oxide sintered body according to any one of claims 1 to 4.
  6.  請求項5に記載のスパッタリングターゲットを用いて製膜することを特徴とする酸化物半導体薄膜の製造方法。 A method for producing an oxide semiconductor thin film, wherein the film is formed using the sputtering target according to claim 5.
  7.  請求項5に記載のスパッタリングターゲットを用いて酸化物半導体薄膜を製膜する工程を含むことを特徴とする薄膜トランジスタの製造方法。 A method for producing a thin film transistor, comprising a step of forming an oxide semiconductor thin film using the sputtering target according to claim 5.
  8.  請求項5に記載のスパッタリングターゲットを用いて酸化物半導体薄膜を製膜する工程、
     前記酸化物半導体薄膜を含む薄膜トランジスタを製造する工程、及び
     前記薄膜トランジスタを電子機器に搭載する工程
    を含むことを特徴とする電子機器の製造方法。
    Forming an oxide semiconductor thin film using the sputtering target according to claim 5;
    The manufacturing method of the electronic device characterized by including the process of manufacturing the thin-film transistor containing the said oxide semiconductor thin film, and the process of mounting the said thin-film transistor in an electronic device.
  9.  In、Al及びLnを含み、
     前記Lnは、La、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb及びLuから選ばれた一種以上の金属元素であり、
     前記In、前記Al及び前記Lnの原子比が、下記の範囲である、酸化物半導体薄膜。
        In/(In+Al+Ln)が0.64以上0.98以下
        Al/(In+Al+Ln)が0.01以上0.18以下
        Ln/(In+Al+Ln)が0.01以上0.18以下
    Including In, Al and Ln,
    Ln is one or more metal elements selected from La, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu;
    The oxide semiconductor thin film whose atomic ratio of said In, said Al, and said Ln is the following range.
    In / (In + Al + Ln) is 0.64 or more and 0.98 or less Al / (In + Al + Ln) is 0.01 or more and 0.18 or less Ln / (In + Al + Ln) is 0.01 or more and 0.18 or less
  10.  請求項9に記載の酸化物半導体薄膜を含む薄膜トランジスタ。 A thin film transistor comprising the oxide semiconductor thin film according to claim 9.
  11.  請求項10に記載の薄膜トランジスタを含む電子機器。 An electronic device comprising the thin film transistor according to claim 10.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0967194A (en) * 1995-01-19 1997-03-11 Ube Ind Ltd Ceramic composite material
JP2008007340A (en) * 2006-06-27 2008-01-17 Fujifilm Corp Garnet type compound and method of manufacturing the same
WO2012043570A1 (en) * 2010-09-29 2012-04-05 東ソー株式会社 Sintered oxide material, method for manufacturing same, sputtering target, oxide transparent electrically conductive film, method for manufacturing same, and solar cell
WO2015098060A1 (en) * 2013-12-27 2015-07-02 出光興産株式会社 Oxide sintered body, method for producing same and sputtering target

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Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0967194A (en) * 1995-01-19 1997-03-11 Ube Ind Ltd Ceramic composite material
JP2008007340A (en) * 2006-06-27 2008-01-17 Fujifilm Corp Garnet type compound and method of manufacturing the same
WO2012043570A1 (en) * 2010-09-29 2012-04-05 東ソー株式会社 Sintered oxide material, method for manufacturing same, sputtering target, oxide transparent electrically conductive film, method for manufacturing same, and solar cell
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