本發明之一實施形態之氧化物燒結體(以下，稱為本發明之燒結體)之特徵在於，包含鈣鈦礦相及由In2
O3
表示之方鐵錳礦相。 本發明之燒結體中之鈣鈦礦相及由In2
O3
表示之方鐵錳礦相例如可藉由X射線繞射(XRD，X ray diffraction)法而自XRD(X ray diffraction，X射線繞射測定)圖檢測出。 本發明之燒結體中之上述鈣鈦礦相較佳為由下述通式(I)表示之化合物。 LnAlO3
(I) (式中，Ln表示選自La、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb及Lu中之一種以上之金屬元素)。 Ln特佳為Sm及Nd之任一者或兩者。 由上述通式(I)表示之化合物具有鈣鈦礦型構造，藉由包含此構造而可成為高密度之燒結體。 由通式(I)表示之鈣鈦礦化合物可為單晶構造亦可為多晶構造。 本發明之燒結體藉由包含由上述通式(I)表示之鈣鈦礦相、及由In2
O3
表示之方鐵錳礦相而可使燒結密度(相對密度)及體積電阻率(體電阻)提高。又，可減小膨脹係數，增大導熱率。又，即便在以使用氛圍焙燒爐於氧氣氛圍下之特殊之條件下、或大氣下等進行之簡便方法焙燒之情形時，亦可形成體積電阻率亦較低且燒結密度亦較高之燒結體。具有上述特性之本發明之燒結體作為靶材較佳。 藉由將本發明之燒結體用作靶材而可抑制應力之產生，提高靶之強度或導熱率，抑制線膨脹係數，抑制靶之微裂痕或崩裂之產生，從而抑制結核或異常放電之產生，可獲得能夠利用大功率進行濺鍍之濺鍍靶。 此外，藉由將本發明之燒結體用作靶材而可獲得高遷移率且由化學氣相沈積(CVD，chemical vapor deposition)等所致之半導體特性之劣化較小的高性能之TFT。 本發明之一實施形態之濺鍍靶(以下，稱為本發明之靶)之特徵在於，使用上述本發明之燒結體製作而成。 本發明之靶係將上述本發明之燒結體研削加工而製成靶材，且將其以金屬銦等貼合於銅板等金屬支架(以下，亦稱為背板或靶支持體)而製造成。 本發明之氧化物燒結體及本發明之靶之製造方法將於以下敍述。 用於本發明之靶之燒結體中之In、Al及Ln之原子比較佳為下述範圍： In/(In＋Al＋Ln)為0.64以上且0.98以下； Al/(In＋Al＋Ln)為0.01以上且0.18以下； Ln/(In＋Al＋Ln)為0.01以上且0.18以下， 更佳為下述範圍： In/(In＋Al＋Ln)為0.70以上且0.96以下； Al/(In＋Al＋Ln)為0.02以上且0.15以下； Ln/(In＋Al＋Ln)為0.02以上且0.15以下。 於In/(In＋Al＋Ln)未達0.64之情形時，有包含所形成之氧化物半導體薄膜之TFT之遷移率變小之虞。於In/(In＋Al＋Ln)超過0.98之情形時，有無法獲得TFT之穩定性之虞，或導電化而難以成為半導體之虞。 於Al/(In＋Al＋Ln)未達0.01之情形時，並未形成由通式(I)表示之鈣鈦礦相，有無法獲得TFT之穩定性之虞，或導電化而難以成為半導體之虞，或有無法進行穩定之濺鍍之虞。另一方面，於Al/(In＋Al＋Ln)超過0.18之情形時，有包含形成之氧化物半導體薄膜之TFT之遷移率變小之虞。 於Ln/(In＋Al＋Ln)未達0.01之情形時，並未形成由通式(I)表示之鈣鈦礦相，有無法獲得TFT之穩定性之虞，或導電化而難以成為半導體之虞，或有無法進行穩定之濺鍍之虞。另一方面，於Ln/(In＋Al＋Ln)超過0.18之情形，有包含所形成之氧化物半導體薄膜之TFT之遷移率變小之虞。 本發明之燒結體進而亦可包含正四價之金屬元素。 藉此，可更穩定地進行濺鍍。 作為正四價之金屬元素，可舉出Sn、Ti、Zr、Hf、Ce、Ge等。本發明之燒結體可包含該等中之一種或二種以上。 較佳為Sn。藉由Sn之摻雜效果而可使體電阻降低，可更穩定地進行濺鍍。 正四價之金屬元素較佳為固溶於由In2
O3
表示之方鐵錳礦相或由通式(I)表示之鈣鈦礦相，更佳為固溶於由In2
O3
表示之方鐵錳礦相。固溶較佳為置換型固溶。 藉此，可更穩定地進行濺鍍。 又，Ln及Al亦可固溶於由In2
O3
表示之方鐵錳礦相。 關於正四價之金屬元素、Ln及Al之固溶，例如可根據XRD測定之晶格常數而鑑定。 正四價之金屬元素之含量相對於本發明之氧化物燒結體中之全部金屬元素，以原子濃度計較佳為100 ppm以上且10000 ppm以下，更佳為500 ppm以上且8000 ppm以下，進而佳為800 ppm以上且6000 ppm以下。 於未達100 ppm之情形時，有體電阻上升之虞。另一方面，於超過10000 ppm之情形時，有包含所形成之氧化物半導體薄膜之TFT導通之虞、或導通/斷開值變小之虞。 本發明之燒結體中之由In2
O3
表示之方鐵錳礦相之存在比率較佳為1～99 wt%，更佳為10～98 wt%。若由In2
O3
表示之方鐵錳礦相之存在比率為上述範圍，則鈣鈦礦相分散於In2
O3
結晶中，藉由摻雜稀土類元素等而亦可考慮應用於除靶素材以外之螢光材料等。 由In2
O3
表示之方鐵錳礦相之存在比率可藉由實施例中記載之方法而測定。 於本發明之燒結體中，較佳為由In2
O3
表示之方鐵錳礦相為主成分。若方鐵錳礦構造以外之結晶構造作為主成分而析出，則有導致遷移率降低之虞。所謂「由In2
O3
表示之方鐵錳礦相為主成分」係指由In2
O3
表示之方鐵錳礦相之存在比率超過50 wt%，較佳為70 wt%以上，更佳為80 wt%以上，進而佳為85 wt%以上。 於本發明之燒結體中，較佳為燒結密度為6.5～7.1 g/cm3
之範圍內，更佳為6.6～7.1 g/cm3
之範圍內。若燒結密度為6.5～7.1 g/cm3
之範圍內，則在用作靶時，可使成為異常放電之原因或結核產生之起點之空隙減少。 燒結密度例如可由阿基米德法測定。 於本發明之燒結體中，體電阻較佳為50 mΩ∙cm以下，更佳為30 mΩ∙cm以下，進而佳為20 mΩ∙cm以下。下限值並無特別限制，但通常為1 mΩ∙cm以上或5 mΩ∙cm以上。 於體電阻為50 mΩ∙cm以下之情形時，於以大功率進行DC濺鍍成膜時，難以產生由靶之帶電引起之異常放電，又，電漿狀態穩定，難以產生火花。又，於使用脈衝DC濺鍍裝置或RF濺鍍裝置、RF＋DC濺鍍裝置之情形時，電漿更加穩定，亦無異常放電等問題，可穩定地進行濺鍍。 體電阻例如可基於四探針法而測定。具體而言，可使用公知之電阻率計並基於四探針法(JIS R 1637)而測定。測定部位為5部位左右，且較佳為將平均值設為體電阻值。 於氧化物燒結體之平面形狀為四邊形之情形時，測定部位較佳為中心、及四角與中心之中間點之4點的共計5部位。 再者，於氧化物燒結體之平面形狀為圓形之情形時，較佳為內切於圓之正方形之中心、及正方形之四角與中心之中間點之4點的共計5部位。 於本發明之燒結體中，3點彎曲強度較佳為120 MPa以上，更佳為140 MPa以上，進而佳為150 MPa以上。 於3點彎曲強度未達120 MPa之情形時，於以大功率濺鍍成膜時，有如下之虞，即，靶之強度較弱，靶破裂，或產生崩裂，所崩裂之破片飛散至靶上而成為異常放電之原因。 3點彎曲強度例如可以JIS R 1601「精細陶瓷之室溫彎曲強度試驗」為標準進行試驗。 具體而言，可使用寬度4 mm、厚度3 mm、長度40 mm之標準試驗片，將試驗片置於配置於固定距離(30 mm)之2支點上，自支點間之中央施加十字頭速度0.5 mm/分鐘之荷重，自試驗片破壞時之最大荷重算出彎曲強度。 於本發明之燒結體中，線膨脹係數較佳為8.0×10-6
K-1
以下，更佳為7.5×10-6
K-1
以下，進而佳為7.0×10-6
K-1
以下。下限值並無特別限制，但通常為5.0×10-6
K-1
以上。 於線膨脹係數超過8.0×10-6
K-1
之情形時，於以大功率濺鍍中被加熱，靶膨脹，於與接合之銅板之間產生變形，從而有因應力而於靶產生微裂痕，或因破裂或崩裂而成為異常放電之原因之虞。 線膨脹係數例如可藉由如下方法而求出，即，使用寬度5 mm、厚度5 mm、長度10 mm之標準試驗片，將升溫速度設置為5℃/分鐘，利用位置檢測機檢測由溫度到達300℃時之熱膨脹所引起之移位。 於本發明之燒結體中，熱導率較佳為5.0 W/m∙K以上，更佳為5.5 W/m∙K以上，進而佳為6.0 W/m∙K以上，最佳為6.5 W/m∙K以上。 上限值並無特別限制，但通常為10 W/m∙K以下。 於熱導率未達5.0 W/m∙K之情形時，於以大功率進行濺鍍成膜時，濺鍍面與被接合之面之溫度不同，有因內部應力而於靶產生微裂痕或破裂、崩裂之虞。 熱導率例如可藉由如下方法而算出，即，使用直徑10 mm、厚度1 mm之標準試驗片，藉由雷射閃光法求出比熱容與熱擴散率，並將其乘以試驗片之密度。 本發明之燒結體之金屬元素本質上包含In、Al、Ln、及任意正四價之金屬元素，於不損及本發明之效果之範圍，亦可另外包含不可避免之雜質。 本發明之燒結體之金屬元素之例如90原子%以上、95原子%以上、98原子%以上、99原子%以上或100原子%亦可包含In、Al及Ln、或In、Al、Ln及正四價之金屬元素。 本發明之燒結體可藉由如下步驟而製造，即：製備包含In之原料粉末、包含Al之原料粉末、及包含Ln之原料粉末之混合粉末；成形混合粉末而製造成形體；及焙燒成形體。 混合粉末亦可包含含有正四價之金屬元素之原料粉末。 原料粉末較佳為氧化物粉末。 使原料粉末之混合比例如對應於欲獲得之燒結體之原子比。 原料粉末之平均粒徑較佳為0.1～1.2 μm，更佳為0.5～1.0 μm以下。原料粉末之平均粒徑可由雷射繞射式粒度分佈裝置等測定。 原料之混合、成形方法並未特別限定，可採用公知之方法進行。又，於混合時亦可添加黏合劑。 原料之混合例如可使用球磨機、珠磨機、噴射磨機或超音波裝置等公知之裝置而進行。混合時間只要適當調整即可，但較佳為6～100小時左右。 成形方法例如可將混合粉末加壓成形而製成成形體。藉由該步驟而可成形為製品之形狀(例如作為濺鍍靶而較佳之形狀)。 可將混合粉末原料填充至成形模具中，通常藉由模具壓製或冷均壓(CIP，cold isostatic pressing)而以例如1000 kg/cm2
以上之壓力實施成形獲得成形體。 再者，於成形處理時，亦可使用聚乙烯醇或聚乙二醇、甲基纖維素、聚乙烯蠟、油酸、硬脂酸等成形助劑。 可將所獲得之成形體例如以1200～1650℃之燒結溫度燒結10小時以上而獲得燒結體。 燒結溫度較佳為1350～1600℃，更佳為1400～1600℃，進而佳為1450～1600℃。燒結時間較佳為10～50小時，更佳為12～40小時，進而佳為13～30小時。 若燒結溫度未達1200℃或燒結時間未達10小時，則並未充分地進行燒結，故靶之電阻並未充分地降低，從而有成為異常放電之原因之虞。另一方面，若焙燒溫度超過1650℃、或焙燒時間超過50小時，則因顯著之晶粒成長而引起平均結晶粒徑之增大、或粗大空孔之產生，從而有成為燒結體強度之降低或異常放電之原因之虞。 於常壓燒結法中，通常將成形體於大氣氛圍或氧氣氛圍中燒結。氧氣氛圍較佳為氧濃度例如為10～50體積%之氛圍。藉由於大氣氛圍下進行升溫過程而可提高燒結體密度。 進而，燒結時之升溫速度較佳為自800℃至燒結溫度(1200～1650℃)為止設為50～150℃/小時。 於本發明之燒結體中，自800℃起向上之溫度範圍為最旺盛進行燒結之範圍。若於該溫度範圍之升溫速度慢於50℃/小時，則晶粒成長變得顯著，有無法達成高密度化之虞。另一方面，若升溫速度快於150℃/小時，則於成形體中產生溫度分佈，有燒結體翹曲或破裂之虞。 自800℃起燒結溫度之升溫速度較佳為60～140℃/小時，更佳為70～130℃/小時。 本發明之濺鍍靶可使用上述本發明之燒結體製作而成。藉此，可利用濺鍍法等真空製程製造氧化物半導體薄膜。 濺鍍靶例如可藉由將燒結體切削或研磨加工並接合於背板而製作。 例如，可藉由切削加工而去除燒結體表面之高氧化狀態之燒結部、或凸凹之面。又，可設為指定之大小。 亦可對表面進行#200號、或#400號、進而#800號之研磨。藉此，可抑制濺鍍中之異常放電或微粒之產生。 保持濺鍍時之冷卻效率，而且接合率較佳為90%以上，更佳為95%以上，進而佳為99%以上。此處所謂接合率表示靶材與靶支持體材經由接合層而接合之面之面積相對於靶材與靶支持體相互重疊之面之面積的比例。接合率通常可藉由超音波探傷裝置等而測定。 對靶材與靶支持體之接合方法進行說明。 對已加工成特定形狀之靶材之與靶支持體之接合面進行表面處理。表面處理中所使用之裝置一般可使用市售之噴擊裝置。例如可舉出不二製作所製造之商品名「PNEUMA BLASTER，SGF-5-B」。作為用於噴擊法之粉末，可使用玻璃、氧化鋁、氧化鋯、SiC等，該等可配合靶材之組成、硬度等而適當選擇。 視需要將所獲得之表面處理完畢的靶材表面洗淨之後，於接合面塗佈金屬銦焊料等接合材料。於同樣視需要實施洗淨處理後之背板之接合面塗佈金屬銦焊料等接合材料。此時，於靶材由不直接熔接於接合材料之材料而構成之情形時，預先藉由濺鍍法、鍍覆法等而於靶材之接合面形成與接合材料之濡濕性優異之銅、鎳等之薄膜層之後，加熱至使用該靶材之接合材料之熔點以上且塗佈接合材料，或亦可使用超音波將接合材料直接塗佈於靶材之接合面。 其次，可將塗佈有接合材料之靶支持體加熱至所使用之接合材料之熔點以上而使表面之接合材料層熔解之後，將上述粉末配置於其表面，將靶材與背板接合之後冷卻至室溫而獲得靶。 本發明之濺鍍靶可應用於直流電(DC，direct current)濺鍍法、高頻(RF，radio frequency射頻)濺鍍法、交流電(AC，aternating current)濺鍍法、脈衝DC濺鍍法等。 藉由使用上述本發明之濺鍍靶進行製膜而可獲得氧化物半導體薄膜。藉此，可形成用於TFT時發揮優異之TFT性能之薄膜。 製膜可藉由蒸鍍法、濺鍍法、離子鍍覆法、脈衝雷射蒸鍍法等進行。 濺鍍於導入有O2
、H2
O等含有氧原子之氣體(氧化性氣體)之氧化性氬氣氛圍下進行即可。藉由於氧化性氣體氛圍下進行濺鍍而可抑制成為所獲得之半導體特性及光穩定性所需要之透光性之阻礙因素之雜質的產生。 上述氧化性氣體之濃度根據所需之膜之半導體特性、尤其載子濃度而適當調整即可。該調整例如亦可藉由基板溫度、濺鍍壓力等進行。 作為濺鍍氣體，自容易控制氣體之組成之觀點而言，較佳為使用Ar-O2
系氣體或Ar-H2
O系氣體，更佳為控制性特優之Ar-O2
系氣體。 藉由使用Ar-O2
系氣體而可獲得具有光穩定性優異之半導體特性之半導體膜。O2
濃度較佳為0.2～50體積%。 於O2
濃度未達0.2體積%之情形時，所獲得之膜著色成黃色，有光穩定性較差之虞。另一方面，於O2
濃度超過50體積%之情形時，濺鍍時薄膜之堆積速度變慢，故有生產成本變高之虞。 又，於將O2
濃度設為10體積%左右之情形時，所獲得之膜藉由熱處理而使載子濃度成為1015
～1018
cm-3
左右，能夠作為優異之半導體膜使用。 濺鍍裝置內之成膜前之壓力(腔室內之壓力)較佳為10-6
～10-3
Pa。 於腔室內之壓力超過10-3
Pa之情形時，會受到殘留於真空中之殘留水分之影響，故有難以進行電阻控制之虞。另一方面，於腔室內之壓力未達10-6
Pa之情形時，抽真空需要時間，故有生產性變差之虞。 濺鍍時之電流密度(將輸入電力除以靶面之面積所得之值)較佳為1～10 W/cm2
。 於電流密度未達1 W/cm2
之情形時，有放電不穩定之虞。另一方面，於電流密度超過10 W/cm2
之情形時，有靶因所產生之熱而破裂之虞。 濺鍍中之壓力較佳為0.01～20 Pa。 於濺鍍壓力未達0.01 Pa之情形時，有放電不穩定之虞。另一方面，於濺鍍壓力超過20 Pa之情形時，有濺鍍放電不穩定之虞，且有濺鍍氣體本身被取入至導電膜中而使膜之特性降低之虞。濺鍍壓力較佳為0.05～5 Pa，更佳為0.1～1 Pa。 作為成膜本發明之氧化物半導體薄膜之基體，可舉出玻璃、陶瓷、塑膠、金屬等。 成膜中之基體溫度並未特別限制，但自容易獲得非晶質膜之觀點而言，較佳為300℃以下。基體溫度於不特意加熱之情形時，為室溫左右即可。亦可於非晶質薄膜之狀態下直接作為半導體元件而使用，但亦可剛一成膜就成膜為非晶質膜，於藉由圖案化而形成島狀之半導體部分之後，利用熱處理使之結晶化，之後，連接源極、汲極電極等而製成薄膜半導體元件。 於成膜後，濺鍍中所導入之氧並未固定於膜中，故對基體進行後期加熱(熱處理)即可。該熱處理較佳為於大氣中、氮氣中或真空中以150～400℃進行，較佳為以200℃～350℃進行。藉由以200℃～350℃進行熱處理，能夠藉由結晶化而防止半導體膜之劣化，抑制半導體膜之載子濃度之變化，或使光穩定優異之帶隙變寬而提高透光率。是否已結晶化係於XRD測定中，根據是否觀察到峰值而判斷。 於熱處理未達150℃之情形時，有薄膜中之氧逐漸排出而引起半導體膜劣化之虞。另一方面，於熱處理超過350℃之情形時，有半導體膜之載子濃度變低之虞。 本發明之一實施形態之氧化物半導體薄膜(以下，稱為本發明之氧化物半導體薄膜)係藉由上述本發明之濺鍍靶製造而成者。 本發明之氧化物半導體薄膜之特徵在於，包含In、Al及Ln，上述Ln係選自La、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb及Lu中之一種以上之金屬元素，上述In、上述Al及上述Ln之原子比為下述範圍： In/(In＋Al＋Ln)為0.64以上且0.98以下； Al/(In＋Al＋Ln)為0.01以上且0.18以下； Ln/(In＋Al＋Ln)為0.01以上且0.18以下。 本發明之氧化物半導體薄膜中之In、Al及Ln之原子比較佳為下述範圍： In/(In＋Al＋Ln)為0.64以上且0.98以下； Al/(In＋Al＋Ln)為0.01以上且0.18以下； Ln/(In＋Al＋Ln)為0.01以上且0.18以下。 更佳為下述範圍： In/(In＋Al＋Ln)為0.70以上且0.96以下； Al/(In＋Al＋Ln)為0.02以上且0.15以下； Ln/(In＋Al＋Ln)為0.02以上且0.15以下。 上述氧化物半導體薄膜之原子比之上下限之具體依據係與本發明的氧化物燒結體之原子比之上下限之具體依據相同。 氧化物半導體薄膜中之各金屬元素之含量(原子比)可藉由利用ICP(Inductive Coupled Plasma，感應耦合電漿)測定或XRF(X-ray Fluorescence，X射線螢光)測定對各元素之存在量進行測定而求出。ICP測定可使用感應電漿發光分析裝置。XRF測定可使用薄膜螢光X射線分析裝置(AZX400，RIGAKU公司製造)。 又，使用扇區型動態次級離子質譜分析儀SIMS(secondary ion mass spectroscopy)分析亦能以與感應電漿發光分析同等之精度分析氧化物半導體薄膜中之各金屬元素之含量(原子比)。將於由感應電漿發光分析裝置或薄膜螢光X射線分析裝置所測定之金屬元素之原子比為已知的標準氧化物薄膜之上表面，由與TFT元件相同之材料以通道長形成有源極、汲極電極而成者作為標準材料，藉由扇區型動態次級離子質譜分析儀SIMS(IMS7f-Auto，AMETEK公司製造)進行氧化物半導體層之分析，獲得各元素之質譜強度，製作已知之元素濃度與質譜強度之校正曲線。其次，當對實際TFT元件之氧化物半導體膜部分根據利用扇區型動態次級離子質譜分析儀SIMS分析所得之質譜強度，使用上述校正曲線算出原子比時，可確認所算出之原子比在另外由薄膜螢光X射線分析裝置或感應電漿發光分析裝置所測定之氧化物半導體膜之原子比之2原子%以內。 本發明之一實施形態之薄膜電晶體(TFT)(以下，稱為本發明之TFT)包含上述氧化物半導體薄膜。氧化物半導體薄膜例如可較佳地用作通道層。 本發明之TFT較佳為具有以下之特性。 TFT之飽和遷移率較佳為1.0 cm2
/V∙s以上且50.0 cm2
/V∙s以下。藉由使TFT之飽和遷移率為1.0 cm2
/V∙s以上，可驅動CMOS影像感測器之傳輸電晶體或消除電晶體、液晶顯示器或有機EL(Electroluminescence，電致發光)顯示器。藉由使TFT之飽和遷移率為50.0 cm2
/V∙s以下，可使斷開電流為10-12
A以下，且接通斷開比為108
以上。 TFT之飽和遷移率可根據施加有20 V汲極電壓之情形時之轉移特性而求出。具體而言，製作轉移特性Id-Vg之曲線圖，算出各Vg之跨導(Gm)，藉由飽和區域之式而求出飽和遷移率。Id係源極、汲極電極間之電流，Vg係於源極、汲極電極間施加電壓Vd時之閘極電壓。 閾值電壓(Vth)較佳為-3.0 V以上且+3.0 V以下，更佳為-2.5 V以上且+2.5 V以下。若閾值電壓為-3.0 V以上且+3.0 V以下，則斷開電流較小，可形成接通斷開比較大之薄膜電晶體，且可與由塊狀之矽晶圓所構成之電路組合而驅動。 於本發明中，閾值電壓(Vth)根據轉移特性之曲線圖而被定義為於Id＝10-9
A之Vg。 接通/斷開比較佳為106
以上且1012
以下，更佳為107
以上且1011
以下，進而佳為108
以上且1011
以下。若接通/斷開比為106
以上，則可驅動液晶顯示器。若接通/斷開比為1012
以下，則能夠進行對比度較大之有機EL面板之驅動，又，可使斷開電流為10-12
A以下，在用於CMOS影像感測器之傳輸電晶體或消除電晶體之情形時，可延長圖像之保持時間或使感度提高。 於本發明中，接通/斷開比係將Vg＝-10 V之Id之值設為斷開電流值，且將Vg＝20 V之Id之值設為接通電流值而算出比[接通/斷開]。 斷開電流值較佳為10-11
A以下，更佳為10-12
A以下。若使斷開電流為10-11
A以下，則能夠進行對比度較大之有機EL面板之驅動，又，在用於CMOS影像感測器之傳輸電晶體或消除電晶體之情形時，可延長圖像之保持時間或使感度提高。 用於本發明之TFT之通道層之氧化物半導體薄膜之缺陷密度較佳為5.0×1016
cm-3
以下，更佳為1.0×1016
cm-3
以下。藉由使缺陷密度如上所述較低而使薄膜電晶體之遷移率進而變高，光照射時之穩定性、對熱之穩定性變高，從而使TFT穩定地作動。 TFT之元件構成並無特別限定，可採用公知之各種元件構成。本發明之TFT亦可應用於場效型電晶體、邏輯電路、記憶體電路、差動放大電路等各種積體電路。進而，除場效型電晶體以外，亦可應用於靜電感應型電晶體、肖特基能障型電晶體、肖特基二極體、及電阻元件。又，例如可用於液晶顯示器或有機電致發光顯示器等顯示裝置等電子機器。 對將本發明之TFT用於顯示裝置之情形進行說明。 圖1(A)係包含本發明之TFT之顯示裝置之俯視圖，圖1(B)係可在將使用本發明之TFT之液晶元件應用於顯示裝置之像素部之情形時使用之像素部之電路之圖，圖1(C)係可在將使用本發明之TFT之有機EL元件應用於顯示裝置之像素部之情形時使用之像素部之電路之圖。 配置於像素部之本發明之TFT可如既已說明般形成。又，本發明之TFT容易設為n通道型，故將驅動電路中可由n通道型電晶體構成之驅動電路之一部分形成於與像素部之電晶體相同之基板上。如此，藉由將上述實施形態中所示之電晶體用於像素部之電晶體或驅動電路而可提供可靠性較高之顯示裝置。 圖1(A)之顯示裝置係主動矩陣型顯示裝置。顯示裝置於基板10上具有像素部11、第1掃描線驅動電路12、第2掃描線驅動電路13、及信號線驅動電路14。於像素部11，自信號線驅動電路14延伸配置有複數個信號線，並且自第1掃描線驅動電路12及第2掃描線驅動電路13延伸配置有複數個掃描線。在掃描線與信號線之交叉區域，分別以矩陣狀設置有具有顯示元件之像素。顯示裝置之基板10經由FPC(Flexible Printed Circuit，撓性印刷電路)等連接部而連接於時序控制電路(亦稱為控制器、控制IC(Integrated Circuit，積體電路))。 圖1(A)中，第1掃描線驅動電路12、第2掃描線驅動電路13、及信號線驅動電路14形成於與像素部11相同之基板10上。因此，設置於外部之驅動電路等零件之數量減少，故可謀求成本之降低。又，於在基板10外部設置有驅動電路之情形時，必需使配線延伸，從而配線間之連接數量增加。於在相同基板10上設置有驅動電路之情形時，可減少其配線間之連接數量，從而可謀求可靠性之提高或良率之提高。 將像素部之電路構成之一例示於圖1(B)。該例係可應用於VA(Vertical Aligned，垂直配向)型液晶顯示裝置之像素部之像素部之電路。 該像素部之電路可應用於在一個像素中具有複數個像素電極之構成。各個像素電極連接於不同之電晶體，各電晶體構成為能以不同之閘極信號驅動。藉此，可獨立地控制施加至多域設計之像素之各個像素電極之信號。 對電晶體24之閘極配線21、與電晶體25之閘極配線22以可賦予不同之閘極信號之方式分離。另一方面，作為資料線發揮功能之源極電極或汲極電極23在電晶體24與電晶體25被共通使用。電晶體24與電晶體25可適當使用本發明之TFT。藉此，可提供可靠性較高之液晶顯示裝置。 於電晶體24電性連接有第1像素電極，於電晶體25電性連接有第2像素電極。第1像素電極與第2像素電極分離。作為第1像素電極與第2像素電極之形狀並無特別限定。例如，第1像素電極設為V字狀即可。 電晶體24之閘極電極係與閘極配線21連接，電晶體25之閘極電極係與閘極配線22連接。可對閘極配線21與閘極配線22賦予不同之閘極信號而使電晶體24與電晶體25之動作時序不同，而控制液晶之配向。 亦可由電容配線20、作為介電體發揮功能之閘極絕緣膜、及與第1像素電極或第2像素電極電性連接之電容電極而形成保持電容。 多域構造於一像素具備第1液晶元件26與第2液晶元件27。第1液晶元件26係由第1像素電極、對向電極及其等之間之液晶層構成，第2液晶元件27係由第2像素電極與、對向電極及其等之間之液晶層構成。 圖1(B)所示之像素部之電路並不限定於此。例如，於圖1(B)所示之像素亦可新追加開關、電阻元件、電容元件、電晶體、感測器或邏輯電路等。 將像素之電路構成之另一例示於圖1(C)。該例係使用有機EL元件之顯示裝置之像素構造，且表示將2個n通道型之電晶體用於1個像素之例。本發明之氧化物半導體薄膜可用於n通道型之電晶體之通道形成區域。該像素部之電路可應用數位時間灰階驅動。 開關用電晶體31及驅動用電晶體32可適當使用本發明之TFT。藉此，可提供可靠性較高之有機EL顯示裝置。 像素部之電路之構成並不限定於圖1(C)所示之像素構成。例如，亦可於圖1(C)所示之像素部之電路追加開關、電阻元件、電容元件、感測器、電晶體或邏輯電路等。 以下對包含本發明之TFT之固體攝像元件之動作進行說明。 CMOS(Complementary Metal Oxide Semiconductor，互補金氧半導體)影像感測器係將電位保持於信號電荷儲存部，並將該電位經由放大電晶體而輸出至垂直輸出線之固體攝像元件。若於CMOS影像感測器中所包含之復位電晶體及/或傳輸電晶體中有洩漏電流，則藉由該洩漏電流引起充電或放電，從而信號電荷儲存部之電位變化。若信號電荷儲存部之電位變化，則放大電晶體之電位亦變化，成為偏離原本之電位之值，從而所攝像之影像劣化。 對將本發明之TFT應用於CMOS影像感測器之復位電晶體及傳輸電晶體之情形時之動作之效果進行說明。再者，放大電晶體亦可應用薄膜電晶體或塊狀電晶體之任一者。 圖2係表示CMOS影像感測器之像素構成之一例之圖。像素係由作為光電轉換元件之光電二極體40、傳輸電晶體41、復位電晶體42、放大電晶體43及各種配線構成，且複數個像素配置成矩陣狀而構成感測器。又，亦可設置與放大電晶體43電性連接之選擇電晶體。記於電晶體記號中之「OS」表示氧化物半導體(Oxide Semiconductor)，「Si」表示矽，其表示應用於各個電晶體時較佳之材料。 光電二極體40連接於傳輸電晶體41之源極側，於傳輸電晶體41之汲極側形成有信號電荷儲存部44(亦稱為FD(Floating Diffusion)：浮動擴散)。於信號電荷儲存部44連接有復位電晶體42之源極及放大電晶體43之閘極。作為其他構成，亦可刪除復位電源線46。例如，有將復位電晶體42之汲極連結於電源線45或垂直輸出線47而不連結於復位電源線46之方法。 [實施例] 以下，舉出實施例更具體地說明本發明，但本發明並不限定於下述實施例，亦能夠在可適合於本發明之主旨之範圍適當地加以變更而實施，且其等任一者均包含於本發明之技術範圍。 [氧化物燒結體之製造] 實施例1～4 以成為下述表1所示之比例之方式稱量氧化釤粉末、氧化銦粉末、及氧化鋁粉末，並裝入至聚乙烯製之坩堝中，藉由乾式球磨機進行72小時混合粉碎而製作混合粉末。 將該混合粉末裝入模具中，以500 kg/cm2
之壓力製成壓製成型體。將該成型體以2000 kg/cm2
之壓力藉由CIP進行緻密化。其次，將該成型體設置於常壓焙燒爐中，於大氣氛圍下以350℃保持3小時之後，以50℃/小時進行升溫，於1350℃燒結40小時，其後，放置冷卻而獲得氧化物燒結體。 [氧化物燒結體之特性評價] (1)XRD之測定 對所獲得之燒結體，藉由X射線繞射測定裝置Smartlab於以下之條件下測定燒結體之X射線繞射(XRD)。藉由粉末X射線繞射圖案綜合分析軟體JADE6(股份公司RIGAKU)分析所獲得之XRD圖，求出燒結體中之結晶相。將結果示於表1。 ∙裝置：Smartlab(股份公司RIGAKU製造) ∙X射線：Cu-Kα線(波長1.5418 Å) ∙2θ-θ反射法、連續掃描(2.0°/分鐘) ∙取樣間隔：0.02° ∙狹縫DS(發散狹縫)，SS(散射狹縫)，RS(受光狹縫)：1 mm 又，將實施例1～4所獲得之燒結體之XRD圖分別示於圖1～4。 自圖1～4可知，各實施例所獲得之燒結體具有表1所示之鈣鈦礦相及方鐵錳礦相。 (2)In2
O3
之存在比率(wt%) 所獲得之燒結體中之In2
O3
之存在比率(wt%)以通常之方法求出。即，自X射線繞射之分佈藉由JADE6進行分析，且藉由全圖案擬合(WPF，whole-pattern fitting)而求出燒結體之結晶構造。進而，自峰值強度比求出In2
O3
之存在比。將結果示於表1。 (3)燒結密度(g/cm3
) 利用阿基米德法測定所獲得之燒結體之燒結密度(g/cm3
)。將結果示於表1。 (4)體電阻(mΩ∙cm) 使用電阻率計Loresta AXMCP-T370(三菱化學股分公司製造)，基於四探針法(JISR 1637)測定所獲得之燒結體之體電阻(mΩ∙cm)。將結果示於表1。 [表1] [
濺鍍靶之製造] 實施例5 以成為下述表2所示之比例之方式稱量氧化釤粉末、氧化銦粉末、及氧化鋁粉末，並裝入至聚乙烯製之坩堝中，藉由乾式球磨機進行72小時混合粉碎而製作混合粉末。 將該混合粉末裝入至模具中，以500 kg/cm2
之壓力製成壓製成型體。將該成型體以2000 kg/cm2
之壓力藉由CIP進行緻密化。其次，將該成型體設置於常壓焙燒爐中，於大氣氛圍下以350℃保持10小時之後，以50℃/小時進行升溫，於1450℃燒結40小時，其後，放置並冷卻，獲得氧化物燒結體。與實施例1～4同樣地進行燒結體之特性評價。將結果示於表2。 對所獲得之氧化物燒結體進行研削研磨，製造4英吋×5 mmt之氧化物燒結體之圓板。使用熔融之金屬銦將該圓板接合於銅製之8 mm厚度之背板。 [濺鍍靶之特性評價] (1)靶之翹曲(mm) 藉由下述方法測定所獲得之靶之翹曲(mm)。將結果示於表2。 將靶靜置於定盤上，使用測隙規測量間隙來作為翹曲量(mm)。 (2)靶之接合率(%) 藉由下述方法測定所獲得之靶之接合率(%)。將結果示於表2。 接合率係由超音波探傷機測量未接合之空隙部分，並按靶面積基準算出接合之部分之比率。 [表2]
[氧化物半導體薄膜之製造] 實施例6 使用實施例5所獲得之濺鍍靶，於附熱氧化膜之矽基板上使用通道形狀之金屬遮罩，藉由濺鍍而成膜氧化物半導體層(通道層)。濺鍍條件為於濺鍍壓＝0.5 Pa、氧分壓＝5%、基板溫度＝室溫下進行，膜厚設定為50 nm。其次，使用源極、汲極形狀之金屬遮罩，成膜50 nm之鈦電極。最後，於空氣中於300℃、1小時之條件下進行退火，以此獲得通道長200 μm、通道寬1000 μm之底閘極、頂觸點之簡易型TFT。作為退火條件，於250℃～450℃、0.5小時～10小時之範圍一面觀察通道部之載子濃度一面適當選擇。 對所獲得之TFT之特性進行評價之結果，遷移率＝14 cm2
/V∙sec，電流值超過10-8
A之閘極電壓之值Vth＞0.45 V，S值(Swing Factor，浮動因子)＝0.72。 將該TFT元件安裝於CVD裝置，於350℃將SiO2
成膜為100 nm之厚度作為鈍化膜，其後，對以300℃、大氣中退火1小時之後之TFT特性進行評價。結果，遷移率＝12 cm2
/V∙sec，電流值超過10-8
A之閘極電壓之值Vth＞0.32 V，S值(Swing Factor)＝0.78，大致可再現CVD前之特性。 又，斷開電流為10-12
A。根據該等結果，亦能夠用於顯示器之顯示裝置之電晶體、或CMOS影像感測器之消除電晶體或傳輸電晶體。 實施例7～9 以成為下述表3所示之比例之方式稱量氧化釹粉末、氧化銦粉末、及氧化鋁粉末，並裝入至聚乙烯製之坩堝中，藉由乾式球磨機進行72小時混合粉碎而製作混合粉末。 將該混合粉末裝入至模具，以500 kg/cm2
之壓力製成壓製成型體。將該成型體以2000 kg/cm2
之壓力藉由CIP進行緻密化。其次，將該成型體設置於常壓焙燒爐中，於大氣氛圍下以350℃保持3小時之後，以50℃/小時進行升溫，於1350℃燒結40小時，其後，放置冷卻而獲得氧化物燒結體。 對所獲得之氧化物燒結體，與實施例1～4同樣地評價氧化物燒結體之特性。將結果示於表3。 [表3]
[濺鍍靶之製造] 實施例10～12 以成為下述表4所示之比例之方式稱量氧化釤粉末、氧化銦粉末、及氧化鋁粉末，並裝入至聚乙烯製之坩堝中，藉由乾式球磨機進行72小時混合粉碎而製作混合粉末。 將該混合粉末裝入至模具，以500 kg/cm2
之壓力製成壓製成型體。將該成型體以1000 kg/cm2
之壓力藉由CIP進行緻密化。其次，將該成型體設置於常壓燒結爐中，於大氣氛圍下以350℃放置3小時之後，以50℃/小時進行升溫，於1420℃燒結28小時，其後，放置冷卻而獲得氧化物燒結體。 對所獲得之氧化物燒結體，與實施例1～4同樣地評價氧化物燒結體之特性。將結果示於表4。 又，將實施例10～12所獲得之燒結體之XRD圖分別顯示於圖9～11。 根據圖9～11可知，各實施例所獲得之燒結體具有表4所示之鈣鈦礦相及方鐵錳礦相。 對所獲得之氧化物燒結體進行研削研磨，製造4英吋×5 mmt之氧化物燒結體之圓板。使用熔融之金屬銦將該圓板接合於銅製之8 mmt厚度之背板。 [濺鍍靶之評價] (1)靶之翹曲(mm) 藉由下述方法測定所獲得之靶之翹曲(mm)。將結果示於表4。 將靶靜置於定盤上，使用測隙規測量間隙來作為翹曲量(mm)。 (2)靶之接合率(%) 藉由下述方法測定所獲得之靶之接合率(%)。將結果示於表4。 接合率係由超音波探傷機測量未接合之部分，並按靶面積基準算出接合之部分之比率。 [表4]
[氧化物半導體薄膜之製造] 實施例13 使用實施例11所獲得之濺鍍靶，於附熱氧化膜之矽基板上使用通道形狀之金屬遮罩，藉由濺鍍而成膜氧化物半導體層(通道層)。濺鍍條件為於濺鍍壓＝0.5Pa、氧分壓＝1%、基板溫度＝室溫下進行，膜厚設定為50 nm。其次，使用源極、汲極形狀之金屬遮罩而成膜50 nm之鈦電極。最後，以空氣中、350℃、1小時之條件進行退火，以此獲得通道長200 μm、通道寬2000 μm之底閘極、頂觸點之簡易型TFT。作為退火條件，於250℃～450℃、0.5小時～10小時之範圍一面觀察通道部之載子濃度一面適當選擇。測定以350℃熱處理1小時後之薄膜之XRD之結果，獲得由In2
O3
表示之方鐵錳礦構造之圖，確認到結晶化。 對所獲得之TFT之特性評價之結果為，遷移率＝17 cm2
/V∙sec，電流值超過10-8
A之閘極電壓之值Vth＞0.15 V，S值(Swing Factor)＝0.22。 將該TFT元件安裝於CVD裝置，於300℃將SiO2
成膜為100 nm之厚度作為鈍化膜，其後，對以350℃、大氣中退火1小時之後之TFT特性進行評價。結果為，遷移率＝21 cm2
/V∙sec，電流值超過10-8
A之閘極電壓之值Vth＞0.24 V，S值(Swing Factor)＝0.26，大致可再現CVD前之特性。又，斷開電流為10-12
A以下。根據該等結果，亦能夠用於顯示器之顯示裝置之電晶體、或CMOS影像感測器之消除電晶體或傳輸電晶體。 [產業上之可利用性] 本發明之氧化物燒結體可用於濺鍍靶，且對用於液晶顯示器或有機EL顯示器等顯示裝置等之薄膜電晶體(TFT)之氧化物半導體薄膜等之製造有用。 以上對本發明之實施形態及/或實施例進行了若干詳細地說明，但業者可於實質上不脫離本發明之新穎示教及效果之情況下容易地對作為該等例示的實施形態及/或實施例加以多種變更。因此，該等多種變更包含於本發明之範圍。 將本案之成為巴黎公約優先權之基礎之日本申請案說明書的全部內容引用於此。The oxide sintered body of one embodiment of the present invention (hereinafter referred to as the sintered body of the present invention) is characterized by including a perovskite phase and a bixbyite phase represented by In 2 O 3. The perovskite phase in the sintered body of the present invention and the bixbyite phase represented by In 2 O 3 can be obtained from XRD (X ray diffraction, X-ray diffraction) by, for example, X-ray diffraction (XRD, X ray diffraction). Radiometry) figure is detected. The perovskite phase in the sintered body of the present invention is preferably a compound represented by the following general formula (I). LnAlO 3 (I) (where Ln represents one or more metal elements selected from La, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu). Ln is particularly preferably either one or both of Sm and Nd. The compound represented by the above general formula (I) has a perovskite-type structure, and by including this structure, a high-density sintered body can be obtained. The perovskite compound represented by the general formula (I) may have a single crystal structure or a polycrystalline structure. The sintered body of the present invention includes the perovskite phase represented by the above-mentioned general formula (I) and the bixbyite phase represented by In 2 O 3 so that the sintered density (relative density) and volume resistivity (bulk resistance) )improve. In addition, the coefficient of expansion can be reduced and the thermal conductivity can be increased. In addition, even when the sintered body is fired by a simple method such as using an atmosphere roasting furnace under special conditions in an oxygen atmosphere or in the atmosphere, a sintered body with a lower volume resistivity and a higher sintered density can be formed. . The sintered body of the present invention having the above-mentioned characteristics is preferable as a target material. By using the sintered body of the present invention as a target material, the generation of stress can be suppressed, the strength or thermal conductivity of the target can be improved, the linear expansion coefficient can be suppressed, the generation of microcracks or cracks in the target can be suppressed, and the generation of nodules or abnormal discharges can be suppressed , Can obtain the sputtering target that can use high power for sputtering. In addition, by using the sintered body of the present invention as a target material, a high-performance TFT with high mobility and less deterioration of semiconductor characteristics due to chemical vapor deposition (CVD) can be obtained. The sputtering target of one embodiment of the present invention (hereinafter referred to as the target of the present invention) is characterized by being produced using the sintered body of the present invention described above. The target of the present invention is manufactured by grinding and processing the sintered body of the present invention described above, and bonding it to a metal support such as a copper plate (hereinafter, also referred to as a backing plate or a target support) with metal indium or the like. . The manufacturing method of the oxide sintered body of the present invention and the target of the present invention will be described below. The atom ratio of In, Al and Ln in the sintered body used in the target of the present invention is preferably in the following range: In/(In+Al+Ln) is 0.64 or more and 0.98 or less; Al/(In+Al+Ln) is 0.01 or more and 0.18 or less; Ln /(In+Al+Ln) is 0.01 or more and 0.18 or less, more preferably the following range: In/(In+Al+Ln) is 0.70 or more and 0.96 or less; Al/(In+Al+Ln) is 0.02 or more and 0.15 or less; Ln/(In+Al+Ln) is 0.02 or more And below 0.15. When In/(In+Al+Ln) is less than 0.64, the mobility of the TFT including the formed oxide semiconductor thin film may decrease. When In/(In+Al+Ln) exceeds 0.98, the stability of the TFT may not be obtained, or it may become conductive and difficult to become a semiconductor. When Al/(In+Al+Ln) is less than 0.01, the perovskite phase represented by the general formula (I) is not formed, and the stability of the TFT may not be obtained, or the conductivity may be difficult to become a semiconductor, or There is a risk that stable sputtering cannot be performed. On the other hand, when Al/(In+Al+Ln) exceeds 0.18, the mobility of the TFT including the formed oxide semiconductor thin film may decrease. When Ln/(In+Al+Ln) is less than 0.01, the perovskite phase represented by the general formula (I) is not formed, and the stability of the TFT may not be obtained, or the conductivity may be difficult to become a semiconductor, or There is a risk that stable sputtering cannot be performed. On the other hand, when Ln/(In+Al+Ln) exceeds 0.18, the mobility of the TFT including the formed oxide semiconductor thin film may decrease. The sintered body of the present invention may further include positive tetravalent metal elements. Thereby, sputtering can be performed more stably. Examples of positive tetravalent metal elements include Sn, Ti, Zr, Hf, Ce, Ge, and the like. The sintered body of the present invention may contain one or two or more of these. Preferably it is Sn. Due to the doping effect of Sn, the bulk resistance can be reduced and sputtering can be performed more stably. The positive tetravalent metal element is preferably solid-soluble in the bixbyite phase represented by In 2 O 3 or the perovskite phase represented by the general formula (I), more preferably solid-soluble in the square represented by In 2 O 3 Ferromanganese phase. The solid solution is preferably a displacement type solid solution. Thereby, sputtering can be performed more stably. In addition, Ln and Al may also be solid-soluble in the bixbyite phase represented by In 2 O 3. The solid solution of positive tetravalent metal elements, Ln and Al can be identified based on the lattice constant measured by XRD, for example. The content of the positive tetravalent metal element relative to all the metal elements in the oxide sintered body of the present invention is preferably 100 ppm or more and 10000 ppm or less in atomic concentration, more preferably 500 ppm or more and 8000 ppm or less, and still more preferably 800 ppm or more and 6000 ppm or less. Below 100 ppm, the volume resistance may increase. On the other hand, when it exceeds 10,000 ppm, there is a possibility that the TFT including the formed oxide semiconductor thin film may be turned on, or the on/off value may become smaller. The existence ratio of the bixbyite phase represented by In 2 O 3 in the sintered body of the present invention is preferably 1 to 99 wt%, more preferably 10 to 98 wt%. If the presence ratio of the bixbyite phase represented by In 2 O 3 is in the above range, the perovskite phase is dispersed in the In 2 O 3 crystals, and it can be considered to be used in de-targeting materials by doping with rare earth elements, etc. Other fluorescent materials, etc. The existence ratio of the bixbyite phase represented by In 2 O 3 can be measured by the method described in the examples. In the sintered body of the present invention, the bixbyite phase represented by In 2 O 3 is preferably the main component. If a crystal structure other than the bixbyite structure is precipitated as a main component, it may cause a decrease in mobility. The so-called "the bixbyite phase represented by In 2 O 3 as the main component" means that the presence ratio of the bixbyite phase represented by In 2 O 3 exceeds 50 wt%, preferably more than 70 wt%, more preferably 80 wt% or more, more preferably 85 wt% or more. In the sintered body of the present invention, the sintered density is preferably in the range of 6.5 to 7.1 g/cm 3 , more preferably in the range of 6.6 to 7.1 g/cm 3 . If the sintered density is in the range of 6.5 to 7.1 g/cm 3 , when used as a target, the voids that cause abnormal discharge or the starting point of nodules can be reduced. The sintered density can be measured by the Archimedes method, for example. In the sintered body of the present invention, the bulk resistance is preferably 50 mΩ·cm or less, more preferably 30 mΩ·cm or less, and still more preferably 20 mΩ·cm or less. The lower limit is not particularly limited, but it is usually 1 mΩ∙cm or more or 5 mΩ∙cm or more. When the volume resistance is less than 50 mΩ·cm, it is difficult to produce abnormal discharge caused by the electrification of the target during DC sputtering with high power, and the plasma state is stable, and it is difficult to generate sparks. In addition, when using a pulsed DC sputtering device, an RF sputtering device, or an RF+DC sputtering device, the plasma is more stable, and there is no problem such as abnormal discharge, and the sputtering can be performed stably. The volume resistance can be measured based on the four-probe method, for example. Specifically, it can be measured based on the four-point probe method (JIS R 1637) using a well-known resistivity meter. The measurement locations are about 5 locations, and it is preferable to set the average value as the volume resistance value. When the planar shape of the oxide sintered body is a quadrilateral, the measurement location is preferably a total of 5 locations including the center and 4 points between the four corners and the center. Furthermore, when the planar shape of the oxide sintered body is a circle, it is preferable to have a total of 5 locations that are inscribed at the center of the square of the circle, and 4 points between the four corners of the square and the center. In the sintered body of the present invention, the three-point bending strength is preferably 120 MPa or more, more preferably 140 MPa or more, and still more preferably 150 MPa or more. When the three-point bending strength is less than 120 MPa, when sputtering with high-power sputtering to form a film, there is a possibility that the strength of the target is weak, the target ruptures, or cracks occur, and the broken fragments fly to the target It becomes the cause of abnormal discharge. The three-point bending strength can be tested according to, for example, JIS R 1601 "Room temperature bending strength test of fine ceramics". Specifically, a standard test piece with a width of 4 mm, a thickness of 3 mm, and a length of 40 mm can be used. The test piece is placed on 2 fulcrums at a fixed distance (30 mm), and a crosshead speed of 0.5 is applied from the center between the fulcrums. For the load of mm/min, the bending strength is calculated from the maximum load when the test piece is broken. In the sintered body of the present invention, the coefficient of linear expansion is preferably 8.0×10 -6 K -1 or less, more preferably 7.5×10 -6 K -1 or less, and still more preferably 7.0×10 -6 K -1 or less. The lower limit is not particularly limited, but it is usually 5.0×10 -6 K -1 or more. When the coefficient of linear expansion exceeds 8.0×10 -6 K -1 , the target is heated during sputtering with high power, and the target expands and deforms between the bonded copper plates, which may cause micro-cracks in the target due to stress. , Or it may be the cause of abnormal discharge due to rupture or cracking. The coefficient of linear expansion can be obtained, for example, by using a standard test piece with a width of 5 mm, a thickness of 5 mm, and a length of 10 mm, setting the heating rate to 5°C/min, and detecting the temperature reached by a position detector. Displacement caused by thermal expansion at 300°C. In the sintered body of the present invention, the thermal conductivity is preferably 5.0 W/m∙K or higher, more preferably 5.5 W/m∙K or higher, still more preferably 6.0 W/m∙K or higher, and most preferably 6.5 W/ m∙K or more. The upper limit is not particularly limited, but it is usually 10 W/m∙K or less. When the thermal conductivity is less than 5.0 W/m∙K, when sputtering with high power, the temperature of the sputtering surface and the surface to be joined is different, and there are micro-cracks or micro-cracks in the target due to internal stress. The risk of rupture or chipping. The thermal conductivity can be calculated, for example, by using a standard test piece with a diameter of 10 mm and a thickness of 1 mm to obtain the specific heat capacity and thermal diffusivity by the laser flash method, and multiply it by the density of the test piece . The metal elements of the sintered body of the present invention essentially include In, Al, Ln, and any positive tetravalent metal elements, so as not to impair the effect of the present invention, it may also contain unavoidable impurities. The metal element of the sintered body of the present invention may include In, Al, and Ln, or In, Al, Ln, and positive four, for example, 90 atomic% or more, 95 atomic% or more, 98 atomic% or more, 99 atomic% or more, or 100 atomic%. Valence of the metal element. The sintered body of the present invention can be manufactured by the following steps: preparing a mixed powder of raw material powder containing In, raw material powder containing Al, and raw material powder containing Ln; forming the mixed powder to produce a molded body; and firing the molded body . The mixed powder may also include raw material powder containing positive tetravalent metal elements. The raw material powder is preferably an oxide powder. The mixing ratio of the raw material powders corresponds to, for example, the atomic ratio of the sintered body to be obtained. The average particle size of the raw material powder is preferably 0.1 to 1.2 μm, more preferably 0.5 to 1.0 μm or less. The average particle size of the raw material powder can be measured by a laser diffraction particle size distribution device or the like. The method of mixing and forming the raw materials is not particularly limited, and it can be performed by a known method. In addition, a binder may be added at the time of mixing. The mixing of the raw materials can be performed using a known device such as a ball mill, a bead mill, a jet mill, or an ultrasonic device. The mixing time may be adjusted appropriately, but it is preferably about 6 to 100 hours. The molding method may be, for example, press-molding the mixed powder to form a molded body. Through this step, it can be formed into the shape of a product (for example, a shape that is preferable as a sputtering target). The mixed powder raw materials can be filled into a forming mold, usually by mold pressing or cold isostatic pressing (CIP, cold isostatic pressing) to form a molded body at a pressure of , for example, 1000 kg/cm 2 or more. Furthermore, during the molding process, molding aids such as polyvinyl alcohol, polyethylene glycol, methyl cellulose, polyethylene wax, oleic acid, and stearic acid may also be used. The obtained molded body can be sintered at a sintering temperature of 1200 to 1650°C for 10 hours or more to obtain a sintered body. The sintering temperature is preferably 1350 to 1600°C, more preferably 1400 to 1600°C, and still more preferably 1450 to 1600°C. The sintering time is preferably 10 to 50 hours, more preferably 12 to 40 hours, and still more preferably 13 to 30 hours. If the sintering temperature is less than 1200°C or the sintering time is less than 10 hours, the sintering is not sufficiently performed, and the resistance of the target is not sufficiently reduced, which may cause abnormal discharge. On the other hand, if the firing temperature exceeds 1650°C, or the firing time exceeds 50 hours, the average crystal grain size increases due to significant crystal grain growth, or coarse pores are generated, which may reduce the strength of the sintered body. Or the cause of abnormal discharge. In the atmospheric sintering method, the formed body is usually sintered in an air atmosphere or an oxygen atmosphere. The oxygen atmosphere is preferably an atmosphere with an oxygen concentration of, for example, 10-50% by volume. The density of the sintered body can be increased due to the heating process under the atmosphere. Furthermore, the temperature increase rate during sintering is preferably set to 50 to 150°C/hour from 800°C to the sintering temperature (1200 to 1650°C). In the sintered body of the present invention, the temperature range from 800°C upward is the most vigorously sintering range. If the temperature increase rate in this temperature range is slower than 50° C./hour, the growth of crystal grains becomes remarkable, and there is a possibility that high density cannot be achieved. On the other hand, if the temperature increase rate is faster than 150°C/hour, a temperature distribution is generated in the molded body, and the sintered body may be warped or cracked. The heating rate of the sintering temperature from 800°C is preferably 60 to 140°C/hour, more preferably 70 to 130°C/hour. The sputtering target of the present invention can be produced using the sintered body of the present invention described above. In this way, the oxide semiconductor thin film can be manufactured by a vacuum process such as sputtering. The sputtering target can be produced, for example, by cutting or polishing a sintered body and joining it to a backing plate. For example, the highly oxidized sintered part on the surface of the sintered body or the convex and concave surface can be removed by cutting. Also, it can be set to a specified size. The surface can also be polished #200, or #400, and then #800. Thereby, the generation of abnormal discharge or particles during sputtering can be suppressed. The cooling efficiency during sputtering is maintained, and the bonding rate is preferably 90% or more, more preferably 95% or more, and still more preferably 99% or more. The bonding rate here means the ratio of the area of the surface where the target material and the target support material are bonded via the bonding layer to the area of the surface where the target material and the target support material overlap each other. The bonding rate can usually be measured by an ultrasonic flaw detection device or the like. The method of joining the target material and the target support will be described. Surface treatment is performed on the joint surface between the target material and the target support that has been processed into a specific shape. The equipment used in surface treatment generally can use commercially available spray equipment. For example, the product name "PNEUMA BLASTER, SGF-5-B" manufactured by Fuji Manufacturing Co., Ltd. can be cited. As the powder used in the blasting method, glass, alumina, zirconia, SiC, etc. can be used, and these can be appropriately selected according to the composition and hardness of the target material. If necessary, after washing the surface of the obtained target material with the surface treatment completed, a bonding material such as metallic indium solder is applied to the bonding surface. Coating metal indium solder and other bonding materials on the bonding surface of the back plate after the cleaning process is also performed as necessary. At this time, when the target material is composed of a material that is not directly welded to the bonding material, a sputtering method, plating method, etc. are used to form copper, which is excellent in wettability with the bonding material, on the bonding surface of the target material in advance. After the thin film layer of nickel or the like, it is heated to above the melting point of the bonding material using the target material and the bonding material is applied, or the bonding material may be directly applied to the bonding surface of the target material using ultrasonic waves. Secondly, the target support coated with the bonding material can be heated to above the melting point of the bonding material used to melt the bonding material layer on the surface, and then the powder can be placed on the surface, and the target and the backing plate can be bonded and then cooled The target is obtained by reaching room temperature. The sputtering target of the present invention can be applied to direct current (DC, direct current) sputtering, high frequency (RF, radio frequency) sputtering, alternating current (AC, aternating current) sputtering, pulsed DC sputtering, etc. . An oxide semiconductor thin film can be obtained by film formation using the sputtering target of the present invention described above. As a result, a thin film that exhibits excellent TFT performance when used for TFT can be formed. Film formation can be performed by vapor deposition, sputtering, ion plating, pulse laser vapor deposition, or the like. The sputtering can be performed under an oxidizing argon atmosphere in which oxygen atoms such as O 2 and H 2 O are introduced (oxidizing gas). By performing sputtering in an oxidizing gas atmosphere, it is possible to suppress the generation of impurities that become a hindrance factor to the optical transparency required for the obtained semiconductor characteristics and light stability. The concentration of the above-mentioned oxidizing gas may be appropriately adjusted according to the required semiconductor characteristics of the film, especially the carrier concentration. This adjustment can also be performed by, for example, substrate temperature, sputtering pressure, and the like. As the sputtering gas, from the viewpoint of easy control of the composition of the gas, it is preferable to use an Ar—O 2 gas or an Ar—H 2 O gas, and more preferably an Ar—O 2 gas having excellent controllability. By using Ar-O 2 gas, a semiconductor film with semiconductor characteristics excellent in light stability can be obtained. The O 2 concentration is preferably 0.2-50% by volume. When the O 2 concentration is less than 0.2% by volume, the obtained film is colored yellow, and the light stability may be poor. On the other hand, when the O 2 concentration exceeds 50% by volume, the deposition rate of the thin film during sputtering becomes slow, which may increase the production cost. In addition, when the O 2 concentration is about 10% by volume, the obtained film is heat-treated so that the carrier concentration becomes about 10 15 to 10 18 cm -3 and can be used as an excellent semiconductor film. The pressure before film formation in the sputtering device (pressure in the chamber) is preferably 10 -6 to 10 -3 Pa. When the pressure in the chamber exceeds 10 -3 Pa, it will be affected by the residual moisture remaining in the vacuum, so it may be difficult to control the resistance. On the other hand, when the pressure in the chamber does not reach 10 -6 Pa, it takes time to evacuate, which may result in poor productivity. The current density during sputtering (the value obtained by dividing the input power by the area of the target surface) is preferably 1-10 W/cm 2 . When the current density is less than 1 W/cm 2 , the discharge may be unstable. On the other hand, when the current density exceeds 10 W/cm 2 , the target may be broken by the heat generated. The pressure in sputtering is preferably 0.01-20 Pa. When the sputtering pressure is less than 0.01 Pa, the discharge may be unstable. On the other hand, when the sputtering pressure exceeds 20 Pa, the sputtering discharge may become unstable, and the sputtering gas itself may be taken into the conductive film to reduce the characteristics of the film. The sputtering pressure is preferably 0.05 to 5 Pa, more preferably 0.1 to 1 Pa. Examples of the substrate for forming the oxide semiconductor thin film of the present invention include glass, ceramics, plastics, metals, and the like. The substrate temperature in film formation is not particularly limited, but from the viewpoint of easy availability of an amorphous film, it is preferably 300° C. or lower. When the temperature of the substrate is not intentionally heated, it should be around room temperature. It can also be used directly as a semiconductor device in the state of an amorphous thin film, but it can also be formed into an amorphous film as soon as the film is formed, and after the island-shaped semiconductor portion is formed by patterning, it is made by heat treatment After crystallization, the source and drain electrodes are connected to form a thin-film semiconductor device. After the film is formed, the oxygen introduced during sputtering is not fixed in the film, so it is sufficient to perform post-heating (heat treatment) on the substrate. The heat treatment is preferably performed at 150-400°C in the atmosphere, nitrogen or vacuum, preferably at 200-350°C. By performing heat treatment at 200°C to 350°C, it is possible to prevent deterioration of the semiconductor film by crystallization, suppress the change in the carrier concentration of the semiconductor film, or widen the band gap with excellent light stability to increase the light transmittance. Whether or not it has been crystallized is determined by XRD measurement based on whether a peak is observed. When the heat treatment does not reach 150°C, the oxygen in the film is gradually discharged, which may cause deterioration of the semiconductor film. On the other hand, when the heat treatment exceeds 350°C, the carrier concentration of the semiconductor film may decrease. The oxide semiconductor thin film of one embodiment of the present invention (hereinafter referred to as the oxide semiconductor thin film of the present invention) is produced by the sputtering target of the present invention described above. The oxide semiconductor thin film of the present invention is characterized in that it contains In, Al and Ln, and the Ln is one or more selected from La, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu The atomic ratio of the above-mentioned In, the above-mentioned Al and the above-mentioned Ln is in the following range: In/(In+Al+Ln) is 0.64 or more and 0.98 or less; Al/(In+Al+Ln) is 0.01 or more and 0.18 or less; Ln/(In+Al+Ln) is 0.01 or more and 0.18 or less. The atomic ratio of In, Al, and Ln in the oxide semiconductor thin film of the present invention is preferably in the following range: In/(In+Al+Ln) is 0.64 or more and 0.98 or less; Al/(In+Al+Ln) is 0.01 or more and 0.18 or less; Ln/( In+Al+Ln) is 0.01 or more and 0.18 or less. More preferably, the following range: In/(In+Al+Ln) is 0.70 or more and 0.96 or less; Al/(In+Al+Ln) is 0.02 or more and 0.15 or less; Ln/(In+Al+Ln) is 0.02 or more and 0.15 or less. The specific basis for the upper and lower limits of the atomic ratio of the oxide semiconductor thin film is the same as the specific basis for the upper and lower limits of the atomic ratio of the oxide sintered body of the present invention. The content (atomic ratio) of each metal element in the oxide semiconductor film can be determined by using ICP (Inductive Coupled Plasma) measurement or XRF (X-ray Fluorescence, X-ray fluorescence) measurement to determine the presence of each element The amount is determined by measuring. An induction plasma luminescence analyzer can be used for ICP measurement. For XRF measurement, a thin-film fluorescent X-ray analyzer (AZX400, manufactured by RIGAKU) can be used. In addition, SIMS (secondary ion mass spectroscopy) analysis using a sector-type dynamic secondary ion mass spectroscopy can also analyze the content (atomic ratio) of each metal element in the oxide semiconductor film with the same accuracy as the induced plasma luminescence analysis. The upper surface of a standard oxide film whose atomic ratio of metal elements measured by an induction plasma luminescence analyzer or a thin-film fluorescent X-ray analyzer is known is formed from the same material as the TFT element with a channel length. The electrode and drain electrode are used as the standard material. The oxide semiconductor layer is analyzed by the sector-type dynamic secondary ion mass spectrometer SIMS (IMS7f-Auto, manufactured by AMETEK) to obtain the mass spectrum intensity of each element. Calibration curve of known element concentration and mass spectrum intensity. Secondly, when calculating the atomic ratio of the oxide semiconductor film part of the actual TFT element based on the intensity of the mass spectrum obtained by the sector-type dynamic secondary ion mass spectrometer SIMS analysis, using the above calibration curve, it can be confirmed that the calculated atomic ratio is different. The atomic ratio of the oxide semiconductor film measured by a thin-film fluorescent X-ray analyzer or an induction plasma luminescence analyzer is within 2 atomic %. A thin film transistor (TFT) (hereinafter referred to as the TFT of the present invention) according to one embodiment of the present invention includes the above-mentioned oxide semiconductor thin film. An oxide semiconductor thin film can be preferably used as the channel layer, for example. The TFT of the present invention preferably has the following characteristics. The saturated mobility of the TFT is preferably 1.0 cm 2 /V∙s or more and 50.0 cm 2 /V∙s or less. By making the saturation mobility of TFT above 1.0 cm 2 /V∙s, it can drive the transmission transistor of CMOS image sensor or eliminate the transistor, liquid crystal display or organic EL (Electroluminescence) display. By making the saturation mobility of the TFT 50.0 cm 2 /V∙s or less, the off current can be 10 -12 A or less, and the on-off ratio can be 10 8 or more. The saturation mobility of the TFT can be obtained from the transfer characteristics when a drain voltage of 20 V is applied. Specifically, a graph of the transfer characteristic Id-Vg is created, the transconductance (Gm) of each Vg is calculated, and the saturation mobility is calculated from the equation of the saturation region. Id is the current between the source and drain electrodes, and Vg is the gate voltage when a voltage Vd is applied between the source and drain electrodes. The threshold voltage (Vth) is preferably -3.0 V or more and +3.0 V or less, more preferably -2.5 V or more and +2.5 V or less. If the threshold voltage is above -3.0 V and below +3.0 V, the turn-off current is small, and a thin film transistor with relatively large turn-on and turn-off can be formed, and it can be combined with a circuit composed of a bulk silicon wafer. drive. In the present invention, the threshold voltage (Vth) is defined as Vg at Id=10 -9 A according to the graph of the transfer characteristic. The on/off ratio is preferably 10 6 or more and 10 12 or less, more preferably 10 7 or more and 10 11 or less, and still more preferably 10 8 or more and 10 11 or less. If the on/off ratio is 10 6 or more, the liquid crystal display can be driven. If the on/off ratio is 10 12 or less, it is possible to drive organic EL panels with higher contrast, and the off current can be 10 -12 A or less. When the crystal or the situation of the transistor is eliminated, the image retention time can be prolonged or the sensitivity can be improved. In the present invention, the on/off ratio is calculated by setting the value of Id at Vg=-10 V as the off current value, and setting the value of Id at Vg=20 V as the on current value to calculate the ratio. ON/OFF]. The off current value is preferably 10 -11 A or less, more preferably 10 -12 A or less. If the cut-off current is 10 -11 A or less, it is possible to drive organic EL panels with high contrast. In addition, when used in the transmission transistor of CMOS image sensor or the situation of eliminating the transistor, the figure can be extended. The holding time of the image may increase the sensitivity. The defect density of the oxide semiconductor film used in the channel layer of the TFT of the present invention is preferably 5.0×10 16 cm -3 or less, more preferably 1.0×10 16 cm -3 or less. By making the defect density lower as described above, the mobility of the thin film transistor is further increased, and the stability during light irradiation and the stability to heat become higher, so that the TFT operates stably. The element structure of the TFT is not particularly limited, and various known element structures can be used. The TFT of the present invention can also be applied to various integrated circuits such as field-effect transistors, logic circuits, memory circuits, and differential amplifier circuits. Furthermore, in addition to field-effect transistors, it can also be applied to electrostatic induction transistors, Schottky barrier transistors, Schottky diodes, and resistance elements. Also, it can be used for electronic equipment such as display devices such as liquid crystal displays and organic electroluminescence displays. The case where the TFT of the present invention is used in a display device will be described. Fig. 1(A) is a top view of a display device including the TFT of the present invention, and Fig. 1(B) is a circuit of a pixel portion that can be used when a liquid crystal element using the TFT of the present invention is applied to the pixel portion of a display device 1(C) is a circuit diagram of a pixel portion that can be used when the organic EL element using the TFT of the present invention is applied to the pixel portion of a display device. The TFT of the present invention arranged in the pixel portion can be formed as already described. In addition, the TFT of the present invention is easy to be an n-channel type, so a part of the driving circuit that can be composed of an n-channel transistor in the driving circuit is formed on the same substrate as the transistor of the pixel portion. In this way, by using the transistor shown in the above embodiment for the transistor or the driving circuit of the pixel portion, a display device with higher reliability can be provided. The display device of Fig. 1(A) is an active matrix display device. The display device has a pixel portion 11, a first scanning line driving circuit 12, a second scanning line driving circuit 13, and a signal line driving circuit 14 on a substrate 10. In the pixel portion 11, a plurality of signal lines are extended from the signal line drive circuit 14, and a plurality of scan lines are extended from the first scan line drive circuit 12 and the second scan line drive circuit 13. In the intersection area between the scan line and the signal line, pixels with display elements are arranged in a matrix, respectively. The substrate 10 of the display device is connected to a timing control circuit (also referred to as a controller or a control IC (Integrated Circuit)) via a connection part such as FPC (Flexible Printed Circuit). In FIG. 1(A), the first scanning line driving circuit 12, the second scanning line driving circuit 13, and the signal line driving circuit 14 are formed on the same substrate 10 as the pixel portion 11. Therefore, the number of parts such as the driving circuit provided outside is reduced, so that the cost can be reduced. In addition, when a drive circuit is provided outside the substrate 10, it is necessary to extend the wiring, which increases the number of connections between the wirings. When driving circuits are provided on the same substrate 10, the number of connections between wirings can be reduced, so that reliability or yield can be improved. An example of the circuit configuration of the pixel portion is shown in FIG. 1(B). This example can be applied to the circuit of the pixel portion of the pixel portion of the VA (Vertical Aligned) type liquid crystal display device. The circuit of the pixel portion can be applied to a configuration having a plurality of pixel electrodes in one pixel. Each pixel electrode is connected to a different transistor, and each transistor is configured to be driven by a different gate signal. Thereby, the signal applied to each pixel electrode of the pixel of the multi-domain design can be independently controlled. The gate wiring 21 of the transistor 24 and the gate wiring 22 of the transistor 25 are separated in such a way that different gate signals can be given. On the other hand, the source electrode or drain electrode 23 that functions as a data line is commonly used in the transistor 24 and the transistor 25. The transistor 24 and the transistor 25 can appropriately use the TFT of the present invention. Thereby, a liquid crystal display device with higher reliability can be provided. The transistor 24 is electrically connected to the first pixel electrode, and the transistor 25 is electrically connected to the second pixel electrode. The first pixel electrode is separated from the second pixel electrode. The shape of the first pixel electrode and the second pixel electrode is not particularly limited. For example, the first pixel electrode may be V-shaped. The gate electrode of the transistor 24 is connected to the gate wiring 21, and the gate electrode of the transistor 25 is connected to the gate wiring 22. Different gate signals can be applied to the gate wiring 21 and the gate wiring 22 to make the operation timings of the transistor 24 and the transistor 25 different, and to control the alignment of the liquid crystal. The capacitor wiring 20, a gate insulating film functioning as a dielectric, and a capacitor electrode electrically connected to the first pixel electrode or the second pixel electrode may also form a holding capacitor. The multi-domain structure includes a first liquid crystal element 26 and a second liquid crystal element 27 in one pixel. The first liquid crystal element 26 is composed of a first pixel electrode, a counter electrode, and a liquid crystal layer between them, and the second liquid crystal element 27 is composed of a second pixel electrode, a counter electrode, and a liquid crystal layer between them. . The circuit of the pixel portion shown in FIG. 1(B) is not limited to this. For example, in the pixel shown in FIG. 1(B), a switch, a resistance element, a capacitance element, a transistor, a sensor, or a logic circuit can be newly added. Another example of the circuit configuration of the pixel is shown in FIG. 1(C). This example is the pixel structure of a display device using organic EL elements, and shows an example of using two n-channel transistors for one pixel. The oxide semiconductor film of the present invention can be used in the channel formation region of n-channel transistors. The circuit of the pixel section can be driven by a digital time gray scale. The switching transistor 31 and the driving transistor 32 can appropriately use the TFT of the present invention. Thereby, an organic EL display device with higher reliability can be provided. The circuit configuration of the pixel portion is not limited to the pixel configuration shown in FIG. 1(C). For example, it is also possible to add a switch, a resistance element, a capacitance element, a sensor, a transistor, or a logic circuit to the circuit of the pixel portion shown in FIG. 1(C). The operation of the solid-state imaging device including the TFT of the present invention will be described below. The CMOS (Complementary Metal Oxide Semiconductor) image sensor maintains the potential in the signal charge storage part, and outputs the potential to the solid-state imaging element of the vertical output line through the amplifying transistor. If there is a leakage current in the reset transistor and/or the transmission transistor included in the CMOS image sensor, the leakage current causes charging or discharging, and the potential of the signal charge storage unit changes. If the potential of the signal charge storage portion changes, the potential of the amplifying transistor also changes, becoming a value that deviates from the original potential, and the captured image is degraded. The effect of the operation when the TFT of the present invention is applied to the reset transistor and the transmission transistor of a CMOS image sensor will be described. Furthermore, the amplifying transistor can also be applied to either a thin film transistor or a bulk transistor. Fig. 2 is a diagram showing an example of the pixel structure of a CMOS image sensor. The pixel is composed of a photodiode 40 as a photoelectric conversion element, a transmission transistor 41, a reset transistor 42, an amplifier transistor 43, and various wirings, and a plurality of pixels are arranged in a matrix to form a sensor. In addition, a selective transistor that is electrically connected to the amplifying transistor 43 can also be provided. The "OS" written in the transistor symbol stands for Oxide Semiconductor, and "Si" stands for silicon, which stands for the best material when applied to each transistor. The photodiode 40 is connected to the source side of the transmission transistor 41, and a signal charge storage portion 44 (also called FD (Floating Diffusion): floating diffusion) is formed on the drain side of the transmission transistor 41. The signal charge storage part 44 is connected with the source of the reset transistor 42 and the gate of the amplifier transistor 43. As another configuration, the reset power supply line 46 may be deleted. For example, there is a method of connecting the drain of the reset transistor 42 to the power line 45 or the vertical output line 47 without connecting to the reset power line 46. [Examples] Hereinafter, examples will be given to explain the present invention more specifically, but the present invention is not limited to the following examples, and can be implemented with appropriate changes within the scope that can be adapted to the gist of the present invention. Any of these are included in the technical scope of the present invention. [Production of oxide sintered body] Examples 1 to 4 Samarium oxide powder, indium oxide powder, and aluminum oxide powder were weighed so as to become the ratio shown in Table 1 below, and put into a crucible made of polyethylene , The mixed powder was produced by mixing and pulverizing in a dry ball mill for 72 hours. The mixed powder is put into a mold, and a press-formed body is formed under a pressure of 500 kg/cm 2. The molded body was densified by CIP at a pressure of 2000 kg/cm 2. Next, the molded body was set in a normal-pressure baking furnace, and after it was kept at 350°C for 3 hours in an atmospheric atmosphere, the temperature was raised at 50°C/hour, and it was sintered at 1350°C for 40 hours. After that, it was left to cool to obtain oxides. Sintered body. [Characteristic evaluation of oxide sintered body] (1) XRD measurement For the obtained sintered body, the X-ray diffraction (XRD) of the sintered body was measured by an X-ray diffraction measuring device Smartlab under the following conditions. Analyze the obtained XRD pattern with the powder X-ray diffraction pattern comprehensive analysis software JADE6 (RIGAKU Co., Ltd.) to find the crystalline phase in the sintered body. The results are shown in Table 1. ∙Device: Smartlab (manufactured by RIGAKU Co., Ltd.) ∙X-ray: Cu-Kα line (wavelength 1.5418 Å) ∙2θ-θ reflection method, continuous scanning (2.0°/min) ∙Sampling interval: 0.02° ∙Slit DS (divergence) Slit), SS (scattering slit), RS (receiving slit): 1 mm In addition, the XRD patterns of the sintered bodies obtained in Examples 1 to 4 are shown in Figs. 1 to 4, respectively. It can be seen from FIGS. 1 to 4 that the sintered body obtained in each example has the perovskite phase and the bixbyite phase shown in Table 1. A sintered body (2) In 2 O 3 ratio of the presence of (wt%) obtained in the presence of In 2 O 3 ratio of (wt%) is usually obtained in the method. That is, the distribution of diffraction from X-rays is analyzed by JADE6, and the crystal structure of the sintered body is obtained by whole-pattern fitting (WPF). Furthermore, the abundance ratio of In 2 O 3 was obtained from the peak intensity ratio. The results are shown in Table 1. (3) sintered density (g / cm 3) Determination of a sintering density of the sintered obtained by the Archimedes method of the body (g / cm 3). The results are shown in Table 1. (4) Volume resistance (mΩ∙cm) Use resistivity meter Loresta AXMCP-T370 (manufactured by Mitsubishi Chemical Corporation) to measure the volume resistance (mΩ∙cm) of the obtained sintered body based on the four-point probe method (JISR 1637) . The results are shown in Table 1. [Table 1] [ Manufacturing of Sputtering Target] Example 5 Samarium oxide powder, indium oxide powder, and aluminum oxide powder were weighed in such a way as to become the ratio shown in Table 2 below, and put into a crucible made of polyethylene, by The dry ball mill performs mixing and pulverization for 72 hours to produce a mixed powder. The mixed powder was put into a mold, and a press-formed body was formed at a pressure of 500 kg/cm 2. The molded body was densified by CIP at a pressure of 2000 kg/cm 2. Next, the molded body was set in a normal-pressure baking furnace, and after maintaining it at 350°C for 10 hours in an atmospheric atmosphere, the temperature was raised at 50°C/hour and sintered at 1450°C for 40 hours. After that, it was left and cooled to obtain oxidation.物Sintered body. The characteristics of the sintered body were evaluated in the same manner as in Examples 1 to 4. The results are shown in Table 2. Grind and grind the obtained oxide sintered body to produce 4 inches ×5 mmt oxide sintered disc. Use molten indium to join the circular plate to a copper back plate with a thickness of 8 mm. [Evaluation of characteristics of sputtering target] (1) Warpage (mm) of the target The warpage (mm) of the obtained target was measured by the following method. The results are shown in Table 2. The target is placed on the fixed plate, and the gap is measured with a feeler gauge as the amount of warpage (mm). (2) Target bonding rate (%) The bonding rate (%) of the obtained target was measured by the following method. The results are shown in Table 2. The bonding rate is measured by the ultrasonic flaw detector for the unbonded void part, and the rate of the bonded part is calculated based on the target area. [Table 2] [Production of oxide semiconductor thin film] Example 6 Using the sputtering target obtained in Example 5, a channel-shaped metal mask was used on a silicon substrate with a thermal oxide film to form an oxide semiconductor layer by sputtering (Channel layer). The sputtering conditions are as follows: sputtering pressure = 0.5 Pa, oxygen partial pressure = 5%, substrate temperature = room temperature, and the film thickness is set to 50 nm. Secondly, a metal mask in the shape of the source and drain is used to form a 50 nm titanium electrode. Finally, annealing was performed in the air at 300°C for 1 hour to obtain a simple TFT with a bottom gate and a top contact with a channel length of 200 μm and a channel width of 1000 μm. As the annealing conditions, select appropriately at the range of 250°C to 450°C, 0.5 hour to 10 hours, while observing the carrier concentration of the channel part. As a result of evaluating the characteristics of the obtained TFT, mobility=14 cm 2 /V∙sec, the value of the gate voltage Vth>0.45 V when the current value exceeds 10 -8 A, S value (Swing Factor, floating factor) = 0.72. This TFT element was mounted in a CVD apparatus, and SiO 2 was formed into a film with a thickness of 100 nm at 350° C. as a passivation film. Then, the TFT characteristics after annealing at 300° C. in the atmosphere for 1 hour were evaluated. As a result, the mobility = 12 cm 2 /V·sec, the gate voltage Vth> 0.32 V when the current value exceeds 10 -8 A, and the S value (Swing Factor) = 0.78, which can roughly reproduce the characteristics before CVD. In addition, the cut-off current is 10 -12 A. According to these results, it can also be used for the transistor of the display device of the display, or the elimination transistor or the transmission transistor of the CMOS image sensor. Examples 7 to 9 The neodymium oxide powder, indium oxide powder, and alumina powder were weighed so as to become the ratio shown in Table 3 below, and put into a crucible made of polyethylene, and performed by a dry ball mill for 72 hours Mix and pulverize to produce mixed powder. The mixed powder was put into a mold, and a press-formed body was formed at a pressure of 500 kg/cm 2. The molded body was densified by CIP at a pressure of 2000 kg/cm 2. Next, the molded body was set in a normal-pressure baking furnace, and after it was kept at 350°C for 3 hours in an atmospheric atmosphere, the temperature was raised at 50°C/hour, and it was sintered at 1350°C for 40 hours. After that, it was left to cool to obtain oxides. Sintered body. With respect to the obtained oxide sintered body, the properties of the oxide sintered body were evaluated in the same manner as in Examples 1 to 4. The results are shown in Table 3. [table 3] [Production of Sputtering Target] Examples 10 to 12 were weighed so that the samarium oxide powder, indium oxide powder, and aluminum oxide powder were in the proportions shown in Table 4 below, and put them into a crucible made of polyethylene. The mixed powder was produced by mixing and pulverizing in a dry ball mill for 72 hours. The mixed powder was put into a mold, and a press-formed body was formed at a pressure of 500 kg/cm 2. The molded body was densified by CIP at a pressure of 1000 kg/cm 2. Next, the molded body was placed in a normal pressure sintering furnace, and then placed in the atmosphere at 350°C for 3 hours, then heated at 50°C/hour, sintered at 1420°C for 28 hours, and then left to cool to obtain oxides Sintered body. With respect to the obtained oxide sintered body, the properties of the oxide sintered body were evaluated in the same manner as in Examples 1 to 4. The results are shown in Table 4. In addition, the XRD patterns of the sintered bodies obtained in Examples 10 to 12 are shown in Figs. 9 to 11, respectively. According to Figs. 9-11, the sintered body obtained in each example has the perovskite phase and the bixbyite phase shown in Table 4. Grind and grind the obtained oxide sintered body to produce 4 inches ×5 mmt oxide sintered disc. Use molten metal indium to join the circular plate to a copper back plate with a thickness of 8 mmt. [Evaluation of Sputtering Target] (1) Warpage (mm) of the target The warpage (mm) of the obtained target was measured by the following method. The results are shown in Table 4. The target is placed on the fixed plate, and the gap is measured with a feeler gauge as the amount of warpage (mm). (2) Target bonding rate (%) The bonding rate (%) of the obtained target was measured by the following method. The results are shown in Table 4. The bonding rate is measured by the ultrasonic flaw detector for the unbonded part, and the rate of the bonded part is calculated based on the target area. [Table 4] [Production of oxide semiconductor thin film] Example 13 Using the sputtering target obtained in Example 11, a channel-shaped metal mask was used on a silicon substrate with a thermal oxide film to form an oxide semiconductor layer by sputtering (Channel layer). The sputtering conditions were as follows: sputtering pressure = 0.5 Pa, oxygen partial pressure = 1%, substrate temperature = room temperature, and the film thickness was set to 50 nm. Secondly, a 50 nm titanium electrode was formed using a metal mask in the shape of the source and drain. Finally, annealing was performed in air at 350°C for 1 hour to obtain a simple TFT with a bottom gate and top contact with a channel length of 200 μm and a channel width of 2000 μm. As the annealing conditions, select appropriately at the range of 250°C to 450°C, 0.5 hour to 10 hours, while observing the carrier concentration of the channel part. The XRD result of the thin film after heat treatment at 350°C for 1 hour was measured, and a bixbyite structure map represented by In 2 O 3 was obtained, and crystallization was confirmed. The result of the characteristic evaluation of the obtained TFT is that mobility=17 cm 2 /V·sec, the value of the gate voltage Vth>0.15 V where the current value exceeds 10 -8 A, and the S value (Swing Factor)=0.22. This TFT element was mounted in a CVD apparatus, and SiO 2 was formed into a thickness of 100 nm at 300° C. as a passivation film. Then, the TFT characteristics after annealing at 350° C. in the atmosphere for 1 hour were evaluated. As a result, the mobility = 21 cm 2 /V∙sec, the gate voltage Vth> 0.24 V with a current value exceeding 10 -8 A, and the S value (Swing Factor) = 0.26, which can roughly reproduce the characteristics before CVD. In addition, the off current is 10 -12 A or less. According to these results, it can also be used for the transistor of the display device of the display, or the elimination transistor or the transmission transistor of the CMOS image sensor. [Industrial Applicability] The oxide sintered body of the present invention can be used for sputtering targets, and for the production of thin-film transistors (TFT) oxide semiconductor films, etc., used in display devices such as liquid crystal displays or organic EL displays. it works. The embodiments and/or embodiments of the present invention have been described in detail above, but the industry can easily compare the exemplary embodiments and/or embodiments without substantially departing from the novel teachings and effects of the present invention. Various changes are made to the embodiment. Therefore, these various changes are included in the scope of the present invention. The entire contents of the specification of the Japanese application which became the basis of the priority of the Paris Convention in this case are quoted here.
