WO2018048154A1

WO2018048154A1 - Semiconductor light emitting device comprising light emitting structure

Info

Publication number: WO2018048154A1
Application number: PCT/KR2017/009649
Authority: WO
Inventors: 장종민; 김창연; 배선민; 임재희; 김재헌
Original assignee: 서울바이오시스 주식회사
Priority date: 2016-09-12
Filing date: 2017-09-04
Publication date: 2018-03-15

Abstract

A semiconductor light emitting device according to an embodiment of the present invention comprises: a light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, which are sequentially stacked; a first conductive pattern making ohmic contact with one surface of the second conductive semiconductor layer; and a second conductive pattern making ohmic contact with the one surface of the second conductive semiconductor layer and having a material different from that of the first conductive pattern, wherein the first conductive pattern makes contact with a portion of the second conductive pattern.

Description

Semiconductor light emitting device comprising a light emitting structure

The present application relates to an electronic device, and more particularly, to a semiconductor light emitting device including a light emitting structure.

A semiconductor light emitting diode (Light Emitting Diode) is a semiconductor device that converts electrical energy into light energy, and is composed of a compound semiconductor that emits light of a specific wavelength according to the energy band gap. Such semiconductor light emitting diodes have a number of advantages, such as long life, low power, and excellent initial driving characteristics, compared to filament-based light sources. For example, semiconductor light emitting diodes are being used in displays, backlight units for liquid crystal displays, lighting, and the like, and their use is expanding to various areas.

In particular, the application of the gallium nitride-based light emitting diode is proceeding to a large sized and high output product as well as small portable products, a light source suitable for the characteristics required for the product is required.

The present application is to provide a semiconductor light emitting device having an improved driving efficiency.

The present application is to provide a semiconductor light emitting device having improved characteristics while having a low forward voltage.

A semiconductor light emitting device according to an embodiment of the present invention, a light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer sequentially stacked; A first conductive pattern in ohmic contact with one surface of the second conductive semiconductor layer; And a second conductive pattern having ohmic contact to the one surface of the second conductive semiconductor layer and having a material different from that of the first conductive pattern. The first conductive pattern contacts a portion of the second conductive pattern.

In at least one example embodiment, the second conductive pattern may surround the first conductive pattern.

In an embodiment, the one surface of the second conductivity-type semiconductor layer is divided into a first portion and a second portion, the second conductive pattern is disposed on the first portion, and the second conductive pattern is the second conductive. The first conductive pattern may be adjacent to an edge of the type semiconductor layer and spaced apart from the edge than the second conductive pattern.

In example embodiments, the first conductive pattern may contact at least some of side surfaces of the second conductive pattern.

In example embodiments, the second conductive pattern may include a lower surface contacting the one surface of the second conductive semiconductor layer and an upper surface opposite to the lower surface, and the first conductive pattern may be one of the upper surfaces of the second conductive pattern. At least a portion of the first conductive layer may be in contact with a side surface of the second conductive pattern.

In an embodiment, in one surface of the second conductive semiconductor layer, the width of the second conductive pattern may be shorter than the width of the first conductive pattern.

In an embodiment, the thickness of the second conductive pattern may be thinner than the thickness of the first conductive pattern.

In at least some of the portions adjacent to the second conductive pattern of the first conductive pattern may have a slop.

In an embodiment, the portion of the first conductive pattern that is adjacent to the second conductive pattern may be thinner as it is closer to the second conductive pattern.

In an embodiment, the portion adjacent to the second conductive pattern of the first conductive pattern is divided into a first region and a second region between the first region and the second conductive pattern, and the first region is The closer to the second conductive pattern, the thinner it is, and the closer to the second conductive pattern, the thicker the second region.

In example embodiments, the first conductive pattern may include a reflective material, and the second conductive pattern may include a transparent material.

In example embodiments, the first conductive pattern may include a reflective metal, and the second conductive pattern may include Ni / Au, indium tin oxide (ITO), zinc-doped indium tin oxide (ZITO), zinc indium oxide (ZIO), Gallium Indium Oxide (GIO), Zinc Tin Oxide (ZTO), Fluorine-doped Tin Oxide (FTO), Zinc Oxide (ZnO), Gallium-doped Zinc Oxide (GZO), Aluminum-doped Zinc Oxide (AZO), and Transparent (TCO) Conductive Oxide) may include at least one material selected from.

In an embodiment, the first conductive pattern may include a reflective metal layer; And a cover metal layer covering the reflective metal layer, wherein the cover metal layer contacts the second conductive pattern, and the reflective metal layer is spaced apart from the second conductive pattern.

In example embodiments, the second conductive pattern may include a side surface facing the reflective metal layer, and the cover metal layer may contact at least a portion of the side surface of the second conductive pattern.

In example embodiments, the second conductive pattern may include a lower surface contacting the second conductive semiconductor layer and an upper surface opposite to the lower surface, and the cover metal layer may be formed with at least a portion of the upper surface of the second conductive pattern. You can contact more.

In example embodiments, a semiconductor light emitting device may be disposed on the first and second conductive patterns and the light emitting structure, and may include a first opening exposing a portion of the first conductive semiconductor layer, and the first and second conductive layers. A first passivation layer having a second opening exposing a portion of at least one of the patterns; An electrode layer disposed on the first passivation layer and in contact with the first conductive semiconductor layer through the first opening; A second passivation layer disposed on the electrode layer, the second passivation layer having a third opening exposing a portion of the electrode layer and a fourth opening exposing at least a portion of the portion exposed by the second opening; A first electrode pad contacting the electrode layer through the third opening; And a second electrode pad contacting at least one of the first and second conductive patterns through the fourth opening.

In example embodiments, the first conductive semiconductor layer may be an n-type semiconductor layer, and the second conductive semiconductor layer may be a p-type semiconductor layer.

A semiconductor light emitting device according to another embodiment of the present invention, the first conductive semiconductor layer; An active layer disposed on the first conductivity type semiconductor layer; A second conductivity type semiconductor layer disposed on the active layer; A first electrode layer contacting the first conductive semiconductor layer; And a second electrode layer contacting the second conductive semiconductor layer, wherein the second electrode layer contacts the second conductive semiconductor layer, the first conductive pattern, and the second conductive semiconductor layer. It may include a second conductive pattern surrounding at least a portion of the first conductive pattern.

A semiconductor light emitting device according to an embodiment of the present invention, a light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer sequentially stacked on a substrate; A first contact electrode layer disposed on the light emitting structure and contacting the first conductive semiconductor layer in a non-light emitting region; And a second contact electrode layer disposed on the light emitting structure, the second contact electrode layer contacting the second conductive semiconductor layer in a light emitting region, wherein the first contact electrode layer contacts the first conductive semiconductor layer. Is equal to or greater than 1.8% of the sum of the non-emission area and the emission area.

In an embodiment, the first contact area may be in the range of 1.8% to 4.5% of the sum.

In an embodiment, the first contact area may be 2.5% of the sum.

In an embodiment, the substrate may be a conductive substrate including GaN.

In example embodiments, a first portion of the portions in which the first contact electrode layer contacts the first conductive semiconductor layer may be positioned at the center of the emission area.

In example embodiments, a second portion of the portions in which the first contact electrode layer contacts the first conductive semiconductor layer may be positioned at an edge of the emission area.

In example embodiments, the second contact electrode layer may include: a reflective metal having ohmic contact with the second conductivity type semiconductor layer; And a conductive pattern having ohmic contact with the second conductive semiconductor layer and having a material different from that of the reflective metal, wherein the conductive pattern may contact at least a portion of the reflective metal.

In example embodiments, the conductive pattern may surround the reflective metal on the second conductive semiconductor layer.

In example embodiments, the light emitting structure may be divided into a mesa region and an etching region, wherein the first conductivity type semiconductor layer is positioned in the mesa region and the etching region, and the active layer and the second conductivity type semiconductor layer are in the mesa region. The light emitting region may be disposed on the first conductive semiconductor layer, and the emission region may correspond to a region where the active layer is located.

In example embodiments, the semiconductor light emitting device may further include a first passivation layer disposed on the light emitting structure and the second contact electrode layer and having a first opening exposing a portion of the first conductivity type semiconductor layer in the non-light emitting region. It may include. In this case, the first contact electrode layer may be disposed on the first passivation layer and contact the first conductive semiconductor layer through the first opening, and the first opening may be positioned at the center of the emission area.

In example embodiments, the first passivation layer may have a second opening exposing a portion of the second contact electrode layer. The semiconductor light emitting device may include a connection electrode layer disposed on the first passivation layer and contacting the second contact electrode layer through the second opening; A second passivation layer disposed on the first contact electrode layer and the connection electrode layer and having a third opening exposing a portion of the first contact electrode layer and a fourth opening exposing a portion of the connection electrode layer; A first electrode pad contacting the first contact electrode layer through the third opening; And a second electrode pad contacting the connection electrode layer through the fourth opening.

A semiconductor light emitting device according to another embodiment of the present invention is a substrate; A light emitting structure including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer sequentially stacked on the substrate, the light emitting structure being divided into a mesa region and an etching region; A first contact electrode layer disposed on the light emitting structure and contacting the first conductivity type semiconductor layer in the etching region; And a second contact electrode layer disposed on the light emitting structure and contacting the second conductive semiconductor layer in the mesa region. The first contact area where the first contact electrode layer contacts the first conductive semiconductor layer is equal to or greater than 1.8% of the sum of the mesa region and the etching region.

According to the present application, a semiconductor light emitting device having an improved driving efficiency is provided.

According to the present application, a semiconductor light emitting device having improved characteristics while having a low forward voltage is provided.

1 is a perspective view showing a semiconductor light emitting device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

3 is a perspective view illustrating a substrate, a first conductive semiconductor layer, an active layer, a second conductive semiconductor layer, and first and second conductive patterns of the semiconductor light emitting device of FIG. 1.

4 is a view illustrating a region A of FIG. 2.

5 is a cross-sectional view illustrating a semiconductor light emitting device according to another exemplary embodiment of the present invention.

6, 7, 8, 9, 10, and 11 are diagrams for describing a method of manufacturing the semiconductor light emitting device of FIG. 5.

12 is a cross-sectional view illustrating a semiconductor light emitting device according to another embodiment of the present invention.

13 is a cross-sectional view illustrating a semiconductor light emitting device according to another embodiment of the present invention.

14 is a cross-sectional view illustrating a semiconductor light emitting device according to another embodiment of the present invention.

15A and 15B are plan views illustrating a semiconductor light emitting device according to another exemplary embodiment of the present invention.

16 is a cross-sectional view taken along the line II-II 'of FIGS. 15A and 15B.

17 is a plan view illustrating a modified embodiment of the semiconductor light emitting device described with reference to FIGS. 15A and 15B.

18 is a cross-sectional view illustrating a semiconductor light emitting device according to another embodiment of the present invention.

19 is a cross-sectional view illustrating an application example of the semiconductor light emitting device of FIG. 18.

20 is a cross-sectional view illustrating a semiconductor light emitting device according to another embodiment of the present invention.

21 is a cross-sectional view illustrating an application example of the semiconductor light emitting device of FIG. 20.

22 is an exploded perspective view illustrating an embodiment of a semiconductor light emitting package including a semiconductor light emitting device.

FIG. 23 is an exploded perspective view illustrating a modified example of the semiconductor light emitting package of FIG. 22.

24 is an exploded perspective view illustrating another embodiment of a semiconductor light emitting package including a semiconductor light emitting device.

25 is a plan view of a semiconductor light emitting device according to an embodiment of the present invention.

FIG. 26 is a diagram illustrating an embodiment of a cross-sectional view taken along the line II ′ of FIG. 25.

27 is an experimental graph showing the relationship between the area of the light emitting area and the light intensity.

28 is an experimental graph illustrating a relationship between an area of first contact regions and a forward voltage of a semiconductor light emitting device.

FIG. 29 is a diagram illustrating another embodiment of a cross-sectional view taken along the line II ′ of FIG. 25.

FIG. 30 is an enlarged view illustrating region A of FIG. 29.

FIG. 31 is an experimental graph illustrating a relationship between an area of first contact regions and a forward voltage of a semiconductor light emitting device according to the exemplary embodiment of FIG. 30.

32, 33A, 33B, 34A, 34B, 35A, 35B, 36A, 36B, 37A, and 37B illustrate a method of manufacturing a semiconductor light emitting device according to the embodiment of FIG. 29. admit.

38 is a plan view of a semiconductor light emitting device according to another embodiment of the present invention.

39 is a plan view of a semiconductor light emitting device according to still another embodiment of the present invention.

40 is an exploded perspective view illustrating an embodiment of a semiconductor light emitting package including a semiconductor light emitting device.

41 is an exploded perspective view illustrating a modification of the semiconductor light emitting package of FIG. 40.

42 is an exploded perspective view illustrating another embodiment of a semiconductor light emitting package including a semiconductor light emitting device.

The description in the background of the technical field of the present invention is only for the purpose of understanding the background art of the technical idea of the present invention, and thus it can be understood as the content corresponding to the prior art known to those skilled in the art. none.

In the following description, for purposes of explanation, numerous specific details are set forth in order to assist in understanding the various embodiments. It may be evident, however, that various embodiments may be practiced without these specific details or in one or more equivalent ways. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various embodiments.

In the drawings, the size or relative size of layers, films, panels, regions, etc. may be exaggerated for clarity. Like reference numerals denote like elements.

Throughout the specification, when an element or layer is described as "connected" to another element or layer, it is not only directly connected, but also indirectly connected between other elements or layers in between. It also includes the case. However, if a part is described as "directly connected" to another part, it will mean that there is no other element between that part and the other part. "At least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" is X one, Y one, Z one, or two of X, Y, and Z or Any combination of the above will be understood (e.g., XYZ, XYY, YZ, ZZ). Here, "and / or" includes all combinations of one or more of the configurations.

Herein, terms such as first, second, etc. may be used to describe various elements, elements, regions, layers, and / or sections, but such elements, elements, regions, layers, and / or the like. Or sections are not limited to these terms. These terms are used to distinguish one element, element, region, layer, and / or section from another element, element, region, layer, and / or section. Thus, the first element, element, region, layer, and / or section in one embodiment may be referred to as the second element, element, region, layer, and / or section in another embodiment.

Spatially relative terms such as "below", "above", and the like may be used for illustrative purposes, thereby describing the relationship of one device or feature to another device (s) or feature (s) as shown in the figures. do. This is only used to indicate the relationship of one component to another component in the drawings, but does not mean an absolute position. For example, when the device shown in the figures is inverted, elements depicted as being "below" of other elements or features are located in the direction of "above" other elements or features. Thus, in one embodiment the term "below" may include both up and down. In addition, the device may be in other directions (eg, rotated 90 degrees or in other directions), and such spatially relative terms used herein are interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Throughout the specification, when a portion "contains" a certain component, it means that it may further include other components, except to exclude other components unless specifically stated otherwise. Unless otherwise defined, terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

1 is a perspective view illustrating a semiconductor light emitting device 100 according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the semiconductor light emitting device 100 may include a substrate 110, a semiconductor structure SS, and first and second electrode pads EP1 and EP2.

The substrate 110 may be an insulating or conductive substrate. For example, the substrate 110 may include GaN, sapphire, SiC, Si, MgAl ₂ O ₄ , MgO, LiAlO ₂ , LiGaO ₂ , and the like.

The semiconductor structure SS is disposed on the substrate 110. The semiconductor structure SS may include at least one groove GRV. The circular groove GRV shown in FIG. 1 is exemplary, and it will be understood that its position, size, and shape may be variously changed according to embodiments. The semiconductor structure SS is described in more detail with reference to FIG. 2.

First and second electrode pads EP1 and EP2 are disposed on the semiconductor structure SS. The first electrode pad EP1 is electrically connected to the first conductive semiconductor layer 120 through the semiconductor structure SS. The first electrode pad EP1 may be connected to the first electrode layer in the semiconductor structure SS. The first electrode layer may contact the first conductivity type semiconductor layer 120 in a region corresponding to the groove GRV. The second electrode pad EP2 is electrically connected to the second conductive semiconductor layer included in the semiconductor structure SS. Voltage or current may be applied to the first conductive semiconductor layer 120 and the second conductive semiconductor layer through the first and second electrode pads EP1 and EP2.

In an embodiment, the semiconductor light emitting device 100 may be a gallium nitride-based semiconductor light emitting device.

FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

Referring to FIG. 2, the semiconductor structure SS of FIG. 1 may include a first conductive semiconductor layer 120, an active layer 130, a second conductive semiconductor layer 140, and first and second conductive patterns 150. 160, a first passivation layer 170, a first electrode layer 180, and a second passivation layer 190.

The first conductive semiconductor layer 120 is a nitride semiconductor containing an n-type impurity. The composition Al _x In _y Ga _1-xy N (0 ≦ x <1, 0 ≦ y <1, 0 ≦ x + y < 1) can be satisfied. For example, the first conductivity type semiconductor layer 120 may include GaN, AlGaN, InGaN, AlInGaN, or the like. For example, the n-type impurity may be Si.

In an embodiment, when the substrate 110 is a conductive substrate including GaN, the impurity concentration of the first conductive semiconductor layer 120 may be higher than that of the substrate. In this case, the substrate 110 may function as a current path together with the first conductivity-type semiconductor layer 120. Current transmitted to the first electrode layer 180 through the second conductive semiconductor layer 140, the active layer 130, and the first conductive semiconductor layer 120 may flow more smoothly by the substrate 110. .

The active layer 130 is disposed on the first conductivity type semiconductor layer 120. In an embodiment, the active layer 130 may have a multi quantum well (MQW) structure in which a quantum well layer and a quantum barrier layer are alternately stacked. For example, each of the quantum well layer and the quantum barrier layer includes materials having different compositions, and the formula In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≤1) may be satisfied. The quantum well layer may include a highly volatile element such as indium (In). For example, the quantum well layer may include In _x Ga _1-x N (0 <x ≦ 1), and the quantum barrier layer may include GaN or AlGaN. In an embodiment, the active layer 130 may have a single quantum well (SQW) structure.

The second conductivity type semiconductor layer 140 is disposed on the active layer 130. The second conductivity-type semiconductor layer 140 is a p-type nitride semiconductor, which satisfies the compositional formula Al _x In _y Ga _1-xy N (0 ≦ x <1, 0 ≦ y <1, 0 ≦ x + y <1). Can be. For example, the second conductivity type semiconductor layer 140 may include AlGaN, GaN, or the like. For example, the p-type impurity may be Mg. In an embodiment, the second conductivity-type semiconductor layer 140 may have a single layer structure or a multilayer structure. When the second conductivity-type semiconductor layer 140 has a multilayer structure, the second conductivity-type semiconductor layer 140 includes a p-type AlGaN layer, a low concentration p-type GaN layer, and a high concentration p-type GaN layer serving as an electron blocking layer. It may include.

The active layer 130 and the second conductive semiconductor layer 140 may be patterned to expose the first conductive semiconductor layer 120 in a region corresponding to the groove GRV (see FIG. 1). It will be appreciated that the position, size, and shape of the opening exposing the first conductivity type semiconductor layer 120 may be changed in various ways.

In an embodiment, the exposed portion of the first conductivity type semiconductor layer 120 may be etched to have a thickness thinner than that of the other portions of the first conductivity type semiconductor layer 120.

The first conductive semiconductor layer 120, the active layer 130, and the second conductive semiconductor layer 140 may form a light emitting structure (ES). When a voltage or current is applied to the light emitting structure ES through the first and second conductivity-type semiconductor layers 120 and 140, the active layer 130 will emit light.

According to an embodiment of the present invention, the first and second

conductive patterns

150 and 160 including different materials are disposed on the second conductive semiconductor layer 140. The first and second

conductive patterns

150 and 160 extend at the same height h from the surface of the substrate 110 in the surface direction (ie, the X direction and the Y direction) of the substrate 110. The first and second

conductive patterns

150 and 160 may function as the second electrode layer 165 contacting the second conductive semiconductor layer 140.

In an embodiment, the first conductive pattern 150 may include a reflective metal. The reflective metal will reflect light emitted from the active layer 130. By providing the reflective metal, the semiconductor light emitting device 100 will emit light in a direction including a vector component in a direction opposite to the Z direction or in a direction opposite to the Z direction. For example, light generated in the active layer 130 may be emitted toward the substrate 110.

The second conductive pattern 160 contacts the second conductive semiconductor layer 140 as well as the first conductive pattern 150. The second conductive pattern 160 is formed in an area adjacent to an edge of the upper surface of the second conductive semiconductor layer 140, and the first conductive pattern 150 is second conductive than the second conductive pattern 160. It may be spaced apart from the edge of the upper surface of the type semiconductor layer 140. On the top surface of the second conductive semiconductor layer 140, the width W1 of the second conductive pattern 160 may be shorter than the width W2 of the first conductive pattern 150.

The second conductive pattern 160 includes a material different from the first conductive pattern 150. The second conductive pattern may include a transparent material. For example, the second conductive pattern 160 may include Ni / Au, indium tin oxide (ITO), zinc-doped indium tin oxide (ZITO), zinc indium oxide (ZIO), gallium indium oxide (GIO), and zinc (ZTO) TinOxide, Fluorine-doped Tin Oxide (FTO), Zinc Oxide (ZnO), Gallium-doped Zinc Oxide (GZO), Aluminum-doped Zinc Oxide (AZO), Transparent Conductive Oxide (TCO), etc. Can be.

In some example embodiments, the first and second

conductive patterns

150 and 160 may have ohmic contacts with the second conductive semiconductor layer 140.

The first passivation layer 170 is disposed on the first conductive semiconductor layer 120, the active layer 130, the second conductive semiconductor layer 140, and the first and second

conductive patterns

150 and 160. do. The first passivation layer 170 has a first opening OP1 exposing the first conductivity type semiconductor layer 120 in a region corresponding to the groove GRV. The first passivation layer 170 has a second opening OP2 exposing at least one of the first and second

conductive patterns

150 and 160. Hereinafter, the second opening OP2 is illustrated as exposing the first conductive pattern 150.

The first electrode layer 180 is disposed on the first passivation layer 170 and the first conductivity type semiconductor layer 120. The first passivation layer 170 allows the first electrode layer 180 to contact the active layer 130, the second conductivity type semiconductor layer 140, and the first and second

conductive patterns

150 and 160. Is blocked. The first electrode layer 180 may contact the first conductive semiconductor layer 120 through the first opening OP1. For example, the first electrode layer 180 may have an ohmic contact with the first conductive semiconductor layer 120 exposed by the first opening OP1.

In an embodiment, the first electrode layer 180 may include at least one of materials such as Au, W, Pt, Si, Ir, Ag, Cu, Ni, Ti, Cr, and alloys thereof.

The second passivation layer 190 is disposed on the first electrode layer 180. The second passivation layer 190 includes a third opening OP3 exposing the first electrode layer 180. In addition, the second passivation layer 190 may include a fourth opening OP4 exposing a portion of the first conductive pattern 150 exposed by the second opening OP2. The fourth opening OP4 may cover a portion of the second opening OP2.

In some example embodiments, each of the first and second passivation layers 170 and 190 may include SiO ₂ , SiN, SiO _x N _y , TiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , TiN, AlN, ZrO ₂ , TiAlN, It may be formed of an insulating material such as TiSiN. In an embodiment, the first and second passivation layers 170 and 190 may be formed as a distributed Bragg reflector (DBR) in which a low refractive material layer and a high refractive material layer of the insulating material are alternately stacked. For example, the first and second passivation layers 170 and 180 may be a multilayer structure including insulating reflecting layers having high reflectivity formed by stacking layers such as SiO ₂ / TiO ₂ or SiO ₂ / Nb ₂ O ₅ . have.

The first and second electrode pads EP1 and EP2 are disposed on the second passivation layer 190. The first electrode pad EP1 may contact the first electrode layer 180 through the third opening OP3. The first electrode pad EP1 may be electrically connected to the first conductive semiconductor layer 120 through the first electrode layer 180. The second electrode pad EP2 may contact the first conductive pattern 150 through the fourth opening OP4. Since the first conductive pattern 150 contacts not only the second conductive semiconductor layer 140 but also the second conductive pattern 160, the second electrode pad EP2 contacts the first and second conductive patterns 150 and 160. ) May be electrically connected to the second conductivity-type semiconductor layer 140.

Within the range in which the embodiment of the present invention is employed, it will be understood that the plan view along the X direction and the Y direction of the semiconductor light emitting device 100 may be variously modified. For example, the position, size, and shape of the semiconductor structure SS (see FIG. 1) and the grooves GRV (see FIG. 1) may be changed. For example, the position, size, and shape of the first and second electrode pads EP1 and EP2 may be changed.

3 illustrates a substrate 110, a first conductive semiconductor layer 120, an active layer 130, a second conductive semiconductor layer 140, and first and second conductive layers of the semiconductor light emitting device 100 of FIG. 1. A perspective view showing the

patterns

150 and 160. 4 is a view illustrating a region A of FIG. 2.

Referring to FIG. 3, first and second

conductive patterns

150 and 160 are stacked on an upper surface of the second conductive semiconductor layer 140. The first and second

conductive patterns

150 and 160 have openings in a region corresponding to the groove GRV of FIG. 1.

The second conductive pattern 160 is adjacent to the edge EG of the upper surface of the second conductive semiconductor layer 140, and the first conductive pattern 150 is the second conductive semiconductor layer than the second conductive pattern 160. It may be spaced apart from the edge EG of the upper surface of 140.

The first and second

conductive patterns

150 and 160 constitute the second electrode layer 165. The second conductive pattern 160 may extend along the edge of the second electrode layer 165, and the first conductive pattern 150 may be surrounded by the second conductive pattern 160. Accordingly, the upper surface of the second conductivity type semiconductor layer 140 may contact the second electrode layer 165 in a large area. The current from the power source is efficiently diffused by the second conductive pattern 160, and the concentration of the current density in the first conductive pattern 150 is prevented. Thus, the semiconductor light emitting device 100 having improved driving performance and driving efficiency is provided.

It is assumed that the second conductive pattern 160 is removed or the second conductive pattern 160 is replaced with an insulating material such as SiO ₂ or SiN _x . Referring to FIG. 4, current from a power source may include a first conductive pattern 150, a second conductive semiconductor layer 140, an active layer 130, a first conductive semiconductor layer 120, and a first electrode layer 180. ) May flow through the first current path CP1.

According to an embodiment of the present invention, the first conductive pattern 150 and the second conductive pattern 160 contact the second conductive semiconductor layer 140. The current from the power source is not only the first current path CP1 but also the second conductive pattern 160, the second conductive semiconductor layer 140, the active layer 130, the first conductive semiconductor layer 120, and the first conductive path 160. It may flow through the second current path CP2 formed by the first electrode layer 180. Accordingly, the current from the power source can flow smoothly through the first and second current paths CP1 and CP2.

The distance between the second conductive pattern 160 and the first electrode layer 180 is shorter than the distance between the first conductive pattern 150 and the first electrode layer 180. This may mean that the second current path CP2 transfers the current more smoothly. By providing the second current path CP2 as well as the first current path CP1, driving performance and driving efficiency of the semiconductor light emitting device 100 may be further improved.

5 is a cross-sectional view illustrating a semiconductor light emitting device 200 according to another embodiment of the present invention.

Referring to FIG. 5, the semiconductor light emitting device 200 may include a substrate 210, a first conductive semiconductor layer 220, an active layer 230, a second conductive semiconductor layer 240, and first and second conductive patterns.

Fields

250 and 260, a first passivation layer 270, a first electrode layer 280, a second passivation layer 290, and first and second electrode patterns EP1 and EP2.

The substrate 210, the first conductive semiconductor layer 220, the active layer 230, the second conductive semiconductor layer 240, the first passivation layer 270, the first electrode layer 280, and the second passivation layer ( 290, and the first and second electrode patterns EP1 and EP2 may include the substrate 110, the first conductive semiconductor layer 120, the active layer 130, and the second conductive semiconductor described with reference to FIG. 2. The same as the layer 140, the first passivation layer 170, the first electrode layer 180, the second passivation layer 190, and the first and second electrode patterns EP1 and EP2 are described. In the following, redundant description is omitted.

The second conductive pattern 260 of the second electrode layer 265 may have a thickness thinner than that of the first conductive pattern 250.

When the thickness THC2 of the second conductive pattern 260 is relatively thick, light generated from the active layer 230 may be absorbed by the second conductive pattern 260 to reduce the light efficiency of the semiconductor light emitting device 200. have. When the thickness THC2 of the second conductive pattern 260 is thin, the amount of light absorbed by the second conductive pattern 260 may be reduced, thereby improving light efficiency of the semiconductor light emitting device 200. According to an embodiment of the present disclosure, the thickness THC2 of the second conductive pattern 260 may be thinner than at least the thickness THC1 of the first conductive pattern 250.

The first and second

conductive patterns

250 and 260 may have appropriate thicknesses THC1 and THC2 so that the first and second

conductive patterns

250 and 260 have appropriate resistance values to efficiently transfer voltage or current. Can be adopted. For example, the thickness THC1 of the first conductive pattern 250 may be about 1 to 1.5 microns, and the thickness THC2 of the second conductive pattern 260 may be about 1000 angstroms. .

In an embodiment, a portion of the first conductive pattern 250 adjacent to the second conductive pattern 260 may have a slop (x, slop). For example, a portion of the first conductive pattern 250 that is adjacent to the second conductive pattern 260 may become thinner as it is adjacent to the second conductive pattern 260. For example, a portion of the first conductive pattern 250 adjacent to the second conductive pattern 260 is divided into a first region and a second region between the first region and the second conductive pattern 260. The first region may be thinner as it is adjacent to the second conductive pattern 260, and the second region may be thicker as it is adjacent to the second conductive pattern 260. To this end, the first conductive pattern 250 may be deposited by a sputtering process. In addition, it will be understood that various shapes in which a portion adjacent to the second conductive pattern 260 of the first conductive pattern 250 may have a slope may be adopted.

If a sharp step exists in a region where the first and second

conductive patterns

250 and 260 contact each other, cracks may occur in the layers disposed on the first and second

conductive patterns

250 and 260. According to an embodiment of the present invention, the portion of the first conductive pattern 250 adjacent to the second conductive pattern 260 has a slop, so that the layers disposed on the first and second

conductive patterns

250 and 260 are disposed. No cracks will occur. Accordingly, the reliability of the layers disposed on the first and second

conductive patterns

250 and 260 is improved.

6 to 11 are diagrams for describing a method of manufacturing the semiconductor light emitting device 200 of FIG. 5.

Referring to FIG. 6, a first conductive semiconductor layer 220, an active layer 230_1, a second conductive semiconductor layer 240_1, and a second conductive layer 260_1 are formed on the substrate 210.

The substrate 210 may be provided as a substrate for growing a semiconductor, and may include at least one selected from GaN, sapphire, SiC, Si, MgAl ₂ O ₄ , MgO, LiAlO ₂ , LiGaO ₂ , and the like. In an embodiment, a plurality of irregularities may be formed on the growth surface of the substrate 210. Such irregularities may be provided selectively. By these irregularities, the crystallinity and the light emission efficiency of the semiconductor layers on the growth surface can be improved. The irregularities may be formed in various shapes such as a dome shape, a rectangle, and a triangle.

The first conductive semiconductor layer 220 and the second conductive semiconductor layer 240_1 may be n-type semiconductor layers and p-type semiconductor layers, respectively.

The second conductive layer 260_1 may lower the resistance of the interface between the second conductive semiconductor layer 240_1 and the second conductive layer 260_1 according to rapid thermal annealing. For example, the second conductive layer 260_1 may have an ohmic contact with the second conductive semiconductor layer 240_1.

In an embodiment, the second conductive layer 260_1 may include Ni / Au, indium tin oxide (ITO), zinc-doped indium tin oxide (ZITO), zinc indium oxide (ZIO), gallium indium oxide (GIO), and zinc (ZTO) TinOxide, Fluorine-doped Tin Oxide (FTO), Zinc Oxide (ZnO), Gallium-doped Zinc Oxide (GZO), Aluminum-doped Zinc Oxide (AZO), or Transparent Conductive Oxide (TCO) .

Referring to FIG. 7, a portion of the first conductive semiconductor layer 220, the active layer 230_1, the second conductive semiconductor layer 240_1, and the second conductive layer 260_1 may be etched to form at least one etching region ( At least one mesa region M defined by E) and the etching region E is defined. Accordingly, the active layer 230, the second conductive semiconductor layer 240, and the second conductive layer 260_2 are disposed in the mesa region M. FIG.

Referring to FIG. 8, the photoresist pattern PR is formed in a portion of the mesa region M and the etching region E. Referring to FIG. For example, forming the photoresist pattern PR may coat the photoresist, selectively remove the photoresist in accordance with exposure and development to form the photoresist pattern PR, and then use a plasma to form a conductive layer ( 260_2) may further include removing the remaining photoresist.

In an embodiment, the angle y formed between the inside of the photoresist pattern PR and the top surface of the second conductive layer 260_2 may be an obtuse angle. For example, the photoresist pattern PR may have an inverse taper shape.

9, a portion of the second conductive layer 260_2 corresponding to the opening of the photoresist pattern PR is etched to form a second conductive pattern 260.

Next, referring to FIG. 10, the first conductive pattern 250 is formed in a region corresponding to the opening of the photoresist pattern PR. A first material corresponding to the first conductive pattern 250 is deposited by, for example, a sputtering process, and is left on the photoresist pattern PR and the photoresist pattern PR according to a lift-off process. The material corresponding to the conductive pattern 250 may be removed.

According to an angle y of the photoresist pattern PR (refer to FIG. 8), a portion of the first conductive pattern 250 adjacent to the second conductive pattern 260 may have a slop x. For example, the first conductive pattern 250 may have a taper shape.

In addition to the processes described with reference to FIGS. 8 through 10, it will be appreciated that various ways for causing the first conductive pattern 250 to have a slope x may be used.

Referring to FIG. 11, a first passivation layer 270, an electrode layer 280, and a second passivation layer 290 are formed. Thereafter, first and second electrode patterns EP1 and EP2 (see FIG. 5) are formed.

12 is a cross-sectional view illustrating a semiconductor light emitting device 300 according to another embodiment of the present invention.

Referring to FIG. 12, the semiconductor light emitting device 300 may include a substrate 310, a first conductive semiconductor layer 320, an active layer 330, a second conductive semiconductor layer 340, and first and second conductive patterns.

Fields

350 and 360, a first passivation layer 370, a first electrode layer 380, a second passivation layer 390, and first and second electrode patterns EP1 and EP2.

The first conductive pattern 350 may have a multilayer structure including a reflective metal layer 351 and a cover metal layer 352. The cover metal layer 352 may prevent deformation of characteristics of the reflective metal layer 351 during the manufacturing process of the semiconductor light emitting device 100. The cover metal layer 352 may function as a barrier layer to prevent the material of the reflective metal layer 351, for example, Ag or Al, from being diffused to another layer by high heat during the manufacturing process. For example, the cover metal layer 352 may prevent the material of the reflective metal layer 351 from being diffused into the first electrode layer 380 to short-circuit the reflective metal layer 351 and the first electrode layer 380. can do. In an embodiment, the reflective metal may include Ag and Al, and the cover metal may include Ni, Ti, Au, Cr, Pt, W, and TiW.

The reflective metal layer 351 is spaced apart from the second conductive pattern 360 by a first distance D1. The cover metal layer 352 covers the reflective metal layer 351 and extends to the second conductive pattern 360. That is, the cover metal layer 352 contacts the second conductive pattern 360. In an embodiment, as shown in FIG. 12, the cover metal layer 352 may contact at least a portion of the side surfaces 360a of the second conductive pattern 360. The reflective metal layer 351 may have a thickness greater than that of the second conductive pattern 360.

13 is a cross-sectional view illustrating a semiconductor light emitting device 400 according to another exemplary embodiment of the present disclosure.

Referring to FIG. 13, the semiconductor light emitting device 400 may include a substrate 410, a first conductive semiconductor layer 420, an active layer 430, a second conductive semiconductor layer 440, and first and second conductive patterns.

Fields

450 and 460, a first passivation layer 470, a first electrode layer 480, a second passivation layer 490, and first and second electrode patterns EP1 and EP2.

The first conductive pattern 450 includes a reflective metal layer 451 and a cover metal layer 452. The reflective metal layer 451 is spaced apart from the second conductive pattern layer 460 by a second distance D2. The cover metal layer 452 covers the reflective metal layer 451 and extends to the second conductive pattern 360. According to the present exemplary embodiment, the cover metal layer 452 contacts at least part of the upper surface 460b as well as the side surface 460a of the second conductive pattern 460. The first conductive pattern 450 may contact the second conductive pattern 460 in a larger area. Accordingly, the current applied to the first conductive pattern 450 may be efficiently distributed to the second conductive pattern 460.

14 is a cross-sectional view illustrating a semiconductor light emitting device 500 according to another embodiment of the present invention.

Referring to FIG. 14, the semiconductor light emitting device 500 may include a substrate 510, a first conductive semiconductor layer 520, an active layer 530, a second conductive semiconductor layer 540, and first and second conductive patterns.

Fields

550 and 560, a first passivation layer 570, a first electrode layer 580, a second passivation layer 590, and first and second electrode patterns EP1 and EP2.

The substrate 510, the first conductive semiconductor layer 520, the active layer 530, the second conductive semiconductor layer 540, and the first and second

conductive patterns

550 and 560 are described with reference to FIG. 2. The substrate 110, the first conductive semiconductor layer 120, the active layer 130, the second conductive semiconductor layer 140, and the first and second

conductive patterns

150 and 160 are described in the same manner. . In the following, redundant description is omitted.

The first passivation layer 570 is disposed on the first conductive semiconductor layer 520, the active layer 530, the second conductive semiconductor layer 540, and the first and second

conductive patterns

550 and 560. do. The first passivation layer 570 includes a fifth opening OP5 exposing the first conductivity type semiconductor layer 520 and a sixth opening OP6 exposing the first conductive pattern 550.

The first electrode layer 580 is disposed on the first passivation layer 570 and the first conductivity type semiconductor layer 520. The first electrode layer 580 contacts the first conductive semiconductor layer 520 through the fifth opening OP5.

According to the present embodiment, a contact metal layer 585 is further provided. The contact metal layer 585 is disposed on the first passivation layer 570 and contacts the first conductive pattern 550 through the sixth opening OP6. By using the contact metal layer 585, the first conductive pattern 550 may be efficiently connected to the second electrode pad EP2.

The contact metal layer 585 is electrically separated from the first electrode layer 580. In the process of manufacturing the semiconductor light emitting device 500, the contact metal layer 585 may be formed by the same process as the first electrode layer 580. For example, the contact metal layer 585 may include at least one of materials such as Al, Au, W, Pt, Si, Ir, Ag, Cu, Ni, Ti, Cr, and alloys thereof, similarly to the first electrode layer 580. It may include.

The second passivation layer 590 is disposed on the first passivation layer 570, the first electrode layer 580, and the contact metal layer 585. The second passivation layer 590 includes a seventh opening OP7 exposing the first electrode layer 580 and an eighth opening OP8 exposing the contact metal layer 585.

The first electrode pad EP1 contacts the first electrode layer 580 through the seventh opening OP7, and the second electrode pad EP2 contacts the contact metal layer 585 through the eighth opening OP8. do.

15A and 15B are plan views illustrating a semiconductor light emitting device 600 according to another exemplary embodiment of the present invention. 16 is a cross-sectional view taken along the line II-II 'of FIGS. 15A and 15B. In FIG. 15B, the active layer 630, the second conductivity type semiconductor layer 640, the first and second

conductive patterns

650 and 660, and the first passivation layer 670 of FIG. 15A may be used for ease of recognition. It is shown as a dotted line.

First, referring to FIGS. 15A and 16, the first conductive semiconductor layer 620, the active layer 630, and the second conductive semiconductor layer 640 are sequentially stacked on the substrate 610. The first conductive semiconductor layer 620, the active layer 630, and the second conductive semiconductor layer 640 constitute a light emitting structure ES.

Mesa region M provided with the active layer 630 and the second conductivity type semiconductor layer 640, and an etching region E, which is a region other than the mesa region M, are defined.

The shape of the mesa region M and the etching region E may be changed in various ways. The mesa region M may be disposed in the central region CNTR, and the etching region E may be disposed in the central portion CNTR and the peripheral region PRR. The etching region E in the central portion CNTR may be defined by the ninth opening OP9. In an embodiment, the active layer 630 and the second conductive semiconductor layer 640 have at least one ninth opening OP9 that exposes the first conductive semiconductor layer 620 in the center portion CNTR. The ninth opening OP9 may extend from the central portion CNTR to the peripheral portion PRR.

First and second

conductive patterns

650 and 660 including different materials are disposed on the second conductive semiconductor layer 640. The first and second

conductive patterns

650 and 660 are provided as the second electrode layer 665 contacting the second conductive semiconductor layer 640. The second conductive pattern 660 may surround the first conductive pattern 650.

The first passivation layer 670 is disposed on the first conductive semiconductor layer 620, the active layer 630, the second conductive semiconductor layer 640, and the first and second

conductive patterns

650 and 660. do. The first passivation layer 670 covers a portion of the ninth opening OP9 but exposes the tenth opening OP10 exposing the first conductive semiconductor layer 620 and the first conductive pattern 650. It has 11 openings OP11.

15B and 16, a first electrode layer 680 and a contact metal layer 685 are disposed on the first passivation layer 670. The first electrode layer 680 contacts the first conductive semiconductor layer 620 through the tenth opening OP10. The contact metal layer 685 contacts the first conductive pattern 650 through the eleventh openings OP11. The contact metal layer 685 will be separated from the first electrode layer 680. The contact metal layer 685 may be formed through the same process as the first electrode layer 680.

The second passivation layer 690 is disposed on the first passivation layer 690, the first electrode layer 680, and the contact metal layer 685. The second passivation layer 690 has a twelfth opening OP12 exposing the first electrode layer 680 and a thirteenth opening OP13 exposing the contact metal layer 685.

The first electrode pad EP1 contacts the first electrode layer 680 through the twelfth opening OP12, and the second electrode pad EP2 contacts the contact metal layer 685 through the thirteenth opening OP13. do.

In FIG. 16, the first and second

conductive patterns

650 and 660 are shown to have the same thickness. However, this is for convenience of recognition and the technical spirit of the present invention is not limited thereto. For example, the second conductive pattern 660 may have a lower thickness than the first conductive pattern 650 as described with reference to FIG. 5. In this case, the first conductive pattern 650 may have a slop in an area adjacent to the second conductive pattern 660.

17 is a plan view illustrating a modified embodiment of the semiconductor light emitting device 600 described with reference to FIGS. 15A and 15B. In FIG. 17, for convenience of description, the first conductive semiconductor layer 620, the active layer 630, the second conductive semiconductor layer 640, the first and second

conductive patterns

650 and 660 ′, And only the first passivation layer 670 is shown.

Referring to FIG. 17, the second conductive pattern 660 ′ may partially surround the first conductive pattern 650 on the top surface of the second conductive semiconductor layer 640. The central portion CNTR of the semiconductor light emitting device may be divided into a first portion RG1 and a second portion RG2. The second conductive pattern 660 ′ is disposed on the second conductive semiconductor layer 640 of the first portion RG1, and is not provided on the second conductive semiconductor layer 640 of the second portion RG2. You may not. In the first portion RG1, the second conductive pattern 660 ′ may be disposed in an area adjacent to an edge of the top surface of the second conductive semiconductor layer 640 than the first conductive pattern 650.

The first portion RG1 and the second portion RG2 may be partitioned in various ways. In the center portion CNTR, a portion of the first conductive semiconductor layer 620 exposed by the first passivation layer 670 having a low area may be defined as the first portion RG1. In the center portion CNTR, a portion of the first conductive semiconductor layer 620 exposed by the first passivation layer 670 having a high proportion may be defined as the second portion RG2. In this case, the current flowing through the second electrode layer 665 ′ of the first portion RG1 may not be diffused and transferred smoothly due to, for example, a distance from the first conductive semiconductor layer 620. have. According to the present exemplary embodiment, the second conductive pattern 660 ′ is provided in at least the first portion RG1, so that not only the first current path CP1 (see FIG. 4) but also the second current path in the first portion RG1. (CP2, see FIG. 4) can be formed.

18 is a cross-sectional view illustrating a semiconductor light emitting device 700 according to another exemplary embodiment of the present invention.

Referring to FIG. 18, the semiconductor light emitting device 700 may include a substrate 710, a first conductive semiconductor layer 720, an active layer 730, a second conductive semiconductor layer 740, and first and second conductive patterns.

Fields

750, 760, and electrode layer 780.

The light emitting structure including the first conductivity type semiconductor layer 720, the active layer 730, and the second conductivity type semiconductor layer 740 is, for example, the active layer 730 and the second conductivity type semiconductor layer by mesa etching. As the partial region of 740 is removed, the first conductivity-type semiconductor layer 720 may be partially exposed. In the exposed region, the first conductivity-type semiconductor layer 720 may contact the electrode layer 780.

The electrode layer 780 may include a material such as Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, or the like, and may have a single layer or two or more layers. The electrode layer 780 may have an ohmic contact with the first conductivity type semiconductor layer 720.

First and second

conductive patterns

750 and 760 may be stacked on the second conductive semiconductor layer 740. The first and second

conductive patterns

750 and 760 may include different materials, and the second conductive pattern 760 may surround the first conductive pattern 750.

In FIG. 18, the first and second

conductive patterns

750 and 760 are shown to have the same thickness. However, the technical idea of the present invention is not limited thereto. For example, the second conductive pattern 760 may have a lower thickness than the first conductive pattern 750. In this case, the first conductive pattern 750 may have a slop in an area adjacent to the second conductive pattern 760.

19 is a cross-sectional view illustrating an application example of the semiconductor light emitting device 700 of FIG. 18.

Referring to FIG. 19, a first bump 701 disposed in a partially exposed region of the first conductive semiconductor layer 720 and contacted with the electrode layer 780, and a first electrode connected to the first bump 701 may be used. Pad 703 may be provided. In addition, a second bump 702 contacted to at least one of the first and second

conductive patterns

750 and 760, and a second electrode pad 704 connected to the second bump 702 may be provided. The first electrode pad 703 and the second electrode pad 704 are mounted on the support 705.

The first and second bumps 701 and 702 may have an appropriate shape, width, and the like, so that the contact resistance of the first and second bumps 701 and 702 employed in the present embodiment is lowered.

When the first conductive pattern 750 is formed of a reflective metal, the reflective metal will reflect light generated from the active layer 730. Light generated from the active layer 730 will be emitted in a direction including a vector component in the direction of the substrate 710.

The technical spirit of the present invention is not limited to the embodiment of FIG. 19. It will be appreciated that the structure for electrically connecting the first and second

conductive patterns

750 and 760 to the electrode pad and the structure for electrically connecting the electrode layer 780 to the other electrode pad may be variously changed. will be. For example, similar to the embodiment described with reference to FIG. 2, the first conductive semiconductor layer 720, the active layer 730, the second conductive semiconductor layer 740, and the first and second conductive patterns ( A plurality of layers (see 170, 180 and 190 of FIG. 2) may be stacked on 750 and 760, and electrode pads (see EP1 and EP2 of FIG. 2) may be stacked. In this case, the electrode layer 780 will be formed like the first electrode layer 180 of FIG. 2.

20 is a cross-sectional view illustrating a semiconductor light emitting device 800 according to another embodiment of the present invention.

Referring to FIG. 20, the semiconductor light emitting device 800 may include a substrate 810, a bonding electrode 815, a first conductive semiconductor layer 820, an active layer 830, a second conductive semiconductor layer 840, and a second conductive semiconductor layer 840. First and second

conductive patterns

850 and 860, and an electrode layer 880.

The bonding electrode 815 is disposed on the substrate 810. The bonding electrode 815 has conductivity and adhesion, and fixes the second conductivity type semiconductor layer 840 to the substrate 810. The substrate 810 supports the

other components

815, 820, 830, 840, 850, 860, and 880, and at the same time serves as an electrode for applying a voltage or current to the second conductivity-type semiconductor layer 840. Can be.

First and second

conductive patterns

850 and 860 are disposed on the bonding electrode 815. That is, the first and second

conductive patterns

850 and 860 are disposed between the substrate 810 and the second conductive semiconductor layer 840. The second conductive pattern 860 is formed of a different material from the first conductive pattern 850 and may surround the first conductive pattern 850.

When the first conductive pattern 850 is formed of a reflective metal, the reflective metal will reflect light generated from the active layer 830. Light generated from the active layer 830 may be emitted in a direction including a vector component in a direction of the first conductivity type semiconductor layer 820.

The electrode layer 880 is disposed on the first conductivity type semiconductor layer 820. The electrode layer 880 may be provided as a transparent electrode. For example, the electrode layer 880 may employ ITO, ZITO, ZIO, GIO, ZTO, FTO, AZO, GZO, TCO, or the like.

In an embodiment, the second conductive pattern 860 may have the same thickness as the first conductive pattern 850. In another embodiment, the second conductive pattern 860 may have a lower thickness than the first conductive pattern 850.

21 is a cross-sectional view illustrating an application example of the semiconductor light emitting device 800 of FIG. 20.

Referring to FIG. 21, at least one wire 802 contacted to the electrode layer 880, a first electrode pad 803 connected to the electrode layer 880 through the wire 802, and the substrate 810 are contacted. The second electrode pad 804 may be provided. The first and

second electrode pads

803 and 804 may be mounted on the support 805.

The method of connecting the electrode layer 880 to the first electrode pad 803 and the method of connecting the first and second

conductive patterns

850 and 860 to the second electrode pad 803 may be variously changed. . For example, the wire 802 connects the electrode layer 880 and the first electrode pad 803, but may be replaced by a vertical electrode extending vertically.

22 is an exploded perspective view illustrating an embodiment of a semiconductor light emitting package 1000 including a semiconductor light emitting device.

Referring to FIG. 22, the semiconductor light emitting package 1000 may include a semiconductor light emitting device 1100, a reflective structure 1200, a support frame 1300, and a wavelength conversion film 1400.

The semiconductor light emitting device 1100 is configured similarly to any one of the semiconductor light emitting devices described with reference to FIGS. 1, 5, 12, 13, 14, 15b, 17, 19, and 21. . In the following, redundant description is omitted.

The reflective structure 1200 may be disposed to surround the semiconductor light emitting device 1100. The reflective structure 1200 may have reflection on light and high heat resistance.

The support frame 1300 is configured to support the semiconductor light emitting device 1100 and the reflective structure 1200. The support frame 1300 includes first and second

upper electrodes

1310 and 1320, and first and second

lower electrodes

1330 and 1340. The first and second

upper electrodes

1310 and 1320 are disposed on an upper surface of the support frame 1300. The first upper electrode 1310 contacts the first electrode pad EP1 (see FIG. 1) of the semiconductor light emitting device 1100, and the second upper electrode 1320 is a second electrode pad of the semiconductor light emitting device 1100 ( EP2, see FIG. 1). The semiconductor light emitting device 1100 may receive power through the first upper electrode 1310 and the second upper electrode 1320. The first and second

lower electrodes

1330 and 1340 are disposed on the bottom surface of the support frame 1300. The first lower electrode 1330 may be connected to the first upper electrode 1310 through conductive vias in the support frame 1300. The second lower electrode 1340 may be connected to the second upper electrode 1320 through another conductive via in the support frame 1300.

The support frame 1300 may further include a heat sink 1350. The heat sink 1350 is disposed on the bottom surface of the support frame 1300 and is configured to discharge heat generated from the semiconductor light emitting device 1100. For example, the support frame 1300 may perform a function of a heat sink.

The wavelength converter 1400 may be coupled to the reflective structure 1300 to cover the semiconductor light emitting device 1100. In an embodiment, the wavelength converter 1400 may have a shape of a film covering the top surface of the semiconductor light emitting device 1100. In an embodiment, the wavelength converter 1400 may have a shape covering not only an upper surface of the semiconductor light emitting device 1100 but also a side surface thereof. The wavelength conversion materials in the wavelength converter 1400 may convert light emitted from the semiconductor light emitting device 1100 into light having a different wavelength. Light from the semiconductor light emitting device 1100 may pass through the wavelength converter 1400 and be emitted as white light. When the wavelength converter 1400 is mounted on the semiconductor light emitting package 1000, the wavelength conversion layer in the semiconductor light emitting device 1100 may be selectively removed.

The semiconductor light emitting package 1000 may further include an electrostatic discharge protection circuit (not shown). The electrostatic discharge protection circuit may be mounted on the support frame 1300 or may be provided as a component of the semiconductor light emitting device 1100. The electrostatic discharge protection circuit may be connected to the first upper electrode 1310 and the second upper electrode 1320.

The semiconductor light emitting package 1000 may further include a transparent cover (not shown) that is mounted on the reflective structure 1200 to protect the semiconductor light emitting device 1100 and the wavelength converter 1400.

FIG. 23 is an exploded perspective view illustrating a modification 2000 of the semiconductor light emitting package 1000 of FIG. 22.

Referring to FIG. 23, the semiconductor light emitting package 2000 includes two or more semiconductor

light emitting devices

2110 and 2120, a reflective structure 2200, a support frame 2300, and a wavelength converter 2400.

The semiconductor light emitting package 2000 may include, for example, two semiconductor

light emitting devices

2110 and 2120. The reflective structure 2200 may be disposed to surround the first and second semiconductor

light emitting devices

2110 and 2120.

The support frame 2300 is configured to support the first and second semiconductor

light emitting devices

2110 and 2120 and the reflective structure 2200. The support frame 2300 includes first upper electrodes 2310_1 and 2310_2, second upper electrodes 2320, first and second

lower electrodes

2330 and 2340, and a heat sink 2350. The first upper electrode 2310_1 is connected to the first electrode pad EP1 of the first semiconductor light emitting device 2110 (see FIG. 1), and the second upper electrode 2320 is formed of the first semiconductor light emitting device 2110. It is connected to the second electrode pad EP2 (see FIG. 1) and the second electrode pad EP2 of the second semiconductor light emitting device 2120, and the first upper electrode 2310_2 is connected to the first of the second semiconductor light emitting device 2120. It is connected to the electrode pad EP1. The first upper electrodes 2310_1 and 2310_2 may be connected to each other. The first lower electrode 2330 is connected to the first upper electrodes 2310_1 and 2310_2. The second lower electrode 2340 is connected to the second upper electrode 2320.

Through the first upper electrodes 2310_1 and 2310_2 and the second upper electrode 2320, the first and second semiconductor

light emitting devices

2110 and 2120 may receive power. The first and second semiconductor

light emitting devices

2110 and 2120 may be connected in parallel with a power source. However, it will be appreciated that the electrical connection relationship between the first and second semiconductor

light emitting devices

2110 and 2120 and the power source may be changed as appropriate.

24 is an exploded perspective view illustrating another embodiment of a semiconductor light emitting package 3000 including a semiconductor light emitting device.

Referring to FIG. 24, the semiconductor light emitting package 3000 includes at least one semiconductor light emitting device 3110 and 3120, a printed circuit board 3200, and a support frame 3300.

The first and second semiconductor light emitting devices 3110 and 3120 are disposed on the printed circuit board 3200. Each of the first and second semiconductor light emitting devices 3110 and 3120 may be a semiconductor light emitting device described with reference to FIGS. 1, 5, 12, 13, 14, 15b, 17, 19, and 21. It is configured like any one of the elements. In the following, redundant description is omitted.

First and second

wavelength conversion layers

3111 and 3121 are stacked on the first and second semiconductor light emitting devices 3110 and 3120, respectively. The wavelength conversion materials included in each wavelength conversion layer may convert light emitted from the semiconductor light emitting device into light having a different wavelength. Light from the semiconductor light emitting element may pass through the wavelength conversion layer and be emitted as white light. The wavelength converting layer may be formed in a sheet shape having a substantially constant thickness, and may be formed in a semi-curable material which is semi-cured at room temperature and flows upon heating, for example, wavelength converting materials such as phosphors. It may be a dispersed film. The wavelength conversion layer may have a structure in which one layer is stacked, or may be formed of multiple layers. When the wavelength conversion layer is formed of multiple layers, each layer may include different kinds of phosphors.

The printed circuit board 3200 is supported by the support frame 3300. The printed circuit board 3200 interfaces the semiconductor light emitting devices 3110 and 3120 and the lower electrodes 3310 to 3340 of the support frame 3300. The printed circuit board 3200 may include first upper electrodes (not shown) and second electrodes respectively connected to the first and second electrode pads EP1 and EP2 of the first semiconductor light emitting device 3110. Second upper electrodes (not shown) connected to the first and second electrode pads EP1 and EP2 of the semiconductor light emitting device 3120 may be included. The first upper electrodes may be connected to the first

lower electrodes

3310 and 3320 on the bottom surface of the support frame 3300. The second upper electrodes may be connected to the second

lower electrodes

3330 and 3340 on the bottom surface of the support frame 3300. The number and shapes of the first upper electrodes and the second upper electrodes can be changed as appropriate.

The support frame 3300 may further include a heat sink 3350 for dissipating heat generated from the semiconductor light emitting devices 3110 and 3120.

The semiconductor light emitting package 3000 may include at least one electrostatic discharge protection circuit connected to electrodes on the printed circuit board 3200, and a transparent cover for protecting the printed circuit board 3200 and the semiconductor light emitting devices 3110 and 3120. It may further include.

25 is a plan view of a semiconductor light emitting device 5100 according to an embodiment of the present invention.

Referring to FIG. 25, the semiconductor light emitting device 5100 may include a semiconductor structure SS disposed on a substrate, and first and second electrode pads EP1 and EP2 disposed on the semiconductor structure SS. . The substrate extends in the first direction X + and the second direction Y +, and the semiconductor structure SS is disposed on the substrate in the third direction Z +. The first and second electrode pads EP1 and EP2 are disposed on the semiconductor structure SS in the third direction Z +.

The semiconductor structure SS includes a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first and second conductive semiconductor layers. Light is generated by recombination of electrons and holes in the active layer by the current flowing through the first and second conductivity-type semiconductor layers. In an embodiment, the semiconductor light emitting device 5100 may be a gallium nitride (GaN) -based semiconductor light emitting device.

The semiconductor structure SS further includes a first electrode layer ELCT1 and a second electrode layer ELCT2. The first electrode layer ELCT1 is electrically connected to the first conductivity type semiconductor layer and may be exposed by the first opening OP1 on the semiconductor structure SS. The exposed first electrode layer ELCT1 contacts the first electrode pad EP1. The second electrode layer ELCT2 is electrically connected to the second conductivity type semiconductor layer and may be exposed by the second opening OP2 on the semiconductor structure SS. The exposed second electrode layer ELCT2 contacts the second electrode pad EP2. As a result, the voltage and current applied through the first electrode pad EP1 are transferred to the first conductive semiconductor layer through the first electrode layer ELCT1 and the voltage and current applied through the second electrode pad EP2. Is transferred to the second conductivity type semiconductor layer through the second electrode layer ELCT2.

The technical idea of the present invention is not limited to the shapes of the electrode layers ELCT1 and ELCT2, the components for the electrical connection between the electrode layers ELCT1 and ELCT2 and the conductive semiconductor layers, and the shapes of the components. Do not. For example, each of the first and second electrode layers ELCT1 and ELCT2 may be directly connected to a corresponding conductive semiconductor layer. As another example, each of the first and second electrode layers ELCT1 and ELCT2 may be connected to the corresponding conductive semiconductor layer through at least one component.

The first electrode layer ELCT1 contacts the first conductivity-type semiconductor layer in the first contact regions CP1 on the semiconductor structure SS. The first contact regions CP1 may be located in the non-light emitting region of the semiconductor light emitting device 5100. The non-light emitting area may correspond to the remaining area other than the area where the active layer of the semiconductor structure SS is located. The second electrode layer ELCT2 contacts the second conductivity type semiconductor layer in the second contact region CP2 on the semiconductor structure SS. The second contact region CP2 may be located in the light emitting region of the semiconductor light emitting device 5100. The emission region may correspond to an area of the active layer of the semiconductor structure SS.

Some of the first contact regions CP1 may be located at the center of the emission area. Accordingly, the current flowing between the first contact regions CP1 and the second contact region CP2 may be efficiently spread. In an embodiment, the remaining of the first contact regions CP1 may be located at an edge of the emission region. In FIG. 25, nine first contact regions CP1 and one second contact region CP2 are illustrated. However, it will be understood that the technical spirit of the present invention is not limited thereto. The number and shape of the first contact regions CP1 and the second contact region CP2 may be variously changed.

According to an embodiment of the present invention, an area of the first contact regions CP1 is equal to or greater than 1.8% of the sum of the non-light emitting region and the light emitting region. In an embodiment, the areas of the first contact regions CP1 may be within 1.8% to 4.5% of the sum of the non-light emitting area and the light emitting area. Accordingly, the semiconductor light emitting device 5100 may be designed to have an improved light intensity while having a low forward voltage.

25 and 26, the semiconductor light emitting device 5100 may include a substrate 5110, a first conductive semiconductor layer 5120, an active layer 5130, a second conductive semiconductor layer 5140, and contact electrode layers ( 5150 and 5170,

passivation layers

5160 and 5180, and electrode pads EP1 and EP2.

The first conductive semiconductor layer 5120, the active layer 5130, and the second conductive semiconductor layer 5140 are sequentially stacked on the substrate 5110.

The substrate 5110 may be a GaN substrate. The substrate 5110 may function as a current path together with the first conductivity type semiconductor layer 5120. The current transferred to the first contact electrode layer 5170 through the second conductive semiconductor layer 5140, the active layer 5130, and the first conductive semiconductor layer 5120 may be distributed by the substrate 5110.

The first conductive semiconductor layer 5120 is a nitride semiconductor containing n-type impurities and may satisfy the compositional formula Al x In y Ga 1-x N y (0 ≦ x <1, 0 ≦ y <1, 0 ≦ x + y <1). Can be. For example, the first conductivity type semiconductor layer 5120 may include GaN, AlGaN, InGaN, AlInGaN, or the like. The first conductive semiconductor layer 5120 may include an n-type dopant such as Si, Ge, Sn, Se, Te, or the like.

The active layer 5130 is disposed on the first conductivity type semiconductor layer 5120. In an embodiment, the active layer 5130 may have a single quantum well (SQW) structure or a multi quantum well (MQW) structure. For example, the quantum well layer and the quantum barrier layer each include materials having different compositions, and the composition formula InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x + y≤1) Can be satisfied. For example, the quantum well layer may have an energy band gap lower than the energy band gap of the quantum barrier layer.

The second conductivity type semiconductor layer 5140 is disposed on the active layer 5130. The second conductivity-type semiconductor layer 5140 is a nitride semiconductor containing p-type impurities, and satisfies the compositional formula AlxInyGa1-x-yN (0≤x <1, 0≤y <1, 0≤x + y <1). Can be. For example, the second conductivity-type semiconductor layer 5140 may include AlGaN, GaN, or the like. The second conductive semiconductor layer 5140 may include p-type dopants such as Mg, Zn, Ca, Sr, and Ba. The second conductivity-type semiconductor layer 5140 may have a single layer structure or a multilayer structure. When the second conductive semiconductor layer 5140 has a multilayer structure, the second conductive semiconductor layer 5140 may include an AlGaN layer, a low concentration p-type GaN layer, a high concentration p-type GaN layer, and the like.

In an embodiment, each of the first conductive semiconductor layer 5120, the active layer 5130, and the second conductive semiconductor layer 5140 may include at least epitaxial deposition, MBE, such as a metal organic chemical vapor deposition (MOCVD). (Molecular Beam Epitaxy), or another epitaxial growth technique suitable for GaN growth.

The emission region EMP of the semiconductor light emitting device 5100 may correspond to a region where the active layer 5130 is located. In the emission region EMP, the first conductive semiconductor layer 5120, the active layer 5130, and the second conductive semiconductor layer 5140 are disposed.

The non-light emitting area NEMP of the semiconductor light emitting device 5100 may correspond to a region where the active layer 5130 is not located. At least a portion of the non-light emitting area NEMP includes an exposed area in which the first conductivity type semiconductor layer 5120 may contact the electrode. The second contact electrode layer 5150 is disposed on the second conductivity type semiconductor layer 5140. The second contact electrode layer 5150 is positioned in the emission area EMP. The second contact electrode layer 5150 may have an ohmic contact with the second conductive semiconductor layer 5140. The second contact electrode layer 5150 may include a reflective metal. The reflective metal reflects light emitted by the active layer 5130 toward the substrate. In an embodiment, an insulating layer 5501 may be further provided on the second conductive semiconductor layer 5140 and on the second contact electrode layer 5150. The insulating layer 5151 may be formed on the outside to protect the second contact electrode layer 5150.

The first passivation layer 5160 is disposed on the first conductive semiconductor layer 5120, the active layer 5130, the second conductive semiconductor layer 5140, and the second contact electrode layer 5150. The first passivation layer 5160 spaces the active layer 5130, the second conductive semiconductor layer 5140, and the second contact electrode layer 5150 and the first contact electrode layer 5170. Accordingly, the active layer 5130, the second conductive semiconductor layer 5140, and the second contact electrode layer 5150 are electrically insulated from the first contact electrode layer 5170. The first passivation layer 5160 may include third and fourth openings OP3 and OP4 exposing the first conductive semiconductor layer 5120, and a fifth opening OP5 exposing the second contact electrode layer 5150. Has

The first contact electrode layer 5170 is disposed on the first passivation layer 5160 and the first conductivity type semiconductor layer 5120. The first contact electrode layer 5170 may contact the first conductivity type semiconductor layer 5120 in the first contact regions CP1 of the non-light emitting region through the third and fourth openings OP3 and OP4. The first contact regions CP1 are positioned in the non-light emitting region NEMP of the semiconductor light emitting device 5100. The first contact electrode layer 5170 may have an ohmic contact with the first conductivity type semiconductor layer 5120.

The connection electrode layer 5175 is formed on the second contact electrode layer 5150 and is disposed on the first passivation layer 5160. The connection electrode layer 5175 may contact the second contact electrode layer 5150 through the fifth opening OP5. In an embodiment, the first contact electrode layer 5170 and the connection electrode layer 5175 may be formed at the same time during the manufacturing process. The first contact electrode layer 5170 and the connection electrode layer 5175 may include the same material. For example, the first contact electrode layer 5170 and the connection electrode layer 5175 may include at least one of materials such as Au, W, Pt, Si, Ir, Ag, Cu, Ni, Ti, Cr, Al, and alloys thereof. It may include.

In an embodiment, the connection electrode layer 5175 may be omitted. In this case, the second contact electrode 5150 may directly contact the second electrode pad EP2 through the fifth opening OP5.

The second passivation layer 5180 is disposed on the first contact electrode layer 5170 and the connection electrode layer 5175. The second passivation layer 5180 includes a first opening OP1 exposing the first contact electrode layer 5170 and a second opening OP2 exposing the connection electrode layer 5175.

In some embodiments, each of the first and

second passivation layers

5160 and 5180 may be formed of an insulating material such as SiO 2, SiN, SiO x N y, TiO 2, Si 3 N 4, Al 2 O 3, TiN, AlN, ZrO 2, TiAlN, TiSiN, Nb 2 O 5, and MgF 2. Can be. In an embodiment, the first and

second passivation layers

5160 and 5180 may be formed as a distributed Bragg reflector (DBR) in which a low refractive material layer and a high refractive material layer of the insulating materials listed above are alternately stacked. have.

The first electrode pad EP1 contacts the first contact electrode layer 5170 through the first opening OP1. Therefore, the first electrode pad EP1 is electrically connected to the first conductivity type semiconductor layer 5120 through the first contact electrode layer 5170. The second electrode pad EP2 contacts the connection electrode layer 5175 through the second opening OP2. Therefore, the second electrode pad EP2 is electrically connected to the second conductivity type semiconductor layer 5140 through the connection electrode layer 5175 and the second contact electrode layer 5150.

The first contact electrode layer 5170 contacts the first electrode pad EP1 through the first opening OP1 and contacts the first conductive semiconductor layer 5120 in the first contact regions CP1. Accordingly, the first contact electrode layer 5170 may function as the first electrode layer ELCT1 of FIG. 25. The connection electrode layer 5175 contacts the second electrode pad EP2 through the second opening OP2, and the second conductivity-type semiconductor layer 5140 in the second contact region CP2 through the second contact electrode layer 5150. ). Accordingly, the connection electrode layer 5175 may function as the second electrode layer ELCT2 of FIG. 25.

27 is an experimental graph showing the relationship between the area of the light emitting area EMP and the light intensity. In FIG. 27, the horizontal axis represents the ratio between the area of the light emitting region EMP and the total area of the semiconductor light emitting element 5100, and the vertical axis represents the light intensity.

Referring to FIGS. 26 and 27, as the area of the emission area EMP increases, the light intensity of the semiconductor light emitting device 5100 may increase. Increasing the area of the emission area EMP means that the area of the active layer 5130 is increased. As the area of the active layer 5130 increases, the light intensity may increase.

Meanwhile, as described with reference to FIGS. 25 and 26, regions CP1 in which the first contact electrode layer 5170 contacts the first conductive semiconductor layer 5120 are positioned in the non-light emitting region EMP. . The area of the non-light emitting area NEMP decreases as the area of the light emitting area EMP increases. Therefore, as the area of the emission area EMP increases, the areas of the first contact areas CP1 may decrease.

When the areas of the first contact regions CP1 are reduced, the current applied to the first electrode pad EP1 may not be smoothly transferred to the first conductive semiconductor layer 5120. This means that the resistance component of the semiconductor light emitting device 5100 is increased and the forward voltage at both ends of the semiconductor light emitting device 5100 (that is, EP1 and EP2 of FIG. 26) may increase. As the forward voltage increases, the power consumption of the semiconductor light emitting device 5100 increases. As a result, when the area of the light emitting area EMP increases, the light intensity of the semiconductor light emitting device 5100 may increase, and power consumption of the semiconductor light emitting device 5100 may also increase.

FIG. 28 is an experimental graph illustrating a relationship between an area of the first contact regions CP1 and a forward voltage Vf of the semiconductor light emitting device 5100. In FIG. 28, the horizontal axis represents the ratio between the areas of the first contact regions CP1 and the entire area of the semiconductor light emitting device 5100, and the vertical axis represents the forward voltage Vf of the semiconductor light emitting device 5100. The total area of the semiconductor light emitting device 5100 may be understood as the total area of the light emitting area EMP and the non-light emitting area NEMP as the unit chip area.

26 and 28, the forward voltage Vf of the semiconductor light emitting device 5100 decreases rapidly until the area of the first contact regions CP1 increases to reach 1.8%. In this area section, power consumption of the semiconductor light emitting device 5100 may decrease. For example, when the area of the first contact regions CP1 is 1%, the forward voltage Vf of the semiconductor light emitting device 5100 may be 5.3V. When the area of the first contact regions CP is 1.8%, the forward voltage Vf of the semiconductor light emitting device 5100 may be 3.9V. On the other hand, when the area of the first contact regions CP1 is larger than 1.8%, the forward voltage Vf of the semiconductor light emitting device 5100 decreases slowly. For example, when the area of the first contact regions CP1 gradually increases to 1.8%, 2%, 3%, 4%, 5%, 6%, 7%, and 8%, the semiconductor light emitting device 5100 ) Maintains a forward voltage (Vf) within the range of 3.8 to 3.9 V. The power consumption of the semiconductor light emitting device 5100 may be substantially maintained when the area of the first contact regions is 1.8% or more. This may be understood that the area of the first contact regions CP1 has a critical significance at 1.8%.

Meanwhile, a current transmitted to the first contact electrode layer 5170 through the second conductive semiconductor layer 5140, the active layer 5130, and the first conductive semiconductor layer 5120 may be a GaN substrate as the substrate 5110. By being used, it can flow more smoothly. When the substrate 5110 is a GaN substrate, the forward voltage Vf of the semiconductor light emitting device 5100 is relatively low. In an embodiment, when the GaN substrate is used, the area of the first contact regions CP1 may have a critical meaning at 1.8%.

In an embodiment, the area of the first contact regions CP1 may be selected as 2.5% due to the process error of the semiconductor light emitting device 5100.

The first contact regions CP1 are disposed in the non-light emitting region NEMP. When the areas of the first contact areas CP1 increase, the areas of the emission area EMP decrease. As described with reference to FIG. 27, as the area of the emission area EMP decreases, the light intensity of the semiconductor light emitting device 5100 may decrease. Considering the light intensity of the semiconductor light emitting device 5100, the area of the first contact regions CP1 may be designed not to exceed 4.5%. For example, the area of the first contact regions CP1 may be within 1.8% to 4.5%.

According to the areas of the selected first contact regions CP1, an area of the second contact region CP2 may be designed. It will be appreciated that the area of the second contact region CP2 can be changed according to the number and shape of each of the first contact regions CP1 and the second contact region CP2. For example, when the area of the first contact regions CP1 is 1.8%, the area of the second contact region CP2 may be 80%. When the area of the first contact regions CP1 is 2.5%, the area of the second contact region CP2 may be 79.3%. When the area of the first contact regions CP1 is 3.5%, the area of the second contact region CP2 may be 78.3%. When the area of the first contact regions CP1 is 4.5%, the area of the second contact region CP2 may be 77.3%.

In an embodiment, when the substrate 5110 is a substrate including sapphire, the area of the first contact regions CP1 may be designed in a range of 8% or less.

Referring to FIG. 29, the semiconductor light emitting device 5100 may include a substrate 5210, a first conductive semiconductor layer 5220, an active layer 5230, a second conductive semiconductor layer 5240, and

contact electrodes

5250 and 5270. ), A conductive pattern 5252, a connection electrode layer 5175,

passivation layers

5260 and 5280, and electrode pads EP1 and EP2.

The substrate 5210, the first conductive semiconductor layer 5220, the active layer 5230, the second conductive semiconductor layer 5240, the

contact electrodes

5250 and 5270, the connection electrode layer 5175, the passivation layers 5260, and the like. 5280, the electrode pads EP1 and EP2 include the substrate 5110 described with reference to FIG. 26, the first conductive semiconductor layer 5120, the active layer 5130, the second conductive semiconductor layer 5140, and the contacts. The

electrodes

5150 and 5170, the connection electrode layer 5175, the

passivation layers

5160 and 5180, and the electrode pads EP1 and EP2 are configured. In the following, redundant description is omitted.

The conductive pattern 5252 may replace the insulating layer 5501 of FIG. 26. The conductive pattern 5252 is in contact with at least a portion of the second contact electrode layer 5250 and is disposed on the second conductive semiconductor layer 5240.

The conductive pattern 5252 is formed in an area adjacent to an edge of the upper surface of the second conductive semiconductor layer 5240, and the second contact electrode layer 5250 is formed of the second conductive semiconductor layer ( 5240 may be spaced apart from the edge of the top surface. The conductive pattern 5252 may be formed to surround at least a portion of the second contact electrode layer 5250 on the second conductive semiconductor layer 5240 (see FIG. 35A). The conductive pattern 5252 may contact the second conductive semiconductor layer 5240 together with the second contact electrode layer 5250. In an embodiment, the conductive pattern 5252 may have an ohmic contact with the second conductive semiconductor layer 5240.

FIG. 30 is an enlarged view illustrating region A of FIG. 29.

Referring to FIG. 30, current from a power source may include a second contact electrode layer 5250, a second conductive semiconductor layer 5240, an active layer 5230, a first conductive semiconductor layer 5220, and a first contact electrode layer ( It may flow through the first current path IP1 defined by 5270. Furthermore, the current from the power source is not only the first current path IP1 but also the conductive pattern 5252, the second conductive semiconductor layer 5240, the active layer 5230, the first conductive semiconductor layer 5220, and the first current path IP1. It may flow through the second current path IP2 formed by the first contact electrode layer 5270. Accordingly, the current from the power supply can flow smoothly through the first and second current paths IP1 and IP2.

The distance between the conductive pattern 5252 and the first contact electrode layer 5270 is shorter than the distance between the second contact electrode layer 5250 and the first contact electrode layer 5270. This may mean that the second current path IP2 transfers the current more smoothly. By providing the second current path IP2 as well as the first current path IP1, driving performance and driving efficiency of the semiconductor light emitting device 5100 may be further improved.

FIG. 31 is an experimental graph illustrating a relationship between an area of the first contact regions CP1 and a forward voltage of the semiconductor light emitting device 5100 of FIG. 30. In FIG. 31, the horizontal axis represents the ratio between the areas of the first contact regions CP1 and the total area of the semiconductor light emitting device 5100, and the vertical axis represents the voltage drop Vf of the semiconductor light emitting device 5100.

Referring to FIG. 31, the first voltage drop Vf1 represents the voltage drop of the semiconductor light emitting device 5100 of FIG. 26. The second voltage drop Vf2 represents the voltage drop of the semiconductor light emitting device 5100 according to the exemplary embodiment of FIG. 29. In the second voltage drop Vf2, the voltage drop of the semiconductor light emitting device 5100 decreases rapidly until the area of the first contact regions CP1 increases to reach 1.8%. On the other hand, when the area of the first contact regions CP1 is larger than 1.8%, the voltage drop of the semiconductor light emitting device 5100 decreases gently. The area of the first contact areas CP1 according to the embodiment of FIG. 29 has a critical meaning at 1.8%.

The semiconductor light emitting device 5100 according to the exemplary embodiment of FIG. 29 may further include a conductive pattern 5252 so that a current may flow through the second current path IP2 as well as the first current path IP1. Therefore, the second voltage drop Vf2 may be lower than the first voltage drop Vf2 in the entire horizontal axis. Accordingly, power consumption of the semiconductor light emitting device 5100 may be further reduced.

32, 33A, 33B, 34A, 34B, 35A, 35B, 36A, 36B, 37A, and 37B illustrate a method of manufacturing the semiconductor light emitting device 5100 of FIG. 29. Figures showing.

First, referring to FIG. 32, a first conductive semiconductor layer 5220, an active layer 5230_1, a second conductive semiconductor layer 5240_1, and a conductive layer 5252_1 are formed on a substrate 5210.

The substrate 5210 may be provided as a substrate for growing a semiconductor, and may be a conductive substrate including GaN. The first conductive semiconductor layer 5220 and the second conductive semiconductor layer 5240_1 may be n-type semiconductor layers and p-type semiconductor layers, respectively.

The conductive layer 5252_1 may lower the resistance of the interface between the second conductive semiconductor layer 5240_1 and the conductive layer 5252_1 according to rapid thermal annealing. For example, the conductive layer 5252_1 may have an ohmic contact with the second conductive semiconductor layer 5240_1.

In an embodiment, the conductive layer 5252_1 may include Ni / Au, indium tin oxide (ITO), zinc-doped indium tin oxide (ZITO), zinc indium oxide (ZIO), gallium indium oxide (GIO), and zinc tin oxide (ZTO). It may be formed of at least one selected from Fluorine-doped Tin Oxide (FTO), Zinc Oxide (ZnO), Gallium-doped Zinc Oxide (GZO), Aluminum-doped Zinc Oxide (AZO), and Transparent Conductive Oxide (TCO).

The first conductive semiconductor layer 5220, the active layer 5230_1, the second conductive semiconductor layer 5240_1, and the conductive layer 5252_1 are etched by at least one etching region E and the etching region E. FIG. The partitioned at least one mesa region M is defined. 33A and 33B, a first conductive semiconductor layer 5220, an active layer 5230, a second conductive semiconductor layer 5240, and a conductive layer 5252_2 are disposed in the mesa region M. Referring to FIGS. The first conductivity type semiconductor layer 5220 is disposed in the etching region E. FIG. At least a portion of the etching region E is located at the center of the mesa region M. The other part of the etching region E is located at the edge of the mesa region M.

34A and 34B, a second contact electrode layer 5250 and a conductive pattern 5252 are formed on the second conductive semiconductor layer 5240. The second contact electrode layer 5250 and the conductive pattern 5252 may correspond to the second contact region CP2. The second contact region CP2 is located in the mesa region M.

In an embodiment, a photoresist pattern for forming the conductive pattern 5252 is formed by etching the conductive layer 5252_2, plasma is irradiated to further remove remaining photoresist, and the photoresist pattern is used as a mask to conduct the The conductive pattern 5252 may be formed by etching the layer 5252_2. Subsequently, the second contact electrode layer 5250 may be formed using the photoresist pattern as a mask, and the photoresist pattern may be removed.

The conductive pattern 5252 may include a material different from that of the second contact electrode layer 5250. The conductive pattern 5252 may include a transparent material. The conductive pattern 5252 may include a material resistant to plasma. For example, the conductive pattern 5252 may include Ni / Au, indium tin oxide (ITO), zinc-doped indium tin oxide (ZITO), zinc indium oxide (ZIO), gallium indium oxide (GIO), and zinc tin oxide (ZTO). , At least one selected from a fluorine-doped tin oxide (FTO), a zinc oxide (ZnO), a gallium-doped zinc oxide (GZO), an aluminum-doped zinc oxide (AZO), a transparent conductive oxide (TCO), and the like. .

35A and 35B, a first passivation layer 5260 is formed. The first passivation layer 5260 has sixth openings OP6 exposing the first conductive semiconductor layer 5220 and seventh openings OP7 exposing the second contact electrode layer 5250. The sixth openings OP6 are formed in the etching region E. FIG. The seventh openings OP7 are formed in the mesa region M.

36A and 36B, a first contact electrode layer 5270 and a connection electrode layer 5175 are formed. The first contact electrode layer 5270 contacts the first conductive semiconductor layer 5220 through the sixth openings OP6 (see FIG. 35B). The first contact regions CP1 may be located in the etching region E. FIG. The connection electrode layer 5175 may contact the second contact electrode layer 5250.

37A and 37B, a second passivation layer 5280 is formed. The second passivation layer 5280 covers components other than a portion of the first contact electrode layer 5270 and a portion of the connection electrode layer 5175. The second passivation layer 5280 includes an eighth opening OP8 exposing the first contact electrode layer 5270 and a ninth opening OP9 exposing the connection electrode layer 5175. The eighth and ninth openings OP8 and OP9 correspond to the first and second openings OP1 and OP2 of FIG. 25, respectively.

Then, as shown in FIGS. 25 and 26, the first and second electrode pads ELCT1 and ELCT2 will be disposed on the exposed first contact electrode layer 5270 and the exposed connection electrode layer 5175, respectively. .

38 is a plan view of a semiconductor light emitting device 5500 according to another exemplary embodiment.

The layout of the semiconductor light emitting device according to the embodiment may be variously changed. Referring to FIG. 38, the semiconductor light emitting device 5500 includes a semiconductor structure SS disposed on a substrate and first and second electrode pads EP1 and EP2 disposed on the semiconductor structure SS. . Except for the first contact regions CP1, the semiconductor light emitting device 5500 may be configured similarly to the semiconductor light emitting device 5100 of FIG. 25. The first contact regions CP1 at the edge of the second contact region CP2 may be disposed at corners of the second contact region CP2.

39 is a plan view of a semiconductor light emitting device 5600 according to still another embodiment of the present invention.

Referring to FIG. 39, the semiconductor light emitting device 5600 may include a semiconductor structure SS disposed on a substrate, and first and second electrode pads EP1 and EP2 disposed on the semiconductor structure SS. . Except for the first contact region CP1, the semiconductor light emitting device 5600 is configured similarly to the semiconductor light emitting device 5100 of FIG. 25. The first contact region CP1 may be provided at the center of the second contact region CP2 and may not be provided at the edge of the second contact region CP2.

Referring to FIG. 40, the semiconductor light emitting package 6000 may include a semiconductor light emitting device 6100, a reflective structure 6200, a support frame 6300, and a wavelength conversion film 6400.

The semiconductor light emitting element 6100 is configured similarly to the semiconductor light emitting element 5100 described with reference to FIG. 25. In the following, redundant description is omitted.

The reflective structure 6200 may be disposed to surround the semiconductor light emitting device 6100. The reflective structure 6200 may have reflection on light and high heat resistance.

The support frame 6300 is configured to support the semiconductor light emitting element 6100 and the reflective structure 6200. The support frame 6300 includes first and second

upper electrodes

6310 and 6320, and first and second

lower electrodes

6330 and 6340. The first and second

upper electrodes

6310 and 6320 are disposed on an upper surface of the support frame 6300. The first upper electrode 6310 contacts the first electrode pad EP1 (see FIG. 25) of the semiconductor light emitting element 6100, and the second upper electrode 6320 is a second electrode pad of the semiconductor light emitting element 6100 ( EP2, see FIG. 25). The semiconductor light emitting device 6100 may receive power through the first upper electrode 6310 and the second upper electrode 6320. The first and second

lower electrodes

6330 and 6340 are disposed on the bottom surface of the support frame 6300. The first lower electrode 6330 may be connected to the first upper electrode 6310 through conductive vias in the support frame 6300. The second lower electrode 6340 may be connected to the second upper electrode 6320 through another conductive via in the support frame 6300.

The support frame 6300 may further include a heat sink 6350. The heat sink 6350 is disposed on the bottom surface of the support frame 6300 and configured to discharge heat generated from the semiconductor light emitting element 6100. For example, the support frame 6300 may perform a function of a heat sink.

The wavelength converter 6400 may be coupled to the reflective structure 6200 to cover the semiconductor light emitting device 6100. In an embodiment, the wavelength converter 6400 may have a shape of a film or glass covering an upper surface of the semiconductor light emitting device 6100. In an embodiment, the wavelength converter 6400 may have a shape covering not only an upper surface of the semiconductor light emitting device 6100 but also a side surface thereof. Wavelength converting materials in the wavelength converter 6400 may convert light emitted from the semiconductor light emitting device 6100 into light having a different wavelength. Light from the semiconductor light emitting device 6100 may pass through the wavelength converter 6400 and be emitted as white light. When the wavelength converter 6400 is mounted on the semiconductor light emitting package 6000, the wavelength conversion layer in the semiconductor light emitting device 6100 may be selectively removed.

The semiconductor light emitting package 6000 may further include an electrostatic discharge protection circuit (not shown). The electrostatic discharge protection circuit may be mounted on the support frame 6300 or provided as a component of the semiconductor light emitting device 6100. The electrostatic discharge protection circuit may be connected to the first upper electrode 6310 and the second upper electrode 6320.

The semiconductor light emitting package 6000 may further include a transparent cover (not shown) mounted on the reflective structure 6200 to protect the semiconductor light emitting device 6100 and the wavelength converter 6400.

Referring to FIG. 41, the semiconductor light emitting package 7000 includes two or more semiconductor

light emitting devices

7110 and 7120, a reflective structure 7200, a support frame 7300, and a wavelength converter 7400.

The semiconductor light emitting package 7000 may include, for example, two semiconductor

light emitting devices

7110 and 7120. The reflective structure 7200 may be disposed to surround the first and second semiconductor

light emitting devices

7110 and 7120.

The support frame 7300 is configured to support the first and second semiconductor

light emitting devices

7110 and 7120 and the reflective structure 7200. The support frame 7300 may include first upper electrodes 7310_1 and 7310_2, second upper electrodes 7320, first and second

lower electrodes

7330 and 7340, and a heat sink 7350. The first upper electrode 7310_1 is connected to the first electrode pad EP1 (see FIG. 25) of the first semiconductor light emitting element 7110, and the second upper electrode 7320 is formed of the first semiconductor light emitting element 7110. It is connected to the second electrode pad EP2 (see FIG. 25) and the second electrode pad EP2 of the second semiconductor light emitting device 7120, and the first upper electrode 7310_2 is connected to the first electrode of the second semiconductor light emitting device 7120. It is connected to the electrode pad EP1. The first upper electrodes 7310_1 and 7310_2 may be connected to each other. The first lower electrode 7330 is connected to the first upper electrodes 7310_1 and 7310_2. The second lower electrode 7340 is connected to the second upper electrode 7320.

The first and second semiconductor

light emitting devices

7110 and 7120 may receive power through the first upper electrodes 7310_1 and 7310_2 and the second upper electrode 7320. The first and second semiconductor

light emitting devices

7110 and 7120 may be connected to a power source in parallel. However, it will be appreciated that the electrical connection relationship between the first and second semiconductor

light emitting devices

7110 and 7120 and the power source may be changed as appropriate.

Referring to FIG. 42, the semiconductor light emitting package 8000 may include at least one semiconductor light emitting device 8210 and 8120, a printed circuit board 8200, and a support frame 8300.

The first and second semiconductor light emitting devices 8210 and 8120 are disposed on the printed circuit board 8200. Each of the first and second semiconductor light emitting devices 8210 and 8120 is configured similarly to the semiconductor light emitting device 5100 described with reference to FIG. 25. In the following, redundant description is omitted.

First and second

wavelength conversion layers

8111 and 8121 are stacked on the first and second semiconductor light emitting devices 8210 and 8120, respectively. The wavelength conversion materials included in each wavelength conversion layer may convert light emitted from the semiconductor light emitting device into light having a different wavelength. Light from the semiconductor light emitting element may pass through the wavelength conversion layer and be emitted as white light. The wavelength converting layer may be formed in a sheet shape having a substantially constant thickness, and may be formed in a semi-curable material which is semi-cured at room temperature and flows upon heating, for example, wavelength converting materials such as phosphors. It may be a dispersed film. The wavelength conversion layer may include glass and phosphor glass having phosphors dispersed in the glass (Phosphor In Glass, PIG). The wavelength conversion layer may have a structure in which one layer is stacked, or may be formed of multiple layers. When the wavelength conversion layer is formed of multiple layers, each layer may include different kinds of phosphors.

The printed circuit board 8200 is supported by the support frame 8300. The printed circuit board 8200 interfaces the semiconductor light emitting devices 8210 and 8120 and the lower electrodes 8310 to 8340 of the support frame 8300. The printed circuit board 8200 may include first upper electrodes (not shown) connected to the first and second electrode pads EP1, EP2 (see FIG. 25) of the first semiconductor light emitting device 8210, and a second, respectively. Second upper electrodes (not shown) connected to the first and second electrode pads EP1 and EP2 of the semiconductor light emitting device 8120 may be included. The first upper electrodes may be connected to the first

lower electrodes

8310 and 8320 on the bottom surface of the support frame 8300. The second upper electrodes may be connected to the second

lower electrodes

8330 and 8340 on the lower surface of the support frame 8300. The number and shapes of the first upper electrodes and the second upper electrodes can be changed as appropriate.

The support frame 8300 may further include a heat sink 8350 for dissipating heat generated from the semiconductor light emitting devices 8210 and 8120.

The semiconductor light emitting package 8000 includes at least one electrostatic discharge protection circuit connected to electrodes on the printed circuit board 8200, and a transparent cover for protecting the printed circuit board 8200 and the semiconductor light emitting devices 8210 and 8120. It may further include.

According to an embodiment of the present invention, the first conductive pattern and the second conductive pattern contact the second conductive semiconductor layer. The current from the power supply can flow not only through the first current path but also through the second current path formed by the second conductive pattern, the second conductive semiconductor layer, the active layer, the first conductive semiconductor layer, and the first electrode layer. . Thus, current from the power source can flow smoothly through the first and second current paths.

According to an embodiment of the present invention, the semiconductor light emitting device includes first contact regions having an area of 1.8% or more of the sum of the emission area and the non-emission area. Therefore, the semiconductor light emitting device may have an improved light intensity while having a low voltage drop.

Claims

A light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer sequentially stacked;

A first conductive pattern in ohmic contact with one surface of the second conductive semiconductor layer; And

A second conductive pattern having ohmic contact to the one surface of the second conductive semiconductor layer and having a material different from that of the first conductive pattern,

And the first conductive pattern contacts a portion of the second conductive pattern.
The method of claim 1,

And the second conductive pattern surrounds the first conductive pattern on the one surface of the second conductive semiconductor layer.
The method of claim 1,

The one surface of the second conductivity type semiconductor layer is divided into a first portion and a second portion,

The second conductive pattern is disposed on the first portion,

And the second conductive pattern is adjacent to an edge of the second conductive semiconductor layer, and the first conductive pattern is spaced apart from the edge than the second conductive pattern.
The method of claim 1,

And the first conductive pattern contacts at least a portion of side surfaces of the second conductive pattern.
The method of claim 1,

The second conductive pattern may include a lower surface contacting the one surface of the second conductive semiconductor layer and an upper surface opposite to the lower surface,

And the first conductive pattern contacts at least a portion of the upper surface of the second conductive pattern and a side surface of the second conductive pattern.
The method of claim 1,

The semiconductor light emitting device of claim 1, wherein the width of the second conductive pattern is shorter than the width of the first conductive pattern.
The method of claim 1,

The thickness of the second conductive pattern is thinner than the thickness of the first conductive pattern.
The method of claim 7, wherein

And at least a portion of the portion adjacent to the second conductive pattern of the first conductive pattern has a slope.
The method of claim 8,

And a portion of the first conductive pattern adjacent to the second conductive pattern becomes thinner as the second conductive pattern is adjacent to the second conductive pattern.
The method of claim 8,

The portion adjacent to the second conductive pattern of the first conductive pattern is divided into a first region and a second region between the first region and the second conductive pattern,

The first region is thinner the closer to the second conductive pattern, the thicker the second region is adjacent to the first conductive pattern.
The method of claim 1,

The first conductive pattern includes a reflective material,

The second conductive pattern includes a transparent material.
The method of claim 1,

The first conductive pattern includes a reflective metal,

The second conductive pattern may include Ni / Au, indium tin oxide (ITO), zinc-doped indium tin oxide (ZITO), zinc indium oxide (ZIO), gallium indium oxide (GIO), zinc tin oxide (ZTO), and fluorine (FTO) A semiconductor light emitting device comprising at least one material selected from -doped tin oxide (ZnO), zinc oxide (ZnO), gallium-doped zinc oxide (GZO), aluminum-doped zinc oxide (AZO), and transparent conductive oxide (TCO) .
The method of claim 1,

The first conductive pattern,

Reflective metal layer; And

A cover metal layer covering the reflective metal layer,

The cover metal layer contacts the second conductive pattern, and the reflective metal layer is spaced apart from the second conductive pattern.
The method of claim 13,

The second conductive pattern includes a side facing the reflective metal layer,

The cover metal layer contacts at least a portion of side surfaces of the second conductive pattern.
The method of claim 13,

The second conductive pattern includes a lower surface contacting the second conductive semiconductor layer and an upper surface opposite to the lower surface,

The cover metal layer further contacts at least a portion of the upper surface of the second conductive pattern.
The method of claim 1,

A first opening disposed on the first and second conductive patterns and the light emitting structure and exposing a portion of the first conductive semiconductor layer, and a part of at least one of the first and second conductive patterns; A first passivation layer having a second opening that exposes the first passivation layer;

An electrode layer disposed on the first passivation layer and in contact with the first conductive semiconductor layer through the first opening;

A second passivation layer disposed on the electrode layer, the second passivation layer having a third opening exposing a portion of the electrode layer and a fourth opening exposing at least a portion of the portion exposed by the second opening;

A first electrode pad contacting the electrode layer through the third opening; And

And a second electrode pad contacting at least one of the first and second conductive patterns through the fourth opening.
The method of claim 1,

And the first conductive semiconductor layer is an n-type semiconductor layer, and the second conductive semiconductor layer is a p-type semiconductor layer.
A first conductivity type semiconductor layer;

An active layer disposed on the first conductivity type semiconductor layer;

A second conductivity type semiconductor layer disposed on the active layer;

A first electrode layer contacting the first conductive semiconductor layer; And

And a second electrode layer contacting the second conductivity type semiconductor layer,

The second electrode layer includes a first conductive pattern that contacts the second conductive semiconductor layer, and a second conductive pattern that contacts the second conductive semiconductor layer and surrounds at least a portion of the first conductive pattern. Light emitting element.
The method of claim 18,

And the first conductive pattern contacts at least a portion of side surfaces of the second conductive pattern.
The method of claim 18,

The second conductive pattern includes a lower surface contacting the second conductive semiconductor layer and an upper surface opposite to the lower surface,

And the first conductive pattern contacts at least a portion of the upper surface of the second conductive pattern and a side surface of the second conductive pattern.
A light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer stacked on a substrate;

A first contact electrode layer disposed on the light emitting structure and contacting the first conductive semiconductor layer in a non-light emitting region; And

A second contact electrode layer disposed on the light emitting structure and contacting the second conductive semiconductor layer in a light emitting region;

And a first contact area in which the first contact electrode layer contacts the first conductive semiconductor layer is 1.8% or more of the sum of the non-light emitting region and the light emitting region.
The method of claim 21,

And the first contact area is in a range of 1.8% to 4.5% of the sum.
The method of claim 22,

And the first contact area is 2.5% of the sum.
The method of claim 21,

The substrate is a semiconductor light emitting device comprising a conductive substrate containing GaN.
The method of claim 21,

And a first portion of the portions in which the first contact electrode layer contacts the first conductive semiconductor layer is positioned at the center of the emission region.
The method of claim 25,

And a second portion of the portions where the first contact electrode layer contacts the first conductivity type semiconductor layer is positioned at an edge of the emission region.
The method of claim 21,

And the first conductive semiconductor layer is an n-type semiconductor layer, and the second conductive semiconductor layer is a p-type semiconductor layer.
The method of claim 21,

The second contact electrode layer,

A reflective metal having ohmic contact with the second conductivity type semiconductor layer; And

An ohmic contact with the second conductive semiconductor layer, the conductive pattern having a material different from that of the reflective metal,

And the conductive pattern contacts at least a portion of the reflective metal.
The method of claim 28,

The conductive pattern surrounds the reflective metal on the second conductivity type semiconductor layer.
The method of claim 21,

The light emitting structure is partitioned into a mesa region and an etching region,

The first conductivity type semiconductor layer is located in the mesa region and the etching region,

The active layer and the second conductivity type semiconductor layer are disposed on the first conductivity type semiconductor layer in the mesa region,

The light emitting region corresponds to a region where the active layer is located.
The method of claim 21,

A first passivation layer disposed on the light emitting structure and the second contact electrode layer and having a first opening exposing a portion of the first conductivity type semiconductor layer in the non-light emitting region,

The first contact electrode layer is disposed on the first passivation layer and contacts the first conductivity type semiconductor layer through the first opening,

And the first opening is positioned at the center of the light emitting area.
The method of claim 31, wherein

The first passivation layer has a second opening that exposes a portion of the second contact electrode layer,

A connection electrode layer disposed on the first passivation layer and contacting the second contact electrode layer through the second opening;

A second passivation layer disposed on the first contact electrode layer and the connection electrode layer and having a third opening exposing a portion of the first contact electrode layer and a fourth opening exposing a portion of the connection electrode layer;

A first electrode pad contacting the first contact electrode layer through the third opening; And

And a second electrode pad contacting the connection electrode layer through the fourth opening.
Board;

A light emitting structure including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer sequentially stacked on the substrate, the light emitting structure being divided into a mesa region and an etching region;

A first contact electrode layer disposed on the light emitting structure and contacting the first conductivity type semiconductor layer in the etching region; And

A second contact electrode layer disposed on the light emitting structure and contacting the second conductive semiconductor layer in the mesa region;

And a first contact area where the first contact electrode layer contacts the first conductive semiconductor layer is 1.8% or more of the sum of the mesa region and the etching region.
The method of claim 33, wherein

And the first contact area is in a range of 1.8% to 4.5% of the sum.