WO2018026191A1 - Light emitting device - Google Patents

Light emitting device Download PDF

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Publication number
WO2018026191A1
WO2018026191A1 PCT/KR2017/008337 KR2017008337W WO2018026191A1 WO 2018026191 A1 WO2018026191 A1 WO 2018026191A1 KR 2017008337 W KR2017008337 W KR 2017008337W WO 2018026191 A1 WO2018026191 A1 WO 2018026191A1
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WO
WIPO (PCT)
Prior art keywords
layer
connection pad
light emitting
semiconductor layer
current blocking
Prior art date
Application number
PCT/KR2017/008337
Other languages
French (fr)
Korean (ko)
Inventor
김지혜
김경완
김예슬
Original Assignee
서울바이오시스주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Priority claimed from KR1020170097775A external-priority patent/KR102386513B1/en
Application filed by 서울바이오시스주식회사 filed Critical 서울바이오시스주식회사
Priority to CN201780048307.0A priority Critical patent/CN109564958A/en
Publication of WO2018026191A1 publication Critical patent/WO2018026191A1/en
Priority to US16/264,866 priority patent/US10840409B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present invention relates to a light emitting device, and more particularly, to a light emitting device having improved current spreading performance.
  • a light-emitting diode refers to a device that makes a small number of carriers (electrons or holes) injected using a pn junction structure of a semiconductor and emits light by recombination thereof.
  • GaAs, AlGaAs, Various colors may be realized by configuring a light emitting source by changing compound semiconductor materials such as GaN, InGaN, and AlGaInP.
  • Such a light emitting device has a smaller power consumption and a longer life than conventional light bulbs or fluorescent lamps, can be installed in a narrow space, and exhibits strong vibration resistance.
  • These light emitting devices are used as display devices and backlights, and because they have excellent characteristics in terms of power consumption reduction and durability, applications have recently been extended to large LCD-TV backlights, automotive headlights, and general lighting. It is necessary to improve the luminous efficiency of the device.
  • An object of the present invention is to provide a light emitting device capable of minimizing current concentration occurring in a region where a connection pad and a nitride-based semiconductor stack are in contact.
  • Another object of the present invention is to provide a light emitting device having improved reliability.
  • Another object of the present invention is to provide a light emitting device capable of preventing the light absorbed and lost by the connection pad in a region where the connection pad and the nitride semiconductor stack are in contact with each other.
  • a light emitting device includes a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer positioned between the first and second conductive semiconductor layers, and the second conductive semiconductor A nitride based semiconductor laminate including an exposed region through the layer and the active layer to expose the first conductive semiconductor layer; A first connection pad electrically connected to the first conductivity type semiconductor layer through the exposed region; A first current blocking layer interposed between the first conductive semiconductor layer and the first connection pad; Second connection pads disposed on the second conductive semiconductor layer; And an upper extension extending from the second connection pad, wherein the upper extension is two or more, the first connection pad is positioned between the upper extensions, and the first current blocking layer is the first conductivity type. In the region between the semiconductor layer and the first connection pad, the region is limited to a part of the region.
  • the light emitting device includes a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer, and penetrates the second conductive semiconductor layer and the active layer to form the first conductive semiconductor layer.
  • a semiconductor stack comprising an exposed area to expose;
  • a first connection pad connected to the first conductive semiconductor layer through the exposed area and a lower extension part extending from the first connection pad;
  • a first current blocking layer positioned between the first connection pad and the first conductive semiconductor layer, wherein the first connection pad includes a first curved area having a radius of curvature R 1 , wherein the first connection pad includes: a first curved area;
  • the current blocking layer includes a second curved area having a radius of curvature R 2 value, wherein the second curved area is disposed adjacent to the inside of the first curved area, and the lower extension part is in contact with the first connection pad.
  • a main extension extending from the connection, wherein the connection includes a third curved region having a radius of curvature R 3 , wherein R
  • the light emitting device of the present invention by disposing a current blocking layer between the connection pad and the first conductive semiconductor layer, the current can be evenly distributed in the first conductive semiconductor layer.
  • light extraction efficiency of the light emitting device may be improved by using a current blocking layer having a high reflectance.
  • the connection pad and the current blocking layer include a curved area, reliability is improved, and the output of the light emitting device can be improved by inducing the flow of current to the lower extension part connected to the connection pad.
  • FIG. 1 is a plan view illustrating a light emitting device according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view taken along the line AA ′ of the top view of FIG. 1.
  • FIG. 3 is a cross-sectional view taken along the line BB ′ of the top view of FIG. 1.
  • FIG. 4 illustrates various forms of a first current blocking layer according to an embodiment of the present invention.
  • FIG. 5 is a plan view illustrating a light emitting device according to another exemplary embodiment of the present invention.
  • FIG. 6 is a cross-sectional view taken along the line AA ′ of the top view of FIG. 5.
  • FIG. 7 is a cross-sectional view taken along the line BB ′ of the top view of FIG. 5.
  • FIG. 11 and 12 show a light emitting device according to another embodiment of the present invention.
  • FIG. 13 and 14 show a light emitting device according to another embodiment of the present invention.
  • 15 and 16 show a light emitting device according to another embodiment of the present invention.
  • 17 and 18 show light emitting devices according to still another embodiment of the present invention.
  • FIG. 19 is an exploded perspective view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a lighting device.
  • FIG. 20 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a display device.
  • 21 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to another display device.
  • FIG. 22 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a head lamp.
  • a light emitting device includes a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer positioned between the first and second conductivity type semiconductor layers, and penetrates the second conductivity type semiconductor layer and the active layer.
  • a nitride based semiconductor laminate including an exposed region exposing the first conductive semiconductor layer; A first connection pad electrically connected to the first conductivity type semiconductor layer through the exposed region; A first current blocking layer interposed between the first conductive semiconductor layer and the first connection pad; Second connection pads disposed on the second conductive semiconductor layer; And an upper extension extending from the second connection pad.
  • the upper extension part is two or more, and the first connection pad is positioned between the upper extension parts, and the first current blocking layer is a partial area in an area between the first conductive semiconductor layer and the first connection pad. Interposed therebetween, the current spreading efficiency can be increased.
  • An area of the first current blocking layer may not exceed 90% of an area between the first conductive semiconductor layer and the first connection pad.
  • the first current blocking layer may include a SiO 2 layer or a distributed Bragg reflective layer.
  • the distributed Bragg reflection layer may have a structure in which an SiO 2 layer and a TiO 2 layer or an SiO 2 layer and an Nb 2 O 5 layer are alternately stacked.
  • the shape of the first current blocking layer may be the same as that of the first connection pad.
  • the light emitting device may further include a second current blocking layer disposed under the second connection pad and under the plurality of upper extensions.
  • the second current blocking layer may include the same material layer as the first current blocking layer.
  • the width of the current blocking layer disposed below the second connection pad is greater than or equal to the width of the second connection pad, and the width of the current blocking layer disposed below the plurality of upper extensions is greater than that of the plurality of upper extensions. It can be greater than or equal to the width.
  • the light emitting device may further include a lower extension part extending from the first connection pad and contacting the first conductivity type semiconductor layer.
  • the light emitting device may further include an ohmic electrode layer positioned on the second conductive semiconductor layer and ohmic contacting the second conductive semiconductor layer.
  • the ohmic electrode layer may include a transparent electrode layer or a metal electrode layer.
  • the light emitting device may further include an insulating layer covering the nitride based semiconductor stack exposed through the exposed region.
  • the insulating layer may include a SiO 2 layer or a distributed Bragg reflective layer.
  • the insulating layer may be formed through the same process as the first current blocking layer.
  • the nitride based semiconductor laminate includes a plurality of exposed regions
  • the exposure area may include a first exposure area including at least one first hole and at least one second hole, and a second exposure area including at least one third hole.
  • the at least one first hole and the at least one second hole may have a circular or polygonal planar shape, and the at least one third hole may have a shape extending in an arbitrary direction from the at least one second hole.
  • the first connection pad may contact the first conductive semiconductor layer through the first exposed region, and the lower extension portion may contact the second conductive semiconductor layer through the second exposed region.
  • the first current blocking layer may be limited to the first exposed region, and may be limited to a partial region between the first conductive semiconductor layer and the first connection pad.
  • the width of the third hole may be smaller than the width of the first hole and the second hole.
  • the light emitting device may further include a first bonding pad electrically connected to the first connection pad and a second bonding pad electrically connected to the second connection pad.
  • the first bonding pad and the second bonding pad may be electrically insulated.
  • the light emitting device may further include an insulating layer disposed between the first bonding pad and the second bonding pad and the nitride crab semiconductor stack.
  • the first bonding pad The second bonding pad may be electrically connected to the first connection pad and the second connection pad through holes formed in the insulating layer, respectively.
  • a light emitting device includes a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer, and includes an exposed area that exposes the first conductivity type semiconductor layer through the second conductivity type semiconductor layer and the active layer.
  • a first connection pad connected to the first conductive semiconductor layer through the exposed area and a lower extension part extending from the first connection pad; And a first current blocking layer positioned between the first connection pad and the first conductive semiconductor layer, wherein the first connection pad includes a first curved area having a radius of curvature R 1 , wherein the first connection pad includes: a first curved area;
  • the current blocking layer includes a second curved area having a radius of curvature R 2 value, wherein the second curved area is disposed adjacent to the inside of the first curved area, and the lower extension part is in contact with the first connection pad.
  • a main extension extending from the connection, wherein the connection includes a third curved region having a radius of curvature R 3 , wherein R 2 is greater than R 3 and less than R 1 .
  • the first curved area and the second curved area share the same center, and the second curved area is formed by virtual straight lines connecting both ends of the first curved area and the first curved area and the center. Located in At this time, the spacing between the first curved region and the second curved region may be kept uniform. Accordingly, the current injected through the first connection pad can be uniformly distributed.
  • the width of the connection of the lower extension may be greater than a distance between the first curved area and the second curved area, and may decrease as the distance from the first connection pad increases.
  • the width of the main extension may be greater than or equal to an interval between the first curved area and the second curved area.
  • the first current blocking layer may be limited to a partial region in the region between the first conductive semiconductor layer and the first connection pad.
  • the region of the first current blocking layer may not exceed 90% of the region between the first conductive semiconductor layer and the first connection pad. This allows the current to be smoothly distributed without increasing the forward voltage.
  • the first current blocking layer may include a single layer or a distributed Bragg reflective layer, and the distributed Bragg reflective layer may have a structure in which an SiO 2 layer and a TiO 2 layer or an SiO 2 layer and an Nb 2 O 5 layer are alternately stacked. have.
  • the light emitting device may further include a third current blocking layer positioned below the lower extension, and the third current blocking layer may include a plurality of dots spaced apart from each other.
  • a width of the third current blocking layer may be greater than a width of the main extension part, and the main extension part may be connected to the first conductive semiconductor layer in a region between the plurality of dots. That is, the main extension part may be connected to the first conductivity type semiconductor layer discontinuously by the third current blocking layer.
  • the light emitting device includes: a second connection pad disposed on the second conductive semiconductor layer; And an upper extension part extending from the second connection pad.
  • the light emitting device may further include an ohmic electrode layer positioned on the second conductive semiconductor layer and in ohmic contact with the second conductive semiconductor layer, and the second connection pad and the upper extension may be disposed on the ohmic electrode layer. Can be located.
  • FIG. 1 to 3 are plan and cross-sectional views illustrating a light emitting device according to an embodiment of the present invention.
  • FIG. 1 is a plan view of the light emitting device
  • FIG. 2 is a cross-sectional view of a portion corresponding to line A-A 'of the plan view of FIG. 1
  • FIG. 3 is a line B-B' of the plan view of FIG. The cross section of the corresponding part is shown.
  • the light emitting device includes a nitride based semiconductor stack 110, a first connection pad 120, a second connection pad 130, and a first current block layer 140. And a second current blocking layer 150.
  • the light emitting device includes a lower extension 120-1 extending in an arbitrary direction from the first connection pad 120 and an upper extension 130-1 extending in an arbitrary direction from the second connection pad 130. ) May be further included.
  • the lower extension part 120-1 may be formed in a singular or plural number from the first connection pad 120 in any direction, and the width of the lower extension part 120-1 may be the width of the first connection pad 120.
  • the upper extension 130-1 may also be formed in the singular or plural in the direction from the second connection pad 130, and the width of the upper extension 130-1 is the width of the second connection pad 130. May be less than or equal to In particular, two upper extensions 130-1 may be formed, and two upper extensions 130-1 may be formed to surround the first connection pad 120. In the present embodiment, two upper extensions 130-1 are shown, but more upper extensions can be formed.
  • the light emitting device may further include a transparent electrode layer 160 and a substrate 101 positioned on the nitride-based semiconductor stack 110.
  • the light emitting device may further include an insulating layer 165 covering the side surface of the semiconductor stacked structure.
  • the light emitting device may have a polygonal planar shape.
  • the light emitting device may have a rectangular planar shape.
  • the light emitting device may have a generally square planar shape, and the third side surface 100c positioned opposite to the first side surface 100a, the second side surface 100b, and the first side surface 100a. And a fourth side surface 100d positioned opposite to the second side surface 100b.
  • the lower extension part 120-1 may extend from the first connection pad 120 and may extend from the fourth side surface 100d toward the second side surface 100b.
  • the upper extension 130-1 may extend from the second connection pad 130, and may have a curved shape from the second side surface 100b toward the fourth side surface 100d.
  • the present invention is not limited thereto.
  • the nitride based semiconductor stack 110 is disposed on the first conductive semiconductor layer 111 located on the substrate 101, the active layer 112 located on the first conductive semiconductor layer 111, and the active layer 112.
  • the second conductive semiconductor layer 113 is positioned.
  • the nitride-based semiconductor stack 110 may include exposed regions 110a and 110b partially exposing the first conductivity-type semiconductor layer 111. In the exposed regions 110a and 110b, the nitride-based semiconductor stack 110 may form a mesa structure.
  • the current spreading efficiency and the light emission pattern of the light emitting device may be adjusted according to the position, shape, and number of the exposed areas 110a and 110b. In particular, referring to FIGS.
  • the exposed regions 110a and 110b may be surrounded by nitride-based semiconductor layers, and may be spaced apart from the edge of the nitride-based semiconductor stack 110.
  • the exposed region 110a may be formed to be spaced apart from the fourth side surface 100d of the light emitting device.
  • the exposed region 110a may be disposed between the upper extensions 130-1 and spaced apart from the fourth side surface 100d of the light emitting device.
  • the light emitting device may include a structure in which the upper extensions 130-1 extend between the fourth side surface 100d and the exposed area 100a. That is, the upper extensions 130-1 may include a structure surrounding the exposed area 110a.
  • the substrate 101 may be selected from a known material such as Al 2 O 3 , SiC, Si, GaAs, GaN, ZnO, GaP, InP, Ge, or the like. Although not shown through the drawings, an uneven pattern may be formed on and / or under the substrate 101.
  • the uneven patterns of the substrate 101 may have a stripe shape, a lens shape, a pillar shape, a horn shape, or the like. Freely selectable
  • the first conductivity type semiconductor layer 111 is a semiconductor layer doped with the first conductivity type dopant.
  • the first conductive semiconductor layer 111 may be formed of at least one of GaN, InN, AlN, InGaN, AlGaN, and InAlGaN, and the first conductive semiconductor layer 111 may be an n-type semiconductor layer.
  • the single-conducting dopant may include at least one of Si, Ge, Sn, Se, and Te, which are n-type dopants.
  • the active layer 112 may be formed in a single quantum well or multiple quantum well (MQW) structure. That is, at least one of GaN, InN, AlN, InGaN, AlGaN, and InAlGaN may be formed using a Group III-V compound semiconductor material.
  • the active layer 112 may have a structure in which InGaN well layers / GaN barrier layers are alternately formed. The active layer 112 generates light while the carrier supplied from the first conductive semiconductor layer 111 and the carrier supplied from the second conductive semiconductor layer 113 are recombined.
  • the carrier supplied from the first conductivity-type semiconductor layer 111 may be electrons, and the second conductivity-type semiconductor layer 113 may be p-type. In the case of the semiconductor layer, the carrier supplied from the second conductivity type semiconductor layer 113 may be a hole.
  • the second conductivity type semiconductor layer 113 may include a semiconductor layer doped with the second conductivity type dopant and may be formed in a single layer or multiple layers.
  • the second conductive semiconductor layer 113 may be formed of at least one of GaN, InN, AlN, InGaN, AlGaN, and InAlGaN, and when the second conductive semiconductor layer 113 is a p-type semiconductor layer, the second The conductive dopant may include one or more of p-type dopants, Mg, Zn, Ca, Sr, and Ba.
  • the light emitting device according to the present invention may include an undoped layer or another buffer layer to improve crystal quality.
  • the conductive semiconductor layer 113 is a p-type semiconductor layer, various functional layers may be included, such as a current blocking layer (not shown) formed between the active layer 112 and the second conductive semiconductor layer 113.
  • the nitride based semiconductor stack 110 may include exposed regions 110a and 110b.
  • the exposed regions 110a and 110 may partially expose the first conductivity type semiconductor layer 111.
  • the exposed regions 110a and 110 may be formed using photo and etching techniques.
  • the exposed regions 110a and 110b may be formed by defining an etching region using a photoresist and etching the second conductive semiconductor layer 113 and the active layer 112 using dry etching such as ICP. Can be.
  • a portion of the first conductivity type semiconductor layer 111 may be etched during the formation of the exposed regions 110a and 110b.
  • the exposed area 110a may have a generally circular or polygonal planar shape.
  • the exposed area 110b may be formed to extend in an arbitrary direction from the exposed area 110a.
  • the exposed area 110b and the exposed area 110a may be connected to each other.
  • the width of the exposed area 110b may be less than or equal to the width of the exposed area 110a.
  • the current spreading efficiency and the light emission pattern of the light emitting device may be adjusted according to the position, shape, and number of the exposed areas 110a and 110b.
  • the exposed region 110a may be formed to be spaced apart from the fourth side surface 100d of the light emitting device.
  • the nitride based semiconductor stack 110 may be located between the exposed region 110a and the fourth side surface 100d.
  • the exposed area 110b may have a structure extending from the exposed area 110ba in the direction of the second side surface 100b at the fourth side surface 100d.
  • the position, shape, and number of the exposed regions 110a and 110b are not limited to those shown in FIG. 1 and may be variously changed within the scope of the present invention.
  • the first connection pad 120 and the lower extension part 120-1 may be electrically connected to the first conductivity type semiconductor layer 111.
  • the first connection pad 120 and the lower extension part 120-1 may make ohmic contact with the first conductivity type semiconductor layer 111. have.
  • the first connection pad 120 and the lower extension part 120-1 may cover a portion of the nitride based semiconductor stack 110.
  • the first connection pad 120 and the lower extension part 120-1 may be electrically connected to the first conductivity type semiconductor layer 111 through the exposed areas 110a and 110b. Accordingly, the portion into which the current is injected into the nitride based semiconductor stack 110 through the first connection pad 120 and the lower extension 120-1 may be controlled according to the position and shape of the exposed regions 110a and 110b. Can be.
  • the exposed area 110b and the exposed area 110a may be connected to each other, so that the first connection pad 120 positioned in the exposed area 110a and the lower extension 120-1 positioned in the exposed area 110b may be connected to each other. Can be electrically connected to each other.
  • the lower extension part 120-1 may have a shape extending in an arbitrary direction from the first connection pad 120, where the width of the lower extension part 120-1 is the width of the first connection pad 120. May be less than or equal to In particular, the lower extension part 120-1 may extend from the first connection pad 120 and may extend from the fourth side surface 100d toward the second side surface 100b.
  • the first connection pad 120 and the lower extension 120-1 may be selected from, but are not limited to, gold (Au), silver (Ag), aluminum (Al), copper (Cu), or an alloy including them. It may be made of at least one conductive material. In addition, the first connection pad 120 and the lower extension part 120-1 may be formed of a plurality of layers. The first connection pad 120 and the lower extension 120-1 may be formed of at least two layers selected from a chromium (Cr) layer, an aluminum (Al) layer, a nickel (Ni) layer, and a gold (Au) layer. .
  • the first connection pad 120 and the lower extension part 120-1 may have a structure in which chromium layers, aluminum layers, chromium layers, nickel layers, and gold layers are sequentially stacked.
  • each layer may have a thickness of, for example, 8.5, 1200, 1600, 900 and 2000 angstroms.
  • the first connection pad 120 and the lower extension part 120-1 may be formed by depositing and patterning a metal material on the nitride based semiconductor stack 110. That is, the present invention is not limited thereto, but the first connection pad 120 and the lower extension part 120-1 may be formed through the same process.
  • the first connection pad 120 formed in the exposed region 110a may also be formed spaced apart from the fourth side surface 100d. have.
  • the nitride based semiconductor stack 110 may be located between the exposed region 110a and the fourth side surface 100d.
  • the second connection pad 130 and the upper extension 130-1 may be positioned on the second conductive semiconductor layer 113 and electrically connected to the second conductive semiconductor layer 113.
  • the second connection pad 130 and the upper extension 130-1 may have various shapes on the second conductivity-type semiconductor layer 113, and a portion into which a current is injected into the nitride-based semiconductor stack 110 is second. It may be controlled according to the position and shape of the connection pad 130 and the upper extension 130-1.
  • the upper extension 130-1 may be singular or plural. For example, referring to FIG. 1, the two upper extensions 130-1 extending from the second connection pad 130 may have a shape surrounding the first connection pad 120.
  • the second connection pad 130 and the upper extension 130-1 may be selected from, but are not limited to, gold (Au), silver (Ag), aluminum (Al), copper (Cu), or an alloy containing them. It may be made of at least one conductive material.
  • the second connection pad 130 and the upper extension 130-1 may be formed of a plurality of layers.
  • the second connection pad 130 and the upper extension 130-1 may be formed of at least two layers selected from, for example, a chromium layer, an aluminum layer, a nickel layer, and a gold layer.
  • the second connection pad 130 and the upper extension 130-1 may have a structure in which a chromium layer, an aluminum layer, a chromium layer, a nickel layer, and a gold layer are sequentially stacked.
  • each layer may have a thickness of, for example, 8.5, 1200, 1600, 900 and 2000 angstroms.
  • the second connection pad 130 and the upper extension 130-1 may be formed by depositing and patterning a metal material on the nitride-based semiconductor stack 110. Although not limited thereto, the second connection pad 130 and the upper extension 130-1 may be formed through the same process. In addition, the second connection pad 130 and the upper extension 130-1 may be formed through the same process as the first connection pad 120 and the lower extension 120-1.
  • first connection pad 120 and the second connection pad 130 are for electrical connection of the light emitting device, and, for example, wire bonding to each of the first connection pad 120 and the second connection pad 130 ( bonding can be done.
  • the light emitting device may be electrically connected to an external device through a wire bonding formed on each of the first connection pad 120 and the second connection pad 130, and may receive power.
  • the transparent electrode layer 160 made of a metal or metal oxide such as Ni / Au, ITO, transparent conducting oxide (TCO) or NiO, ZnO, etc. Can be formed.
  • the transparent electrode layer 160 may be referred to as an ohmic electrode layer.
  • the transparent electrode layer 160 may increase ohmic contact by forming an ohmic contact on the second conductive semiconductor layer 113, and the transparent electrode layer 160 maintains a transmittance of a predetermined level or more to improve efficiency and brightness of the light emitting device. It can increase.
  • the light emitting device when the light emitting device includes the transparent electrode layer 160, the light emitting device is between the second connection pad 130 and the second conductive semiconductor layer 113, and the upper extension 130-1 and the second conductive material.
  • the transparent electrode layer 160 may be interposed between the type semiconductor layers 113.
  • the transparent electrode layer 160 may include an opening 160a.
  • the second connection pads 130 may directly contact the second current blocking layer 150.
  • the opening 160a is formed between the second connection pad 130 and the second current blocking layer 150, and the width of the opening 160a may be smaller than the width of the second connection pad 130. Therefore, a portion of the second connection pad 130 may contact the transparent electrode layer 160 in the boundary region, and a portion of the second connection pad 130 may contact the second current blocking layer 150 through the opening 160a in the central region. have. Due to the step formed by the opening 160a under the second connection pad 160, the coupling force of the second connection pad 160 may be increased, thereby improving the structural stability of the light emitting device.
  • the first current blocking layer 140 may be interposed between the first connection pad 120 and the first conductivity type semiconductor layer 111 in the exposed region 110a.
  • the first current blocking layer 140 may be referred to as an n-type current blocking layer.
  • the first current blocking layer 140 may be interposed in a portion of the region between the first connection pad 120 and the first conductive semiconductor layer 111, and thus, the first current blocking layer 120 may be formed from the first conductive pad 120. The current may be effectively distributed to the semiconductor layer 111.
  • the first connection pad 120 in a structure in which the first connection pad 120 is positioned between the upper extensions 130-1, when the first current blocking layer 140 does not exist, the first connection pad is present. There may be a problem that the horizontal dispersion of the current injected through the 120 is not smoothly made. That is, in the structure as shown in FIG. 1, when the first current blocking layer 140 does not exist, an upper extension portion formed around the first connection pad 120 is provided with current injected into the first connection pad 120. Problems concentrated on 130-1) may occur.
  • the light emitting device according to the present invention has a structure in which the first connection pad 120 is spaced apart from the fourth side surface 100d of the light emitting device. The pad may further extend between the pad 120 and the fourth side surface 100d to surround the first connection pad. Similarly, in such a structure, a problem may occur in which the horizontal dispersion of current is not smoothly performed.
  • the first current blocking layer 140 may be interposed between the first conductive semiconductor layer 111 and the first connection pad 120.
  • the first current blocking layer 140 may prevent the current injected from the first connection pad 120 from being concentrated on the first conductive semiconductor layer 111 positioned below the first current blocking layer 140. That is, by the first current blocking layer 140, the injected current may be distributed to the lower extension 120-1, and accordingly, the first conductive semiconductor under the first connection pad 120 is located at a specific position. Concentration of current in the layer can be prevented.
  • the first current blocking layer 140 may be interposed between the first connection pad 120 and the first conductivity-type semiconductor layer 111 in the exposed region 110a.
  • the first current blocking layer 140 may have any shape, for example, a circle, a rectangle, a triangle, and the like, but is not limited thereto.
  • the first current blocking layer 140 may have a circular shape similar to that of the exposed region 110a.
  • the present invention is not limited thereto, and the first current blocking layer 140 may have various shapes and sizes as described later with reference to FIG. 4.
  • the area of the first current blocking layer 140 may be limited to a predetermined level in the exposed area 110a. That is, although the first current blocking layer 140 may be formed to have an arbitrary width at any position in the exposed region 110a, the first current blocking layer 140 may be formed at an arbitrary area. It should not exceed 90%. This is because when the area of the first current blocking layer 140 is increased, the current is well distributed and thus the power of the light emitting device can be improved, but when the area is increased by a certain level or more, the forward voltage of the light emitting device is forward. This is because voltage, Vf) may increase rapidly. Therefore, the area of the first current blocking layer 140 between the first connection pad 120 and the first conductive semiconductor layer 111 is the first connection pad 120 and the first conductive semiconductor layer 111.
  • the area of the first current blocking layer 140 between the first connection pad 120 and the first conductive semiconductor layer 111 is the first connection pad 120 and the first conductive semiconductor layer 111. If the level is 90% between them, the maximum efficiency of the light emitting device can be achieved. That is, the output of the light emitting device can be maximized without increasing the forward voltage. If the area of the first current blocking layer 140 is between the first connection pad 120 and the first conductivity-type semiconductor layer 111, the first connection pad 120 and the first conductivity-type semiconductor layer 111 may be used. If it is 90% or more between them, the forward voltage may increase due to the lack of the n-contact region.
  • the top surface of the first connection pad 120 is disposed. Steps can occur. Due to the step, the area of the upper surface of the first connection pad 120 is increased.
  • the ball sear test (BST) may be increased due to an increase in the area of the upper surface of the first connection pad 120, thereby increasing adhesion between the wire and the first connection pad 120 during wire bonding (not shown). have.
  • the first current blocking layer 140 may include a distributed Bragg reflector (DBR) in which an SiO 2 layer or a low refractive material layer and a high refractive material layer are alternately stacked.
  • DBR distributed Bragg reflector
  • the distributed Bragg reflective layer has a structure in which an SiO 2 layer and a TiO 2 layer or an SiO 2 layer and an Nb 2 O 5 layer are alternately stacked, thereby making it an insulating reflective layer having high reflectance.
  • the distributed Bragg reflector may have high reflectivity for light in a specific wavelength range depending on structural properties and materials.
  • the light emitting device may further include a second current blocking layer 150.
  • the second current blocking layer 150 is interposed between the second connection pad 130 and the second conductive semiconductor layer 113 and between the upper extension 130-1 and the second conductive semiconductor layer 113. Can increase the current spreading efficiency.
  • the second conductive semiconductor layer 113 is a p-type semiconductor layer
  • the second current blocking layer 150 may be referred to as a p-type current blocking layer.
  • the second current blocking layer 150 is disposed between the second connection pad 130 and the second conductive semiconductor layer 113 and the upper extension 130-1.
  • the second conductive semiconductor layer 113 may be interposed below the transparent electrode layer 160.
  • the width of the second current blocking layer 150 interposed between the second connection pad 130 and the second conductive semiconductor layer 113 may be greater than or equal to that of the second connection pad 130.
  • the width of the second current blocking layer 150 interposed between the upper extensions 130-1 and the second conductive semiconductor layer 113 may be greater than or equal to that of the upper extensions 130-1. have.
  • the second current blocking layer 150 may include the same material layer as the first current blocking layer 140. That is, the second current blocking layer 150 may include a distributed Bragg reflector (DBR) in which an SiO 2 layer or a low refractive material layer and a high refractive material layer are alternately stacked.
  • DBR distributed Bragg reflector
  • the distributed Bragg reflective layer has a structure in which an SiO 2 layer and a TiO 2 layer or an SiO 2 layer and an Nb 2 O 5 layer are alternately stacked, thereby making it an insulating reflective layer having high reflectance.
  • the second current blocking layer 150 may be formed through the same process as the first current blocking layer 140.
  • the light emitting device may further include an insulating layer 165 covering the side surface of the nitride based semiconductor laminate 110. 2 and 3, some side surfaces of the nitride based semiconductor stack 110 may be exposed in the exposed regions 110a and 110b. In detail, side surfaces of the active layer 112 and the second conductivity-type semiconductor layer 113 may be exposed in the exposed regions 110a and 110b. In addition, some side surfaces of the first conductivity-type semiconductor layer 111 may be exposed in the exposed regions 110a and 110b.
  • the insulating layer 165 may cover the side surface of the nitride based semiconductor laminate 110 exposed in the exposed region 110a. This is to block electrical connection between the wire and the nitride-based semiconductor stack 110 in the case where wire bonding is performed on the first connection pad 120 in the exposed region 110a. Reliability of the light emitting device may be improved through the insulating layer 165.
  • FIG. 4 illustrates various forms of the first current blocking layer 140 according to an embodiment of the present invention.
  • 4A to 4H illustrate some regions, that is, regions C of FIG. 1, for the purpose of describing various forms of the first current blocking layer 140.
  • the first current blocking layer 140 is defined between the first connection pad 120 and the first conductivity-type semiconductor layer 111 in the exposed region 110a and a partial region thereof. Intervened in Here, the first current blocking layer 140 is not formed in the other area beyond the area between the first connection pad 120 and the first conductivity type semiconductor layer 111 in the exposed area 110a. In addition, the first current blocking layer 140 is interposed in a partial region between the first connection pad 120 and the first conductive semiconductor layer 111 and is not interposed in the remaining region between the first connection pad 120 and the first connection pad ( 120 and the first conductivity-type semiconductor layer 111 may be electrically connected to each other, and the forward voltage of the light emitting device may be prevented. In addition, the first current blocking layer 140 may be interposed in a portion of the exposed region 110b between the lower extension part 120-1 and the first conductivity type semiconductor layer 111.
  • the first current blocking layer 140 may include the first connection pad 120 and the first conductive semiconductor layer 111 in the exposed region 110a. It is formed not only in the interregion but also in other parts of the exposed region 110a. However, the lower portion of the first current blocking layer 140 is removed between the first connection pad 120 and the first conductive semiconductor layer 111 as shown in FIG. 4B, or FIG. 4C. And some side surfaces as shown in (d) of FIG. 4, or may have a form in which the center portion is removed as shown in (e) of FIG. 4. The first connection pad 120 and the first conductivity-type semiconductor layer 111 may be electrically connected through the removed or recessed portions, and the area occupied by the first current blocking layer 140 may be limited so that the forward voltage may be reduced. The rise of can be prevented.
  • the first current blocking layer 140 may include the first connection pad 120 and the first conductivity-type semiconductor layer 111 in the exposed region 110a. It can be seen that not only the inter-region but also other portions of the exposed region 110a are formed. In addition, the first current blocking layer 140 may be separated into two parts. However, the present invention is not limited thereto, and the first current blocking layer 140 may be separated into more portions. The first connection pad 120 and the first conductive semiconductor layer 111 may be electrically connected to each other through the separated region, and the region occupied by the first current blocking layer 140 may be limited, thereby preventing the forward voltage. Elevation can be prevented.
  • the first current blocking layer 140 is exceptionally formed in the entire exposed area 110a. Therefore, the first connection pad 120 and the first conductive semiconductor layer 111 may not be electrically connected in the exposed region 110a. However, since the lower extension part 120-1 electrically connected to the first connection pad 120 is electrically connected to the first conductivity type semiconductor layer 111 through the exposure area 110b, as a result, the first connection pad may be used. 120 is also electrically connected to the first conductivity type semiconductor layer 111.
  • FIG. 5 to 7 are plan views and cross-sectional views for describing a light emitting device according to another embodiment of the present invention.
  • FIG. 5 is a plan view of the light emitting device
  • FIG. 6 shows a cross section of a portion corresponding to the line A-A 'of the plan view of FIG. 5
  • FIG. 7 corresponds to the line B-B' of the plan view of FIG. The cross section of the part to be shown is shown.
  • the exposed regions 110a and 110b, the first connection pad 120, the lower extension 120-1, and the second connection are compared with the embodiments described with reference to FIGS. 1 to 3. There is a difference in the shape, the size and the number of the pad and the upper extension (130-1).
  • the light emitting device of the present embodiment may further include an ohmic electrode layer 160, an insulating layer 170, and bonding pads 180a and 180b.
  • the light emitting device of the present embodiment will be described based on differences, and detailed descriptions of the same components will be omitted.
  • the light emitting device includes a nitride based semiconductor stack 110, a first connection pad 120, a second connection pad 130, a first current blocking layer 140, and a second current blocking. Layer 150.
  • the light emitting device includes a lower extension 120-1 extending in an arbitrary direction from the first connection pad 120 and an upper extension 130-1 extending in an arbitrary direction from the second connection pad 130. More).
  • the light emitting device may have a rectangular planar shape.
  • the light emitting device may have a generally square planar shape, and the third side surface 100c positioned opposite to the first side surface 100a, the second side surface 100b, and the first side surface 100a. And a fourth side surface 100d positioned opposite to the second side surface 100b.
  • the present invention is not limited thereto.
  • the nitride based semiconductor layer 110 includes a first conductive semiconductor layer 111, an active layer 112 positioned on the first conductive semiconductor layer 111, and a second conductive semiconductor layer positioned on the active layer 112. (113).
  • the nitride-based semiconductor stack 110 may include regions 110a and 110b partially exposing the first conductivity-type semiconductor layer 111. The current dispersion efficiency and the light emission pattern of the light emitting device may be adjusted according to the position, shape, and number of the exposed areas 110a and 110b.
  • regions 110a and 110b partially exposed to the first conductivity-type semiconductor layer 111 may include holes. That is, the exposed area 110a may include first holes 110a-1 and 110a-2 and second holes 110a-3. The exposed area 110a may be referred to as a first exposed area. A plurality of first holes 110a-1 and 110a-2 and a plurality of second holes 110a-3 may be formed. The first holes 110a-1 and 110b-2 and the second holes 110a-3 may have a planar shape of generally circular or polygonal shape. The exposed area 110b may be formed to extend in an arbitrary direction from the second hole 110a-3. The exposed area 110b may be referred to as a second exposed area. In addition, the exposed area 110b may be referred to as a third hole.
  • the third hole (or the exposed area) 110b and the second hole 110a-3 may be connected to each other.
  • the width of the third hole 110b may be less than or equal to the width of the first holes 110a-1 and 110a-2 and the second holes 110a-3.
  • the first holes 110a-1 and 110a-2 and the second holes 110a-3 may have a circular planar shape and may be formed in plural.
  • the third hole 110b may extend from the second hole 100a-3 and may extend from the first side surface 100a toward the third side surface 100c.
  • the first connection pad 120 may be electrically connected to the first conductive semiconductor layer 111, and in particular, the first connection pad 120 may be in ohmic contact with the first conductive semiconductor layer 111. That is, the first connection pad 120 is formed in the exposed region 110a including the first holes 110a-1 and 110a-2 and the second holes 110a-3 to form the first conductive semiconductor layer 111. ) May be electrically connected. Therefore, the portion of the current injected into the nitride-based semiconductor stack 110 through the first connection pad 120 may be controlled according to the position and shape of the exposed region 110a. As illustrated in FIG. 5, a plurality of first connection pads 120 may be formed in a predetermined pattern based on the exposed area 110a, but is not limited thereto.
  • the lower extension part 120-1 may be formed in the exposed area (or the third hole) 110b to be electrically connected to the first conductivity type semiconductor layer 111.
  • the exposed area 110b is connected to the second hole 110a-3, and thus the lower extension part 120-1 is electrically connected to the first connection pad 120 formed in the second hole 110a-3. Can be connected.
  • the lower extension part 120-1 may be formed in plural in a predetermined pattern based on the exposed area 110b as shown in FIG. 5, but is not limited thereto.
  • the light emitting device may include a second connection pad 130.
  • the second connection pad 130 may be positioned on the nitride based semiconductor stack 110 and may be in ohmic contact with the second conductivity type semiconductor layer 113.
  • the second connection pads 130 may be formed in plural.
  • the light emitting device may include an upper extension part 130-1 extending from some second connection pads 130.
  • the upper extension 130-1 may be formed to extend from the third side surface 100c toward the first side surface 100a and may be formed in plural.
  • a plurality of second connection pads 130 and upper extensions 130-1 may be formed in a predetermined pattern as illustrated in FIG. 5, but is not limited thereto.
  • first connection pad 120 and the second connection pad 130 are for electrical connection of the nitride-based semiconductor stack 110, for example, the first connection pad 120 and the second connection pad 130. May be electrically connected to the first bonding pads 180a and the second bonding pads 180b, respectively.
  • the light emitting device may be electrically connected to an external device through the first bonding pad 180a and the second bonding pad 180b and may be supplied with power.
  • the first current blocking layer 140 may be interposed between the first connection pad 120 and the first conductive semiconductor layer 111.
  • the first current blocking layer 140 is interposed in a portion of the region between the first connection pad 120 and the first conductive semiconductor layer 111 so that the current can be effectively distributed to the first conductive semiconductor layer 111. Can help.
  • the current is injected through the first connection pad 120. This may not occur smoothly.
  • the first current blocking layer 140 is interposed between the first conductive semiconductor layer 111 and the first connection pad 120 to effectively distribute the current.
  • the first current blocking layer 140 may be interposed between the first connection pad 120 and the first conductivity-type semiconductor layer 111 in the exposed region 110a.
  • the first current blocking layer 140 may have any shape, for example, a circle, a rectangle, a triangle, and the like, but is not limited thereto.
  • the first current blocking layer 140 may have a circular shape similar to that of the exposed region 110a. However, it is not limited thereto.
  • the first current blocking layer 140 may be one of various shapes of the first current blocking layer 140 shown in FIG. 4.
  • the area of the first current blocking layer 140 may be limited to a predetermined level in the exposed area 110a. That is, the first current blocking layer 140 may be formed to have an arbitrary width in any area of the exposed area 110a, but the first current blocking layer 140 may be formed in any area of the area between the first connection pad 120 and the first conductivity type semiconductor layer 111. It should not occupy more than 90%. This is because when the area of the first current blocking layer 140 is increased, the current is well distributed and the power of the light emitting device is improved, but when the area is increased by a certain level or more, the forward voltage of the light emitting device is increased. This is because Vf) may increase rapidly.
  • the area of the first current blocking layer 140 may be limited to 90% or less between the first connection pad 120 and the first conductivity-type semiconductor layer 111 in the exposed region 110a.
  • the area of the first current blocking layer 140 is 90% of the area between the first connection pad 120 and the first conductive semiconductor layer 111, the maximum efficiency of the light emitting device can be achieved. That is, the output of the light emitting device can be maximized without increasing the forward voltage.
  • the area of the first current blocking layer 140 is greater than or equal to 90% of the area where the first connection pad 120 and the first conductive semiconductor layer 111 contact each other, the forward direction may occur due to the lack of the n-contact region. The voltage can be raised.
  • the first current blocking layer 140 may include a distributed Bragg reflector (DBR) in which an SiO 2 layer or a low refractive material layer and a high refractive material layer are alternately stacked.
  • DBR distributed Bragg reflector
  • the distributed Bragg reflective layer has a structure in which an SiO 2 layer and a TiO 2 layer or an SiO 2 layer and an Nb 2 O 5 layer are alternately stacked, thereby making it an insulating reflective layer having high reflectance.
  • a step may occur on the top surface of the first connection pad 120.
  • the light emitting device may further include a second current blocking layer 150.
  • the second current blocking layer 150 may be interposed between the second connection pad 130 and the upper extension 130-1 and the second conductive semiconductor layer 113 to increase the current dispersion efficiency.
  • the second conductive semiconductor layer 113 is a p-type semiconductor layer
  • the second current blocking layer 150 may be referred to as a p-type current blocking layer.
  • the light emitting device includes the ohmic electrode layer 160
  • the second current blocking layer 150 is disposed between the second connection pad 130 and the upper extension 130-1 and the second conductive semiconductor layer 113.
  • the ohmic electrode layer 160 may be interposed below.
  • the ohmic electrode layer 160 may be a transparent electrode layer or a metal electrode layer.
  • the width of the second current blocking layer 150 interposed between the second connection pad 130 and the second conductive semiconductor layer 113 may be greater than or equal to that of the second connection pad 130.
  • the width of the second current blocking layer 150 interposed between the upper extension 130-1 and the second conductive semiconductor layer 113 may be equal to or greater than the width of the upper extension 130-1.
  • the second current blocking layer 150 may include the same material layer as the first current blocking layer 140.
  • the second current blocking layer 150 may be formed through the same process as the first current blocking layer 140.
  • the light emitting device may further include an insulating layer 170 formed on the nitride based semiconductor stack 110.
  • the insulating layer 170 may include a distributed Bragg reflector (DBR) in which an SiO 2 layer or a low refractive material layer and a high refractive material layer are alternately stacked.
  • DBR distributed Bragg reflector
  • the distributed Bragg reflective layer has a structure in which an SiO 2 layer and a TiO 2 layer or an SiO 2 layer and an Nb 2 O 5 layer are alternately stacked, thereby making it an insulating reflective layer having high reflectance.
  • the insulating layer 170 may include a plurality of openings 190a and 190b.
  • the first connection pad 120 and the first bonding pad 180a to be described later may be electrically connected through the opening 190a.
  • the second connection pad 130 and the second bonding pad 180b to be described later may be electrically connected through the opening 190b.
  • a plurality of openings 190a and openings 190b may be formed.
  • the first bonding pads 180a and the second bonding pads 180b may be electrically connected to the first connection pads 120 and the second connection pads 130, respectively. 5 to 7, the first bonding pad 180a may be in contact with the first connection pad 120 through the openings 190a, and the second bonding pad 180b may be through the openings 190b. It may be in contact with the second connection pad 130.
  • FIG. 8 to 10 are plan views and cross-sectional views for describing a light emitting device according to still another embodiment of the present invention. Specifically, FIG. 8 is a plan view of the light emitting device, FIG. 9 is an enlarged view of the region ⁇ of FIG. 8, and FIG.
  • the light emitting device according to the present embodiment has the same configuration as that of the light emitting device shown in FIG. 1, except that the first connection pad 220, the lower extension part 220-1, the first current blocking layer 240, and the insulation are provided. There are some differences in the shape of layer 265.
  • the light emitting device according to the present embodiment further includes a third current blocking layer 270.
  • the description of the same configuration is omitted, with reference to the planar shape thereof enlarged in Fig. 9 will be described mainly on the difference.
  • the edge of the first connection pad 220 is connected to the first conductivity type semiconductor layer 111.
  • the edge of the first connection pad 220 includes a first curved area 221.
  • the edge of the first connection pad 220 may include straight regions.
  • the shape of the edge of the first connection pad 220 may be the same as or similar to the shape of the outermost edge of the region where the first connection pad 220 and the first conductive semiconductor layer 111 contact each other. Accordingly, the edge of the first connection pad 220 and the outermost edge of the region where the first connection pad 220 and the first conductive semiconductor layer 111 contact each other may be used in the same sense.
  • the first curved area 221 means at least a portion of the edge.
  • the first curved area 221 may have a radius of curvature R 1 . That is, the first curved area 221 may have a curvature of 1 / R 1 .
  • the first curved area 221 may connect straight areas. Referring to FIG. 9, it is disclosed that four first curved areas 221 connect four straight areas in the first connection pad 220.
  • the first connection pad 220 may not include the angled portion. have.
  • the first connection pad 220 may be formed by depositing a metal in a lift-off method using a mask.
  • the mask for forming the first connection pad 200 may also include an angled portion.
  • the deposition of the metal on the angled portion of the mask may not be performed smoothly. In this case, it is difficult to obtain the first connection pad 220 according to the designed shape.
  • the first connection pad 220 is designed not to include the angled area as the first connection pad 220 includes the first curved areas 221, the first connection pad 220 having the designed shape can be easily obtained.
  • first connection pad 220 when the first connection pad 220 includes an angled portion, current injected through a wire bonded to the first connection pad 220 may be concentrated on the angled portion of the first connection pad 220. This may prevent the current from being evenly distributed in the horizontal direction in the light emitting device, and as a result, may lower the output of the light emitting device.
  • the first connection pad 220 is designed not to include the angled portion as the first curved area 221 includes the first curved region 221, the current concentration phenomenon does not occur as described above, and thus the current is evenly distributed in the horizontal direction. Can be. Accordingly, electrostatic discharge (ESD) and electro over stress (EOS) of the light emitting device can be improved.
  • ESD electrostatic discharge
  • EOS electro over stress
  • the first current blocking layer 240 may be interposed between the first connection pad 220 and the first conductive semiconductor layer 111.
  • the first current blocking layer 240 may be interposed in a portion of the region between the first connection pad 220 and the first conductive semiconductor layer 111, and thus, the first current blocking layer 220 may be disposed from the first conductive pad 220.
  • the current may be effectively distributed to the semiconductor layer 111.
  • the planar shape of the first current blocking layer 240 may be very similar to the planar shape of the first connection pad 220.
  • An edge of the first current blocking layer 240 may include a second curved area.
  • an edge of the first current blocking layer 240 may include straight regions.
  • the second curved area 241 may be disposed adjacent to the inside of the first curved area 221.
  • the first curved region 221 and the second curved region 241 may share the same center (not shown), and the second curved region 241 may be connected to the first curved region 221. It may be located within the sector region formed through the center.
  • the second curved region 241 is the first curved region 221.
  • the second curved area 241 may have a radius of curvature R 2 , where the R 2 value may be smaller than the R 1 value. Accordingly, the distance G1 between the first curved area 221 and the second curved area 241 positioned inside thereof may be maintained uniformly.
  • the interval G1 of the first curved region 221 and the second curved region 241 is equal to the interval between the linear region of the first connection pad 220 and the linear region of the first current blocking layer 240. Can be formed. Accordingly, the width of the region where the first connection pad 220 and the first conductive semiconductor layer 111 are defined by the first current blocking layer 240 may be uniformly formed. Through this, the current injected through the first connection pad 220 may be uniformly distributed in all directions.
  • the lower extension part 220-1 may extend from the first connection pad 220 and may be connected to the first conductive semiconductor layer 111. Referring to FIG. 9, the lower extension part 220-1 may include a connection part 220-1a and a main extension part 220-1b. The connection part 220-1a may connect the main extension part 220-1b to the first connection pad 220.
  • the planar shape of the connecting portion 220-1a is shown.
  • the edge of the connector 220-1a may include a third curved area 221-1.
  • the connection part 220-1a may include two third curved areas 221-1, where the third curved area 221-1 may have a radius of curvature R 3 .
  • the width G2 of the connection part 220-1a may decrease as the distance from the first connection pad 220 increases.
  • the minimum width of the connecting portion 220-1a may be larger than the gap G1 between the first curved area 221 and the second curved area 241.
  • connection portion 220-1a having a relatively large area.
  • width G2 of the connecting portion 220-1a is relatively wide, the risk that the connecting portion 220-1a may be disconnected from the first connection pad 220 is reduced, so that the reliability of the light emitting device is improved. Can be improved.
  • the R 3 value may be smaller than the R 1 value and the R 2 value. That is, the third curved area 221-1 may have a greater degree of bending than the first curved area 221 and the second curved area 241.
  • the width of the connection portion 220-1a adjacent to the first connection pad 220 becomes relatively large. That is, the planar area of the connection part 220-1a may be relatively widened relatively. This requires a wider exposure area 110a, 110b, whereby the light emitting area is reduced and the output of the light emitting device can be reduced.
  • the width G3 of the main extension part 220-1b may be greater than or equal to the gap G1 between the first curved area 221 and the second curved area 241.
  • the width G3 of the main extension part 220-1b may be 5 ⁇ m
  • the interval G1 between the first curved area 221 and the second curved area 241 may be 4 ⁇ m.
  • the width G3 of the main extension part 220-1b and the gap G1 between the first curved area 221 and the second curved area 241 are not limited thereto, and are within the scope of the present invention. It can be changed in various ways.
  • the gap G1 between the first curved region 221 and the second curved region 241 is a region in which the first connection pad 220 is connected to the first conductive semiconductor layer 111. Is associated with. That is, as the distance G1 between the first curved region 221 and the second curved region 241 increases, the area where the first connection pad 220 is connected to the first conductive semiconductor layer 111 increases. .
  • the width G2 of the connecting portion 220-1a is made larger than the gap G1 between the first curved region 221 and the second curved region 241, or the width of the main extension portion 220-1b.
  • the current that is injected into the first connection pad 220 is lower than the extended portion 220-1 by making G3 greater than the distance G1 between the first curved region 221 and the second curved region 241. Can be guided more smoothly towards the side.
  • the insulating layer 265 may cover a portion of the side surface of the semiconductor stack 110 in the exposed region 110a. Specifically, portions of the side surfaces of the active layer 112 and the second conductivity-type semiconductor layer 113 may be exposed in the exposed region 110a. The insulating layer 265 covers the exposed side surfaces of the active layer 112 and the second conductive semiconductor layer 113 so that the wires bonded to the first connection pads 220 are exposed. The connection with the second conductive semiconductor layer 113 can be prevented. Accordingly, the reliability of the light emitting device can be increased.
  • the insulating layer 265 according to the present embodiment may be disposed under the lower extension part 220-1, unlike the insulating layer 265 shown in FIGS. 1 to 3. That is, the insulating layer 265 according to the present exemplary embodiment may have a single unbroken strip shape, and a part of the insulating layer 265 may be covered by the lower extension part 220-1. Accordingly, the insulating layer 265 according to the present embodiment may have higher structural stability than the insulating layer 265 of FIGS. 1 to 3 in the disconnected form. For example, a portion of the insulating layer 265 according to the present embodiment is fixed by the lower extension part 220-1, so that the risk of peeling may be reduced.
  • the width G2 of the connection portion 220-1a is equal to the width G1 of the gap G1 of the first curved region 221 and the second curved region 241 or the width of the main extension portion 220-1b ( Can be relatively larger than G3). Accordingly, the area in which the connecting portion 220-1a contacts the first conductive semiconductor layer 111 may be relatively large, and in this case, the current may not be smoothly injected into the main extension portion 220-1b. Therefore, a part of the insulating layer 265 is disposed below the connecting portion 220-1a to limit the connection area between the connecting portion 220-1a and the first conductivity type semiconductor layer 111, thereby extending the main extension portion 220-1b. Can increase the injection current.
  • the third current blocking layer 270 may be located below the lower extension 220-1. 8 and 10, the third current blocking layer 270 may include a plurality of dots spaced apart from each other. The width of the third current blocking layer 270 may be greater than the width of the lower extension part 220-1, specifically, the main extension part 220-1b. Accordingly, the third current blocking layer 270 may limit the main extension portion 220-1b from being connected to the first conductive semiconductor layer 111.
  • the main extension part 220-1b may be connected to the first conductivity type semiconductor layer 111 discontinuously by the third current blocking layer 270. That is, the main extension part 220-1b may be connected to the first conductivity type semiconductor layer 111 only in a region between the plurality of dots.
  • the distance between each dot may be controlled to control the distance between the lower extension part 220-1 and the first conductivity type semiconductor layer 111.
  • the distance between each dot is not particularly limited and may be variously set. For example, the distance between each dot may be set the same.
  • the third current blocking layer 270 allows the current injected through the first connection pad 220 to be delivered to the lower extension part 220-1, specifically, to the end of the main extension part 220-1b, The current can be injected into a wide area. However, the third current blocking layer 270 is not disposed at the end of the main extension part 220-1b. This is for the terminal of the main extension part 220-1b to be connected to the first conductivity type semiconductor layer 111 so that a current can be smoothly injected into the upper extension part 130-1 or the second connection pad 130. .
  • FIG. 11 and 12 are plan views illustrating light emitting devices according to still another exemplary embodiment of the present invention. Specifically, FIG. 11 is a plan view of the light emitting device according to the present embodiment, and FIG. 12 is an enlarged view of the region ⁇ of FIG.
  • the light emitting device has the same configuration as that of the light emitting device disclosed in FIGS. 8 to 10, and has a side shape, a first connection pad 320, a lower extension part 320-1, There is a difference in the shape of the upper extension 230-1 and the first current blocking layer 340.
  • the description of the same configuration will be omitted, and the description will be focused on the differences.
  • Side surfaces of the semiconductor stack 110 may include a plurality of grooves 110g. Referring to FIG. 11, near each side surface 100a to 100d of the light emitting device, the semiconductor stack 110 is formed of the first conductive semiconductor layer 111 through the second conductive semiconductor layer 113 and the active layer 112. ) May include an exposed area 110c.
  • side surfaces of the active layer 112 and the second conductivity-type semiconductor layer 113 may be exposed along the side surfaces 100a to 100d of the light emitting device.
  • a portion of the side surface of the first conductivity type semiconductor layer 111 may be exposed.
  • Side surfaces of the exposed active layer 112 and the second conductive semiconductor layer 113 (and the first conductive semiconductor layer 111) may include a plurality of grooves 110g recessed inwardly. The plurality of grooves 110g may be formed along each side surface 100a to 100d of the light emitting device, as shown in FIG. 11.
  • the plurality of grooves 110g may improve extraction efficiency of light emitted through side surfaces of the exposed active layer 112 and the second conductive semiconductor layer 113. That is, the total internal reflection of light emitted through the side surfaces of the active layer 112 and the second conductive semiconductor layer 113 through the plurality of grooves 110g may be reduced, thereby improving the overall light extraction efficiency of the light emitting device. Can be.
  • the planar shape of the first connection pad 320 and the first current blocking layer 340 is enlarged.
  • the edge of the first connection pad 320 includes a first curved area.
  • the first connection pad 320 may include two first curved areas 321 and 322 positioned with two lower extensions 320-1 interposed therebetween.
  • the two first curved areas 321 and 322 may have the same radius of curvature R 1 as the first connection pad 320 has a circular shape. That is, the first curved areas 321 and 322 may have a curvature of 1 / R 1 .
  • the first current blocking layer 340 is interposed between the first connection pad 320 and the first conductivity type semiconductor layer 111 and may include a second curved region 341.
  • the second curved area 341 has a single curvature of R 2 values. May have a radius.
  • the radius of curvature R 1 of the first curved regions 321 and 322 located relatively outside may be greater than the radius of curvature R 2 of the second curved region 341 located relatively inside.
  • the gap G1 between the first curved areas 321 and 322 and the second curved area 341 may be kept uniform. Accordingly, the width G1 of the region where the first connection pad 320 and the first conductive semiconductor layer 111 contact each other, defined by the first current blocking layer 340, may be uniformly formed. Through this, uniform distribution of the current injected through the first connection pad 320 may be achieved.
  • the lower extension part 320-1 may be formed in plural. 11 and 12, two lower extensions 320-1 extend from the first connection pad 320 to extend from the fourth side 100d to the second side 100b of the light emitting device. Is disclosed. However, the shape and number of the lower extensions 320-1 are not limited to those disclosed in FIGS. 11 and 12, and may be variously changed in the scope of the present invention.
  • Each of the lower extensions 320-1 may include a connection portion 320-1a and a main extension portion 320-1b.
  • the connection part 320-1a may connect the main extension part 320-1b to the first connection pad 320.
  • the edge of the connector 320-1a may include a third curved area 321-1.
  • the third curved area 321-1 may have a radius of curvature R 3 .
  • the width G2 of the connection part 320-1a may decrease as the distance from the first connection pad 320 increases.
  • the width G2 of the connection part 320-1a adjacent to the first connection pad 320 is larger than the gap G1 between the first curved areas 321 and 322 and the second curved area 341.
  • Can be. Accordingly, a relatively large proportion of the current injected through the first connection pad 320 may be injected toward the connection portion 320-1a having a relatively large area.
  • the R 3 value may be formed smaller than the R 1 value and the R 2 value. That is, the third curved area 321-1 may have a greater degree of bending than the first curved areas 321 and 322 and the second curved area 341.
  • the width of the connection part 320-1a adjacent to the first connection pad 320 becomes relatively large. That is, the planar area of the connection part 320-1a may be relatively widened relatively. This requires a wider exposure area 100a, 100b, whereby the light emitting area can be reduced to reduce the output of the light emitting device.
  • the main extension part 320-1b may include a straight area and a curved area positioned between the straight area and the connection part 320-1a.
  • the width G3 of the main extension part 320-1b may be greater than or equal to the gap G1 between the first curved areas 321 and 322 and the second curved area 341.
  • the upper extension 230-1 extends from the second connection pad 230 and may be formed in plural. Referring to FIG. 11, three upper extensions 230-1 extending from the second connection pad 230 are shown.
  • the upper extensions 230-1 may generally extend from the second side surface 100b of the light emitting device toward the fourth side surface 100d.
  • the two upper extensions 230-1 may have a shape surrounding the lower extensions 320-1 and the first connection pad 320, and the other upper extension 230-1 is formed. It may be located between two lower extensions 320-1.
  • the current flows in the horizontal direction. It can be distributed smoothly.
  • FIG. 13 and 14 are plan views illustrating light emitting devices according to still another exemplary embodiment of the present invention. Specifically, FIG. 13 is a plan view of the light emitting device according to the present embodiment, and FIG. 14 is an enlarged view of the region ⁇ in FIG.
  • the light emitting device according to the present embodiment has the same configuration as that of the light emitting device disclosed in FIGS. 8 to 10, except that the exposed area, the first connection pad 420, the lower extension part 420-1, and the first current blocking device are provided. There are some differences in the shape of layer 440 and top extension 330-1. In addition, the light emitting device according to the present embodiment does not include the third current blocking layer. Hereinafter, the description of the same configuration will be omitted, and will be described based on the difference.
  • the exposed regions 110a and 110b may expose the first conductive semiconductor layer 111 through the second conductive semiconductor layer 113 and the active layer 112. Referring to FIG. 13, the exposed area 110a for the first connection pad 420 is positioned adjacent to an area where the first side surface 100a and the fourth side surface 100d of the light emitting device meet, and the lower extension portion ( The exposed area 110b for the 420-1 may be located adjacent to the first side surface 100a.
  • the first connection pad 420 may be connected to the first conductivity type semiconductor layer 111 through the exposure area 100a.
  • the edge of the first connection pad 420 may include a straight region and a first curved region 421.
  • two first curved regions 421 may be formed on a side surface of the semiconductor stack 110 exposed during the formation of the exposed region 110a. It may be located adjacently.
  • Each of the first curved regions 421 has a radius of curvature R 1 and may connect straight regions.
  • the first current blocking layer 440 is interposed between the first connection pad 420 and the first conductive semiconductor layer 111, and the edges of the first current blocking layer 440 have a straight region and a second curved region ( 441).
  • the second curved area 441 has a radius of curvature R 2 and may be located inside the first curved area 421.
  • the first curved area 421 and the second curved area 441 share the same center, and the first curved area 421 is formed through the second curved area 441 and the first curved area 421. It may be located inside the fan shape to be formed. That is, the second curved area may be located in an area formed by an imaginary straight line connecting the first curved area, both ends of the first curved area, and the center.
  • the R 2 value is smaller than the R 1 value.
  • the gap G1 between the first curved area 421 and the second curved area 441 may be maintained uniformly.
  • the interval G1 between the first curved region 421 and the second curved region 441 is equal to the interval between the linear region of the first connection pad 420 and the linear region of the first current blocking layer 440. May be the same.
  • the width of the region defined by the first current blocking layer 440 and the first connection pad 420 and the first conductive semiconductor layer 111 may be uniformly formed.
  • a width of a region where the first connection pad 420 and the first conductive semiconductor layer 111 contact each other may be uniformly formed. Through this, uniform distribution of the current injected through the first connection pad 420 may be achieved.
  • the lower extension part 420-1 may be connected to the first conductivity type semiconductor layer 111 in the exposed region 110b formed along the first side surface 100a of the light emitting device.
  • the lower extension part 420-1 may extend from the first connection pad 420 along the first side surface 100a of the light emitting device.
  • the lower extension part 420-1 may include a connection part 420-1a and a main extension part 420-1b.
  • the connection part 420-1a may connect the main extension part 420-1b with the first connection pad 420.
  • the edge of the connector 420-1a may include a third curved area 421-1.
  • the third curved area 421-1 may have a radius of curvature R 3 .
  • the connection part 420-1a according to the present embodiment includes a single third curved area 421-1 and a single third curved area 421. -1) is disposed adjacent the side of the exposed semiconductor stack 110.
  • the present invention is not limited thereto, but the width G2 or the width of the connection portion 420-1a according to the present embodiment may be smaller than the width or width of the connection portion 420-1a disclosed in FIGS. 8 and 12. have. Accordingly, in the light emitting device according to the present exemplary embodiment, since the insulating layer 465 is not disposed under the connection portion 420-1a having a relatively small width or width, the connection portion 420-1a is entirely formed of the first conductive semiconductor layer 111. ) Can be connected.
  • the width G2 of the connection part 420-1a may decrease as the distance from the first connection pad 420 increases.
  • the width G2 of the connection portion 420-1a adjacent to the first connection pad 420 may be greater than the gap G1 between the first curved area 421 and the second curved area 441. have. Accordingly, a relatively large ratio of currents injected through the first connection pads 420 may be injected toward the connection portion 420-1a having a relatively large area.
  • the R 3 value may be formed smaller than the R 1 value and the R 2 value. That is, the third curved area 421-1 may have a greater degree of bending than the first curved area 421 and the second curved area 441.
  • the width G2 of the connection portion 420-1a adjacent to the first connection pad 420 becomes relatively large. That is, the planar area of the connection portion 420-1a may become relatively wider. This requires a wider exposure area 100a, 100b, whereby the light emitting area can be reduced to reduce the output of the light emitting device.
  • the width G3 of the main extension part 420-1b may be greater than or equal to the gap G1 between the first curved area 421 and the second curved area 441.
  • the upper extension 330-1 may extend from the second connection pad 330. Referring to FIG. 13, the upper extension part 330-1 may extend from the second connection pad 330 in the direction of the fourth side surface 100d of the light emitting device.
  • the upper extension 330-1 and the lower extension 420-1 may be disposed to face each other, and thus the injected current may be widely distributed to the entire region of the light emitting device.
  • FIG. 15 and 16 are plan views illustrating light emitting devices according to still another exemplary embodiment of the present invention. Specifically, FIG. 15 is a plan view of the light emitting device according to the present embodiment, and FIG. 16 is an enlarged view of the region ⁇ of FIG.
  • the light emitting device has the same configuration as that of the light emitting device disclosed in FIGS. 8 to 10, but includes a plurality of light emitting cells directly or indirectly connected to each other, the first connection pad 520, There are some differences in the shape of the lower extension 520-1, the first current blocking layer 540, the second connection pad 430, and the upper extension 430-1. Hereinafter, the description of the same configuration will be omitted, and will be described based on the difference.
  • the light emitting device may include first to third light emitting cells C1, C2 and C3, fourth to sixth light emitting cells D1, D2 and D3, and seventh to ninth light emission.
  • the light emitting device may include a first connection pad 520 and a second connection pad 430, and may include upper extensions 430-1a and 430-1b and lower extensions 520-1. have.
  • the upper extension 430-1 may be divided into an auxiliary upper extension 430-1a and a main upper extension 430-1b.
  • the first to third light emitting cells C1, C2, and C3 may be separated from the fourth to sixth light emitting cells D1, D2, and D3 by the separating grooves 115.
  • the fourth to sixth light emitting cells D1, D2, and D3 may be separated from the seventh to ninth light emitting cells E1, E2, and E3 by the separating grooves 117. Accordingly, the first light emitting cell C1, the second light emitting cell C2, and the third light emitting cell C3 share the first conductive semiconductor layer 111a, and the fourth light emitting cell D1 and the fifth light emitting cell C1.
  • the light emitting cell D2 and the sixth light emitting cell D3 may share the first conductivity type semiconductor layer 111b.
  • the seventh light emitting cell E1, the eighth light emitting cell E2, and the ninth light emitting cell E3 may share the first conductivity-type semiconductor layer 111c.
  • the separation grooves 115 and 117 are formed by an isolation process, and the substrate 101 may be exposed in the separation grooves 115 and 117.
  • the first light emitting cell C1 and the second light emitting cell C2, the fourth light emitting cell D1 and the fifth light emitting cell D2, and the seventh light emitting cell E1 and the eighth light emitting cell E2. May be separated by a mesa etching process for forming mesa grooves 113a exposing the first conductivity type semiconductor layers 111a, 111b, and 111c.
  • the silver may be separated by a mesa etching process of forming a mesa groove 113b exposing the first conductivity type semiconductor layers 111a, 111b, and 111c.
  • the semiconductor stack 110 including the first conductivity type semiconductor layers 111a, 111b, and 111c, the active layer 112, and the second conductivity type semiconductor layer 113 may include mesa grooves 113a and 113b and separation grooves ( The first to ninth light emitting cells C1, C2, C3, D1, D2, D3, E1, E2, and E3 may be separated by the 115 and 117.
  • the first light emitting cell C1 and the third light emitting cell C3 may have a symmetrical shape with respect to an imaginary line connecting the first connection pad 520 and the second connection pad 430.
  • Each of the fourth to sixth light emitting cells D1, D2, and D3 may have the same shape.
  • the seventh light emitting cell E1 and the ninth light emitting cell E3 may have symmetrical shapes with respect to an imaginary line connecting the first connection pad 520 and the second connection pad 430.
  • the second light emitting cell C2 on which the second connection pad 430 is formed and the eighth light emitting cell E2 associated with the formation of the first connection pad 520 are relatively different from other light emitting cells in shape.
  • the first connection pad 520 is disposed adjacent to the fourth side surface 100d of the light emitting element, and the second connection pad 430 is disposed near the second side surface 100b opposite to the first connection pad 520. Can be.
  • the first connection pad 520 may be disposed on the mesa groove 113c. That is, a portion of the lower end of the eighth light emitting cell E2 near the fourth side surface 100d of the light emitting device may be mesa-etched to form the first connection pad 520, so that the mesa groove 113c may be formed.
  • the mesa groove 113c may correspond to the exposed area 100a in the above-described embodiments. Side surfaces of the semiconductor stack 110 may be exposed through the mesa groove 113c.
  • the first connection pad 520 may be disposed in the mesa groove 113c and electrically connected to the first conductive semiconductor layer 111c.
  • the first current blocking layer 540 may be disposed under the first connection pad 520.
  • the first current blocking layer 540 is disposed between the first connection pad 520 and the first conductivity type semiconductor layer 111c to smoothly distribute the current injected into the first conductivity type semiconductor layer 111c. can do.
  • the width of the first current blocking layers 540 and 111c may be smaller than that of the first connection pads 520. That is, the horizontal and vertical widths of the first current blocking layer 540 are smaller than those of the first connection pads 520, and thus may be located in some regions of the first connection pads 520.
  • the width of the first current blocking layer 540 may be limited to 90% or less of the width of the first connection pad 520.
  • the insulating layer 565 may cover the side surface of the mesa groove 113c on which the first connection pad 520 is disposed. As shown in FIGS. 15 and 16, the insulating layer 565 may cover a side surface of the mesa groove 113c and may also be formed at a portion through which the lower extension portion 520-1 passes to have a single curved shape. have. In a portion where the lower extension 520-1 passes, the insulating layer 565 may be formed first, and a lower extension 520-1 may be formed thereon.
  • one end of the lower extension parts 520-1 is disposed in the separation grooves 115 and 117. It is electrically connected to the other end is spaced apart from the main upper extension (430-1b), it may be surrounded by the main upper extension (430-1b).
  • an insulating layer 151 extending from the second current blocking layer 150 may be positioned below the connection unit 520-2.
  • the insulating layer 151 may cover the side surface of the semiconductor stack 110, which may be exposed in the isolation grooves 115 and 117, so that the connection unit 520-2 is connected to the side surface of the semiconductor stack 110. Can be prevented, and the reliability of the light emitting element can be improved.
  • the lower extensions 520-1 include two straight regions connected to the first connection pads 520 and connected to each other.
  • the two straight regions may be parallel to the horizontal direction and the vertical direction of the light emitting device, and may be perpendicular to each other.
  • the linear region in the horizontal direction connects the linear region in the vertical direction with the first connection pad 520.
  • the seventh to ninth light emitting cells E1 and E2 near the fourth side surface 100d of the light emitting device for forming the lower extension 520-1 (particularly, the horizontal area in the horizontal direction). , Part of E3) may be mesa etched.
  • one end of the lower extension part 520-1 is connected to the first connection pad 520, and the other end is spaced apart from the main upper extension part 430-1b, but the main upper extension part ( 430-1b).
  • the second connection pad 430 may be formed on the second light emitting cell C2.
  • the second current blocking layer 150 may be positioned below the second connection pad 430.
  • the second current blocking layer 150 may be interposed between the transparent electrode layer 160 and the second conductive semiconductor layer 113 under the second connection pad 430.
  • the width of the second current blocking layer 150 may be greater than the width of the second connection pad 430.
  • a portion of the transparent electrode layer 160 may be positioned under the second connection pad 430 and may include an opening 160a exposing the second current blocking layer 150.
  • the opening 160a may have a circular shape.
  • auxiliary upper extensions 430-1a and main upper extensions 430-1b may be disposed on the transparent electrode layer 160.
  • the auxiliary upper extension portions 430-1a may electrically connect between the main upper extensions 430-1b on the first to third light emitting cells C1, C2, and C3.
  • the auxiliary upper extension 430-1a includes a main upper extension 430-1b on the first light emitting cell C1 and a main upper extension on the second light emitting cell C2.
  • 430-1b may be connected. Accordingly, the first light emitting cell C1 and the second light emitting cell C2 may be electrically connected to each other.
  • the auxiliary upper extension 430-1a uses the main upper extension 430-1b as the first to third light emitting cells C1. It may be connected to the lower extension portion 520-1 of, C2 and C3.
  • the auxiliary upper extension 430-1a may be straight and may be positioned on the same axis as the lower extension 520-1.
  • One end of the auxiliary upper extension 430-1a may be connected to the main upper extension 430-1a, and the other end may be connected to the connection unit 520-2.
  • the main upper extension 430-1b may be disposed to surround a portion of the end and side surfaces of the lower extension 520-1. Accordingly, a part of the main upper extension 430-1b may be disposed on one side of the lower extension 520-1, and another part may be disposed on the other side opposite to one side of the lower extension 520-1. have.
  • the main upper extension 430-1b may have a symmetrical structure with respect to a straight line passing through the lower extension 520-1.
  • the first, fourth and seventh light emitting cells are the first group, the second, the 5th and 8th light emitting cells (C2, D2, E2) the second group, and the third, 6 and 9
  • the light emitting cells C3, D3, and E3 may be defined as a third group.
  • Each of the light emitting cells in each group may be electrically connected in series through the auxiliary upper extension 430-1a and the connection unit 520-2.
  • the first group, the second group, and the third group may be electrically connected in parallel through a horizontal linear region of the auxiliary upper extension 430-1a and the lower extension 520-1.
  • the edge of the first connection pad 520 may include a straight region and a first curved region 541.
  • two first curved areas 541 are arranged to be symmetrical with respect to the lower extension 520-1.
  • the first curved regions 541 may be located adjacent to a side surface of the semiconductor stack 110 that is exposed during the formation of the mesa groove 113c.
  • Each first curved region 541 has a radius of curvature R 1 and may be connected to a straight region.
  • the first current blocking layer 540 is interposed between the first connection pad 520 and the first conductive semiconductor layer 111c, and the edge of the first current blocking layer 540 has a straight region and a second curved region ( 521).
  • the second curved area 521 has a radius of curvature R 2 and may be located inside the first curved area 541.
  • the R 2 value is smaller than the R 1 value.
  • the gap G1 between the first curved area 541 and the second curved area 521 may be maintained uniformly.
  • the interval G1 between the first curved region 541 and the second curved region 521 is equal to the interval between the linear region of the first connection pad 520 and the linear region of the first current blocking layer 540. May be the same.
  • the width of the region defined by the first current blocking layer 540 and the first connection pad 520 and the first conductivity type semiconductor layer 111c may be uniformly formed.
  • a width of a region where the first connection pad 520 and the first conductive semiconductor layer 111c contact each other may be uniformly formed.
  • Each of the lower extensions 520-1 may include a connecting portion 520-1a and a main extension 520-1b.
  • the connection part 520-1a may connect the main extension part 520-1b to the first connection pad 520.
  • the edge of the connector 520-1a may include a third curved area 521-1.
  • the third curve area (521-1) may have a radius of curvature R 3 values.
  • the width G2 of the connection part 520-1a may decrease as the distance from the first connection pad 520 increases.
  • the width G2 of the connection portion 520-1a adjacent to the first connection pad 520 may be larger than the gap G1 between the first curved area 541 and the second curved area 521. have. Accordingly, a relatively large proportion of the current injected through the first connection pad 520 may be injected toward the connection portion 520-1a having a relatively large area.
  • the R3 value may be formed smaller than the R1 value and the R2 value.
  • the width G3 of the main extension part 520-1b may be greater than or equal to the gap G1 between the first curved area 541 and the second curved area 521.
  • FIG. 17 and 18 are plan views illustrating light emitting devices according to still another exemplary embodiment of the present invention. Specifically, FIG. 17 is a plan view of the light emitting device according to the present embodiment, and FIG. 18 is an enlarged view of the area ⁇ in FIG.
  • the light emitting device has the same configuration as that of the light emitting device disclosed in FIGS. 8 to 10, but includes a plurality of light emitting cells connected to each other, and the first connection pad 620 and the lower extension part. There is a slight difference in the shape of 620-1, the first current blocking layer 640, the second connection pad 530, and the upper extension 530-1. Hereinafter, the description of the same configuration will be omitted, and will be described based on the difference.
  • the light emitting device may include first to fourth light emitting cells C1, C2, D1, and D2.
  • the light emitting device may include a first connection pad 620 and a second connection pad 530, and may include upper extension parts 530-1 and lower extension parts 620-1.
  • the upper extension 530-1 may be divided into an auxiliary upper extension 530-1 and a main upper extension 530-1.
  • the first to fourth light emitting cells C1, C2, D1, and D2 may be separated through mesa grooves 113a and 113b exposing the first conductive semiconductor layers 111a and 111b.
  • the first light emitting cell C1 and the second light emitting cell C2, and the third light emitting cell D1 and the fourth light emitting cell D2 connect the first connection pad 620 and the second connection pad 530. It may have a shape symmetrical with respect to one virtual line.
  • first connection pad 620 may be disposed near the fourth side surface 100d of the light emitting device
  • second connection pad 530 may be disposed near the second side surface 100b of the light emitting device. As illustrated in FIG. 17, the first connection pad 620 and the second connection pad 530 may be disposed to face each other.
  • the first connection pad 620 may be disposed on the mesa groove 113c. That is, in order to form the first connection pad 620, near the fourth side surface 100d of the light emitting device, a portion of the lower end of the third light emitting cell D1 and the fourth light emitting cell D2 is mesa-etched to form a mesa groove. 113c may be formed. Side surfaces of the semiconductor stack 110 may be exposed through the mesa groove 113c.
  • the first connection pad 620 may be disposed in the mesa groove 113c and electrically connected to the first conductivity type semiconductor layer 111c.
  • the first current blocking layer 640 is interposed in a partial region between the first connection pad 620 and the first conductive semiconductor layer 111b to smoothly distribute currents.
  • the insulating layer 665 may cover the side surface of the mesa groove 113c on which the first connection pad 620 is disposed. As shown in FIGS. 15 and 16, the insulating layer 665 may cover a side surface of the mesa groove 113c and may also be formed at a portion through which the lower extension 620-1 passes to have a single curved shape. have.
  • one end of the lower extension parts 620-1 is electrically connected to the connection unit 620-2 disposed in the mesa groove 113b, and the other end thereof is the main part. It may be spaced apart from the upper extension 530-1b, and may be surrounded by the main upper extension 530-1b.
  • an insulating layer 151 extending from the second current blocking layers 150 and 150 may be positioned below the connection unit 620-2.
  • the insulating layer 151 may cover the side surface of the semiconductor stack 110, which may be exposed in the mesa groove 113b, so that the connection unit 620-2 may be connected to the side surface of the semiconductor stack 110. It can prevent and improve the reliability of a light emitting element.
  • the lower extension parts 620-1 are connected to the first connection pad 620 and include a straight area and a curved area.
  • the curved area may connect the straight area to the first connection pad 620.
  • the shape of the lower extension part 620-1 is based on an imaginary line connecting the first connection pad 620 and the second connection pad 530. Can be symmetrical to each other.
  • the second connection pad 530 is disposed on the mesa groove 113a and may be disposed over the first light emitting cell C1 and the second light emitting cell C2.
  • a second current blocking layer 150 that is wider than the second connection pad 530 is disposed below the second connection pad 530. Accordingly, the second connection pad 530 may be disconnected from the first conductivity type semiconductor layer 111a by the second current blocking layer 150 in the mesa groove 113a.
  • the transparent electrode layer 160 may be interposed between the second connection pad 530 and the second current blocking layer 150, and the second connection pad 530 is formed of the second conductive semiconductor layer through the transparent electrode layer 160. And may be connected to 113.
  • auxiliary upper extensions 530-1a and main upper extensions 530-1b may be disposed on the transparent electrode layer 160.
  • the auxiliary upper extension 530-1a may connect the main upper extension 530-1b to the second connection pad 530 on the first and second light emitting cells C1 and C2. Accordingly, the first light emitting cell C1 and the second light emitting cell C2 may be electrically connected to each other.
  • the auxiliary upper extension 530-1a connects the main upper extension 530-1b to the first and second light emitting cells C1 and C2. It may be connected to the lower extension 620-1.
  • one end of the auxiliary upper extension 530-1a is connected to the main upper extension 530-1b, and the other end is connected to the connection unit 620-2. Can be.
  • the main upper extension 530-1b may be disposed to surround a portion of the end and side surfaces of the lower extension 620-1. Therefore, a part of the main upper extension 530-1b may be disposed on one side of the lower extension 620-1, and another part may be disposed on the other side opposite to one side of the lower extension 620-1. have.
  • FIG. 18 is an enlarged plan view of the first connection pad 620, the first current blocking layer 640, and the lower extension 620-1. Referring to Fig. 18, these planar shapes will be examined.
  • the edge of the first connection pad 620 may include a straight region and a first curved region 621.
  • the first curved area 621 may be located adjacent to the side surface of the semiconductor stack 110 exposed during the formation of the mesa groove 113c.
  • the first curved area 621 has a radius of curvature R 1 .
  • the first current blocking layer 640 is interposed between the first connection pad 620 and the first conductive semiconductor layer 111b, and the edge of the first current blocking layer 640 has a straight region and a second curved region ( 641).
  • the second curved area 641 has a radius of curvature R 2 and may be located inside the first curved area 621. That is, the second curved area 641 may share the same center as the first curved area 621, and may be located in a sector formed through the center and the first curved area 621. Here, the R 2 value is smaller than the R 1 value.
  • the interval G1 between the first curved area 621 and the second curved area 641 may be maintained uniformly.
  • the interval G1 between the first curved region 621 and the second curved region 641 is equal to the interval between the linear region of the first connection pad 620 and the linear region of the first current blocking layer 640. May be the same.
  • Each lower extension 620-1 may include a connection 620-1a and a main extension 620-1b.
  • the connection part 620-1a may connect the main extension part 620-1b to the first connection pad 620.
  • An insulating layer 665 may be disposed below the connection portion 620-1a.
  • the edge of the connector 620-1a may include a third curved area 621-1.
  • the third curved area 621-1 may have a radius of curvature R 3 .
  • the width G2 of the connection portion 620-1a may decrease as the distance from the first connection pad 620 increases.
  • the width G2 of the connection portion 620-1a adjacent to the first connection pad 620 may be larger than the gap G1 between the first curved area 621 and the second curved area 641. have. Accordingly, a relatively large proportion of the current injected through the first connection pad 620 may be injected toward the connection portion 620-1a having a relatively large width.
  • the R 3 value may be formed smaller than the R 1 value and the R 2 value.
  • the width G3 of the main extension 620-1b may be greater than or equal to the gap G1 between the first curved area 621 and the second curved area 641.
  • FIG. 19 is an exploded perspective view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a lighting device.
  • the lighting apparatus includes a diffusion cover 1010, a light emitting device module 1020, and a body portion 1030.
  • the body portion 1030 may accommodate the light emitting device module 1020, and the diffusion cover 1010 may be disposed on the body portion 1030 to cover the upper portion of the light emitting device module 1020.
  • the body part 1030 is not limited as long as it can receive and support the light emitting device module 1020 and supply electric power to the light emitting device module 1020.
  • the body portion 1030 may include a body case 1031, a power supply device 1033, a power case 1035, and a power connection portion 1037.
  • the power supply device 1033 is accommodated in the power case 1035 and electrically connected to the light emitting device module 1020 and may include at least one IC chip.
  • the IC chip may adjust, convert, or control the characteristics of the power supplied to the light emitting device module 1020.
  • the power case 1035 may receive and support the power supply 1033, and the power case 1035 to which the power supply 1033 is fixed may be located inside the body case 1031. .
  • the power connection unit 115 may be disposed at a lower end of the power case 1035 and may be coupled to the power case 1035. Accordingly, the power connection unit 1037 may be electrically connected to the power supply device 1033 inside the power case 1035 to serve as a path through which external power may be supplied to the power supply device 1033.
  • the light emitting device module 1020 includes a substrate 1023 and a light emitting device 1021 disposed on the substrate 1023.
  • the light emitting device module 1020 may be provided on the body case 1031 and electrically connected to the power supply device 1033.
  • the substrate 1023 is not limited as long as it can support the light emitting device 1021.
  • the substrate 1023 may be a printed circuit board including wiring.
  • the substrate 1023 may have a shape corresponding to the fixing portion of the upper portion of the body case 1031 so as to be stably fixed to the body case 1031.
  • the light emitting device 1021 may include at least one of the light emitting devices according to the embodiments of the present invention described above.
  • the diffusion cover 1010 may be disposed on the light emitting device 1021, and may be fixed to the body case 1031 to cover the light emitting device 1021.
  • the diffusion cover 1010 may have a translucent material and may adjust the directivity of the lighting device by adjusting the shape and the light transmittance of the diffusion cover 1010. Therefore, the diffusion cover 1010 may be modified in various forms according to the purpose of use of the lighting device and the application aspect.
  • FIG. 20 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a display device.
  • the display device includes a display panel 2110, a backlight unit providing light to the display panel 2110, and a panel guide supporting a lower edge of the display panel 2110.
  • the display panel 2110 is not particularly limited and may be, for example, a liquid crystal display panel including a liquid crystal layer.
  • a gate driving PCB for supplying a driving signal to the gate line may be further located at the edge of the display panel 2110.
  • the gate driving PCB is not configured in a separate PCB, but may be formed on the thin film transistor substrate.
  • the backlight unit includes a light source module including at least one substrate and a plurality of light emitting devices 2160.
  • the backlight unit may further include a bottom cover 2180, a reflective sheet 2170, a diffusion plate 2131, and optical sheets 2130.
  • the bottom cover 2180 may be opened upward to accommodate the substrate, the light emitting device 2160, the reflective sheet 2170, the diffusion plate 2131, and the optical sheets 2130.
  • the bottom cover 2180 may be combined with the panel guide.
  • the substrate may be disposed under the reflective sheet 2170 and be surrounded by the reflective sheet 2170.
  • the present invention is not limited thereto, and when the reflective material is coated on the surface, the reflective material may be positioned on the reflective sheet 2170.
  • a plurality of substrates may be formed, and the plurality of substrates may be arranged in a side-by-side arrangement, but is not limited thereto and may be formed of a single substrate.
  • the light emitting device 2160 may include at least one of the light emitting devices according to the embodiments of the present invention described above.
  • the light emitting devices 2160 may be regularly arranged in a predetermined pattern on the substrate.
  • a lens 2210 may be disposed on each light emitting device 2160 to improve uniformity of light emitted from the plurality of light emitting devices 2160.
  • the diffusion plate 2131 and the optical sheets 2130 are positioned on the light emitting device 2160. Light emitted from the light emitting device 2160 may be supplied to the display panel 2110 in the form of a surface light source through the diffusion plate 2131 and the optical sheets 2130.
  • the light emitting device according to the embodiments of the present invention may be applied to the direct type display device as the present embodiment.
  • 21 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment is applied to a display device.
  • the display device including the backlight unit includes a display panel 3210 on which an image is displayed and a backlight unit disposed on a rear surface of the display panel 3210 to irradiate light.
  • the display apparatus includes a frame 240 that supports the display panel 3210 and accommodates the backlight unit, and covers 3240 and 3280 that surround the display panel 3210.
  • the display panel 3210 is not particularly limited and may be, for example, a liquid crystal display panel including a liquid crystal layer.
  • a gate driving PCB for supplying a driving signal to the gate line may be further located at an edge of the display panel 3210.
  • the gate driving PCB is not configured in a separate PCB, but may be formed on the thin film transistor substrate.
  • the display panel 3210 may be fixed by covers 3240 and 3280 positioned at upper and lower portions thereof, and the cover 3280 positioned at lower portions thereof may be coupled to the backlight unit.
  • the backlight unit for providing light to the display panel 3210 may include a lower cover 3270 having a portion of an upper surface thereof, a light source module disposed on one side of the lower cover 3270, and positioned in parallel with the light source module to provide point light. And a light guide plate 3250 for converting to surface light.
  • the backlight unit according to the present exemplary embodiment is disposed on the light guide plate 3250 and is disposed below the light guide plate 3250 and the optical sheets 3230 for diffusing and condensing light.
  • the display apparatus may further include a reflective sheet 3260 reflecting in the direction of the display panel 3210.
  • the light source module includes a substrate 3220 and a plurality of light emitting devices 3110 spaced apart from each other by a predetermined interval on one surface of the substrate 3220.
  • the substrate 3220 is not limited as long as it supports the light emitting device 3110 and is electrically connected to the light emitting device 3110.
  • the substrate 3220 may be a printed circuit board.
  • the light emitting device 3110 may include at least one light emitting device according to the embodiments of the present invention described above. Light emitted from the light source module is incident to the light guide plate 3250 and is supplied to the display panel 3210 through the optical sheets 3230. Through the light guide plate 3250 and the optical sheets 3230, the point light sources emitted from the light emitting devices 3110 may be transformed into surface light sources.
  • the light emitting device according to the embodiments of the present invention may be applied to the edge type display device as the present embodiment.
  • FIG. 22 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a head lamp.
  • the head lamp includes a lamp body 4070, a substrate 4020, a light emitting device 4010, and a cover lens 4050. Furthermore, the head lamp may further include a heat dissipation unit 4030, a support rack 4060, and a connection member 4040.
  • the substrate 4020 is fixed by the support rack 4060 and spaced apart from the lamp body 4070.
  • the substrate 4020 is not limited as long as it is a substrate capable of supporting the light emitting device 4010.
  • the substrate 4020 may be a substrate having a conductive pattern such as a printed circuit board.
  • the light emitting device 4010 is positioned on the substrate 4020 and may be supported and fixed by the substrate 4020.
  • the light emitting device 4010 may be electrically connected to an external power source through the conductive pattern of the substrate 4020.
  • the light emitting device 4010 may include at least one light emitting device according to the embodiments of the present invention described above.
  • the cover lens 4050 is positioned on a path along which light emitted from the light emitting device 4010 travels.
  • the cover lens 4050 may be disposed to be spaced apart from the light emitting device 4010 by the connecting member 4040, and to be disposed in a direction to provide light emitted from the light emitting device 4010. Can be.
  • the connection member 4040 may fix the cover lens 4050 with the substrate 4020 and may be disposed to surround the light emitting device 4010 to serve as a light guide for providing the light emitting path 4045.
  • connection member 4040 may be formed of a light reflective material or coated with a light reflective material.
  • the heat dissipation unit 4030 may include a heat dissipation fin 4031 and / or a heat dissipation fan 4033, and dissipate heat generated when the light emitting device 4010 is driven to the outside.
  • the light emitting device may be applied to the head lamp, in particular, a vehicle head lamp as in the present embodiment.

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Abstract

The present invention relates to a light emitting device and, more particularly, to a light emitting device in which a current blocking layer is disposed between a first connection pad and a first conductivity type semiconductor layer to increase a dispersion efficiency of a current injected into the first conductivity type semiconductor layer, a curved region is included in the connection pad and the current blocking layer to improve reliability and a current flow is induced to a lower extension connected to the connection pad to thereby improve an output.

Description

발광소자Light emitting element
본 발명은 발광소자에 관한 것으로, 특히 전류 분산 성능을 개선한 발광소자에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting device, and more particularly, to a light emitting device having improved current spreading performance.
발광소자(light-emitting diode; LED)는 반도체의 p-n 접합 구조를 이용하여 주입된 소수 캐리어(전자 또는 정공)를 만들고 이들의 재결합에 의하여 소정의 빛을 발산하는 소자를 지칭하며, GaAs, AlGaAs, GaN, InGaN, AlGaInP 등의 화합물 반도체(compound semiconductor) 재료의 변경을 통해 발광원을 구성함으로써 다양한 색을 구현할 수 있다.A light-emitting diode (LED) refers to a device that makes a small number of carriers (electrons or holes) injected using a pn junction structure of a semiconductor and emits light by recombination thereof. GaAs, AlGaAs, Various colors may be realized by configuring a light emitting source by changing compound semiconductor materials such as GaN, InGaN, and AlGaInP.
이러한 발광소자는 기존의 전구 또는 형광등에 비해 소모 전력이 작고 수명이 길며, 협소한 공간에 설치 가능하고 진동에 강한 특성을 보인다. 이러한 발광소자는 표시 소자 및 백라이트로 이용되고 있으며, 소모 전력의 절감과 내구성 측면에서 우수한 특성을 갖기 때문에 최근 대형 LCD-TV 백라이트, 자동차 헤드라이트, 일반 조명에까지 응용이 점차 확대되고 있으며, 이를 위해서는 발광소자의 발광 효율의 개선이 필요하다.Such a light emitting device has a smaller power consumption and a longer life than conventional light bulbs or fluorescent lamps, can be installed in a narrow space, and exhibits strong vibration resistance. These light emitting devices are used as display devices and backlights, and because they have excellent characteristics in terms of power consumption reduction and durability, applications have recently been extended to large LCD-TV backlights, automotive headlights, and general lighting. It is necessary to improve the luminous efficiency of the device.
본 발명이 해결하고자 하는 과제는, 접속 패드와 질화물계 반도체 적층이 접하는 영역에서 발생되는 전류 집중 현상을 최소화 할 수 있는 발광소자를 제공하는 것이다.SUMMARY OF THE INVENTION An object of the present invention is to provide a light emitting device capable of minimizing current concentration occurring in a region where a connection pad and a nitride-based semiconductor stack are in contact.
본 발명이 해결하고자 하는 또 다른 과제는 신뢰성이 향상된 발광 소자를 제공하는 것이다.Another object of the present invention is to provide a light emitting device having improved reliability.
본 발명이 해결하고자 하는 또 다른 과제는 접속 패드와과 질화물계 반도체 적층이 접하는 영역에서, 접속 패드에 의해 광이 흡수되어 손실되는 것을 방지할 수 있는 발광소자를 제공하는 것이다.Another object of the present invention is to provide a light emitting device capable of preventing the light absorbed and lost by the connection pad in a region where the connection pad and the nitride semiconductor stack are in contact with each other.
본 발명의 일 실시예에 의한 발광소자는 제1 도전형 반도체층, 제2 도전형 반도체층 및 상기 제1 및 제2 도전형 반도체층 사이에 위치하는 활성층을 포함하고, 상기 제2 도전형 반도체층 및 활성층을 관통하여 상기 제1 도전형 반도체층을 노출시키는 노출 영역을 포함하는 질화물계 반도체 적층; 상기 노출 영역을 통해 상기 제1 도전형 반도체층에 전기적으로 연결되는 제1 접속 패드; 상기 제1 도전형 반도체층과 상기 제1 접속 패드 사이에 개재된 제1 전류 차단층; 상기 제2 도전형 반도체층 상에 배치된 제2 접속 패드; 및 상기 제2 접속 패드로부터 연장된 상부 연장부를 포함하고, 상기 상부 연장부는 2개 이상이며, 상기 제1 접속 패드는 상기 상부 연장부들 사이에 위치하고, 상기 제1 전류 차단층은 상기 제1 도전형 반도체층과 상기 제1 접속 패드 사이의 영역에서는, 일부 영역에 한정되어 개재된다.A light emitting device according to an embodiment of the present invention includes a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer positioned between the first and second conductive semiconductor layers, and the second conductive semiconductor A nitride based semiconductor laminate including an exposed region through the layer and the active layer to expose the first conductive semiconductor layer; A first connection pad electrically connected to the first conductivity type semiconductor layer through the exposed region; A first current blocking layer interposed between the first conductive semiconductor layer and the first connection pad; Second connection pads disposed on the second conductive semiconductor layer; And an upper extension extending from the second connection pad, wherein the upper extension is two or more, the first connection pad is positioned between the upper extensions, and the first current blocking layer is the first conductivity type. In the region between the semiconductor layer and the first connection pad, the region is limited to a part of the region.
본 발명의 다른 실시예에 따른 발광 소자는 제1 도전형 반도체층, 활성층 및 제2 도전형 반도체층을 포함하되, 상기 제2 도전형 반도체층 및 활성층을 관통하여 상기 제1 도전형 반도체층을 노출시키는 노출 영역을 포함하는 반도체 적층; 상기 노출 영역을 통해 상기 제1 도전형 반도체층에 접속하는 제1 접속 패드 및 상기 제1 접속 패드로부터 연장되는 하부 연장부; 및 상기 제1 접속 패드와 제1 도전형 반도체층 사이에 위치하는 제1 전류 차단층을 포함하고, 상기 제1 접속 패드는 곡률 반경 R1 값을 갖는 제1 곡선 영역을 포함하되, 상기 제1 전류 차단층은 곡률 반경 R2 값을 갖는 제2 곡선 영역을 포함하되, 상기 제2 곡선 영역은 상기 제1 곡선 영역의 내측에 인접하여 배치되며, 상기 하부 연장부는 상기 제1 접속 패드와 접하는 연결부 및 상기 연결부에서 연장하는 메인 연장부를 포함하고, 상기 연결부는 곡률 반경 R3 값을 갖는 제3 곡선 영역을 포함하고, 상기 R2는 R3보다 크고 R1보다 작다.The light emitting device according to another embodiment of the present invention includes a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer, and penetrates the second conductive semiconductor layer and the active layer to form the first conductive semiconductor layer. A semiconductor stack comprising an exposed area to expose; A first connection pad connected to the first conductive semiconductor layer through the exposed area and a lower extension part extending from the first connection pad; And a first current blocking layer positioned between the first connection pad and the first conductive semiconductor layer, wherein the first connection pad includes a first curved area having a radius of curvature R 1 , wherein the first connection pad includes: a first curved area; The current blocking layer includes a second curved area having a radius of curvature R 2 value, wherein the second curved area is disposed adjacent to the inside of the first curved area, and the lower extension part is in contact with the first connection pad. And a main extension extending from the connection, wherein the connection includes a third curved region having a radius of curvature R 3 , wherein R 2 is greater than R 3 and less than R 1 .
본 발명의 발광소자에 의하면 접속 패드와 제1 도전형 반도체층 사이에 전류 차단층을 배치함으로써, 제1 도전형 반도체층 내에서 전류를 고르게 분산시킬 수 있다. 또한, 반사율이 높은 전류 차단층을 이용함으로써 발광소자의 광 추출 효율이 향상될 수 있다. 또한, 접속 패드와 전류 차단층이 곡선 영역을 포함하여, 신뢰성이 향상되며, 또한 접속 패드에 연결되는 하부 연장부로 전류의 흐름을 유도하여 발광 소자의 출력을 향상시킬 수 있다.According to the light emitting device of the present invention, by disposing a current blocking layer between the connection pad and the first conductive semiconductor layer, the current can be evenly distributed in the first conductive semiconductor layer. In addition, light extraction efficiency of the light emitting device may be improved by using a current blocking layer having a high reflectance. In addition, since the connection pad and the current blocking layer include a curved area, reliability is improved, and the output of the light emitting device can be improved by inducing the flow of current to the lower extension part connected to the connection pad.
도 1은 본 발명의 일 실시예에 따른 발광소자를 설명하기 위한 평면도이다.1 is a plan view illustrating a light emitting device according to an embodiment of the present invention.
도 2는 도 1의 평면도의 A-A'선을 따라 취해진 단면도이다.2 is a cross-sectional view taken along the line AA ′ of the top view of FIG. 1.
도 3는 도 1의 평면도의 B-B'선을 따라 취해진 단면도이다.3 is a cross-sectional view taken along the line BB ′ of the top view of FIG. 1.
도 4는 본 발명의 일 실시 예에 따른 제1 전류 차단층의 다양한 형태를 나타낸다.4 illustrates various forms of a first current blocking layer according to an embodiment of the present invention.
도 5는 본 발명의 다른 실시예에 따른 발광소자를 설명하기 위한 평면도이다.5 is a plan view illustrating a light emitting device according to another exemplary embodiment of the present invention.
도 6은 도 5의 평면도의 A-A'선을 따라 취해진 단면도이다.6 is a cross-sectional view taken along the line AA ′ of the top view of FIG. 5.
도 7는 도 5의 평면도의 B-B'선을 따라 취해진 단면도이다.FIG. 7 is a cross-sectional view taken along the line BB ′ of the top view of FIG. 5.
도 8 내지 10은 본 발명의 또 다른 실시예에 따른 발광 소자를 나타낸다.8 to 10 show a light emitting device according to another embodiment of the present invention.
도 11 및 12는 본 발명의 또 다른 실시예에 따른 발광 소자를 나타낸다.11 and 12 show a light emitting device according to another embodiment of the present invention.
도 13 및 14는 본 발명의 또 다른 실시예에 따른 발광 소자를 나타낸다.13 and 14 show a light emitting device according to another embodiment of the present invention.
도 15 및 16은 본 발명의 또 다른 실시예에 따른 발광 소자를 나타낸다.15 and 16 show a light emitting device according to another embodiment of the present invention.
도 17 및 18은 본 발명의 또 다른 실시예에 따른 발광 소자를 나타낸다.17 and 18 show light emitting devices according to still another embodiment of the present invention.
도 19는 본 발명의 일 실시예에 따른 발광소자를 조명 장치에 적용한 예를 설명하기 위한 분해 사시도이다.19 is an exploded perspective view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a lighting device.
도 20은 본 발명의 일 실시예에 따른 발광소자를 디스플레이 장치에 적용한 예를 설명하기 위한 단면도이다.20 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a display device.
도 21은 본 발명의 일 실시예에 따른 발광소자를 또 다른 디스플레이 장치에 적용한 예를 설명하기 위한 단면도이다.21 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to another display device.
도 22는 본 발명의 일 실시예에 따른 발광소자를 헤드 램프에 적용한 예를 설명하기 위한 단면도이다.22 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a head lamp.
이하, 첨부한 도면들을 참조하여 본 발명의 실시예들을 상세히 설명한다. 다음에 소개되는 실시예들은 본 발명이 속하는 기술분야의 통상의 기술자에게 본 발명의 사상이 충분히 전달될 수 있도록 하기 위해 예로서 제공되는 것이다. 따라서, 본 발명은 이하 설명되는 실시예들에 한정되지 않고 다른 형태로 구체화될 수도 있다. 그리고, 도면들에 있어서, 구성요소의 폭, 길이, 두께 등은 편의를 위하여 과장되어 표현될 수도 있다. 또한, 하나의 구성요소가 다른 구성요소의 "상부에" 또는 "상에" 있다고 기재된 경우 각 부분이 다른 부분의 "바로 상부" 또는 "바로 상에" 있는 경우뿐만 아니라 각 구성요소와 다른 구성요소 사이에 또 다른 구성요소가 개재된 경우도 포함한다. 명세서 전체에 걸쳐서 동일한 참조번호들은 동일한 구성요소들을 나타낸다.Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention; The following embodiments are provided as examples to sufficiently convey the spirit of the present invention to those skilled in the art to which the present invention pertains. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. In the drawings, widths, lengths, thicknesses, and the like of components may be exaggerated for convenience. In addition, when one component is described as "on" or "on" another component, each component is different from each other as well as when the component is "just above" or "on" the other component. It also includes a case where another component is interposed therebetween. Like numbers refer to like elements throughout.
본 발명의 일 실시예에 따르면, 발광소자가 제공된다. 이 발광 소자는 제1 도전형 반도체층, 제2 도전형 반도체층 및 상기 제1 및 제2 도전형 반도체층 사이에 위치하는 활성층을 포함하고, 상기 제2 도전형 반도체층 및 활성층을 관통하여 상기 제1 도전형 반도체층을 노출시키는 노출 영역을 포함하는 질화물계 반도체 적층; 상기 노출 영역을 통해 상기 제1 도전형 반도체층에 전기적으로 연결되는 제1 접속 패드; 상기 제1 도전형 반도체층과 상기 제1 접속 패드 사이에 개재된 제1 전류 차단층; 상기 제2 도전형 반도체층 상에 배치된 제2 접속 패드; 및 상기 제2 접속 패드로부터 연장된 상부 연장부를 포함한다. 상기 상부 연장부는 2개 이상이며, 상기 제1 접속 패드는 상기 상부 연장부들 사이에 위치하고, 상기 제1 전류 차단층은 상기 제1 도전형 반도체층과 상기 제1 접속 패드 사이의 영역에서는, 일부 영역에 한정되어 개재되어 전류 확산 효율을 높일 수 있다.According to an embodiment of the present invention, a light emitting device is provided. The light emitting device includes a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer positioned between the first and second conductivity type semiconductor layers, and penetrates the second conductivity type semiconductor layer and the active layer. A nitride based semiconductor laminate including an exposed region exposing the first conductive semiconductor layer; A first connection pad electrically connected to the first conductivity type semiconductor layer through the exposed region; A first current blocking layer interposed between the first conductive semiconductor layer and the first connection pad; Second connection pads disposed on the second conductive semiconductor layer; And an upper extension extending from the second connection pad. The upper extension part is two or more, and the first connection pad is positioned between the upper extension parts, and the first current blocking layer is a partial area in an area between the first conductive semiconductor layer and the first connection pad. Interposed therebetween, the current spreading efficiency can be increased.
상기 제1 전류 차단층의 영역은 상기 제1 도전형 반도체층과 상기 제1 접속 패드 사이 영역의 90%를 초과하지 않을 수 있다.An area of the first current blocking layer may not exceed 90% of an area between the first conductive semiconductor layer and the first connection pad.
또한 상기 제1 전류 차단층은 SiO2층 또는 분포 브래그 반사층을 포함할 수 있다.In addition, the first current blocking layer may include a SiO 2 layer or a distributed Bragg reflective layer.
여기서, 상기 분포 브래그 반사층은 SiO2층과 TiO2층 또는 SiO2층과 Nb2O5층이 교대로 적층된 구조를 가질 수 있다.The distributed Bragg reflection layer may have a structure in which an SiO 2 layer and a TiO 2 layer or an SiO 2 layer and an Nb 2 O 5 layer are alternately stacked.
제1 전류 차단층의 형상은 상기 제1 접속 패드의 형상과 동일할 수 있다.The shape of the first current blocking layer may be the same as that of the first connection pad.
또한 상기 발광소자는 상기 제2 접속 패드의 하부 및 상기 복수의 상부 연장부들 하부에 배치된 제2 전류 차단층을 더 포함할 수 있다.The light emitting device may further include a second current blocking layer disposed under the second connection pad and under the plurality of upper extensions.
여기서, 상기 제2 전류 차단층은 상기 제1 전류 차단층과 동일한 물질층을 포함할 수 있다.Here, the second current blocking layer may include the same material layer as the first current blocking layer.
상기 제2 접속 패드 하부에 배치된 전류 차단층의 폭은 상기 제2 접속 패드의 폭보다 크거나 같고, 상기 복수의 상부 연장부들 하부에 배치된 전류 차단층의 폭은 상기 복수의 상부 연장부들의 폭보다 크거나 같을 수 있다.The width of the current blocking layer disposed below the second connection pad is greater than or equal to the width of the second connection pad, and the width of the current blocking layer disposed below the plurality of upper extensions is greater than that of the plurality of upper extensions. It can be greater than or equal to the width.
상기 발광소자는 제1 접속 패드로부터 연장되며, 상기 제1 도전형 반도체층에 콘택하는 하부 연장부를 더 포함할 수 있다.The light emitting device may further include a lower extension part extending from the first connection pad and contacting the first conductivity type semiconductor layer.
상기 발광소자는 상기 제2 도전형 반도체층 상에 위치하며, 상기 제2 도전형 반도체층에 오믹 콘택하는 오믹 전극층을 더 포함할 수 있다.The light emitting device may further include an ohmic electrode layer positioned on the second conductive semiconductor layer and ohmic contacting the second conductive semiconductor layer.
상기 오믹 전극층은 투명 전극층 또는 메탈 전극층을 포함할 수 있다. The ohmic electrode layer may include a transparent electrode layer or a metal electrode layer.
상기 발광 소자는 상기 노출 영역을 통해 노출되는 질화물계 반도체 적층을 덮는 절연층을 더 포함할 수 있다.The light emitting device may further include an insulating layer covering the nitride based semiconductor stack exposed through the exposed region.
상기 절연층은 SiO2층 또는 분포 브래그 반사층을 포함할 수 있다.The insulating layer may include a SiO 2 layer or a distributed Bragg reflective layer.
상기 절연층은 상기 제1 전류 차단층과 동일한 공정을 통해 형성될 수 있다.The insulating layer may be formed through the same process as the first current blocking layer.
상기 질화물계 반도체 적층은 복수개의 노출 영역을 포함하고, The nitride based semiconductor laminate includes a plurality of exposed regions,
상기 노출 영 역은 적어도 하나의 제1 홀 및 적어도 하나의 제2 홀을 포함하는 제1 노출 영역, 적어도 하나의 제3 홀을 포함하는 제2 노출영역을 포함할 수 있다.The exposure area may include a first exposure area including at least one first hole and at least one second hole, and a second exposure area including at least one third hole.
상기 적어도 하나의 제1 홀 및 적어도 하나의 제2홀은 원형 또는 다각형의 평면 형상이고, 상기 적어도 하나의 제3홀은 상기 적어도 하나의 제2 홀로부터 임의의 방향으로 연장되는 형상일 수 있다.The at least one first hole and the at least one second hole may have a circular or polygonal planar shape, and the at least one third hole may have a shape extending in an arbitrary direction from the at least one second hole.
상기 제1 접속 패드는 상기 제1 노출 영역을 통해 상기 제1 도전형 반도체층과 접하고, 상기 하부 연장부는 상기 제2 노출 영역을 통해 상기 제2 도전형 반도체층과 접할 수 있다. The first connection pad may contact the first conductive semiconductor layer through the first exposed region, and the lower extension portion may contact the second conductive semiconductor layer through the second exposed region.
상기 제1 전류 차단층은 상기 제1 노출 영역에 한정되어, 상기 제1 도전형 반도체층과 상기 제1 접속 패드 사이의 일부 영역에 한정되어 개재될 수 있다.The first current blocking layer may be limited to the first exposed region, and may be limited to a partial region between the first conductive semiconductor layer and the first connection pad.
상기 제3홀의 폭은 상기 제1 홀 및 제2 홀의 폭보다 작을 수 있다.The width of the third hole may be smaller than the width of the first hole and the second hole.
상기 발광 소자는 상기 제1 접속 패드와 전기적으로 연결되는 제1 본딩 패드 및 상기 제2 접속 패드와 전기적으로 연결되는 제2 본딩 패드를 더 포함할 수 있다.The light emitting device may further include a first bonding pad electrically connected to the first connection pad and a second bonding pad electrically connected to the second connection pad.
상기 제1 본딩 패드 및 상기 제2 본딩 패드는 전기적으로 절연될 수 있다.The first bonding pad and the second bonding pad may be electrically insulated.
상기 발광소자는 상기 제1 본딩 패드 및 상기 제2 본딩 패드와 상기 질화물게 반도체 적층 사이에 위치하는 절연층을 더 포함할 수 있다.The light emitting device may further include an insulating layer disposed between the first bonding pad and the second bonding pad and the nitride crab semiconductor stack.
상기 제1 본딩 패드 상기 제2 본딩 패드는 상기 절연층에 형성된 홀들을 통해 각각 제1 접속 패드 및 제2 접속 패드와 전기적으로 연결될 수 있다.The first bonding pad The second bonding pad may be electrically connected to the first connection pad and the second connection pad through holes formed in the insulating layer, respectively.
본 발명의 다른 실시예에 따르면, 발광소자가 제공된다. 이 발광 소자는 제1 도전형 반도체층, 활성층 및 제2 도전형 반도체층을 포함하되, 상기 제2 도전형 반도체층 및 활성층을 관통하여 상기 제1 도전형 반도체층을 노출시키는 노출 영역을 포함하는 반도체 적층; 상기 노출 영역을 통해 상기 제1 도전형 반도체층에 접속하는 제1 접속 패드 및 상기 제1 접속 패드로부터 연장되는 하부 연장부; 및 상기 제1 접속 패드와 제1 도전형 반도체층 사이에 위치하는 제1 전류 차단층을 포함하고, 상기 제1 접속 패드는 곡률 반경 R1 값을 갖는 제1 곡선 영역을 포함하되, 상기 제1 전류 차단층은 곡률 반경 R2 값을 갖는 제2 곡선 영역을 포함하되, 상기 제2 곡선 영역은 상기 제1 곡선 영역의 내측에 인접하여 배치되며, 상기 하부 연장부는 상기 제1 접속 패드와 접하는 연결부 및 상기 연결부에서 연장하는 메인 연장부를 포함하고, 상기 연결부는 곡률 반경 R3 값을 갖는 제3 곡선 영역을 포함하고, 상기 R2는 R3보다 크고 R1보다 작다.According to another embodiment of the present invention, a light emitting device is provided. The light emitting device includes a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer, and includes an exposed area that exposes the first conductivity type semiconductor layer through the second conductivity type semiconductor layer and the active layer. Semiconductor lamination; A first connection pad connected to the first conductive semiconductor layer through the exposed area and a lower extension part extending from the first connection pad; And a first current blocking layer positioned between the first connection pad and the first conductive semiconductor layer, wherein the first connection pad includes a first curved area having a radius of curvature R 1 , wherein the first connection pad includes: a first curved area; The current blocking layer includes a second curved area having a radius of curvature R 2 value, wherein the second curved area is disposed adjacent to the inside of the first curved area, and the lower extension part is in contact with the first connection pad. And a main extension extending from the connection, wherein the connection includes a third curved region having a radius of curvature R 3 , wherein R 2 is greater than R 3 and less than R 1 .
여기서, 제1 곡선 영역과 제2 곡선 영역은 동일한 중심을 공유하고, 제2 곡선 영역은, 제1 곡선 영역과 제1 곡선 영역의 양단과 상기 중심을 연결하는 가상의 직선들에 의해 형성되는 영역 내에 위치한다. 이 때, 제1 곡선 영역 및 제2 곡선 영역 사이의 간격은 균일하게 유지될 수 있다. 이에 따라 제1 접속 패드를 통해 주입되는 전류가 균일하게 분산될 수 있다.Here, the first curved area and the second curved area share the same center, and the second curved area is formed by virtual straight lines connecting both ends of the first curved area and the first curved area and the center. Located in At this time, the spacing between the first curved region and the second curved region may be kept uniform. Accordingly, the current injected through the first connection pad can be uniformly distributed.
여기서, 상기 하부 연장부의 연결부의 폭은 상기 제1 곡선 영역 및 제2 곡선 영역 사이의 간격보다 크고, 상기 제1 접속 패드로부터 멀어질수록 감소할 수 있다. 또한, 상기 메인 연장부의 폭은 상기 제1 곡선 영역 및 제2 곡선 영역 사이의 간격보다 크거나 같을 수 있다. Here, the width of the connection of the lower extension may be greater than a distance between the first curved area and the second curved area, and may decrease as the distance from the first connection pad increases. In addition, the width of the main extension may be greater than or equal to an interval between the first curved area and the second curved area.
여기서, 제1 전류 차단층은 상기 제1 도전형 반도체층과 상기 제1 접속 패드 사이의 영역에서는, 일부 영역에 한정되어 개재될 수 있다. 예를 들어, 상기 제1 전류 차단층의 영역은 상기 제1 도전형 반도체층과 상기 제1 접속 패드 사이 영역의 90%를 초과하지 않을 수 있다. 이를 통해 순방향 전압이 상승되지 않으면서도 전류가 원활하게 분산될 수 있다. Here, the first current blocking layer may be limited to a partial region in the region between the first conductive semiconductor layer and the first connection pad. For example, the region of the first current blocking layer may not exceed 90% of the region between the first conductive semiconductor layer and the first connection pad. This allows the current to be smoothly distributed without increasing the forward voltage.
여기서, 상기 제1 전류 차단층은 단일층 또는 분포 브래그 반사층을 포함하고, 상기 분포 브래그 반사층은 SiO2층과 TiO2층 또는 SiO2층과 Nb2O5층이 교대로 적층된 구조를 가질 수 있다.The first current blocking layer may include a single layer or a distributed Bragg reflective layer, and the distributed Bragg reflective layer may have a structure in which an SiO 2 layer and a TiO 2 layer or an SiO 2 layer and an Nb 2 O 5 layer are alternately stacked. have.
또한, 발광 소자는 상기 하부 연장부 아래 위치하는 제3 전류 차단층을 더 포함하고, 상기 제3 전류 차단층은 서로 이격된 복수의 도트를 포함할 수 있다.In addition, the light emitting device may further include a third current blocking layer positioned below the lower extension, and the third current blocking layer may include a plurality of dots spaced apart from each other.
이때, 상기 제3 전류 차단층의 폭은 상기 메인 연장부의 폭보다 크고, 상기 메인 연장부는 상기 복수의 도트들 사이의 영역에서 상기 제1 도전형 반도체층에 접속될 수 있다. 즉, 상기 메인 연장부는 상기 제3 전류 차단층에 의해 불연속적으로 상기 제1 도전형 반도체층에 접속될 수 있다.In this case, a width of the third current blocking layer may be greater than a width of the main extension part, and the main extension part may be connected to the first conductive semiconductor layer in a region between the plurality of dots. That is, the main extension part may be connected to the first conductivity type semiconductor layer discontinuously by the third current blocking layer.
또한. 발광 소자는 상기 제2 도전형 반도체층 상에 배치되는 제2 접속 패드; 및 상기 제2 접속 패드로부터 연장되는 상부 연장부를 더 포함할 수 있다.Also. The light emitting device includes: a second connection pad disposed on the second conductive semiconductor layer; And an upper extension part extending from the second connection pad.
또한, 발광 소자는 상기 제2 도전형 반도체층 상에 위치하며, 상기 제2 도전형 반도체층에 오믹 콘택하는 오믹 전극층을 더 포함하고, 상기 제2 접속 패드 및 상기 상부 연장부는 상기 오믹 전극층 상에 위치할 수 있다. The light emitting device may further include an ohmic electrode layer positioned on the second conductive semiconductor layer and in ohmic contact with the second conductive semiconductor layer, and the second connection pad and the upper extension may be disposed on the ohmic electrode layer. Can be located.
이하, 첨부된 도면들을 참조하여 본 발명의 실시예들에 대해 구체적으로 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 3은 본 발명의 일 실시예에 따른 발광소자를 설명하기 위한 평면도 및 단면도들이다. 구체적으로, 도 1은 상기 발광소자의 평면도이고, 도 2는 도 1의 평면도의 A-A'선에 대응하는 부분의 단면을 도시하고, 도 3은 도 1의 평면도의 B-B'선에 대응하는 부분의 단면을 도시한다.1 to 3 are plan and cross-sectional views illustrating a light emitting device according to an embodiment of the present invention. Specifically, FIG. 1 is a plan view of the light emitting device, FIG. 2 is a cross-sectional view of a portion corresponding to line A-A 'of the plan view of FIG. 1, and FIG. 3 is a line B-B' of the plan view of FIG. The cross section of the corresponding part is shown.
도 1 내지 도 3를 참조하면, 상기 발광소자는 질화물계 반도체 적층(110), 제1 접속 패드(120), 제2 접속 패드(130), 제1 전류 차단층(current block layer) (140) 및 제2 전류 차단층(150)을 포함한다. 나아가, 상기 발광소자는 제1 접속 패드(120)로부터 임의의 방향으로 연장된 하부 연장부(120-1) 및 제2 접속 패드(130)로부터 임의의 방향으로 연장된 상부 연장부(130-1)를 더 포함할 수 있다. 하부 연장부(120-1)는 제1 접속 패드(120)로부터 임의의 방향으로 단수 또는 복수 개 형성될 수 있으며, 하부 연장부(120-1)의 폭은 제1 접속 패드(120)의 폭보다 작거나 같을 수 있다. 상부 연장부(130-1) 또한 제2 접속 패드(130)로부터 임의의 방향으로 단수 또는 복수 개 형성될 수 있으며, 상부 연장부(130-1)의 폭은 제2 접속 패드(130)의 폭보다 작거나 같을 수 있다. 특히, 상부 연장부(130-1)는 2개가 형성될 수 있으며, 2개의 상부 연장부(130-1)가 제1 접속 패드(120)를 감싸는 형상으로 형성될 수 있다. 본 실시예에서, 2개의 상부 연장부(130-1)를 도시하지만, 더 많은 상부 연장부가 형성될 수 있다. 1 to 3, the light emitting device includes a nitride based semiconductor stack 110, a first connection pad 120, a second connection pad 130, and a first current block layer 140. And a second current blocking layer 150. In addition, the light emitting device includes a lower extension 120-1 extending in an arbitrary direction from the first connection pad 120 and an upper extension 130-1 extending in an arbitrary direction from the second connection pad 130. ) May be further included. The lower extension part 120-1 may be formed in a singular or plural number from the first connection pad 120 in any direction, and the width of the lower extension part 120-1 may be the width of the first connection pad 120. May be less than or equal to The upper extension 130-1 may also be formed in the singular or plural in the direction from the second connection pad 130, and the width of the upper extension 130-1 is the width of the second connection pad 130. May be less than or equal to In particular, two upper extensions 130-1 may be formed, and two upper extensions 130-1 may be formed to surround the first connection pad 120. In the present embodiment, two upper extensions 130-1 are shown, but more upper extensions can be formed.
상기 발광소자는 질화물계 반도체 적층(110) 상에 위치하는 투명 전극층(160) 및 기판(101)을 더 포함할 수 있다. 또한, 상기 발광소자는 반도체 적층 구조의 측면을 덮는 절연층(165)을 더 포함할 수 있다. 또한, 상기 발광소자는 다각형의 평면 형상을 가질 수 있다. 특히, 상기 발광소자는 사각형의 평면 형상을 가질 수 있다. 본 실시예에서, 상기 발광소자는 대체로 정방형의 평면 형상을 가질 수 있으며, 제1 측면(100a), 제2 측면(100b), 제1 측면(100a)에 반대하여 위치하는 제3 측면(100c), 및 제2 측면(100b)에 반대하여 위치하는 제4 측면(100d)을 포함할 수 있다. 도 1을 참조하면, 하부 연장부(120-1)는 제1 접속 패드(120)로부터 연장되되, 제4 측면(100d)으로부터 제2 측면(100b)을 향해 연장되는 형태로 형성될 수 있다. 또한 상부 연장부(130-1)는 제2 접속 패드(130)로부터 연장되되, 제2 측면(100b)으로부터 제4 측면(100d)을 향해 곡선 형태를 가질 수 있다. 다만, 본 발명이 이에 한정되는 것은 아니다.The light emitting device may further include a transparent electrode layer 160 and a substrate 101 positioned on the nitride-based semiconductor stack 110. In addition, the light emitting device may further include an insulating layer 165 covering the side surface of the semiconductor stacked structure. In addition, the light emitting device may have a polygonal planar shape. In particular, the light emitting device may have a rectangular planar shape. In the present embodiment, the light emitting device may have a generally square planar shape, and the third side surface 100c positioned opposite to the first side surface 100a, the second side surface 100b, and the first side surface 100a. And a fourth side surface 100d positioned opposite to the second side surface 100b. Referring to FIG. 1, the lower extension part 120-1 may extend from the first connection pad 120 and may extend from the fourth side surface 100d toward the second side surface 100b. In addition, the upper extension 130-1 may extend from the second connection pad 130, and may have a curved shape from the second side surface 100b toward the fourth side surface 100d. However, the present invention is not limited thereto.
질화물계 반도체 적층(110)은 기판(101) 상에 위치하는 제1 도전형 반도체층(111), 제1 도전형 반도체층(111) 상에 위치하는 활성층(112), 활성층(112) 상에 위치하는 제2 도전형 반도체층(113)을 포함한다. 또한, 질화물계 반도체 적층(110)은 제1 도전형 반도체층(111)을 부분적으로 노출시키는 노출 영역(110a, 110b)을 포함할 수 있다. 노출 영역(110a, 110b)에서, 질화물계 반도체 적층(110)은 메사(mesa) 구조를 이룰 수 있다. 노출 영역(110a, 110b)의 위치, 형태, 및 개수에 따라 전류 분산 효율 및 발광소자의 발광 패턴이 조절될 수 있다. 특히, 도 1 및 도 3을 참조하면 노출 영역(110a, 110b)은 질화물계 반도체층들로 둘러싸일 수 있으며, 질화물계 반도체 적층(110)의 가장자리로부터 이격될 수 있다. 특히, 노출 영역(110a)은 발광소자의 제4 측면(100d)으로부터 이격되어 형성될 수 있다. 나아가, 노출 영역(110a)은 상부 연장부(130-1)들 사이에 위치하고 발광소자의 제4 측면(100d)으로부터 이격되어 형성될 수 있다. The nitride based semiconductor stack 110 is disposed on the first conductive semiconductor layer 111 located on the substrate 101, the active layer 112 located on the first conductive semiconductor layer 111, and the active layer 112. The second conductive semiconductor layer 113 is positioned. In addition, the nitride-based semiconductor stack 110 may include exposed regions 110a and 110b partially exposing the first conductivity-type semiconductor layer 111. In the exposed regions 110a and 110b, the nitride-based semiconductor stack 110 may form a mesa structure. The current spreading efficiency and the light emission pattern of the light emitting device may be adjusted according to the position, shape, and number of the exposed areas 110a and 110b. In particular, referring to FIGS. 1 and 3, the exposed regions 110a and 110b may be surrounded by nitride-based semiconductor layers, and may be spaced apart from the edge of the nitride-based semiconductor stack 110. In particular, the exposed region 110a may be formed to be spaced apart from the fourth side surface 100d of the light emitting device. In addition, the exposed region 110a may be disposed between the upper extensions 130-1 and spaced apart from the fourth side surface 100d of the light emitting device.
도면에는 비록 도시되지 않았지만, 본 발명에 따른 발광 소자는 상부 연장부(130-1)들이 제4 측면(100d)과 노출 영역(100a) 사이까지 연장되는 구조를 포함할 수 있다. 즉 상부 연장부(130-1)들이 노출 영역(110a)을 감싸는 구조를 포함할 수 있다.Although not shown in the drawings, the light emitting device according to the present invention may include a structure in which the upper extensions 130-1 extend between the fourth side surface 100d and the exposed area 100a. That is, the upper extensions 130-1 may include a structure surrounding the exposed area 110a.
기판(101)은 Al2O3, SiC, Si, GaAs, GaN, ZnO, GaP, InP, Ge 등과 같은 공지의 재료를 선택하여 이용할 수 있다. 도면을 통해 도시되지 않았지만, 상기 기판(101)의 위 및/또는 아래에는 요철 패턴이 형성될 수 있다, 기판(101)의 상기 요철 패턴의 형상은 스트라이프 형상, 렌즈 형상, 기둥 형상, 뿔 형상 등 자유롭게 선택 가능하다.The substrate 101 may be selected from a known material such as Al 2 O 3 , SiC, Si, GaAs, GaN, ZnO, GaP, InP, Ge, or the like. Although not shown through the drawings, an uneven pattern may be formed on and / or under the substrate 101. The uneven patterns of the substrate 101 may have a stripe shape, a lens shape, a pillar shape, a horn shape, or the like. Freely selectable
제1 도전형 반도체층(111)은 제1 도전형 도펀트가 도핑된 반도체층이다. 상기 제1 도전형 반도체층(111)은 GaN, InN, AlN, InGaN, AlGaN, InAlGaN 중 적어도 하나로 형성될 수 있으며, 상기 제1 도전형 반도체층(111)이 n형 반도체층인 경우, 상기 제1 도전형 도펀트는 n형 도펀트인 Si, Ge, Sn, Se, Te 중 1종 이상을 포함할 수 있다.The first conductivity type semiconductor layer 111 is a semiconductor layer doped with the first conductivity type dopant. The first conductive semiconductor layer 111 may be formed of at least one of GaN, InN, AlN, InGaN, AlGaN, and InAlGaN, and the first conductive semiconductor layer 111 may be an n-type semiconductor layer. The single-conducting dopant may include at least one of Si, Ge, Sn, Se, and Te, which are n-type dopants.
활성층(112)은 단일 양자 우물 또는 다중 양자 우물(MQW) 구조로 형성될 수 있다. 즉, 3족-5족 화합물 반도체 재료를 이용하여 GaN, InN, AlN, InGaN, AlGaN, InAlGaN 중 적어도 하나로 형성될 수 있다. 예컨대 활성층(112)은 InGaN 우물층/GaN 장벽층이 교대로 형성된 구조를 가질 수 있다. 상기 활성층(112)은 제1 도전형 반도체층(111)에서 공급되는 캐리어와 제2 도전형 반도체층(113)에서 공급되는 캐리어가 재결합하면서 광을 발생시킨다. 상기 제1 도전형 반도체층(111)이 n형 반도체층인 경우, 상기 제1 도전형 반도체층(111)에서 공급되는 캐리어는 전자일 수 있고, 제2 도전형 반도체층(113)이 p형 반도체층인 경우, 상기 제2 도전형 반도체층(113)에서 공급되는 캐리어는 정공일 수 있다.The active layer 112 may be formed in a single quantum well or multiple quantum well (MQW) structure. That is, at least one of GaN, InN, AlN, InGaN, AlGaN, and InAlGaN may be formed using a Group III-V compound semiconductor material. For example, the active layer 112 may have a structure in which InGaN well layers / GaN barrier layers are alternately formed. The active layer 112 generates light while the carrier supplied from the first conductive semiconductor layer 111 and the carrier supplied from the second conductive semiconductor layer 113 are recombined. When the first conductivity-type semiconductor layer 111 is an n-type semiconductor layer, the carrier supplied from the first conductivity-type semiconductor layer 111 may be electrons, and the second conductivity-type semiconductor layer 113 may be p-type. In the case of the semiconductor layer, the carrier supplied from the second conductivity type semiconductor layer 113 may be a hole.
제2 도전형 반도체층(113)은 제2 도전형 도펀트가 도핑된 반도체층을 포함하며, 단층 또는 다층으로 형성될 수 있다. 상기 제2 도전형 반도체층(113)은 GaN, InN, AlN, InGaN, AlGaN, InAlGaN 중 적어도 하나로 형성될 수 있으며, 제2 도전형 반도체층(113)이 p형 반도체층인 경우, 상기 제2 도전형 도펀트는 p형 도펀트인 Mg, Zn, Ca, Sr, Ba 중 1종 이상을 포함할 수 있다.The second conductivity type semiconductor layer 113 may include a semiconductor layer doped with the second conductivity type dopant and may be formed in a single layer or multiple layers. The second conductive semiconductor layer 113 may be formed of at least one of GaN, InN, AlN, InGaN, AlGaN, and InAlGaN, and when the second conductive semiconductor layer 113 is a p-type semiconductor layer, the second The conductive dopant may include one or more of p-type dopants, Mg, Zn, Ca, Sr, and Ba.
발명에 따른 발광소자는 제1 도전형 반도체층(111), 활성층(112) 및 제2 도전형 반도체층(113) 이외에도 결정 품질 향상을 위하여 비도핑층이나 기타 버퍼층을 포함할 수 있으며, 제2 도전형 반도체층(113)이 p형 반도체층인 경우, 활성층(112)과 제2 도전형 반도체층(113) 사이에 형성되는 전류차단층(미도시)과 같이 다양한 기능층들이 포함될 수 있다.In addition to the first conductive semiconductor layer 111, the active layer 112, and the second conductive semiconductor layer 113, the light emitting device according to the present invention may include an undoped layer or another buffer layer to improve crystal quality. When the conductive semiconductor layer 113 is a p-type semiconductor layer, various functional layers may be included, such as a current blocking layer (not shown) formed between the active layer 112 and the second conductive semiconductor layer 113.
도 1 내지 도 3을 참조하면, 질화물계 반도체 적층(110)은 노출 영역(110a, 110b)을 포함할 수 있다. 노출 영역(110a, 110)은 제1 도전형 반도체층(111)을 부분적으로 노출시킬 수 있다. 노출 영역(110a, 110)은 사진 및 식각 기술을 이용하여 형성될 수 있다. 예를 들어, 포토레지스트를 이용하여 식각 영역을 정의하고, ICP와 같은 건식 식각을 이용하여 제2 도전형 반도체층(113)과 활성층(112)을 식각함으로써 노출 영역(110a, 110b)이 형성될 수 있다. 또는 노출 영역(110a, 110b) 형성 과정에서 제1 도전형 반도체층(111)의 일부가 식각될 수 있다. 노출 영역(110a)은 대체로 원형 또는 다각형의 평면 형상을 가질 수 있다. 노출 영역(110b)은, 노출 영역(110a)으로부터 임의의 방향으로 연장되는 형태로 형성될 수 있다. 이때, 노출 영역(110b)과 노출 영역(110a)은 서로 연결될 수 있다. 또한, 노출 영역(110b)의 폭은 노출 영역(110a)의 폭보다 작거나 같을 수 있다. 노출 영역(110a, 110b) 위치, 형태 및 개수에 따라 전류 분산 효율 및 발광소자의 발광 패턴이 조절될 수 있다. 도 1을 참조하면, 노출 영역(110a)은 발광소자의 제4 측면(100d)으로부터 이격되어 형성될 수 있다. 노출 영역(110a)과 제4 측면(100d) 사이에 질화물계 반도체 적층(110)이 위치할 수 있다. 또한, 노출 영역(110b)은 노출 영역(110ba)으로부터 제4 측면(100d)에서 제2 측면(100b) 방향으로 연장되는 구조를 가질 수 있다. 다만, 노출 영역(110a, 110b)의 위치, 형태 및 개수는 도 1에 도시된 것으로 제한되지 않으며, 본 발명의 목적 범위 내에서 다양하게 변경될 수 있다.1 to 3, the nitride based semiconductor stack 110 may include exposed regions 110a and 110b. The exposed regions 110a and 110 may partially expose the first conductivity type semiconductor layer 111. The exposed regions 110a and 110 may be formed using photo and etching techniques. For example, the exposed regions 110a and 110b may be formed by defining an etching region using a photoresist and etching the second conductive semiconductor layer 113 and the active layer 112 using dry etching such as ICP. Can be. Alternatively, a portion of the first conductivity type semiconductor layer 111 may be etched during the formation of the exposed regions 110a and 110b. The exposed area 110a may have a generally circular or polygonal planar shape. The exposed area 110b may be formed to extend in an arbitrary direction from the exposed area 110a. In this case, the exposed area 110b and the exposed area 110a may be connected to each other. In addition, the width of the exposed area 110b may be less than or equal to the width of the exposed area 110a. The current spreading efficiency and the light emission pattern of the light emitting device may be adjusted according to the position, shape, and number of the exposed areas 110a and 110b. Referring to FIG. 1, the exposed region 110a may be formed to be spaced apart from the fourth side surface 100d of the light emitting device. The nitride based semiconductor stack 110 may be located between the exposed region 110a and the fourth side surface 100d. In addition, the exposed area 110b may have a structure extending from the exposed area 110ba in the direction of the second side surface 100b at the fourth side surface 100d. However, the position, shape, and number of the exposed regions 110a and 110b are not limited to those shown in FIG. 1 and may be variously changed within the scope of the present invention.
제1 접속 패드(120) 및 하부 연장부(120-1)는 제1 도전형 반도체층(111)에 전기적으로 접속될 수 있으며, 특히, 제1 도전형 반도체층(111)에 오믹 컨택할 수 있다. 제1 접속 패드(120) 및 하부 연장부(120-1)는 질화물계 반도체 적층(110)의 일부를 덮을 수 있다. 제1 접속 패드(120) 및 하부 연장부(120-1)는 노출영역(110a, 110b)을 통해서 제1 도전형 반도체층(111)과 전기적으로 접속될 수 있다. 이에 따라, 제1 접속 패드(120) 및 하부 연장부(120-1)를 통해 질화물계 반도체 적층(110)으로 전류가 주입되는 부분은 노출 영역(110a, 110b)의 위치 및 형태 등에 따라 제어될 수 있다. 노출 영역(110b)과 노출 영역(110a)은 서로 연결될 수 있고, 따라서 노출 영역(110a)에 위치하는 제1 접속 패드(120) 및 노출 영역(110b)에 위치하는 하부 연장부(120-1)가 서로 전기적으로 연결될 수 있다. 하부 연장부(120-1)는 제1 접속 패드(120)로부터 임의의 방향으로 연장된 형상을 가질 수 있고, 여기서 하부 연장부(120-1)의 폭은 제1 접속 패드(120)의 폭보다 작거나 같을 수 있다. 특히, 하부 연장부(120-1)는 제1 접속 패드(120)로부터 연장되되, 제4 측면(100d)으로부터 제2 측면(100b)을 향해 연장되는 형태로 형성될 수 있다. The first connection pad 120 and the lower extension part 120-1 may be electrically connected to the first conductivity type semiconductor layer 111. In particular, the first connection pad 120 and the lower extension part 120-1 may make ohmic contact with the first conductivity type semiconductor layer 111. have. The first connection pad 120 and the lower extension part 120-1 may cover a portion of the nitride based semiconductor stack 110. The first connection pad 120 and the lower extension part 120-1 may be electrically connected to the first conductivity type semiconductor layer 111 through the exposed areas 110a and 110b. Accordingly, the portion into which the current is injected into the nitride based semiconductor stack 110 through the first connection pad 120 and the lower extension 120-1 may be controlled according to the position and shape of the exposed regions 110a and 110b. Can be. The exposed area 110b and the exposed area 110a may be connected to each other, so that the first connection pad 120 positioned in the exposed area 110a and the lower extension 120-1 positioned in the exposed area 110b may be connected to each other. Can be electrically connected to each other. The lower extension part 120-1 may have a shape extending in an arbitrary direction from the first connection pad 120, where the width of the lower extension part 120-1 is the width of the first connection pad 120. May be less than or equal to In particular, the lower extension part 120-1 may extend from the first connection pad 120 and may extend from the fourth side surface 100d toward the second side surface 100b.
제1 접속 패드(120) 및 하부 연장부(120-1)는, 이에 제한되는 것은 아니지만, 금(Au), 은(Ag), 알루미늄(Al), 구리(Cu), 또는 이들을 포함한 합금 중에서 선택된 적어도 하나의 도전성 재료로 이루어질 수 있다. 또한 제1 접속 패드(120) 및 하부 연장부(120-1)는 복수의 층으로 이루어질 수 있다. 제1 접속 패드(120) 및 하부 연장부(120-1)는 크롬(Cr) 층, 알루미늄(Al) 층, 니켈(Ni) 층 및 금(Au) 층 중에서 선택된 적어도 두 층으로 이루어 질 수 있다. 예를 들어, 제1 접속 패드(120) 및 하부 연장부(120-1)는 크롬 층, 알루미늄 층, 크롬 층, 니켈 층 및 금 층이 순차적으로 적층된 구조를 가질 수 있다. 여기서 각 층은, 예를 들어, 8.5, 1200, 1600, 900 및 2000 옹스트롱(angstrom)의 두께를 가질 수 있다.The first connection pad 120 and the lower extension 120-1 may be selected from, but are not limited to, gold (Au), silver (Ag), aluminum (Al), copper (Cu), or an alloy including them. It may be made of at least one conductive material. In addition, the first connection pad 120 and the lower extension part 120-1 may be formed of a plurality of layers. The first connection pad 120 and the lower extension 120-1 may be formed of at least two layers selected from a chromium (Cr) layer, an aluminum (Al) layer, a nickel (Ni) layer, and a gold (Au) layer. . For example, the first connection pad 120 and the lower extension part 120-1 may have a structure in which chromium layers, aluminum layers, chromium layers, nickel layers, and gold layers are sequentially stacked. Here each layer may have a thickness of, for example, 8.5, 1200, 1600, 900 and 2000 angstroms.
제1 접속 패드(120) 및 하부 연장부(120-1)는 질화물계 반도체 적층(110) 상에 금속 물질을 증착하고, 이를 패터닝하여 형성될 수 있다. 즉, 이에 한정되는 것은 아니나, 제1 접속 패드(120) 및 하부 연장부(120-1)는 동일한 공정을 통해 형성될 수 있다. The first connection pad 120 and the lower extension part 120-1 may be formed by depositing and patterning a metal material on the nitride based semiconductor stack 110. That is, the present invention is not limited thereto, but the first connection pad 120 and the lower extension part 120-1 may be formed through the same process.
노출 영역(110a)이 발광소자의 제4 측면(100d)으로부터 이격되는 것에 따라, 노출 영역(110a) 내에서 형성되는 제1 접속 패드(120) 또한 제4 측면(100d)으로부터 이격되어 형성될 수 있다. 노출 영역(110a)과 제4 측면(100d) 사이에 질화물계 반도체 적층(110)이 위치할 수 있다.As the exposed region 110a is spaced apart from the fourth side surface 100d of the light emitting device, the first connection pad 120 formed in the exposed region 110a may also be formed spaced apart from the fourth side surface 100d. have. The nitride based semiconductor stack 110 may be located between the exposed region 110a and the fourth side surface 100d.
제2 접속 패드(130) 및 상부 연장부(130-1)는 제2 도전형 반도체층(113) 상에 위치하며, 제2 도전형 반도체층(113)과 전기적으로 접속될 수 있다. 제2 접속 패드(130) 및 상부 연장부(130-1)는 제2 도전형 반도체층(113) 상에서 다양한 형태를 가질 수 있으며, 질화물계 반도체 적층(110)으로 전류가 주입되는 부분은 제2 접속 패드(130) 및 상부 연장부(130-1)의 위치 및 형태 등에 따라 제어될 수 있다. 상부 연장부(130-1)는 단수 또는 복수 개 일 수 있다. 예를 들어, 도 1을 참조하면, 제2 접속 패드(130)로부터 연장된 두 개의 상부 연장부(130-1)는 제1 접속 패드(120)를 감싸는 형상을 가질 수 있다. 제2 접속 패드(130) 및 상부 연장부(130-1)는, 이에 제한되는 것은 아니지만, 금(Au), 은(Ag), 알루미늄(Al), 구리(Cu), 또는 이들을 포함한 합금 중에서 선택된 적어도 하나의 도전성 재료로 이루어질 수 있다. 또한 제2 접속 패드(130) 및 상부 연장부(130-1)는 복수의 층으로 이루어질 수 있다. 제2 접속 패드(130) 및 상부 연장부(130-1)는, 예를 들어, 크롬 층, 알루미늄 층, 니켈 층 및 금 층 중에서 선택된 적어도 두 층으로 이루어 질 수 있다. 예를 들어, 제2 접속 패드(130) 및 상부 연장부(130-1)는 크롬 층, 알루미늄 층, 크롬 층, 니켈 층 및 금 층이 순차적으로 적층된 구조를 가질 수 있다. 여기서 각 층은, 예를 들어, 8.5, 1200, 1600, 900 및 2000 옹스트롱(angstrom)의 두께를 가질 수 있다. 제2 접속 패드(130) 및 상부 연장부(130-1)는 질화물계 반도체 적층(110) 상에 금속 물질을 증착하고, 이를 패터닝하여 형성될 수 있다. 이에 한정되는 것은 아니나, 제2 접속 패드(130) 및 상부 연장부(130-1)는 동일한 공정을 통해 형성될 수 있다. 또한, 제2 접속 패드(130) 및 상부 연장부(130-1)는 제1 접속 패드(120) 및 하부 연장부(120-1)와 동일한 공정을 통해 형성될 수 있다.The second connection pad 130 and the upper extension 130-1 may be positioned on the second conductive semiconductor layer 113 and electrically connected to the second conductive semiconductor layer 113. The second connection pad 130 and the upper extension 130-1 may have various shapes on the second conductivity-type semiconductor layer 113, and a portion into which a current is injected into the nitride-based semiconductor stack 110 is second. It may be controlled according to the position and shape of the connection pad 130 and the upper extension 130-1. The upper extension 130-1 may be singular or plural. For example, referring to FIG. 1, the two upper extensions 130-1 extending from the second connection pad 130 may have a shape surrounding the first connection pad 120. The second connection pad 130 and the upper extension 130-1 may be selected from, but are not limited to, gold (Au), silver (Ag), aluminum (Al), copper (Cu), or an alloy containing them. It may be made of at least one conductive material. In addition, the second connection pad 130 and the upper extension 130-1 may be formed of a plurality of layers. The second connection pad 130 and the upper extension 130-1 may be formed of at least two layers selected from, for example, a chromium layer, an aluminum layer, a nickel layer, and a gold layer. For example, the second connection pad 130 and the upper extension 130-1 may have a structure in which a chromium layer, an aluminum layer, a chromium layer, a nickel layer, and a gold layer are sequentially stacked. Here each layer may have a thickness of, for example, 8.5, 1200, 1600, 900 and 2000 angstroms. The second connection pad 130 and the upper extension 130-1 may be formed by depositing and patterning a metal material on the nitride-based semiconductor stack 110. Although not limited thereto, the second connection pad 130 and the upper extension 130-1 may be formed through the same process. In addition, the second connection pad 130 and the upper extension 130-1 may be formed through the same process as the first connection pad 120 and the lower extension 120-1.
여기서 제1 접속 패드(120) 및 제2 접속 패드(130)는 발광소자의 전기적 연결을 위한 것으로, 예를 들어, 제1 접속 패드(120) 및 제2 접속 패드(130) 각각에 와이어 본딩(bonding)이 이루어 질 수 있다. 제1 접속 패드(120) 및 제2 접속 패드(130) 각각에 이루어진 와이어 본딩을 통해 발광소자는 외부 장치와 전기적으로 연결될 수 있고, 전원을 공급 받을 수 있다.Here, the first connection pad 120 and the second connection pad 130 are for electrical connection of the light emitting device, and, for example, wire bonding to each of the first connection pad 120 and the second connection pad 130 ( bonding can be done. The light emitting device may be electrically connected to an external device through a wire bonding formed on each of the first connection pad 120 and the second connection pad 130, and may receive power.
제2 도전형 반도체층(113)이 p형 반도체층인 경우, 그 상부에는 Ni/Au, ITO, TCO(Transparent Conducting Oxide) 또는 NiO, ZnO 등의 금속 또는 금속산화물로 이루어진 투명 전극층(160)이 형성될 수 있다. 상기 투명 전극층(160)은 오믹 전극층으로 지칭될 수 있다. 투명 전극층(160)은 제2 도전형 반도체층(113)에 오믹 컨택을 형성하여 전류 확산 효과를 높일 수 있다, 또한 투명 전극층(160)은 일정 수준 이상의 투과율을 유지하여 발광소자의 효율과 휘도를 높일 수 있다. 여기서, 발광소자가 투명 전극층(160)을 포함하는 경우, 발광소자는 제2 접속 패드(130)와 제2 도전형 반도체층(113) 사이, 그리고 상부 연장부(130-1)와 제2 도전형 반도체층(113) 사이에 투명 전극층(160)이 개재되는 구조를 가질 수 있다. When the second conductivity-type semiconductor layer 113 is a p-type semiconductor layer, the transparent electrode layer 160 made of a metal or metal oxide such as Ni / Au, ITO, transparent conducting oxide (TCO) or NiO, ZnO, etc. Can be formed. The transparent electrode layer 160 may be referred to as an ohmic electrode layer. The transparent electrode layer 160 may increase ohmic contact by forming an ohmic contact on the second conductive semiconductor layer 113, and the transparent electrode layer 160 maintains a transmittance of a predetermined level or more to improve efficiency and brightness of the light emitting device. It can increase. Here, when the light emitting device includes the transparent electrode layer 160, the light emitting device is between the second connection pad 130 and the second conductive semiconductor layer 113, and the upper extension 130-1 and the second conductive material. The transparent electrode layer 160 may be interposed between the type semiconductor layers 113.
도 1 및 도 3을 참조하면, 투명 전극층(160)은 개구부(160a)를 포함할 수 있다. 개구부(160a)를 통해, 제2 접속 패드(130)는 제2 전류 차단층(150)과 직접 접촉될 수 있다. 개구부(160a)는 제2 접속 패드(130)와 제2 전류 차단층(150) 사이에 형성되어 있으며, 그 폭은 제2 접속 패드(130)의 폭보다 작을 수 있다. 따라서, 제2 접속 패드(130)는 테투리 영역에서 그 일부가 투명 전극층(160)과 접촉되고, 또한 중심 영역에서 그 일부가 개구부(160a)를 통해 제2 전류 차단층(150)과 접촉될 수 있다. 제2 접속 패드(160) 아래에 개구부(160a)에 의해 형성되는 단차로 인하여, 제2 접속 패드(160)의 결합력이 높아 질 수 있고, 그에 따라 발광 소자의 구조적 안정성이 향상될 수 있다.1 and 3, the transparent electrode layer 160 may include an opening 160a. Through the openings 160a, the second connection pads 130 may directly contact the second current blocking layer 150. The opening 160a is formed between the second connection pad 130 and the second current blocking layer 150, and the width of the opening 160a may be smaller than the width of the second connection pad 130. Therefore, a portion of the second connection pad 130 may contact the transparent electrode layer 160 in the boundary region, and a portion of the second connection pad 130 may contact the second current blocking layer 150 through the opening 160a in the central region. have. Due to the step formed by the opening 160a under the second connection pad 160, the coupling force of the second connection pad 160 may be increased, thereby improving the structural stability of the light emitting device.
제1 전류 차단층(140)은, 노출 영역(110a) 내에서, 제1 접속 패드(120)와 제1 도전형 반도체층(111) 사이에 개재될 수 있다. 제1 도전형 반도체층(111)이 n형 반도체층인 경우, 제1 전류 차단층(140)은 n형 전류 차단층으로 지칭될 수 있다. 제1 전류 차단층(140)은 제1 접속 패드(120)와 제1 도전형 반도체층(111) 사이의 일부 영역에 개재될 수 있고, 그에 따라 제1 접속 패드(120)로부터 제1 도전형 반도체층(111)으로 효과적으로 전류가 넓게 분산될 수 있다. The first current blocking layer 140 may be interposed between the first connection pad 120 and the first conductivity type semiconductor layer 111 in the exposed region 110a. When the first conductive semiconductor layer 111 is an n-type semiconductor layer, the first current blocking layer 140 may be referred to as an n-type current blocking layer. The first current blocking layer 140 may be interposed in a portion of the region between the first connection pad 120 and the first conductive semiconductor layer 111, and thus, the first current blocking layer 120 may be formed from the first conductive pad 120. The current may be effectively distributed to the semiconductor layer 111.
특히, 도 1에서와 같이, 제1 접속 패드(120)가 상부 연장부(130-1)들 사이에 위치하는 구조에서, 제1 전류 차단층(140)이 존재하지 않은 경우, 제1 접속 패드(120)를 통해 주입되는 전류의 수평 분산이 원활하게 이루어지지 않은 문제점이 발생될 수 있다. 즉, 도 1에 개시된 것과 같은 구조에서 제1 전류 차단층(140)이 존재 하지 않은 경우, 제1 접속 패드(120)로 주입되는 전류가 제1 접속 패드(120) 주위에 형성된 상부 연장부(130-1)들로 집중되는 문제점이 발생될 수 있다. 또한, 도면에는 도시되지 않았지만, 본 발명에 따른 발광 소자는 제1 접속 패드(120)가 발광소자의 제4 측면(100d)으로부터 이격된 구조에서, 상부 연장부(130-1)들이 제1 접속 패드(120)와 제4 측면(100d) 사이까지 더 연장되어 제1 접속 패드를 감쌀 수 있다. 이러한 구조에서도 마찬가지로 전류의 수평 분산이 원활하게 이루어지지 않은 문제점이 발생될 수 있다. In particular, as shown in FIG. 1, in a structure in which the first connection pad 120 is positioned between the upper extensions 130-1, when the first current blocking layer 140 does not exist, the first connection pad is present. There may be a problem that the horizontal dispersion of the current injected through the 120 is not smoothly made. That is, in the structure as shown in FIG. 1, when the first current blocking layer 140 does not exist, an upper extension portion formed around the first connection pad 120 is provided with current injected into the first connection pad 120. Problems concentrated on 130-1) may occur. In addition, although not shown in the drawings, the light emitting device according to the present invention has a structure in which the first connection pad 120 is spaced apart from the fourth side surface 100d of the light emitting device. The pad may further extend between the pad 120 and the fourth side surface 100d to surround the first connection pad. Similarly, in such a structure, a problem may occur in which the horizontal dispersion of current is not smoothly performed.
이를 해결하기 위한 목적으로, 제1 전류 차단층(140)이 제1 도전형 반도체층(111)과 제1 접속 패드(120) 사이에 개재될 수 있다. 제1 전류 차단층(140)은 제1 접속 패드(120)로부터 주입되는 전류가 그 아래 위치하는 제1 도전형 반도체층(111)으로 집중되는 것을 방지할 수 있다. 즉, 제1 전류 차단층(140)에 의해, 주입되는 전류가 하부 연장부(120-1)로 분산 될 수 있고 그에 따라 특정 위치, 즉 제1 접속 패드(120) 아래의 제1 도전형 반도체층에 전류가 집중되는 것이 방지될 수 있다.In order to solve this problem, the first current blocking layer 140 may be interposed between the first conductive semiconductor layer 111 and the first connection pad 120. The first current blocking layer 140 may prevent the current injected from the first connection pad 120 from being concentrated on the first conductive semiconductor layer 111 positioned below the first current blocking layer 140. That is, by the first current blocking layer 140, the injected current may be distributed to the lower extension 120-1, and accordingly, the first conductive semiconductor under the first connection pad 120 is located at a specific position. Concentration of current in the layer can be prevented.
구체적으로, 제1 전류 차단층(140)은 노출 영역(110a) 내에서 제1 접속 패드(120)와 제1 도전형 반도체층(111) 사이에 개재될 수 있다. 제1 전류 차단층(140)은, 예를 들어, 원형, 사각형, 삼각형 등 임의의 형상을 가질 수 있으며 그 제한은 없다. 특히, 제1 전류 차단층(140)은 노출 영역(110a)의 형상과 유사한 원형 형상을 가질 수 있다. 하지만, 이에 한정되는 것은 아니며, 제1 전류 차단층(140)은, 추후 도 4를 통해 언급되는 것처럼, 다양한 형상 및 크기를 가질 수 있다.In detail, the first current blocking layer 140 may be interposed between the first connection pad 120 and the first conductivity-type semiconductor layer 111 in the exposed region 110a. The first current blocking layer 140 may have any shape, for example, a circle, a rectangle, a triangle, and the like, but is not limited thereto. In particular, the first current blocking layer 140 may have a circular shape similar to that of the exposed region 110a. However, the present invention is not limited thereto, and the first current blocking layer 140 may have various shapes and sizes as described later with reference to FIG. 4.
다만, 제1 전류 차단층(140)의 면적은 노출 영역(110a) 내에서 일정 수준으로 제한될 수 있다. 즉, 제1 전류 차단층(140)은 노출 영역(110a) 내의 임의의 위치에서 임의의 넓이로 형성될 수 있지만, 제1 접속 패드(120)와 제1 도전형 반도체층(111) 사이 영역의 90%를 초과하지 않아야 한다. 이는 제1 전류 차단층(140)의 면적이 증가하는 경우, 전류 분산이 잘 이루어져서 발광소자의 출력(power)이 향상될 수 있지만 일정 수준 이상 그 면적이 증가하는 경우, 발광소자의 순방향 전압(forward voltage, Vf)이 급격하게 증가할 수 있기 때문이다. 따라서, 제1 접속 패드(120)와 제1 도전형 반도체층(111)이 사이에서의 제1 전류 차단층(140)의 면적은 제1 접속 패드(120)와 제1 도전형 반도체층(111)이 사이 면적의 90% 이하로 제한된다. 특히, 제1 접속 패드(120)와 제1 도전형 반도체층(111)이 사이에서 제1 전류 차단층(140)의 면적이 제1 접속 패드(120)와 제1 도전형 반도체층(111)이 사이의 90% 수준인 경우, 발광소자의 최대 효율이 달성 될 수 있다. 즉, 순방향 전압 상승 없이 발광소자의 출력이 최대가 될 수 있다. 만약, 제1 접속 패드(120)와 제1 도전형 반도체층(111)이 사이에서 제1 전류 차단층(140)의 면적이 제1 접속 패드(120)와 제1 도전형 반도체층(111)이 사이의 90% 이상이 되는 경우, n-컨택 영역의 부족으로 인하여 순방향 전압이 상승될 수 있다.However, the area of the first current blocking layer 140 may be limited to a predetermined level in the exposed area 110a. That is, although the first current blocking layer 140 may be formed to have an arbitrary width at any position in the exposed region 110a, the first current blocking layer 140 may be formed at an arbitrary area. It should not exceed 90%. This is because when the area of the first current blocking layer 140 is increased, the current is well distributed and thus the power of the light emitting device can be improved, but when the area is increased by a certain level or more, the forward voltage of the light emitting device is forward. This is because voltage, Vf) may increase rapidly. Therefore, the area of the first current blocking layer 140 between the first connection pad 120 and the first conductive semiconductor layer 111 is the first connection pad 120 and the first conductive semiconductor layer 111. ) Is limited to 90% or less of the area between. In particular, the area of the first current blocking layer 140 between the first connection pad 120 and the first conductive semiconductor layer 111 is the first connection pad 120 and the first conductive semiconductor layer 111. If the level is 90% between them, the maximum efficiency of the light emitting device can be achieved. That is, the output of the light emitting device can be maximized without increasing the forward voltage. If the area of the first current blocking layer 140 is between the first connection pad 120 and the first conductivity-type semiconductor layer 111, the first connection pad 120 and the first conductivity-type semiconductor layer 111 may be used. If it is 90% or more between them, the forward voltage may increase due to the lack of the n-contact region.
도 2 및 도3을 참조하면, 제1 전류 차단층(140)이 제1 접속 패드(120)와 제1 도전형 반도체층(111) 사이에 개재되는 경우, 제1 접속 패드(120)의 상면에 단차가 생길 수 있다. 상기 단차로 인하여, 제1 접속 패드(120)의 상면의 면적이 증가하게 된다. 제1 접속 패드(120) 상면의 면적 증가로 BST(ball sear test)가 상승될 수 있고, 그에 따라 추후 와이어 본딩 시(미도시) 와이어와 제1 접속 패드(120) 사이의 접착력이 증대 될 수 있다.2 and 3, when the first current blocking layer 140 is interposed between the first connection pad 120 and the first conductive semiconductor layer 111, the top surface of the first connection pad 120 is disposed. Steps can occur. Due to the step, the area of the upper surface of the first connection pad 120 is increased. The ball sear test (BST) may be increased due to an increase in the area of the upper surface of the first connection pad 120, thereby increasing adhesion between the wire and the first connection pad 120 during wire bonding (not shown). have.
나아가, 제1 전류 차단층(140)은 SiO2층 또는 저굴절 물질층과 고굴절 물질층이 교대로 적층된 분포 브래그 반사기(DBR)를 포함할 수 있다. 예컨대, 분포 브래그 반사층은 SiO2층과 TiO2층 또는 SiO2층과 Nb2O5층이 교대로 적층된 구조를 가짐으로써, 반사율이 높은 절연 반사층이 될 수 있다. 분포 브래그 반사기는 구조적 특성 및 재질에 따라 특정 파장대의 빛에 대한 반사율이 높은 특성을 가질 수 있다. Further, the first current blocking layer 140 may include a distributed Bragg reflector (DBR) in which an SiO 2 layer or a low refractive material layer and a high refractive material layer are alternately stacked. For example, the distributed Bragg reflective layer has a structure in which an SiO 2 layer and a TiO 2 layer or an SiO 2 layer and an Nb 2 O 5 layer are alternately stacked, thereby making it an insulating reflective layer having high reflectance. The distributed Bragg reflector may have high reflectivity for light in a specific wavelength range depending on structural properties and materials.
발광소자는 제2 전류 차단층(150)을 더 포함할 수 있다. 제2 전류 차단층(150)은 제2 접속 패드(130)와 제2 도전형 반도체층(113) 사이, 그리고 상부 연장부(130-1)와 제2 도전형 반도체층(113) 사이에 개재되어 전류 확산 효율을 증대 시킬 수 있다. 제2 도전형 반도체층(113)이 p형 반도체층인 경우, 제2 전류 차단층(150)은 p형 전류 차단층으로 지칭될 수 있다. 발광소자가 투명 전극층(160)을 포함하는 경우, 제2 전류 차단층(150)은, 제2 접속 패드(130)와 제2 도전형 반도체층(113) 사이, 그리고 상부 연장부(130-1)와 제2 도전형 반도체층(113) 사이에서, 투명 전극층(160) 아래에 개재될 수 있다. 제2 접속 패드(130)와 제2 도전형 반도체층(113) 사이에 개재된 제2 전류 차단층(150)의 폭은 제2 접속 패드(130) 보다 크거나 같을 수 있다. 또한, 상부 연장부(130-1)들과 제2 도전형 반도체층(113) 사이에 개재된 제2 전류 차단층(150)의 폭은 상부 연장부(130-1)들 보다 크거나 같을 수 있다.The light emitting device may further include a second current blocking layer 150. The second current blocking layer 150 is interposed between the second connection pad 130 and the second conductive semiconductor layer 113 and between the upper extension 130-1 and the second conductive semiconductor layer 113. Can increase the current spreading efficiency. When the second conductive semiconductor layer 113 is a p-type semiconductor layer, the second current blocking layer 150 may be referred to as a p-type current blocking layer. When the light emitting device includes the transparent electrode layer 160, the second current blocking layer 150 is disposed between the second connection pad 130 and the second conductive semiconductor layer 113 and the upper extension 130-1. ) And the second conductive semiconductor layer 113, may be interposed below the transparent electrode layer 160. The width of the second current blocking layer 150 interposed between the second connection pad 130 and the second conductive semiconductor layer 113 may be greater than or equal to that of the second connection pad 130. In addition, the width of the second current blocking layer 150 interposed between the upper extensions 130-1 and the second conductive semiconductor layer 113 may be greater than or equal to that of the upper extensions 130-1. have.
제2 전류 차단층(150)은 제1 전류 차단층(140)과 동일한 물질층을 포함할 수 있다. 즉, 제2 전류 차단층(150)은 SiO2층 또는 저굴절 물질층과 고굴절 물질층이 교대로 적층된 분포 브래그 반사기(DBR)를 포함할 수 있다. 예컨대, 분포 브래그 반사층은 SiO2층과 TiO2층 또는 SiO2층과 Nb2O5층이 교대로 적층된 구조를 가짐으로써, 반사율이 높은 절연 반사층이 될 수 있다. 제2 전류 차단층(150)은 제1 전류 차단층(140)과 동일할 공정을 통해 형성될 수 있다. The second current blocking layer 150 may include the same material layer as the first current blocking layer 140. That is, the second current blocking layer 150 may include a distributed Bragg reflector (DBR) in which an SiO 2 layer or a low refractive material layer and a high refractive material layer are alternately stacked. For example, the distributed Bragg reflective layer has a structure in which an SiO 2 layer and a TiO 2 layer or an SiO 2 layer and an Nb 2 O 5 layer are alternately stacked, thereby making it an insulating reflective layer having high reflectance. The second current blocking layer 150 may be formed through the same process as the first current blocking layer 140.
또한, 발광 소자는 질화물계 반도체 적층(110) 구조의 측면을 덮는 절연층(165)을 더 포함할 수 있다. 도 2 및 도 3을 참조하면, 노출영역(110a, 110b)에서 질화물계 반도체 적층(110)의 일부 측면이 노출될 수 있다. 구체적으로 노출영역(110a, 110b)에서 활성층(112) 및 제2 도전형 반도체층(113)의 측면이 노출될 수 있다. 또한, 노출영역(110a, 110b)에서 제1 도전형 반도체층(111)의 일부 측면이 노출될 수 있다. In addition, the light emitting device may further include an insulating layer 165 covering the side surface of the nitride based semiconductor laminate 110. 2 and 3, some side surfaces of the nitride based semiconductor stack 110 may be exposed in the exposed regions 110a and 110b. In detail, side surfaces of the active layer 112 and the second conductivity-type semiconductor layer 113 may be exposed in the exposed regions 110a and 110b. In addition, some side surfaces of the first conductivity-type semiconductor layer 111 may be exposed in the exposed regions 110a and 110b.
절연층(165)은 노출영역(110a)에서 노출된 질화물계 반도체 적층(110)의 측면을 덮을 수 있다. 이는 노출영역(110a)에서 제1 접속 패드(120)에 와이어 본딩이 이루어 지는 경우(미도시), 상기 와이어와 질화물계 반도체 적층(110) 측면의 전기적 연결을 차단하기 위한 것이다. 절연층(165)을 통해 발광소자의 신뢰성이 향상될 수 있다.The insulating layer 165 may cover the side surface of the nitride based semiconductor laminate 110 exposed in the exposed region 110a. This is to block electrical connection between the wire and the nitride-based semiconductor stack 110 in the case where wire bonding is performed on the first connection pad 120 in the exposed region 110a. Reliability of the light emitting device may be improved through the insulating layer 165.
도 4는 본 발명의 일 실시 예에 따른 제1 전류 차단층(140)의 다양한 형태를 나타낸다. 도 4의(a) 내지 4의(h)는 제1 전류 차단층(140)의 다양한 형태를 설명하기 위한 목적으로 도 1의 일부 영역, 즉 C 영역을 나타내는 것이다. 4 illustrates various forms of the first current blocking layer 140 according to an embodiment of the present invention. 4A to 4H illustrate some regions, that is, regions C of FIG. 1, for the purpose of describing various forms of the first current blocking layer 140.
도 4의(a)를 참조하면, 제1 전류 차단층(140)은 노출 영역(110a) 내에서 제1 접속 패드(120)와 제1 도전형 반도체층(111) 사이에 한정되어 그 일부 영역에 개재된다. 여기서, 제1 전류 차단층(140)은 노출영역(110a) 내에서 제1 접속 패드(120)와 제1 도전형 반도체층(111) 사이의 영역을 넘어 그 이외의 영역에 형성되지 않는다. 또한, 제1 전류 차단층(140)은 제1 접속 패드(120)와 제1 도전형 반도체층(111) 사이에서 일부 영역에 개재되고, 그 사이의 나머지 영역에는 개재되지 않아 제1 접속 패드(120)와 제1 도전형 반도체층(111)이 전기적으로 연결될 수 있고 또한 발광소자의 순방향 전압 상승을 방지할 수 있다. 또한 제1 전류 차단층(140)은 노출 영역(110b)에서 하부 연장부(120-1)와 제1 도전형 반도체층(111) 사이의 일부 영역에도 개재될 수 있다.Referring to FIG. 4A, the first current blocking layer 140 is defined between the first connection pad 120 and the first conductivity-type semiconductor layer 111 in the exposed region 110a and a partial region thereof. Intervened in Here, the first current blocking layer 140 is not formed in the other area beyond the area between the first connection pad 120 and the first conductivity type semiconductor layer 111 in the exposed area 110a. In addition, the first current blocking layer 140 is interposed in a partial region between the first connection pad 120 and the first conductive semiconductor layer 111 and is not interposed in the remaining region between the first connection pad 120 and the first connection pad ( 120 and the first conductivity-type semiconductor layer 111 may be electrically connected to each other, and the forward voltage of the light emitting device may be prevented. In addition, the first current blocking layer 140 may be interposed in a portion of the exposed region 110b between the lower extension part 120-1 and the first conductivity type semiconductor layer 111.
도 4의(b) 내지 도 4의(e)를 참조하면, 제1 전류 차단층(140)은 노출 영역(110a) 내에서 제1 접속 패드(120)와 제1 도전형 반도체층(111) 사이 영역뿐 아니라, 노출 영역(110a) 내의 다른 부분에서도 형성되어 있다. 다만, 제1 전류 차단층(140)은 제1 접속 패드(120)와 제1 도전형 반도체층(111) 사이에서 도 4의(b)와 같이 하단 부분이 제거 되거나, 도 4의(c) 및 도 4의(d)와 같이 일부 측면들이 패이거나, 도 4의(e)와 같이 가운데 부분이 제거된 형태를 가질 수 있다. 이와 같이 제거되거나 패인 부분들을 통해 제1 접속 패드(120)와 제1 도전형 반도체층(111)이 전기적으로 연결될 수 있고, 또한, 제1 전류 차단층(140)이 차지하는 영역이 제한되어 순방향 전압의 상승이 방지될 수 있다.Referring to FIGS. 4B through 4E, the first current blocking layer 140 may include the first connection pad 120 and the first conductive semiconductor layer 111 in the exposed region 110a. It is formed not only in the interregion but also in other parts of the exposed region 110a. However, the lower portion of the first current blocking layer 140 is removed between the first connection pad 120 and the first conductive semiconductor layer 111 as shown in FIG. 4B, or FIG. 4C. And some side surfaces as shown in (d) of FIG. 4, or may have a form in which the center portion is removed as shown in (e) of FIG. 4. The first connection pad 120 and the first conductivity-type semiconductor layer 111 may be electrically connected through the removed or recessed portions, and the area occupied by the first current blocking layer 140 may be limited so that the forward voltage may be reduced. The rise of can be prevented.
도 4의(f) 및 도 4의(g)를 참조하면, 제1 전류 차단층(140)은 노출 영역(110a) 내에서 제1 접속 패드(120)와 제1 도전형 반도체층(111) 사이 영역뿐 아니라, 노출 영역(110a)의 내의 다른 부분에서 형성되어 있음을 알 수 있다. 또한, 제1 전류 차단층(140)은 두 부분으로 분리될 수 있다. 하지만, 이에 제한 되는 것은 아니며, 제1 전류 차단층(140)은 더 많은 부분으로 분리되어 형성될 수 있다. 이와 같이 분리된 영역을 통해 제1 접속 패드(120)와 제1 도전형 반도체층(111)이 전기적으로 연결될 수 있고, 또한, 제1 전류 차단층(140)이 차지하는 영역이 제한되어 순방향 전압의 상승이 방지될 수 있다. Referring to FIGS. 4F and 4G, the first current blocking layer 140 may include the first connection pad 120 and the first conductivity-type semiconductor layer 111 in the exposed region 110a. It can be seen that not only the inter-region but also other portions of the exposed region 110a are formed. In addition, the first current blocking layer 140 may be separated into two parts. However, the present invention is not limited thereto, and the first current blocking layer 140 may be separated into more portions. The first connection pad 120 and the first conductive semiconductor layer 111 may be electrically connected to each other through the separated region, and the region occupied by the first current blocking layer 140 may be limited, thereby preventing the forward voltage. Elevation can be prevented.
도 4의(h)를 참조하면, 제1 전류 차단층(140)은 예외적으로 노출 영역(110a) 전체에 형성되어 있다. 따라서 노출 영역(110a)에서는 제1 접속 패드(120)와 제1 도전형 반도체층(111)은 전기적으로 연결될 수 없다. 다만, 제1 접속 패드(120)와 전기적으로 연결된 하부 연장부(120-1)가 노출 영역(110b)를 통해 제1 도전형 반도체층(111)과 전기적으로 연결되므로, 결과적으로 제1 접속 패드(120)도 제1 도전형 반도체층(111)과 전기적으로 연결되게 된다. Referring to FIG. 4H, the first current blocking layer 140 is exceptionally formed in the entire exposed area 110a. Therefore, the first connection pad 120 and the first conductive semiconductor layer 111 may not be electrically connected in the exposed region 110a. However, since the lower extension part 120-1 electrically connected to the first connection pad 120 is electrically connected to the first conductivity type semiconductor layer 111 through the exposure area 110b, as a result, the first connection pad may be used. 120 is also electrically connected to the first conductivity type semiconductor layer 111.
도 5 내지 도 7은 본 발명의 다른 실시예에 따른 발광소자를 설명하기 위한 평면도 및 단면도들이다. 구체적으로, 도 5는 발광소자의 평면도이고, 도 6은 도 5의 평면도의 A-A'선에 대응하는 부분의 단면을 도시하고, 도 7은 도 5의 평면도의 B-B'선에 대응하는 부분의 단면을 도시한다.5 to 7 are plan views and cross-sectional views for describing a light emitting device according to another embodiment of the present invention. Specifically, FIG. 5 is a plan view of the light emitting device, FIG. 6 shows a cross section of a portion corresponding to the line A-A 'of the plan view of FIG. 5, and FIG. 7 corresponds to the line B-B' of the plan view of FIG. The cross section of the part to be shown is shown.
본 실시예의 발광소자는 도 1 내지 도 3을 참조하여 설명한 실시예들과 비교하여, 노출 영역(110a, 110b), 제1 접속 패드(120), 하부 연장부(120-1), 제2 접속(130) 패드 및 상부 연장부(130-1)들의 형상, 크기 및 개수 등에서 차이가 있다. 또한 본 실시예의 발광소자는 오믹 전극층(160), 절연층(170) 및 본딩패드들(180a, 180b)를 더 포함할 수 있다. 이하 차이점을 중심으로 본 실시예의 발광소자에 관하여 설명하며, 동일한 구성에 대한 상세한 설명은 생략한다. In the light emitting device of the present embodiment, the exposed regions 110a and 110b, the first connection pad 120, the lower extension 120-1, and the second connection are compared with the embodiments described with reference to FIGS. 1 to 3. There is a difference in the shape, the size and the number of the pad and the upper extension (130-1). In addition, the light emitting device of the present embodiment may further include an ohmic electrode layer 160, an insulating layer 170, and bonding pads 180a and 180b. Hereinafter, the light emitting device of the present embodiment will be described based on differences, and detailed descriptions of the same components will be omitted.
도 5 내지 도 7을 참조하면, 상기 발광소자는 질화물계 반도체 적층(110), 제1 접속 패드(120), 제2 접속 패드(130), 제1 전류 차단층(140) 및 제2 전류 차단층(150)을 포함한다. 나아가, 상기 발광소자는 제1 접속 패드(120)로부터 임의의 방향으로 연장된 하부 연장부(120-1) 및 제2 접속 패드(130)로부터 임의의 방향으로 연장된 상부 연장부(130-1)을 더 포함한다. 또한, 상기 발광소자는 사각형의 평면 형상을 가질 수 있다. 본 실시예에서, 상기 발광소자는 대체로 정방형의 평면 형상을 가질 수 있으며, 제1 측면(100a), 제2 측면(100b), 제1 측면(100a)에 반대하여 위치하는 제3 측면(100c), 및 제2 측면(100b)에 반대하여 위치하는 제4 측면(100d)을 포함할 수 있다. 다만 본 발명이 이에 한정되는 것은 아니다.5 to 7, the light emitting device includes a nitride based semiconductor stack 110, a first connection pad 120, a second connection pad 130, a first current blocking layer 140, and a second current blocking. Layer 150. In addition, the light emitting device includes a lower extension 120-1 extending in an arbitrary direction from the first connection pad 120 and an upper extension 130-1 extending in an arbitrary direction from the second connection pad 130. More). In addition, the light emitting device may have a rectangular planar shape. In the present embodiment, the light emitting device may have a generally square planar shape, and the third side surface 100c positioned opposite to the first side surface 100a, the second side surface 100b, and the first side surface 100a. And a fourth side surface 100d positioned opposite to the second side surface 100b. However, the present invention is not limited thereto.
질화물계 반도체 적층(110)은 제1 도전형 반도체층(111), 제1 도전형 반도체층(111) 상에 위치하는 활성층(112), 활성층(112) 상에 위치하는 제2 도전형 반도체층(113)을 포함한다. 또한, 질화물계 반도체 적층(110)은 제1 도전형 반도체층(111)을 부분적으로 노출시키는 영역(110a, 110b)을 포함할 수 있다. 노출 영역(110a, 110b)의 위치, 형태, 및 개수에 따라 전류 분산 효율 및 발광 장치의 발광 패턴이 조절될 수 있다.The nitride based semiconductor layer 110 includes a first conductive semiconductor layer 111, an active layer 112 positioned on the first conductive semiconductor layer 111, and a second conductive semiconductor layer positioned on the active layer 112. (113). In addition, the nitride-based semiconductor stack 110 may include regions 110a and 110b partially exposing the first conductivity-type semiconductor layer 111. The current dispersion efficiency and the light emission pattern of the light emitting device may be adjusted according to the position, shape, and number of the exposed areas 110a and 110b.
도 5를 참조하면, 제1 도전형 반도체층(111)이 부분적으로 노출되는 영역(110a, 110b)은 홀들을 포함할 수 있다. 즉, 노출 영역(110a)은 제1 홀(110a-1, 110a-2) 및 제2 홀(110a-3)을 포함할 수 있다. 노출 영역(110a)은 제1 노출 영역으로 지칭될 수 있다. 제1 홀(110a-1, 110a-2) 및 제2 홀(110a-3)은 각각 복수로 형성될 수 있다. 제1 홀(110a-1, 110b-2) 및 제2홀(110a-3)은 대체로 원형 또는 다각형의 평면 형상을 가질 수 있다. 노출 영역(110b)은 제2 홀(110a-3)로부터 임의의 방향으로 연장되는 형태로 형성될 수 있다. 노출 영역(110b)은 제2 노출 영역으로 지칭될 수 있다. 또한 노출 영역(110b)은 제3 홀로 지칭될 수 있다. 이 때, 제 3홀(또는 노출 영역)(110b)과 제2 홀(110a-3)은 서로 연결될 수 있다. 또한, 제 3홀(110b)의 폭은 제1 홀(110a-1, 110a-2) 및 제2 홀(110a-3)의 폭보다 작거나 같을 수 있다. Referring to FIG. 5, regions 110a and 110b partially exposed to the first conductivity-type semiconductor layer 111 may include holes. That is, the exposed area 110a may include first holes 110a-1 and 110a-2 and second holes 110a-3. The exposed area 110a may be referred to as a first exposed area. A plurality of first holes 110a-1 and 110a-2 and a plurality of second holes 110a-3 may be formed. The first holes 110a-1 and 110b-2 and the second holes 110a-3 may have a planar shape of generally circular or polygonal shape. The exposed area 110b may be formed to extend in an arbitrary direction from the second hole 110a-3. The exposed area 110b may be referred to as a second exposed area. In addition, the exposed area 110b may be referred to as a third hole. In this case, the third hole (or the exposed area) 110b and the second hole 110a-3 may be connected to each other. In addition, the width of the third hole 110b may be less than or equal to the width of the first holes 110a-1 and 110a-2 and the second holes 110a-3.
예컨대, 도 5에 도시된 바와 같이, 제1 홀(110a-1, 110a-2) 및 제2 홀(110a-3)은 원형의 평면 형상을 가지며, 복수로 형성될 수 있다. 제3 홀(110b)은 제2 홀(100a-3)로부터 연장되되, 제1 측면(100a)으로부터 제3 측면(100c)을 향해 연장되는 형태로 형성될 수 있다.For example, as illustrated in FIG. 5, the first holes 110a-1 and 110a-2 and the second holes 110a-3 may have a circular planar shape and may be formed in plural. The third hole 110b may extend from the second hole 100a-3 and may extend from the first side surface 100a toward the third side surface 100c.
제1 접속 패드(120)는 제1 도전형 반도체층(111)에 전기적으로 접속될 수 있으며, 특히, 제1 도전형 반도체층(111)에 오믹 컨택할 수 있다. 즉, 제1 접속 패드(120)는 제1 홀(110a-1, 110a-2) 및 제2 홀(110a-3)들을 포함하는 노출 영역(110a) 내에 형성되어 제1 도전형 반도체층(111)과 전기적으로 접속될 수 있다. 따라서, 제1 접속 패드(120)를 통해 질화물계 반도체 적층(110)으로 전류가 주입되는 부분은 노출 영역(110a)의 위치 및 형태 등에 따라 제어될 수 있다. 제1 접속 패드(120)는 도 5에 도시된 것과 같이 노출영역(110a)을 기초로 일정한 패턴으로 복수 개가 형성될 수 있으나, 이제 제한되는 것은 아니다.The first connection pad 120 may be electrically connected to the first conductive semiconductor layer 111, and in particular, the first connection pad 120 may be in ohmic contact with the first conductive semiconductor layer 111. That is, the first connection pad 120 is formed in the exposed region 110a including the first holes 110a-1 and 110a-2 and the second holes 110a-3 to form the first conductive semiconductor layer 111. ) May be electrically connected. Therefore, the portion of the current injected into the nitride-based semiconductor stack 110 through the first connection pad 120 may be controlled according to the position and shape of the exposed region 110a. As illustrated in FIG. 5, a plurality of first connection pads 120 may be formed in a predetermined pattern based on the exposed area 110a, but is not limited thereto.
하부 연장부(120-1)는 노출 영역(또는 제3 홀)(110b) 내에 형성되어 제1 도전형 반도체층(111)에 전기적으로 접속될 수 있다. 노출 영역(110b)은 제2 홀(110a-3)과 연결되는 구조이며, 따라서 하부 연장부(120-1)는 제2 홀(110a-3) 내에 형성된 제1 접속 패드(120)와 전기적으로 연결될 수 있다. 하부 연장부(120-1)는 도 5에 도시된 것과 같이 노출영역(110b)을 기초로 일정한 패턴으로 복수 개가 형성될 수 있으나, 이제 제한되는 것은 아니다.The lower extension part 120-1 may be formed in the exposed area (or the third hole) 110b to be electrically connected to the first conductivity type semiconductor layer 111. The exposed area 110b is connected to the second hole 110a-3, and thus the lower extension part 120-1 is electrically connected to the first connection pad 120 formed in the second hole 110a-3. Can be connected. The lower extension part 120-1 may be formed in plural in a predetermined pattern based on the exposed area 110b as shown in FIG. 5, but is not limited thereto.
본 실시예에 따른 발광소자는 제2 접속 패드(130)를 포함할 수 있다. 제2 접속 패드(130)는 질화물계 반도체 적층(110) 상에 위치하여, 제2 도전형 반도체층(113)과 오믹 컨택할 수 있다. 제2 접속 패드(130)는 복수로 형성될 수 있다. 또한, 발광소자는 일부 제2 접속 패드(130) 로부터 연장된 상부 연장부(130-1)를 포함할 수 있다. 상부 연장부(130-1)는 제3 측면(100c)으로부터 제1 측면(100a)을 향해 연장되는 형태로 형성될 수 있으며, 복수로 형성될 수 있다. 제2 접속 패드(130)는 및 상부 연장부(130-1)는 도 5에 도시된 것과 같이 일정한 패턴으로 복수 개가 형성될 수 있으나, 이에 제한되는 것은 아니다.The light emitting device according to the present embodiment may include a second connection pad 130. The second connection pad 130 may be positioned on the nitride based semiconductor stack 110 and may be in ohmic contact with the second conductivity type semiconductor layer 113. The second connection pads 130 may be formed in plural. In addition, the light emitting device may include an upper extension part 130-1 extending from some second connection pads 130. The upper extension 130-1 may be formed to extend from the third side surface 100c toward the first side surface 100a and may be formed in plural. A plurality of second connection pads 130 and upper extensions 130-1 may be formed in a predetermined pattern as illustrated in FIG. 5, but is not limited thereto.
여기서 제1 접속 패드(120) 및 제2 접속 패드(130)는 질화물계 반도체 적층(110)의 전기적 연결을 위한 것으로, 예를 들어, 제1 접속 패드(120) 및 제2 접속 패드(130)는 각각 제1 본딩 패드(180a) 및 제2 본딩 패드(180b)와 전기적으로 연결될 수 있다. 제1 본딩 패드(180a) 및 제2 본딩 패드(180b)를 통해 발광소자는 외부 장치와 전기적으로 연결될 수 있고, 전원을 공급 받을 수 있다.Here, the first connection pad 120 and the second connection pad 130 are for electrical connection of the nitride-based semiconductor stack 110, for example, the first connection pad 120 and the second connection pad 130. May be electrically connected to the first bonding pads 180a and the second bonding pads 180b, respectively. The light emitting device may be electrically connected to an external device through the first bonding pad 180a and the second bonding pad 180b and may be supplied with power.
제1 전류 차단층(140)은 제1 접속 패드(120)와 제1 도전형 반도체층(111) 사이에 개재될 수 있다. 제1 접속 패드(120)와 제1 도전형 반도체층(111) 사이의 일부 영역에 제1 전류 차단층(140)이 개재되어, 제1 도전형 반도체층(111)으로 효과적으로 전류가 넓게 분산될 수 있도록 도울 수 있다. 특히, 도 5에서와 같이, 제1 접속 패드(120)들이 상부 연장부(130-1)들 사이에 위치하는 구조의 발광소자의 경우, 제1 접속 패드(120)를 통해 주입되는 전류의 분산이 원활하게 이루어지지 않은 문제점이 발생될 수 있다. 이를 해결하기 위해, 제1 도전형 반도체층(111)과 제1 접속 패드(120) 사이에 제1 전류 차단층(140)이 개재되어 효과적으로 전류가 넓게 분산될 수 있다. The first current blocking layer 140 may be interposed between the first connection pad 120 and the first conductive semiconductor layer 111. The first current blocking layer 140 is interposed in a portion of the region between the first connection pad 120 and the first conductive semiconductor layer 111 so that the current can be effectively distributed to the first conductive semiconductor layer 111. Can help. In particular, as shown in FIG. 5, in the case of a light emitting device having a structure in which the first connection pads 120 are positioned between the upper extensions 130-1, the current is injected through the first connection pad 120. This may not occur smoothly. In order to solve this problem, the first current blocking layer 140 is interposed between the first conductive semiconductor layer 111 and the first connection pad 120 to effectively distribute the current.
구체적으로, 제1 전류 차단층(140)은, 노출 영역(110a) 내에서, 제1 접속 패드(120)와 제1 도전형 반도체층(111) 사이에 개재될 수 있다. 제1 전류 차단층(140)은, 예를 들어, 원형, 사각형, 삼각형 등 임의의 형상을 가질 수 있으며 그 제한은 없다. 특히, 제1 전류 차단층(140)은 노출 영역(110a)의 형상과 유사한 원형 형상을 가질 수 있다. 하지만, 이에 한정되는 것은 아니다. 또한, 제1 전류 차단층(140)은 도 4에 나타난 제1 전류 차단층(140)의 여러 가지 형상들 중 하나일 수 있다. In detail, the first current blocking layer 140 may be interposed between the first connection pad 120 and the first conductivity-type semiconductor layer 111 in the exposed region 110a. The first current blocking layer 140 may have any shape, for example, a circle, a rectangle, a triangle, and the like, but is not limited thereto. In particular, the first current blocking layer 140 may have a circular shape similar to that of the exposed region 110a. However, it is not limited thereto. In addition, the first current blocking layer 140 may be one of various shapes of the first current blocking layer 140 shown in FIG. 4.
제1 전류 차단층(140)의 면적은 노출 영역(110a) 내에서 일정 수준으로 제한될 수 있다. 즉, 제1 전류 차단층(140)은 노출 영역(110a)의 임의의 영역에서 임의의 넓이로 형성될 수 있지만, 제1 접속 패드(120)와 제1 도전형 반도체층(111) 사이 영역의 90% 이상을 차지하지 않아야 한다. 이는 제1 전류 차단층(140)의 면적이 증가하는 경우, 전류 분산이 잘 이루어져서 발광소자의 출력(power)이 향상되지만 일정 수준 이상 그 면적이 증가하는 경우, 발광소자의 순방향 전압(forward voltage, Vf)이 급격하게 증가할 수 있기 때문이다. 따라서, 제1 전류 차단층(140)의 면적은 노출 영역(110a)에서 제1 접속 패드(120)와 제1 도전형 반도체층(111)이 사이의 90% 이하로 제한 될 수 있다. 특히, 제1 전류 차단층(140)의 면적이 제1 접속 패드(120)와 제1 도전형 반도체층(111) 사이 영역의 90% 수준인 경우, 발광소자의 최대 효율이 달성될 수 있다. 즉, 순방향 전압 상승 없이 발광소자의 출력이 최대가 될 수 있다. 만약, 제1 전류 차단층(140)의 면적이 제1 접속 패드(120)와 제1 도전형 반도체층(111)이 접하는 면적의 90% 이상이 되는 경우, n-컨택 영역의 부족으로 인하여 순방향 전압이 상승될 수 있다.The area of the first current blocking layer 140 may be limited to a predetermined level in the exposed area 110a. That is, the first current blocking layer 140 may be formed to have an arbitrary width in any area of the exposed area 110a, but the first current blocking layer 140 may be formed in any area of the area between the first connection pad 120 and the first conductivity type semiconductor layer 111. It should not occupy more than 90%. This is because when the area of the first current blocking layer 140 is increased, the current is well distributed and the power of the light emitting device is improved, but when the area is increased by a certain level or more, the forward voltage of the light emitting device is increased. This is because Vf) may increase rapidly. Therefore, the area of the first current blocking layer 140 may be limited to 90% or less between the first connection pad 120 and the first conductivity-type semiconductor layer 111 in the exposed region 110a. In particular, when the area of the first current blocking layer 140 is 90% of the area between the first connection pad 120 and the first conductive semiconductor layer 111, the maximum efficiency of the light emitting device can be achieved. That is, the output of the light emitting device can be maximized without increasing the forward voltage. If the area of the first current blocking layer 140 is greater than or equal to 90% of the area where the first connection pad 120 and the first conductive semiconductor layer 111 contact each other, the forward direction may occur due to the lack of the n-contact region. The voltage can be raised.
나아가, 제1 전류 차단층(140)은 SiO2층 또는 저굴절 물질층과 고굴절 물질층이 교대로 적층된 분포 브래그 반사기(DBR)를 포함할 수 있다. 예컨대, 분포 브래그 반사층은 SiO2층과 TiO2층 또는 SiO2층과 Nb2O5층이 교대로 적층된 구조를 가짐으로써, 반사율이 높은 절연 반사층이 될 수 있다.Further, the first current blocking layer 140 may include a distributed Bragg reflector (DBR) in which an SiO 2 layer or a low refractive material layer and a high refractive material layer are alternately stacked. For example, the distributed Bragg reflective layer has a structure in which an SiO 2 layer and a TiO 2 layer or an SiO 2 layer and an Nb 2 O 5 layer are alternately stacked, thereby making it an insulating reflective layer having high reflectance.
제1 전류 차단층(140)이 제1 접속 패드(120)와 제1 도전형 반도체층(111) 사이에 개재되는 경우, 제1 접속 패드(120)의 상면에 단차(미도시)가 생길 수 있다. When the first current blocking layer 140 is interposed between the first connection pad 120 and the first conductive semiconductor layer 111, a step (not shown) may occur on the top surface of the first connection pad 120. have.
발광소자는 제2 전류 차단층(150)을 더 포함할 수 있다. 제2 전류 차단층(150)은 제2 접속 패드(130) 및 상부 연장부(130-1)와 제2 도전형 반도체층(113) 사이에 개재되어 전류 분산 효율을 증대 시킬 수 있다. 제2 도전형 반도체층(113)이 p형 반도체층인 경우, 제2 전류 차단층(150)은 p형 전류 차단층으로 지칭될 수 있다. 발광소자가 오믹 전극층(160)을 포함하는 경우, 제2 전류 차단층(150)은 제2 접속 패드(130) 및 상부 연장부(130-1)와 제2 도전형 반도체층(113) 사이에서 오믹 전극층(160) 아래에 개재될 수 있다. 오믹 전극층(160)은 투명 전극층 또는 메탈 전극층일 수 있다. 제2 접속 패드(130)와 제2 도전형 반도체층(113) 사이에 개재된 제2 전류 차단층(150)의 폭은 제2 접속 패드(130) 보다 크거나 같을 수 있다. 또한, 상부 연장부(130-1)와 제2 도전형 반도체층(113) 사이에 개재된 제2 전류 차단층(150)의 폭은 상부 연장부(130-1)들 의 폭보다 크거나 같을 수 있다. 제2 전류 차단층(150)은 제1 전류 차단층(140)과 동일한 물질층을 포함할 수 있다. 제2 전류 차단층(150)은 제1 전류 차단층(140)과 동일할 공정을 통해 형성될 수 있다.The light emitting device may further include a second current blocking layer 150. The second current blocking layer 150 may be interposed between the second connection pad 130 and the upper extension 130-1 and the second conductive semiconductor layer 113 to increase the current dispersion efficiency. When the second conductive semiconductor layer 113 is a p-type semiconductor layer, the second current blocking layer 150 may be referred to as a p-type current blocking layer. When the light emitting device includes the ohmic electrode layer 160, the second current blocking layer 150 is disposed between the second connection pad 130 and the upper extension 130-1 and the second conductive semiconductor layer 113. The ohmic electrode layer 160 may be interposed below. The ohmic electrode layer 160 may be a transparent electrode layer or a metal electrode layer. The width of the second current blocking layer 150 interposed between the second connection pad 130 and the second conductive semiconductor layer 113 may be greater than or equal to that of the second connection pad 130. In addition, the width of the second current blocking layer 150 interposed between the upper extension 130-1 and the second conductive semiconductor layer 113 may be equal to or greater than the width of the upper extension 130-1. Can be. The second current blocking layer 150 may include the same material layer as the first current blocking layer 140. The second current blocking layer 150 may be formed through the same process as the first current blocking layer 140.
발광소자는 질화물계 반도체 적층(110) 상에 형성된 절연층(170)을 더 포함할 수 있다. 절연층(170)은 SiO2층 또는 저굴절 물질층과 고굴절 물질층이 교대로 적층된 분포 브래그 반사기(DBR)를 포함할 수 있다. 예컨대, 분포 브래그 반사층은 SiO2층과 TiO2층 또는 SiO2층과 Nb2O5층이 교대로 적층된 구조를 가짐으로써, 반사율이 높은 절연 반사층이 될 수 있다. 절연층(170)은 복수의 개구부(190a, 190b)를 포함할 수 있다. 개구부(190a)를 통해 제1 접속 패드(120)와 추후 언급될 제1 본딩 패드(180a)가 전기적으로 접속될 수 있다. 또한 개구부(190b)를 통해 제2 접속 패드(130)와 추후 언급될 제2 본딩 패드(180b)가 전기적을 연결될 수 있다. 개구부(190a) 및 개구부(190b)는 복수개가 형성될 수 있다. The light emitting device may further include an insulating layer 170 formed on the nitride based semiconductor stack 110. The insulating layer 170 may include a distributed Bragg reflector (DBR) in which an SiO 2 layer or a low refractive material layer and a high refractive material layer are alternately stacked. For example, the distributed Bragg reflective layer has a structure in which an SiO 2 layer and a TiO 2 layer or an SiO 2 layer and an Nb 2 O 5 layer are alternately stacked, thereby making it an insulating reflective layer having high reflectance. The insulating layer 170 may include a plurality of openings 190a and 190b. The first connection pad 120 and the first bonding pad 180a to be described later may be electrically connected through the opening 190a. In addition, the second connection pad 130 and the second bonding pad 180b to be described later may be electrically connected through the opening 190b. A plurality of openings 190a and openings 190b may be formed.
제1 본딩패드(180a) 및 제2 본딩패드(180b)는 각각 제1 접속 패드(120) 및 제2 접속 패드(130)에 전기적으로 연결될 수 있다. 도 5 내지 도 7을 참조하면, 제1 본딩패드(180a)는 개구부(190a)들을 통해 제1 접속 패드(120)과 접촉될 수 있고, 제2 본딩패드(180b)는 개구부(190b)들을 통해 제2 접속 패드(130)와 접촉될 수 있다.The first bonding pads 180a and the second bonding pads 180b may be electrically connected to the first connection pads 120 and the second connection pads 130, respectively. 5 to 7, the first bonding pad 180a may be in contact with the first connection pad 120 through the openings 190a, and the second bonding pad 180b may be through the openings 190b. It may be in contact with the second connection pad 130.
도 8 내지 10은 본 발명의 또 다른 실시예에 따른 발광 소자를 설명하기 위한 평면도들 및 단면도를 나타낸다. 구체적으로 도 8은 상기 발광 소자의 평면도이고, 도 9는 도 8의 영역 α를 확대 도시한 것이고, 도 10은 도 8의 C-C'선에 대응하는 부분의 단면을 도시다.8 to 10 are plan views and cross-sectional views for describing a light emitting device according to still another embodiment of the present invention. Specifically, FIG. 8 is a plan view of the light emitting device, FIG. 9 is an enlarged view of the region α of FIG. 8, and FIG.
본 실시예에 따른 발광 소자는 도 1에 개시된 발광 소자와 대부분의 구성이 동일하며, 다만 제1 접속 패드(220), 하부 연장부(220-1), 제1 전류 차단층(240) 및 절연층(265)의 형상에 있어서 다소 차이가 존재한다. 또한 본 실시예에 따른 발광 소자는 제3 전류 차단층(270)을 더 포함 한다. 이하 동일한 구성에 대한 설명은 생략되며, 도 9에 확대 도시된 이들의 평면 형상을 참조하여 그 차이점 위주로 기술 된다.The light emitting device according to the present embodiment has the same configuration as that of the light emitting device shown in FIG. 1, except that the first connection pad 220, the lower extension part 220-1, the first current blocking layer 240, and the insulation are provided. There are some differences in the shape of layer 265. In addition, the light emitting device according to the present embodiment further includes a third current blocking layer 270. Hereinafter, the description of the same configuration is omitted, with reference to the planar shape thereof enlarged in Fig. 9 will be described mainly on the difference.
도 9에서 제1 접속 패드(220)의 평면도가 나타나 있다. 제1 접속 패드(220)는 제1 도전형 반도체층(111)과 접속된다. 도 9를 참조하면, 제1 접속 패드(220)의 테두리는 제1 곡선 영역(221)을 포함한다. 또한 제1 접속 패드(220)의 테두리는 직선 영역들을 포함할 수 있다. 제1 접속 패드(220)의 테두리의 형상은 제1 접속 패드(220)와 제1 도전형 반도체층(111)이 접하는 영역의 최 외각 테두리의 형상과 동일하거나 유사할 수 있다. 이에 따라, 제1 접속 패드(220)의 테두리와 제1 접속 패드(220)와 제1 도전형 반도체층(111)이 접하는 영역의 최 외각 테두리는 동일한 의미로 사용될 수 있다. 제1 곡선 영역(221)은 상기 테두리의 적어도 일부를 의미한다.9 is a plan view of the first connection pad 220. The first connection pad 220 is connected to the first conductivity type semiconductor layer 111. Referring to FIG. 9, the edge of the first connection pad 220 includes a first curved area 221. In addition, the edge of the first connection pad 220 may include straight regions. The shape of the edge of the first connection pad 220 may be the same as or similar to the shape of the outermost edge of the region where the first connection pad 220 and the first conductive semiconductor layer 111 contact each other. Accordingly, the edge of the first connection pad 220 and the outermost edge of the region where the first connection pad 220 and the first conductive semiconductor layer 111 contact each other may be used in the same sense. The first curved area 221 means at least a portion of the edge.
제1 곡선 영역(221)은 곡률 반경 R1 값을 가질 수 있다. 즉, 제1 곡선 영역(221)은 1/R1의 곡률을 가질 수 있다. 제1 곡선 영역(221)은 직선 영역들을 연결할 수 있다. 도 9를 참조하면, 제1 접속 패드(220)에서 네 개의 제1 곡선 영역(221)들이 네 개의 직선 영역들을 연결하는 것이 개시되어 있다.The first curved area 221 may have a radius of curvature R 1 . That is, the first curved area 221 may have a curvature of 1 / R 1 . The first curved area 221 may connect straight areas. Referring to FIG. 9, it is disclosed that four first curved areas 221 connect four straight areas in the first connection pad 220.
제1 접속 패드(220)가 제1 곡선 영역(221)들을 포함하고, 제1 곡선 영역(221)들이 직선 영역들을 연결하는 것에 따라, 제1 접속 패드(220)는 각진 부분을 포함하지 않을 수 있다. As the first connection pad 220 includes the first curved regions 221 and the first curved regions 221 connect the straight regions, the first connection pad 220 may not include the angled portion. have.
이는, 먼저 제1 접속 패드(220)의 형성을 위한 공정에 있어서, 유리하게 작용될 수 있다. 예를 들어, 제1 접속 패드(220)는 마스크를 이용한 리프트 오프 방식으로 메탈을 증착하여 형성될 수 있다. 이때, 제1 접속 패드(220)가 각진 부분을 포함하도록 설계된 경우, 제1 접속 패드(200) 형성을 위한 마스크도 마찬가지로 각진 부분을 포함하게 된다. 제1 접속 패드(220) 형성을 위한 메탈을 증착할 때, 상기 마스크의 각진 부분에서 메탈의 증착이 원활하게 이루어지지 않을 수 있다. 이 경우 설계된 형상에 따른 제1 접속 패드(220)를 얻기 어렵다. 반대로, 제1 접속 패드(220)가 제1 곡선 영역(221)들을 포함하는 것에 따라 각진 영역을 포함하지 않도록 설계된 경우, 설계된 형상의 제1 접속 패드(220)를 용이하게 얻을 수 있다.This may be advantageously performed first in the process for forming the first connection pad 220. For example, the first connection pad 220 may be formed by depositing a metal in a lift-off method using a mask. In this case, when the first connection pad 220 is designed to include an angled portion, the mask for forming the first connection pad 200 may also include an angled portion. When depositing the metal for forming the first connection pad 220, the deposition of the metal on the angled portion of the mask may not be performed smoothly. In this case, it is difficult to obtain the first connection pad 220 according to the designed shape. On the contrary, when the first connection pad 220 is designed not to include the angled area as the first connection pad 220 includes the first curved areas 221, the first connection pad 220 having the designed shape can be easily obtained.
또한, 제1 접속 패드(220)가 각진 부분을 포함하는 경우, 제1 접속 패드(220)에 본딩 된 와이어를 통해 주입되는 전류가 제1 접속 패드(220)의 각진 부분에 집중될 수 있다. 이는 발광 소자에서 전류가 수평 방향으로 고르게 분산되는 것을 방해하여, 결과적으로 발광 소자의 출력을 저하시킬 수 있다. 제1 접속 패드(220)가 제1 곡선 영역(221)을 포함하는 것에 따라 각진 부분을 포함하지 않도록 설계되는 경우, 위와 같은 전류 집중 현상이 발생되지 않으며, 그에 따라 전류가 수평 방향으로 고르게 분산될 수 있다. 이에 따라, 발광 소자의 ESD(electro static discharge), EOS(electro over stress)가 개선될 수 있다.In addition, when the first connection pad 220 includes an angled portion, current injected through a wire bonded to the first connection pad 220 may be concentrated on the angled portion of the first connection pad 220. This may prevent the current from being evenly distributed in the horizontal direction in the light emitting device, and as a result, may lower the output of the light emitting device. When the first connection pad 220 is designed not to include the angled portion as the first curved area 221 includes the first curved region 221, the current concentration phenomenon does not occur as described above, and thus the current is evenly distributed in the horizontal direction. Can be. Accordingly, electrostatic discharge (ESD) and electro over stress (EOS) of the light emitting device can be improved.
제1 전류 차단층(240)은 제1 접속 패드(220)와 제1 도전형 반도체층(111) 사이에 개재될 수 있다. 제1 전류 차단층(240)은 제1 접속 패드(220)와 제1 도전형 반도체층(111) 사이의 일부 영역에 개재될 수 있고, 그에 따라 제1 접속 패드(220)로부터 제1 도전형 반도체층(111)으로 효과적으로 전류가 넓게 분산될 수 있다.The first current blocking layer 240 may be interposed between the first connection pad 220 and the first conductive semiconductor layer 111. The first current blocking layer 240 may be interposed in a portion of the region between the first connection pad 220 and the first conductive semiconductor layer 111, and thus, the first current blocking layer 220 may be disposed from the first conductive pad 220. The current may be effectively distributed to the semiconductor layer 111.
도 9에 확대 도시된 제1 전류 차단층(240)의 평면 형상을 참조하면, 제1 전류 차단층(240)의 평면 형상은 제1 접속 패드(220)의 평면 형상과 매우 유사할 수 있다. 제1 전류 차단층(240)의 테두리는 제2 곡선 영역을 포함할 수 있다. 또한, 제1 전류 차단층(240)의 테두리는 직선 영역들을 포함할 수 있다. 이때, 제2 곡선 영역(241)은 제1 곡선 영역(221)의 내측에 인접하여 배치될 수 있다. 예를 들어, 제1 곡선 영역(221)과 제2 곡선 영역(241)을 동일한 중심(미도시)을 공유할 수 있으며, 이때, 제2 곡선 영역(241)은 제1 곡선 영역(221)과 상기 중심을 통해 형성되는 부채꼴 영역 내에 위치할 수 있다. 즉, 제1 곡선 영역(221)의 양단과 상기 중심을 연결하는 가상의 선 및 제1 곡선 영역(221)에 의해 형성되는 영역 내에서, 제2 곡선 영역(241)은 제1 곡선 영역(221)과 나란히 위치할 수 있다. 또한, 제2 곡선 영역(241)은 곡률 반경 R2 값을 가질 수 있으며, 여기서 R2 값은 R1 값에 비해 더 작을 수 있다. 이에 따라, 제1 곡선 영역(221)과 그 내측에 위치하는 제2 곡선 영역(241)의 간격(G1)이 균일하게 유지될 수 있다. Referring to the planar shape of the first current blocking layer 240 enlarged in FIG. 9, the planar shape of the first current blocking layer 240 may be very similar to the planar shape of the first connection pad 220. An edge of the first current blocking layer 240 may include a second curved area. In addition, an edge of the first current blocking layer 240 may include straight regions. In this case, the second curved area 241 may be disposed adjacent to the inside of the first curved area 221. For example, the first curved region 221 and the second curved region 241 may share the same center (not shown), and the second curved region 241 may be connected to the first curved region 221. It may be located within the sector region formed through the center. That is, in the region formed by the imaginary line connecting the both ends of the first curved region 221 and the center and the first curved region 221, the second curved region 241 is the first curved region 221. ) Can be placed next to each other. In addition, the second curved area 241 may have a radius of curvature R 2 , where the R 2 value may be smaller than the R 1 value. Accordingly, the distance G1 between the first curved area 221 and the second curved area 241 positioned inside thereof may be maintained uniformly.
또한, 제1 곡선 영역(221)과 제2 곡선 영역(241)의 간격(G1)은 제1 접속 패드(220)의 직선 영역과 제1 전류 차단층(240)의 직선 영역 사이의 간격과 동일하게 형성될 수 있다. 이에 따라, 제1 전류 차단층(240)에 의해 정의되는, 제1 접속 패드(220)와 제1 도전형 반도체층(111)이 접하는 영역의 폭이 균일하게 형성될 수 있다. 이를 통해, 제1 접속 패드(220)를 통해 주입되는 전류가 모든 방향으로 균일하게 분배될 수 있다.In addition, the interval G1 of the first curved region 221 and the second curved region 241 is equal to the interval between the linear region of the first connection pad 220 and the linear region of the first current blocking layer 240. Can be formed. Accordingly, the width of the region where the first connection pad 220 and the first conductive semiconductor layer 111 are defined by the first current blocking layer 240 may be uniformly formed. Through this, the current injected through the first connection pad 220 may be uniformly distributed in all directions.
하부 연장부(220-1)는 제1 접속 패드(220)로부터 연장되며, 제1 도전형 반도체층(111)과 접속될 수 있다. 도 9를 참조하면, 하부 연장부(220-1)는 연결부(220-1a) 및 메인 연장부(220-1b)를 포함할 수 있다. 연결부(220-1a)는 메인 연장부(220-1b)를 제1 접속 패드(220)에 연결할 수 있다.The lower extension part 220-1 may extend from the first connection pad 220 and may be connected to the first conductive semiconductor layer 111. Referring to FIG. 9, the lower extension part 220-1 may include a connection part 220-1a and a main extension part 220-1b. The connection part 220-1a may connect the main extension part 220-1b to the first connection pad 220.
도 9에서, 연결부(220-1a)의 평면 형상이 나타나 있다. 도 9를 참조하면, 연결부(220-1a)의 테두리는 제3 곡선 영역(221-1)을 포함할 수 있다. 연결부(220-1a)는 두 개의 제3 곡선 영역(221-1)을 포함할 수 있으며, 여기서 제3 곡선 영역(221-1)은 곡률 반경 R3 값을 가질 수 있다. 연결부(220-1a)가 제3 곡선 영역(221-1)을 포함하는 것에 따라, 연결부(220-1a)의 폭(G2)은 제1 접속 패드(220)로부터 멀어질수록 감소할 수 있다. 다만, 연결부(220-1a)의 최소 폭은 제1 곡선 영역(221)과 제2 곡선 영역(241) 사이의 간격(G1)보다 크게 형성될 수 있다. 그에 따라, 제1 접속 패드(220)를 통해 주입되는 전류 중 비교적 큰 비율이, 비교적 큰 넓이를 갖는 연결부(220-1a) 쪽으로 원활하게 주입될 수 있다. 또한, 연결부(220-1a)의 폭(G2)이 상대적으로 넓게 형성되는 경우, 연결부(220-1a)가 제1 접속 패드(220)와 단선될 수 있는 위험이 감소하여, 발광 소자의 신뢰성이 향상될 수 있다.In FIG. 9, the planar shape of the connecting portion 220-1a is shown. Referring to FIG. 9, the edge of the connector 220-1a may include a third curved area 221-1. The connection part 220-1a may include two third curved areas 221-1, where the third curved area 221-1 may have a radius of curvature R 3 . As the connection part 220-1a includes the third curved area 221-1, the width G2 of the connection part 220-1a may decrease as the distance from the first connection pad 220 increases. However, the minimum width of the connecting portion 220-1a may be larger than the gap G1 between the first curved area 221 and the second curved area 241. Accordingly, a relatively large proportion of the current injected through the first connection pad 220 may be smoothly injected into the connection portion 220-1a having a relatively large area. In addition, when the width G2 of the connecting portion 220-1a is relatively wide, the risk that the connecting portion 220-1a may be disconnected from the first connection pad 220 is reduced, so that the reliability of the light emitting device is improved. Can be improved.
다만, R3 값은 R1 값 및 R2 값에 비해 작게 형성될 수 있다. 즉, 제3 곡선 영역(221-1)은 제1 곡선 영역(221) 및 제2 곡선 영역(241)에 비해 굽은 정도가 더 클 수 있다. 여기서, R3 값이 R1 값이나 R2 값보다 크다면, 제1 접속 패드(220)에 인접하는 연결부(220-1a)의 폭이 상대적으로 매우 커지게 된다. 즉, 연결부(220-1a)의 평면 영역이 상대적으로 매우 넓어지게 질 수 있다. 이는, 더 넓은 노출 영역(110a, 110b)을 요구하게 되며, 그에 따라 발광 영역이 감소하여 발광 소자의 출력이 감소될 수 있다.However, the R 3 value may be smaller than the R 1 value and the R 2 value. That is, the third curved area 221-1 may have a greater degree of bending than the first curved area 221 and the second curved area 241. Here, when the value of R 3 is greater than the value of R 1 or R 2 , the width of the connection portion 220-1a adjacent to the first connection pad 220 becomes relatively large. That is, the planar area of the connection part 220-1a may be relatively widened relatively. This requires a wider exposure area 110a, 110b, whereby the light emitting area is reduced and the output of the light emitting device can be reduced.
메인 연장부(220-1b)의 일단은 상기 연결부(220-1a)에 접속된다. 메인 연장부(220-1b)의 폭(G3)은 상기 제1 곡선 영역(221) 및 제2 곡선 영역(241) 사이의 간격(G1)보다 크거나 같을 수 있다. 예를 들어, 메인 연장부(220-1b)의 폭(G3)은 5㎛이고, 상기 제1 곡선 영역(221) 및 제2 곡선 영역(241) 사이의 간격(G1)은 4㎛일 수 있다. 다만, 메인 연장부(220-1b)의 폭(G3) 및 제1 곡선 영역(221) 및 제2 곡선 영역(241) 사이의 간격(G1)은 이에 제한되는 것은 아니며, 본 발명의 목적 범위 내에서 다양하게 변경될 수 있다. One end of the main extension part 220-1b is connected to the connection part 220-1a. The width G3 of the main extension part 220-1b may be greater than or equal to the gap G1 between the first curved area 221 and the second curved area 241. For example, the width G3 of the main extension part 220-1b may be 5 μm, and the interval G1 between the first curved area 221 and the second curved area 241 may be 4 μm. . However, the width G3 of the main extension part 220-1b and the gap G1 between the first curved area 221 and the second curved area 241 are not limited thereto, and are within the scope of the present invention. It can be changed in various ways.
앞서 언급된 것처럼, 상기 제1 곡선 영역(221) 및 제2 곡선 영역(241) 사이의 간격(G1)은 상기 제1 접속 패드(220)가 제1 도전형 반도체층(111)에 접속되는 영역과 관련된다. 즉, 제1 곡선 영역(221) 및 제2 곡선 영역(241) 사이의 간격(G1)이 클수록 제1 접속 패드(220)가 제1 도전형 반도체층(111)에 접속되는 면적이 증가하게 된다. 연결부(220-1a)의 폭(G2)을 상기 제1 곡선 영역(221) 및 상기 제2 곡선 영역(241)사이의 간격(G1)보다 크게 하거나, 또는 메인 연장부(220-1b)의 폭(G3)을 상기 제1 곡선 영역(221) 및 제2 곡선 영역(241) 사이의 간격(G1)보다 크게 하여, 제1 접속 패드(220)로 주입되는 전류가 하부 연장부(220-1) 쪽으로 더 원활하게 유도(guide)될 수 있다.As mentioned above, the gap G1 between the first curved region 221 and the second curved region 241 is a region in which the first connection pad 220 is connected to the first conductive semiconductor layer 111. Is associated with. That is, as the distance G1 between the first curved region 221 and the second curved region 241 increases, the area where the first connection pad 220 is connected to the first conductive semiconductor layer 111 increases. . The width G2 of the connecting portion 220-1a is made larger than the gap G1 between the first curved region 221 and the second curved region 241, or the width of the main extension portion 220-1b. The current that is injected into the first connection pad 220 is lower than the extended portion 220-1 by making G3 greater than the distance G1 between the first curved region 221 and the second curved region 241. Can be guided more smoothly towards the side.
절연층(265)은 노출 영역(110a)에서 반도체 적층(110)의 측면의 일부를 덮을 수 있다. 구체적으로, 노출 영역(110a)에서 활성층(112) 및 제2 도전형 반도체층(113)의 측면 일부가 노출될 수 있다. 절연층(265)은 활성층(112) 및 제2 도전형 반도체층(113)의 노출된 측면을 덮어, 제1 접속 패드(220)에 본딩(bonding)되는 와이어가 상기 노출된 활성층(112) 및 제2 도전형 반도체층(113)과 접속되는 것을 차단할 수 있다. 이에 따라, 발광 소자의 신뢰성이 높아질 수 있다.The insulating layer 265 may cover a portion of the side surface of the semiconductor stack 110 in the exposed region 110a. Specifically, portions of the side surfaces of the active layer 112 and the second conductivity-type semiconductor layer 113 may be exposed in the exposed region 110a. The insulating layer 265 covers the exposed side surfaces of the active layer 112 and the second conductive semiconductor layer 113 so that the wires bonded to the first connection pads 220 are exposed. The connection with the second conductive semiconductor layer 113 can be prevented. Accordingly, the reliability of the light emitting device can be increased.
도 9 및 도 10을 참조하면, 본 실시예에 따른 절연층(265)은 도 1 내지 3에 개시된 절연층(265)과 달리 하부 연장부(220-1) 아래에도 배치될 수 있다. 즉, 본 실시예에 따른 절연층(265)은 단절되지 않은 하나의 띠 형태를 갖고, 그 일부가 하부 연장부(220-1)에 의해 덮이는 구조를 가질 수 있다. 그에 따라, 본 실시예에 따른 절연층(265)은 단절된 형태의 도 1 내지 3의 절연층(265) 보다 더 높은 구조적 안정성을 가질 수 있다. 예를 들어, 본 실시예에 따른 절연층(265)은 그 일부가 하부 연장부(220-1)에 의해 고정되어, 박리 위험이 감소될 수 있다. 9 and 10, the insulating layer 265 according to the present embodiment may be disposed under the lower extension part 220-1, unlike the insulating layer 265 shown in FIGS. 1 to 3. That is, the insulating layer 265 according to the present exemplary embodiment may have a single unbroken strip shape, and a part of the insulating layer 265 may be covered by the lower extension part 220-1. Accordingly, the insulating layer 265 according to the present embodiment may have higher structural stability than the insulating layer 265 of FIGS. 1 to 3 in the disconnected form. For example, a portion of the insulating layer 265 according to the present embodiment is fixed by the lower extension part 220-1, so that the risk of peeling may be reduced.
또한, 앞서 언급된 것처럼 연결부(220-1a)의 폭(G2)이 제1 곡선 영역(221) 및 제2 곡선 영역(241)의 간격(G1) 또는 메인 연장부(220-1b)의 폭(G3)보다 상대적으로 클 수 있다. 이에 따라, 연결부(220-1a)가 제1 도전형 반도체층(111)과 접하는 면적이 상대적으로 클 수 있고, 이 경우 메인 연장부(220-1b)쪽으로 전류가 원활하게 주입되지 않을 수 있다. 따라서, 절연층(265)의 일부가 연결부(220-1a) 아래에 배치되어, 연결부(220-1a)와 제1 도전형 반도체층(111)의 접속 영역을 제한하여 메인 연장부(220-1b)쪽으로 전류의 주입량을 더 높일 수 있다.Also, as mentioned above, the width G2 of the connection portion 220-1a is equal to the width G1 of the gap G1 of the first curved region 221 and the second curved region 241 or the width of the main extension portion 220-1b ( Can be relatively larger than G3). Accordingly, the area in which the connecting portion 220-1a contacts the first conductive semiconductor layer 111 may be relatively large, and in this case, the current may not be smoothly injected into the main extension portion 220-1b. Therefore, a part of the insulating layer 265 is disposed below the connecting portion 220-1a to limit the connection area between the connecting portion 220-1a and the first conductivity type semiconductor layer 111, thereby extending the main extension portion 220-1b. Can increase the injection current.
제3 전류 차단층(270)은 하부 연장부(220-1) 아래 위치할 수 있다. 도 8 및 도 10을 참조하면, 제3 전류 차단층(270)은 서로 이격된 복수의 도트를 포함할 수 있다. 제3 전류 차단층(270)의 폭은 하부 연장부(220-1), 구체적으로 메인 연장부(220-1b)의 폭보다 클 수 있다. 그에 따라 제3 전류 차단층(270)은 메인 연장부(220-1b)가 제1 도전형 반도체층(111)에 접속되는 것을 제한 할 수 있다. 메인 연장부(220-1b)는 제3 전류 차단층(270)에 의해 불연속적으로 상기 제1 도전형 반도체층(111)에 접속될 수 있다. 즉, 메인 연장부(220-1b)는 상기 복수의 도트들 사이의 영역에서만 제1 도전형 반도체층(111)에 접속될 수 있다. 각각의 도트 사이의 이격 거리를 제어하여, 하부 연장부(220-1)가 제1 도전형 반도체층(111)에 접속되는 거리를 제어할 수 있다. 각 도트 사이의 거리는 특별히 제한되지 않으며, 다양하게 설정될 수 있다. 예를 들어, 각 도트 사이의 거리는 동일하게 설정될 수 있다. The third current blocking layer 270 may be located below the lower extension 220-1. 8 and 10, the third current blocking layer 270 may include a plurality of dots spaced apart from each other. The width of the third current blocking layer 270 may be greater than the width of the lower extension part 220-1, specifically, the main extension part 220-1b. Accordingly, the third current blocking layer 270 may limit the main extension portion 220-1b from being connected to the first conductive semiconductor layer 111. The main extension part 220-1b may be connected to the first conductivity type semiconductor layer 111 discontinuously by the third current blocking layer 270. That is, the main extension part 220-1b may be connected to the first conductivity type semiconductor layer 111 only in a region between the plurality of dots. The distance between each dot may be controlled to control the distance between the lower extension part 220-1 and the first conductivity type semiconductor layer 111. The distance between each dot is not particularly limited and may be variously set. For example, the distance between each dot may be set the same.
제3 전류 차단층(270)은 제1 접속 패드(220)를 통해 주입되는 전류가 하부 연장부(220-1), 구체적으로 메인 연장부(220-1b)의 말단까지 전달될 수 있게 하여, 넓은 영역으로 전류가 주입되도록 할 수 있다. 다만, 메인 연장부(220-1b)의 말단에는 제3 전류 차단층(270)이 배치되지 않는다. 이는 메인 연장부(220-1b)의 말단이 제1 도전형 반도체층(111)과 접속되어 상부 연장부(130-1) 또는 제2 접속 패드(130)쪽으로 전류가 원활하게 주입되게 하기 위한 것이다.The third current blocking layer 270 allows the current injected through the first connection pad 220 to be delivered to the lower extension part 220-1, specifically, to the end of the main extension part 220-1b, The current can be injected into a wide area. However, the third current blocking layer 270 is not disposed at the end of the main extension part 220-1b. This is for the terminal of the main extension part 220-1b to be connected to the first conductivity type semiconductor layer 111 so that a current can be smoothly injected into the upper extension part 130-1 or the second connection pad 130. .
도 11 및 12는 본 발명의 또 다른 실시에에 따른 발광 소자를 설명하기 위한 평면도들이다. 구체적으로, 도 11은 본 실시예에 따른 발광 소자의 평면도를 나타내고, 도 12는 도 11의 영역 β를 확대 도시한 것이다.11 and 12 are plan views illustrating light emitting devices according to still another exemplary embodiment of the present invention. Specifically, FIG. 11 is a plan view of the light emitting device according to the present embodiment, and FIG. 12 is an enlarged view of the region β of FIG.
본 실시예에 따른 발광 소자는 도 8 내지 10 에 개시된 발광 소자와 대부분의 구성이 동일하며, 반도체 적층(110)의 측면 형상 및 제1 접속 패드(320), 하부 연장부(320-1), 상부 연장부(230-1), 제1 전류 차단층(340)의 형상에 있어서 차이가 존재한다. 이하 동일한 구성에 대한 설명은 생략되며, 그 차이점을 중심으로 기술된다.The light emitting device according to the present exemplary embodiment has the same configuration as that of the light emitting device disclosed in FIGS. 8 to 10, and has a side shape, a first connection pad 320, a lower extension part 320-1, There is a difference in the shape of the upper extension 230-1 and the first current blocking layer 340. Hereinafter, the description of the same configuration will be omitted, and the description will be focused on the differences.
반도체 적층(110)의 측면은 복수의 그루브(groove) (110g)를 포함할 수 있다. 도 11을 참조하면, 발광 소자의 각 측면들(100a 내지 100d) 근처에서, 반도체 적층(110)은 제2 도전형 반도체층(113) 및 활성층(112)을 통해 제1 도전형 반도체층(111)을 노출시키는 노출영역(110c)을 포함할 수 있다. Side surfaces of the semiconductor stack 110 may include a plurality of grooves 110g. Referring to FIG. 11, near each side surface 100a to 100d of the light emitting device, the semiconductor stack 110 is formed of the first conductive semiconductor layer 111 through the second conductive semiconductor layer 113 and the active layer 112. ) May include an exposed area 110c.
노출영역(110c)이 형성됨에 따라, 발광 소자의 측면들(100a 내지 100d)을 따라 활성층(112) 및 제2 도전형 반도체층(113)의 측면이 노출될 수 있다. 또한, 제1 도전형 반도체층(111)의 측면 일부가 노출될 수 있다. 상기 노출된 활성층(112), 제2 도전형 반도체층(113)(및 제1 도전형 반도체층(111))의 측면은 내측으로 함입된 복수의 그루브(110g)들을 포함할 수 있다. 복수의 그루브(110g)들은, 도 11에 도시된 것과 같이, 발광 소자의 각 측면들(100a 내지 100d)을 따라 형성될 수 있다. As the exposed region 110c is formed, side surfaces of the active layer 112 and the second conductivity-type semiconductor layer 113 may be exposed along the side surfaces 100a to 100d of the light emitting device. In addition, a portion of the side surface of the first conductivity type semiconductor layer 111 may be exposed. Side surfaces of the exposed active layer 112 and the second conductive semiconductor layer 113 (and the first conductive semiconductor layer 111) may include a plurality of grooves 110g recessed inwardly. The plurality of grooves 110g may be formed along each side surface 100a to 100d of the light emitting device, as shown in FIG. 11.
복수의 그루브(110g)들은 상기 노출된 활성층(112) 및 제2 도전형 반도체층(113)의 측면을 통해 방출되는 광의 추출 효율을 향상시킬 수 있다. 즉, 복수의 그루브(110g)를 통해 활성층(112) 및 제2 도전형 반도체층(113)의 측면을 통해 방출되는 광의 내부 전반사가 감소될 수 있고, 그에 따라 발광 소자의 전체적인 광 추출 효율이 향상될 수 있다. The plurality of grooves 110g may improve extraction efficiency of light emitted through side surfaces of the exposed active layer 112 and the second conductive semiconductor layer 113. That is, the total internal reflection of light emitted through the side surfaces of the active layer 112 and the second conductive semiconductor layer 113 through the plurality of grooves 110g may be reduced, thereby improving the overall light extraction efficiency of the light emitting device. Can be.
도 12에서 제1 접속 패드(320) 및 제1 전류 차단층(340)의 평면 형상이 확대 도시되어 있다. 도 12를 참조하면, 제1 접속 패드(320)의 테두리는 제1 곡선 영역을 포함한다. 예를 들어, 제1 접속 패드(320)는 두 개의 하부 연장부(320-1)를 사이에 두고 위치하는 두 개의 제1 곡선 영역들(321, 322)을 포함할 수 있다. 여기서, 두 개의 제1 곡선 영역들(321, 322)은 제1 접속 패드(320)가 원형 형상을 갖는 것에 따라, 동일하게 곡률 반경 R1 값을 가질 수 있다. 즉, 제1 곡선 영역들(321, 322)은 1/R1의 곡률을 가질 수 있다.In FIG. 12, the planar shape of the first connection pad 320 and the first current blocking layer 340 is enlarged. Referring to FIG. 12, the edge of the first connection pad 320 includes a first curved area. For example, the first connection pad 320 may include two first curved areas 321 and 322 positioned with two lower extensions 320-1 interposed therebetween. Here, the two first curved areas 321 and 322 may have the same radius of curvature R 1 as the first connection pad 320 has a circular shape. That is, the first curved areas 321 and 322 may have a curvature of 1 / R 1 .
제1 전류 차단층(340)은 제1 접속 패드(320)와 제1 도전형 반도체층(111) 사이에 개재되며, 제2 곡선 영역(341)을 포함할 수 있다. 도 12에 도시된 것과 같이, 제1 전류 차단층(340)이 제1 접속 패드(320)와 유사하게 원형의 평면 형상을 가지므로, 제2 곡선 영역(341)은 R2 값의 단일의 곡률 반경을 가질 수 있다. 이때, 상대적으로 외측에 위치하는 제1 곡선 영역(321, 322)의 곡률 반경 R1 값이 상대적으로 내측에 위치하는 제2 곡선 영역(341)의 곡률 반경 R2 값보다 클 수 있다.The first current blocking layer 340 is interposed between the first connection pad 320 and the first conductivity type semiconductor layer 111 and may include a second curved region 341. As shown in FIG. 12, since the first current blocking layer 340 has a circular planar shape similar to the first connection pad 320, the second curved area 341 has a single curvature of R 2 values. May have a radius. In this case, the radius of curvature R 1 of the first curved regions 321 and 322 located relatively outside may be greater than the radius of curvature R 2 of the second curved region 341 located relatively inside.
제1 곡선 영역들(321, 322)과 제2 곡선 영역(341) 사이의 간격(G1)은 균일하게 유지될 수 있다. 이에 따라, 제1 전류 차단층(340)에 의해 정의되는, 제1 접속 패드(320)와 제1 도전형 반도체층(111)이 접하는 영역의 폭(G1)이 균일하게 형성될 수 있다. 이를 통해, 제1 접속 패드(320)를 통해 주입되는 전류의 균일한 분배가 이루어 질 수 있다. The gap G1 between the first curved areas 321 and 322 and the second curved area 341 may be kept uniform. Accordingly, the width G1 of the region where the first connection pad 320 and the first conductive semiconductor layer 111 contact each other, defined by the first current blocking layer 340, may be uniformly formed. Through this, uniform distribution of the current injected through the first connection pad 320 may be achieved.
하부 연장부(320-1)는 복수로 형성될 수 있다. 도 11 및 도 12를 참조하면, 두 개의 하부 연장부(320-1)들이 제1 접속 패드(320)로부터 연장되어 발광 소자의 제4 측면(100d)에서 제2 측면(100b)으로 연장되는 것이 개시되어 있다. 다만, 하부 연장부(320-1)들의 형상 및 개수가 도 11 및 도 12에 개시된 것으로 제한되는 것은 아니며, 본 발명의 목적 범위에서 다양하게 변경될 수 있다. The lower extension part 320-1 may be formed in plural. 11 and 12, two lower extensions 320-1 extend from the first connection pad 320 to extend from the fourth side 100d to the second side 100b of the light emitting device. Is disclosed. However, the shape and number of the lower extensions 320-1 are not limited to those disclosed in FIGS. 11 and 12, and may be variously changed in the scope of the present invention.
각각의 하부 연장부들(320-1)은 연결부(320-1a) 및 메인 연장부(320-1b)를 포함할 수 있다. 연결부(320-1a)는 메인 연장부(320-1b)를 제1 접속 패드(320)에 연결할 수 있다. 도 12에 개시된 연결부(320-1a)의 평면 형상을 참조하면, 연결부(320-1a)의 테두리는 제3 곡선 영역(321-1)을 포함할 수 있다. 이때, 제3 곡선 영역(321-1)은 곡률 반경 R3 값을 가질 수 있다. Each of the lower extensions 320-1 may include a connection portion 320-1a and a main extension portion 320-1b. The connection part 320-1a may connect the main extension part 320-1b to the first connection pad 320. Referring to the planar shape of the connector 320-1a disclosed in FIG. 12, the edge of the connector 320-1a may include a third curved area 321-1. In this case, the third curved area 321-1 may have a radius of curvature R 3 .
연결부(320-1a)가 제3 곡선 영역(321-1)을 포함하는 것에 따라, 연결부(320-1a)의 폭(G2)은 제1 접속 패드(320)로부터 멀어질수록 감소할 수 있다. 다만, 제1 접속 패드(320)에 인접하는 연결부(320-1a)의 폭(G2)은 제1 곡선 영역(321, 322)과 제2 곡선 영역(341) 사이의 간격(G1)보다 크게 형성될 수 있다. 그에 따라, 제1 접속 패드(320)를 통해 주입되는 전류 중 비교적 큰 비율이, 비교적 큰 넓이를 갖는 연결부(320-1a) 쪽으로 주입될 수 있다.As the connection part 320-1a includes the third curved area 321-1, the width G2 of the connection part 320-1a may decrease as the distance from the first connection pad 320 increases. However, the width G2 of the connection part 320-1a adjacent to the first connection pad 320 is larger than the gap G1 between the first curved areas 321 and 322 and the second curved area 341. Can be. Accordingly, a relatively large proportion of the current injected through the first connection pad 320 may be injected toward the connection portion 320-1a having a relatively large area.
여기서, R3 값은 R1 값 및 R2 값에 비해 작게 형성될 수 있다. 즉, 제3 곡선 영역(321-1)은 제1 곡선 영역(321, 322) 및 제2 곡선 영역(341)에 비해 굽은 정도가 더 클 수 있다. 여기서, R3 값이 R1 값이나 R2 값보다 크다면, 제1 접속 패드(320)에 인접하는 연결부(320-1a)의 폭이 상대적으로 매우 커지게 된다. 즉, 연결부(320-1a)의 평면 영역이 상대적으로 매우 넓어지게 질 수 있다. 이는, 더 넓은 노출 영역(100a, 100b)을 요구하게 되며, 그에 따라 발광 영역이 감소하여 발광 소자의 출력을 감소시킬 수 있다.Here, the R 3 value may be formed smaller than the R 1 value and the R 2 value. That is, the third curved area 321-1 may have a greater degree of bending than the first curved areas 321 and 322 and the second curved area 341. Here, when the value of R 3 is greater than the value of R 1 or R 2 , the width of the connection part 320-1a adjacent to the first connection pad 320 becomes relatively large. That is, the planar area of the connection part 320-1a may be relatively widened relatively. This requires a wider exposure area 100a, 100b, whereby the light emitting area can be reduced to reduce the output of the light emitting device.
메인 연장부(320-1b)의 일단은 상기 연결부(320-1a)에 접속된다. 메인 연장부(320-1b)는 직선 영역 및 상기 직선 영역과 연결부(320-1a) 사이에 위치하는 곡선 영역을 포함할 수 있다. 메인 연장부(320-1b)의 폭(G3)은 상기 제1 곡선 영역(321, 322) 및 제2 곡선 영역(341) 사이의 간격(G1)보다 크거나 같을 수 있다.One end of the main extension part 320-1b is connected to the connection part 320-1a. The main extension part 320-1b may include a straight area and a curved area positioned between the straight area and the connection part 320-1a. The width G3 of the main extension part 320-1b may be greater than or equal to the gap G1 between the first curved areas 321 and 322 and the second curved area 341.
상부 연장부(230-1)는 제2 접속 패드(230)로부터 연장되며, 복수로 형성될 수 있다. 도 11을 참조하면, 제2 접속 패드(230)로부터 연장된 세 개의 상부 연장부(230-1)들이 도시되어 있다. 상부 연장부(230-1)들은 대체로 발광 소자의 제2 측면(100b)으로부터 제4 측면(100d) 방향으로 연장될 수 있다. 이때, 두 개의 상부 연장부(230-1)들은 하부 연장부(320-1)들 및 제1 접속 패드(320)를 감싸는 형상을 가질 수 있으며, 다른 하나의 상부 연장부(230-1)는 두 개의 하부 연장부(320-1)들 사이에 위치할 수 있다. 도 11에 개시된 것과 같은 제1 접속 패드(320), 하부 연장부(320-1)들, 제2 접속 패드(230) 및 상부 연장부(230-1)들의 배치를 통해, 전류가 수평 방향으로 원활하게 분산될 수 있다.The upper extension 230-1 extends from the second connection pad 230 and may be formed in plural. Referring to FIG. 11, three upper extensions 230-1 extending from the second connection pad 230 are shown. The upper extensions 230-1 may generally extend from the second side surface 100b of the light emitting device toward the fourth side surface 100d. In this case, the two upper extensions 230-1 may have a shape surrounding the lower extensions 320-1 and the first connection pad 320, and the other upper extension 230-1 is formed. It may be located between two lower extensions 320-1. Through the arrangement of the first connection pads 320, the lower extensions 320-1, the second connection pads 230, and the upper extensions 230-1 as shown in FIG. 11, the current flows in the horizontal direction. It can be distributed smoothly.
도 13 및 14는 본 발명의 또 다른 실시에에 따른 발광 소자를 설명하기 위한 평면도들이다. 구체적으로, 도 13은 본 실시예에 따른 발광 소자의 평면도를 나타내고, 도 14는 도 13의 영역 γ를 확대 도시한 것이다.13 and 14 are plan views illustrating light emitting devices according to still another exemplary embodiment of the present invention. Specifically, FIG. 13 is a plan view of the light emitting device according to the present embodiment, and FIG. 14 is an enlarged view of the region γ in FIG.
본 실시예에 따른 발광 소자는 도 8 내지 도 10에 개시된 발광 소자와 대부분의 구성이 동일하며, 다만 노출 영역, 제1 접속 패드(420), 하부 연장부(420-1), 제1 전류 차단층(440) 및 상부 연장부(330-1)의 형상에 있어서 다소 차이가 존재한다. 또한, 본 실시예에 따른 발광 소자는 제3 전류 차단층을 포함하지 않는다. 이하 동일한 구성에 대한 설명은 생략하며, 그 차이점을 중심으로 기술 된다. The light emitting device according to the present embodiment has the same configuration as that of the light emitting device disclosed in FIGS. 8 to 10, except that the exposed area, the first connection pad 420, the lower extension part 420-1, and the first current blocking device are provided. There are some differences in the shape of layer 440 and top extension 330-1. In addition, the light emitting device according to the present embodiment does not include the third current blocking layer. Hereinafter, the description of the same configuration will be omitted, and will be described based on the difference.
노출 영역(110a, 110b)은 제2 도전형 반도체층(113) 및 활성층(112)을 통해 제1 도전형 반도체층(111)을 노출시킬 수 있다. 도 13을 참조하면, 제1 접속 패드(420)를 위한 노출 영역(110a)은 발광 소자의 제1 측면(100a)과 제4 측면(100d)이 만나는 영역에 인접하여 위치하며, 하부 연장부(420-1)를 위한 노출 영역(110b)은 제1 측면(100a)에 인접하여 위치할 수 있다.The exposed regions 110a and 110b may expose the first conductive semiconductor layer 111 through the second conductive semiconductor layer 113 and the active layer 112. Referring to FIG. 13, the exposed area 110a for the first connection pad 420 is positioned adjacent to an area where the first side surface 100a and the fourth side surface 100d of the light emitting device meet, and the lower extension portion ( The exposed area 110b for the 420-1 may be located adjacent to the first side surface 100a.
제1 접속 패드(420)는 노출 영역(100a)을 통해 제1 도전형 반도체층(111)에 접속될 수 있다. 제1 접속 패드(420)의 테두리는 직선 영역 및 제1 곡선 영역(421)을 포함할 수 있다. 예를 들어, 도 14에 개시된 제1 접속 패드(420)의 평면 형상을 참조하면, 두 개의 제1 곡선 영역(421)들이 노출 영역(110a) 형성과정에서 노출되는 반도체 적층(110)의 측면에 인접하여 위치할 수 있다. 각각의 제1 곡선 영역(421)은 곡률 반경 R1 값을 가지며, 직선 영역을 연결할 수 있다. The first connection pad 420 may be connected to the first conductivity type semiconductor layer 111 through the exposure area 100a. The edge of the first connection pad 420 may include a straight region and a first curved region 421. For example, referring to the planar shape of the first connection pad 420 illustrated in FIG. 14, two first curved regions 421 may be formed on a side surface of the semiconductor stack 110 exposed during the formation of the exposed region 110a. It may be located adjacently. Each of the first curved regions 421 has a radius of curvature R 1 and may connect straight regions.
제1 전류 차단층(440)은 제1 접속 패드(420)와 제1 도전형 반도체층(111) 사이에 개재되며, 제1 전류 차단층(440)의 테두리는 직선 영역 및 제2 곡선 영역(441)을 포함할 수 있다. 제2 곡선 영역(441)은 곡률 반경 R2 값을 가지며, 제1 곡선 영역(421) 내측에 위치할 수 있다. 구체적으로, 제1 곡선 영역(421)과 제2 곡선 영역(441)은 동일한 중심을 공유하며, 제1 곡선 영역(421)은 제2 곡선 영역(441)과 제1 곡선 영역(421)을 통해 형성되는 부채꼴의 내부에 위치할 수 있다. 즉, 제2 곡선 영역은, 제1 곡선 영역과 제1 곡선 영역의 양단과 상기 중심을 연결하는 가상의 직선에 의해 형성되는 영역 내에 위치할 수 있다. 여기서, R2 값은 R1 값보다 작다. 또한, 제1 곡선 영역(421)과 제2 곡선 영역(441) 사이의 간격(G1)은 균일하게 유지될 수 있다. 또한, 제1 곡선 영역(421)과 제2 곡선 영역(441) 사이의 간격(G1)은 제1 접속 패드(420)의 직선 영역과 제1 전류 차단층(440)의 직선 영역 사이의 간격과 동일할 수 있다. 이에 따라, 제1 전류 차단층(440)에 의해 정의되는, 제1 접속 패드(420)와 제1 도전형 반도체층(111)이 접하는 영역의 폭이 균일하게 형성될 수 있다. 특히, 노출된 반도체 적층(110)과 인접한 부분에서, 제1 접속 패드(420)와 제1 도전형 반도체층(111)이 접하는 영역의 폭이 균일하게 형성될 수 있다. 이를 통해, 제1 접속 패드(420)를 통해 주입되는 전류의 균일한 분배가 이루어 질 수 있다.The first current blocking layer 440 is interposed between the first connection pad 420 and the first conductive semiconductor layer 111, and the edges of the first current blocking layer 440 have a straight region and a second curved region ( 441). The second curved area 441 has a radius of curvature R 2 and may be located inside the first curved area 421. In detail, the first curved area 421 and the second curved area 441 share the same center, and the first curved area 421 is formed through the second curved area 441 and the first curved area 421. It may be located inside the fan shape to be formed. That is, the second curved area may be located in an area formed by an imaginary straight line connecting the first curved area, both ends of the first curved area, and the center. Here, the R 2 value is smaller than the R 1 value. In addition, the gap G1 between the first curved area 421 and the second curved area 441 may be maintained uniformly. In addition, the interval G1 between the first curved region 421 and the second curved region 441 is equal to the interval between the linear region of the first connection pad 420 and the linear region of the first current blocking layer 440. May be the same. Accordingly, the width of the region defined by the first current blocking layer 440 and the first connection pad 420 and the first conductive semiconductor layer 111 may be uniformly formed. In particular, in a portion adjacent to the exposed semiconductor stack 110, a width of a region where the first connection pad 420 and the first conductive semiconductor layer 111 contact each other may be uniformly formed. Through this, uniform distribution of the current injected through the first connection pad 420 may be achieved.
하부 연장부(420-1)는 발광 소자의 제1 측면(100a)을 따라 형성된 노출 영역(110b)에서, 제1 도전형 반도체층(111)에 접속될 수 있다. 하부 연장부(420-1)는 제1 접속 패드(420)로부터 발광 소자의 제1 측면(100a)을 따라 연장될 수 있다.The lower extension part 420-1 may be connected to the first conductivity type semiconductor layer 111 in the exposed region 110b formed along the first side surface 100a of the light emitting device. The lower extension part 420-1 may extend from the first connection pad 420 along the first side surface 100a of the light emitting device.
하부 연장부(420-1)는 연결부(420-1a) 및 메인 연장부(420-1b)를 포함할 수 있다. 연결부(420-1a)는 메인 연장부(420-1b)를 제1 접속 패드(420)와 연결할 수 있다. 도 14에 도시된 연결부(420-1a)의 평면 형상을 참조하면, 연결부(420-1a)의 테두리는 제3 곡선 영역(421-1)을 포함할 수 있다. 제3 곡선 영역(421-1)은 곡률 반경 R3 값을 가질 수 있다. 다만, 도 8 및 도 12에 개시된 실시예와는 달리, 본 실시예에 따른 연결부(420-1a)는 단일의 제3 곡선 영역(421-1)을 포함하며, 단일의 제3 곡선 영역(421-1)은 노출된 반도체 적층(110)의 측면에 인접하여 배치된다. 따라서, 이에 제한되는 것은 아니지만, 본 실시예에 따른 연결부(420-1a)의 폭(G2) 또는 넓이는 도 8 및 도 12에 개시된 연결부(420-1a)의 폭 또는 넓이와 비교하여 더 작을 수 있다. 따라서, 본 실시예에 따른 발광 소자는 절연층(465)이 비교적 작은 폭 또는 넓이를 갖는 연결부(420-1a) 아래 배치되지 않아, 연결부(420-1a)가 전체적으로 제1 도전형 반도체층(111)에 접속될 수 있다.The lower extension part 420-1 may include a connection part 420-1a and a main extension part 420-1b. The connection part 420-1a may connect the main extension part 420-1b with the first connection pad 420. Referring to the planar shape of the connector 420-1a illustrated in FIG. 14, the edge of the connector 420-1a may include a third curved area 421-1. The third curved area 421-1 may have a radius of curvature R 3 . However, unlike the embodiment disclosed in FIGS. 8 and 12, the connection part 420-1a according to the present embodiment includes a single third curved area 421-1 and a single third curved area 421. -1) is disposed adjacent the side of the exposed semiconductor stack 110. Therefore, the present invention is not limited thereto, but the width G2 or the width of the connection portion 420-1a according to the present embodiment may be smaller than the width or width of the connection portion 420-1a disclosed in FIGS. 8 and 12. have. Accordingly, in the light emitting device according to the present exemplary embodiment, since the insulating layer 465 is not disposed under the connection portion 420-1a having a relatively small width or width, the connection portion 420-1a is entirely formed of the first conductive semiconductor layer 111. ) Can be connected.
연결부(420-1a)가 제3 곡선 영역(421-1)을 포함하는 것에 따라, 연결부(420-1a)의 폭(G2)은 제1 접속 패드(420)로부터 멀어질수록 감소할 수 있다. 다만, 제1 접속 패드(420)에 인접하는 연결부(420-1a)의 폭(G2)은 제1 곡선 영역(421)과 제2 곡선 영역(441) 사이의 간격(G1)보다 크게 형성될 수 있다. 그에 따라, 제1 접속 패드(420)를 통해 주입되는 전류 중 비교적 큰 비율이, 비교적 큰 넓이를 갖는 연결부(420-1a) 쪽으로 주입될 수 있다.As the connection part 420-1a includes the third curved area 421-1, the width G2 of the connection part 420-1a may decrease as the distance from the first connection pad 420 increases. However, the width G2 of the connection portion 420-1a adjacent to the first connection pad 420 may be greater than the gap G1 between the first curved area 421 and the second curved area 441. have. Accordingly, a relatively large ratio of currents injected through the first connection pads 420 may be injected toward the connection portion 420-1a having a relatively large area.
여기서, R3 값은 R1 값 및 R2 값에 비해 작게 형성될 수 있다. 즉, 제3 곡선 영역(421-1)은 제1 곡선 영역(421) 및 제2 곡선 영역(441)에 비해 굽은 정도가 더 클 수 있다. 여기서, R3 값이 R1 값이나 R2 값보다 크다면, 제1 접속 패드(420)에 인접하는 연결부(420-1a)의 폭(G2)이 상대적으로 매우 커지게 된다. 즉, 연결부(420-1a)의 평면 영역이 상대적으로 매우 넓어지게 질 수 있다. 이는, 더 넓은 노출 영역(100a, 100b)을 요구하게 되며, 그에 따라 발광 영역이 감소하여 발광 소자의 출력을 감소시킬 수 있다.Here, the R 3 value may be formed smaller than the R 1 value and the R 2 value. That is, the third curved area 421-1 may have a greater degree of bending than the first curved area 421 and the second curved area 441. Here, when the value of R 3 is greater than the value of R 1 or R 2 , the width G2 of the connection portion 420-1a adjacent to the first connection pad 420 becomes relatively large. That is, the planar area of the connection portion 420-1a may become relatively wider. This requires a wider exposure area 100a, 100b, whereby the light emitting area can be reduced to reduce the output of the light emitting device.
메인 연장부(420-1b)의 일단은 상기 연결부(420-1a)에 접속된다. 메인 연장부(420-1b)의 폭(G3)은 상기 제1 곡선 영역(421) 및 제2 곡선 영역(441) 사이의 간격(G1)보다 크거나 같을 수 있다.One end of the main extension part 420-1b is connected to the connection part 420-1a. The width G3 of the main extension part 420-1b may be greater than or equal to the gap G1 between the first curved area 421 and the second curved area 441.
상부 연장부(330-1)는 제2 접속 패드(330)로부터 연장될 수 있다. 도 13을 참조하면, 상부 연장부(330-1)는 제2 접속 패드(330)로부터 발광 소자의 제 4측면(100d) 방향으로 연장될 수 있다. 상부 연장부(330-1)와 하부 연장부(420-1)는 서로 대향하여 배치될 수 있으며, 이에 따라 주입되는 전류가 발광 소자의 전 영역으로 넓게 분산될 수 있다.The upper extension 330-1 may extend from the second connection pad 330. Referring to FIG. 13, the upper extension part 330-1 may extend from the second connection pad 330 in the direction of the fourth side surface 100d of the light emitting device. The upper extension 330-1 and the lower extension 420-1 may be disposed to face each other, and thus the injected current may be widely distributed to the entire region of the light emitting device.
도 15 및 16은 본 발명의 또 다른 실시예에 따른 발광 소자를 설명하기 위한 평면도들이다. 구체적으로, 도 15는 본 실시예에 따른 발광 소자의 평면도를 나타내고, 도 16은 도 15의 영역 λ를 확대 도시한 것이다.15 and 16 are plan views illustrating light emitting devices according to still another exemplary embodiment of the present invention. Specifically, FIG. 15 is a plan view of the light emitting device according to the present embodiment, and FIG. 16 is an enlarged view of the region λ of FIG.
본 실시예에 따른 발광 소자는 도 8 내지 도 10에 개시된 발광 소자와 대부분의 구성이 동일하며, 다만, 서로 직 간접적으로 연결되는 복수의 발광셀들을 포함하는 것과, 제1 접속 패드(520), 하부 연장부(520-1), 제1 전류 차단층(540), 제2 접속 패드(430), 상부 연장부(430-1)의 형상에 있어서 다소 차이가 존재한다. 이하 동일한 구성에 대한 설명은 생략하며, 그 차이점을 중심으로 기술 된다. The light emitting device according to the present embodiment has the same configuration as that of the light emitting device disclosed in FIGS. 8 to 10, but includes a plurality of light emitting cells directly or indirectly connected to each other, the first connection pad 520, There are some differences in the shape of the lower extension 520-1, the first current blocking layer 540, the second connection pad 430, and the upper extension 430-1. Hereinafter, the description of the same configuration will be omitted, and will be described based on the difference.
도 15를 참조하면, 본 실시예에 따른 발광 소자는 제1 내지 제3 발광셀(C1, C2, C3), 제4 내지 제6 발광셀(D1, D2, D3) 및 제7 내지 제9 발광셀(E1, E2, E3)을 포함할 수 있다. 또한, 발광 소자는 제1 접속 패드(520) 및 제2 접속 패드(430)를 포함하며, 상부 연장부(430-1a, 430-1b)들과 하부 연장부(520-1)들을 포함할 수 있다. 상부 연장부(430-1)는 보조 상부 연장부(430-1a) 및 주 상부 연장부(430-1b)로 구분될 수 있다.Referring to FIG. 15, the light emitting device according to the present embodiment may include first to third light emitting cells C1, C2 and C3, fourth to sixth light emitting cells D1, D2 and D3, and seventh to ninth light emission. Cells E1, E2, E3. In addition, the light emitting device may include a first connection pad 520 and a second connection pad 430, and may include upper extensions 430-1a and 430-1b and lower extensions 520-1. have. The upper extension 430-1 may be divided into an auxiliary upper extension 430-1a and a main upper extension 430-1b.
제1 내지 제3 발광셀(C1, C2, C3)은 분리 홈(115)에 의해 제4 내지 제6 발광셀(D1, D2, D3)로부터 분리될 수 있다. 또한, 제4 내지 제6 발광셀(D1, D2, D3)은 분리 홈(117)에 의해 제7 내지 제9 발광셀(E1, E2, E3)로부터 분리될 수 있다. 이에 따라, 제1 발광셀(C1), 제2 발광셀(C2)과 제3 발광셀(C3)은 제1 도전형 반도체층(111a)을 공유하며, 제4 발광셀(D1), 제5 발광셀(D2)과 제6 발광셀(D3)은 제1 도전형 반도체층(111b)을 공유할 수 있다. 또한, 제7 발광셀(E1), 제8 발광셀(E2)과 제9 발광셀(E3)은 제1 도전형 반도체층(111c)을 공유할 수 있다. 분리 홈(115, 117)은 아이솔레이션 공정에 의해 형성되며, 분리 홈(115, 117)에서 기판(101)이 노출될 수 있다. The first to third light emitting cells C1, C2, and C3 may be separated from the fourth to sixth light emitting cells D1, D2, and D3 by the separating grooves 115. In addition, the fourth to sixth light emitting cells D1, D2, and D3 may be separated from the seventh to ninth light emitting cells E1, E2, and E3 by the separating grooves 117. Accordingly, the first light emitting cell C1, the second light emitting cell C2, and the third light emitting cell C3 share the first conductive semiconductor layer 111a, and the fourth light emitting cell D1 and the fifth light emitting cell C1. The light emitting cell D2 and the sixth light emitting cell D3 may share the first conductivity type semiconductor layer 111b. In addition, the seventh light emitting cell E1, the eighth light emitting cell E2, and the ninth light emitting cell E3 may share the first conductivity-type semiconductor layer 111c. The separation grooves 115 and 117 are formed by an isolation process, and the substrate 101 may be exposed in the separation grooves 115 and 117.
이와 달리, 제1 발광셀(C1)과 제2 발광셀(C2), 제4 발광셀(D1)과 제5 발광셀(D2), 그리고 제7 발광셀(E1)과 제8 발광셀(E2)은 제1 도전형 반도체층(111a, 111b, 111c)을 노출시키는 메사 홈(113a)을 형성하는 메사 식각 공정에 의해 각각 분리될 수 있다. 또한, 제2 발광셀(C2)과 제3 발광셀(C3), 제5 발광셀(D2)과 제6 발광셀(D3), 그리고 제8 발광셀(E2)과 제9 발광셀(E3)은 제1 도전형 반도체층(111a, 111b, 111c)을 노출시키는 메사 홈(113b)을 형성하는 메사 식각 공정에 의해 각각 분리될 수 있다. Alternatively, the first light emitting cell C1 and the second light emitting cell C2, the fourth light emitting cell D1 and the fifth light emitting cell D2, and the seventh light emitting cell E1 and the eighth light emitting cell E2. ) May be separated by a mesa etching process for forming mesa grooves 113a exposing the first conductivity type semiconductor layers 111a, 111b, and 111c. In addition, the second light emitting cell C2 and the third light emitting cell C3, the fifth light emitting cell D2 and the sixth light emitting cell D3, and the eighth light emitting cell E2 and the ninth light emitting cell E3. The silver may be separated by a mesa etching process of forming a mesa groove 113b exposing the first conductivity type semiconductor layers 111a, 111b, and 111c.
즉, 제1 도전형 반도체층(111a, 111b, 111c), 활성층(112) 및 제2 도전형 반도체층(113)을 포함하는 반도체 적층(110)은 메사 홈(113a, 113b) 및 분리 홈(115, 117)에 의해 제1 내지 제9 발광셀들(C1, C2, C3, D1, D2, D3, E1, E2, E3)로 분리 될 수 있다.That is, the semiconductor stack 110 including the first conductivity type semiconductor layers 111a, 111b, and 111c, the active layer 112, and the second conductivity type semiconductor layer 113 may include mesa grooves 113a and 113b and separation grooves ( The first to ninth light emitting cells C1, C2, C3, D1, D2, D3, E1, E2, and E3 may be separated by the 115 and 117.
제1 발광셀(C1)과 제3 발광셀(C3)은 제1 접속 패드(520)와 제2 접속 패드(430)를 연결한 가상선을 기준으로 대칭되는 형상을 가질 수 있다. 제4 내지 제6 발광셀들(D1, D2, D3) 각각의 형상은 서로 동일할 수 있다. 또한, 제7 발광셀(E1)과 제9 발광셀(E3)은 제1 접속 패드(520)와 제2 접속 패드(430)를 연결한 가상선을 기준으로 서로 대칭되는 형상을 가질 수 있다.The first light emitting cell C1 and the third light emitting cell C3 may have a symmetrical shape with respect to an imaginary line connecting the first connection pad 520 and the second connection pad 430. Each of the fourth to sixth light emitting cells D1, D2, and D3 may have the same shape. In addition, the seventh light emitting cell E1 and the ninth light emitting cell E3 may have symmetrical shapes with respect to an imaginary line connecting the first connection pad 520 and the second connection pad 430.
여기서, 제2 접속 패드(430)가 형성된 제2 발광셀(C2) 및 제1 접속 패드(520)의 형성과 관련된 제8 발광셀(E2)은 다른 발광셀들과 그 형상에 있어서 비교적 큰 차이를 갖는다. 제1 접속 패드(520)는 발광 소자의 제 4측면(100d)에 인접하여 배치되고, 제2 접속 패드(430)는 제1 접속 패드(520)에 대향하여 제2 측면(100b) 근처에 배치될 수 있다.Here, the second light emitting cell C2 on which the second connection pad 430 is formed and the eighth light emitting cell E2 associated with the formation of the first connection pad 520 are relatively different from other light emitting cells in shape. Has The first connection pad 520 is disposed adjacent to the fourth side surface 100d of the light emitting element, and the second connection pad 430 is disposed near the second side surface 100b opposite to the first connection pad 520. Can be.
제1 접속 패드(520)는 메사 홈(113c) 상에 배치될 수 있다. 즉, 제1 접속 패드(520) 형성을 위해 발광 소자의 제4 측면(100d) 근처의 제8 발광셀(E2)의 하단 일부가 메사 식각되어, 메사 홈(113c)이 형성될 수 있다. 여기서 메사홈(113c)은 앞서 개시된 실시예들에서 노출 영역(100a)에 대응될 수 있다. 메사 홈(113c)을 통해 반도체 적층(110)의 측면이 노출될 수 있다. 제1 접속 패드(520)는 메사 홈(113c) 내에 배치되어 제1 도전형 반도체층(111c)에 전기적으로 접속될 수 있다. The first connection pad 520 may be disposed on the mesa groove 113c. That is, a portion of the lower end of the eighth light emitting cell E2 near the fourth side surface 100d of the light emitting device may be mesa-etched to form the first connection pad 520, so that the mesa groove 113c may be formed. The mesa groove 113c may correspond to the exposed area 100a in the above-described embodiments. Side surfaces of the semiconductor stack 110 may be exposed through the mesa groove 113c. The first connection pad 520 may be disposed in the mesa groove 113c and electrically connected to the first conductive semiconductor layer 111c.
상기 제1 접속 패드(520) 하부에 제1 전류 차단층(540)이 배치될 수 있다. 제1 전류 차단층(540)은 제1 접속 패드(520)와 제1 도전형 반도체층(111c) 사이에 배치되어, 제1 도전형 반도체층(111c)으로 주입되는 전류의 수평 분산을 원활하게 할 수 있다. 제1 전류 차단층(540)(111c)의 넓이는 제1 접속 패드(520)보다 작을 수 있다. 즉, 제1 전류 차단층(540)의 가로 및 세로 폭은 제1 접속 패드(520)의 그것보다 작으며, 따라서 제1 접속 패드(520)의 일부 영역에 위치할 수 있다. 예를 들어, 제1 전류 차단층(540)의 넓이는 제1 접속 패드(520)의 넓이의 90% 이하로 제한될 수 있다. The first current blocking layer 540 may be disposed under the first connection pad 520. The first current blocking layer 540 is disposed between the first connection pad 520 and the first conductivity type semiconductor layer 111c to smoothly distribute the current injected into the first conductivity type semiconductor layer 111c. can do. The width of the first current blocking layers 540 and 111c may be smaller than that of the first connection pads 520. That is, the horizontal and vertical widths of the first current blocking layer 540 are smaller than those of the first connection pads 520, and thus may be located in some regions of the first connection pads 520. For example, the width of the first current blocking layer 540 may be limited to 90% or less of the width of the first connection pad 520.
절연층(565)이 제1 접속 패드(520)가 배치된 메사 홈(113c)의 측면을 덮을 수 있다. 도 15 및 16에 도시된 바와 같이, 절연층(565)은 메사 홈(113c)의 측면을 덮고, 또한 하부 연장부(520-1)가 지나는 부분에도 형성되어 전체적으로 연결된 하나의 곡선 형상을 가질 수 있다. 하부 연장부(520-1)가 지나는 부분에서, 절연층(565)이 먼저 형성되고, 그 위에 하부 연장부(520-1)가 형성될 수 있다. The insulating layer 565 may cover the side surface of the mesa groove 113c on which the first connection pad 520 is disposed. As shown in FIGS. 15 and 16, the insulating layer 565 may cover a side surface of the mesa groove 113c and may also be formed at a portion through which the lower extension portion 520-1 passes to have a single curved shape. have. In a portion where the lower extension 520-1 passes, the insulating layer 565 may be formed first, and a lower extension 520-1 may be formed thereon.
제1 내지 6 발광셀들(C1, C2, C3, D1, D2, D3)에서, 하부 연장부(520-1)들의 일단은 분리 홈(115, 117) 내에 배치되는 연결 유닛(520-2)과 전기적으로 연결되고, 타단은 주 상부 연장부(430-1b)와 이격되되, 주 상부 연장부(430-1b)로 둘러 싸여 질 수 있다. 다만, 연결 유닛(520-2) 아래에는 제2 전류 차단층(150)으로부터 연장된 절연층(151)이 위치할 수 있다. 상기 절연층(151)은 분리 홈(115, 117)에서 노출될 수 있는 반도체 적층(110)의 측면을 덮을 수 있고, 그에 따라 연결 유닛(520-2)이 반도체 적층(110)의 측면과 접속되는 것을 방지하여, 발광 소자의 신뢰성을 높일 수 있다.In the first to sixth light emitting cells C1, C2, C3, D1, D2, and D3, one end of the lower extension parts 520-1 is disposed in the separation grooves 115 and 117. It is electrically connected to the other end is spaced apart from the main upper extension (430-1b), it may be surrounded by the main upper extension (430-1b). However, an insulating layer 151 extending from the second current blocking layer 150 may be positioned below the connection unit 520-2. The insulating layer 151 may cover the side surface of the semiconductor stack 110, which may be exposed in the isolation grooves 115 and 117, so that the connection unit 520-2 is connected to the side surface of the semiconductor stack 110. Can be prevented, and the reliability of the light emitting element can be improved.
제7 및 제9 발광셀들(E1, E3)에서, 하부 연장부(520-1)들은 제1 접속 패드(520)에 접속되며 상호 연결된 두 개의 직선 영역을 포함한다. 두 개의 직선 영역은 발광 소자의 가로 방향과 세로 방향에 평행하고, 서로 직교할 수 있다. 가로 방향의 직선 영역이 세로 방향의 직선 영역과 제1 접속 패드(520)를 연결한다. 도 15에 도시된 것처럼, 하부 연장부(520-1)(특히 가로 방향의 직선 영역)의 형성을 위해, 발광 소자의 제 4 측면(100d) 근처의 제 7 내지 제9 발광셀(E1, E2, E3)의 일부 영역이 메사 식각될 수 있다. In the seventh and ninth light emitting cells E1 and E3, the lower extensions 520-1 include two straight regions connected to the first connection pads 520 and connected to each other. The two straight regions may be parallel to the horizontal direction and the vertical direction of the light emitting device, and may be perpendicular to each other. The linear region in the horizontal direction connects the linear region in the vertical direction with the first connection pad 520. As shown in FIG. 15, the seventh to ninth light emitting cells E1 and E2 near the fourth side surface 100d of the light emitting device for forming the lower extension 520-1 (particularly, the horizontal area in the horizontal direction). , Part of E3) may be mesa etched.
제 8 발광셀(E2)에서, 하부 연장부(520-1)의 일단은 제1 접속 패드(520)에 연결되고, 타단은 주 상부 연장부(430-1b)와 이격되되 주 상부 연장부(430-1b)로 둘러 싸여 질 수 있다.In the eighth light emitting cell E2, one end of the lower extension part 520-1 is connected to the first connection pad 520, and the other end is spaced apart from the main upper extension part 430-1b, but the main upper extension part ( 430-1b).
제2 접속 패드(430)는 제2 발광셀(C2) 상에 형성될 수 있다. 제2 접속 패드(430) 하부에 제2 전류 차단층(150)이 위치할 수 있다. 구체적으로, 제2 전류 차단층(150)은 제2 접속 패드(430) 하부에서 투명 전극층(160)과 제2 도전형 반도체층(113) 사이에 개재될 수 있다. 제2 전류 차단층(150)의 폭은 제2 접속 패드(430)의 폭보다 더 클 수 있다. 투명 전극층(160)의 일부는 제2 접속 패드(430) 하부에 위치하며, 제2 전류 차단층(150)을 노출시키는 개구부(160a)를 포함할 수 있다. 개구부(160a)는 원형 형상을 가질 수 있다. 투명 전극층(160)에 개구부(160a)를 형성함으로써, 제2 접속 패드(430)의 접착력이 증대될 수 있다. The second connection pad 430 may be formed on the second light emitting cell C2. The second current blocking layer 150 may be positioned below the second connection pad 430. In detail, the second current blocking layer 150 may be interposed between the transparent electrode layer 160 and the second conductive semiconductor layer 113 under the second connection pad 430. The width of the second current blocking layer 150 may be greater than the width of the second connection pad 430. A portion of the transparent electrode layer 160 may be positioned under the second connection pad 430 and may include an opening 160a exposing the second current blocking layer 150. The opening 160a may have a circular shape. By forming the openings 160a in the transparent electrode layer 160, the adhesive force of the second connection pads 430 may be increased.
한편, 투명 전극층(160) 상에 보조 상부 연장부(430-1a)들 및 주 상부 연장부(430-1b)들이 배치될 수 있다. 보조 상부 연장부(4301-1a)는 제1 내지 제3 발광셀(C1, C2, C3) 상에서 주 상부 연장부(430-1b)들 사이를 전기적으로 연결할 수 있다. 예를 들어, 도 15을 참조하면, 보조 상부 연장부(430-1a)는 제1 발광셀(C1) 상의 주 상부 연장부(430-1b)와 제2 발광셀(C2) 상의 주 상부 연장부(430-1b)를 연결할 수 있다. 이에 따라, 제1 발광셀(C1)과 제2 발광셀(C2)이 전기적으로 연결될 수 있다. Meanwhile, auxiliary upper extensions 430-1a and main upper extensions 430-1b may be disposed on the transparent electrode layer 160. The auxiliary upper extension portions 430-1a may electrically connect between the main upper extensions 430-1b on the first to third light emitting cells C1, C2, and C3. For example, referring to FIG. 15, the auxiliary upper extension 430-1a includes a main upper extension 430-1b on the first light emitting cell C1 and a main upper extension on the second light emitting cell C2. 430-1b may be connected. Accordingly, the first light emitting cell C1 and the second light emitting cell C2 may be electrically connected to each other.
제4 내지 제9 발광셀(D1, D2, D3, E1, E2, E3)에서, 보조 상부 연장부(430-1a)는 주 상부 연장부(430-1b)를 1 내지 제3 발광셀(C1, C2, C3)의 하부 연장부(520-1)와 연결할 수 있다. 보조 상부 연장부(430-1a)는 직선 형상일 수 있으며, 하부 연장부(520-1)와 동일 축 상에 위치할 수 있다. 보조 상부 연장부(430-1a)의 일단은 주 상부 연장부(430-1a)에 연결되고, 타단은 연결 유닛(520-2)에 연결될 수 있다.In the fourth to ninth light emitting cells D1, D2, D3, E1, E2, and E3, the auxiliary upper extension 430-1a uses the main upper extension 430-1b as the first to third light emitting cells C1. It may be connected to the lower extension portion 520-1 of, C2 and C3. The auxiliary upper extension 430-1a may be straight and may be positioned on the same axis as the lower extension 520-1. One end of the auxiliary upper extension 430-1a may be connected to the main upper extension 430-1a, and the other end may be connected to the connection unit 520-2.
주 상부 연장부(430-1b)는 하부 연장부(520-1)의 단부 및 측면 일부를 감싸도록 배치될 수 있다. 따라서, 주 상부 연장부(430-1b)의 일부는 하부 연장부(520-1)의 일측에 배치되고, 또 다른 일부는 하부 연장부(520-1)의 일측에 대향하는 타측에 배치될 수 있다. 주 상부 연장부(430-1b)는 하부 연장부(520-1)를 지나는 직선에 대해 대칭 구조를 가질 수 있다.The main upper extension 430-1b may be disposed to surround a portion of the end and side surfaces of the lower extension 520-1. Accordingly, a part of the main upper extension 430-1b may be disposed on one side of the lower extension 520-1, and another part may be disposed on the other side opposite to one side of the lower extension 520-1. have. The main upper extension 430-1b may have a symmetrical structure with respect to a straight line passing through the lower extension 520-1.
도 15에서, 제1, 4 및 7발광셀(C1, D1, E1)을 제1 그룹, 제2, 5 및 8 발광셀(C2, D2, E2)을 제2 그룹, 그리고 제3, 6 및 9 발광셀(C3, D3, E3)을 제3 그룹으로 정의할 수 있다. 각 그룹 내에서 각각의 발광셀들은 보조 상부 연장부(430-1a) 및 연결 유닛(520-2)를 통해 전기적으로 직렬 연결될 수 있다. 또한 제1 그룹, 제2 그룹 및 제3 그룹은 보조 상부 연장부(430-1a) 및 하부 연장부(520-1)의 가로 방향의 직선 영역을 통해 전기적으로 병렬 연결될 수 있다. In Figure 15, the first, fourth and seventh light emitting cells (C1, D1, E1) are the first group, the second, the 5th and 8th light emitting cells (C2, D2, E2) the second group, and the third, 6 and 9 The light emitting cells C3, D3, and E3 may be defined as a third group. Each of the light emitting cells in each group may be electrically connected in series through the auxiliary upper extension 430-1a and the connection unit 520-2. In addition, the first group, the second group, and the third group may be electrically connected in parallel through a horizontal linear region of the auxiliary upper extension 430-1a and the lower extension 520-1.
도 16을 통해, 제1 접속 패드(520), 제1 전류 차단층(540) 및 하부 연장부(520-1)에 대한 평면도가 확대 도시되어 있다. 도 16을 참조하면 이들의 평면 형상에 대해 검토한다.16, an enlarged plan view of the first connection pad 520, the first current blocking layer 540, and the lower extension 520-1 is shown. With reference to FIG. 16, these planar shapes are examined.
먼저, 제1 접속 패드(520)의 테두리는 직선 영역 및 제1 곡선 영역(541)을 포함할 수 있다. 예를 들어, 도 16에 개시된 제1 접속 패드(520)의 평면 형상을 참조하면, 두 개의 제1 곡선 영역(541)들이 하부 연장부(520-1)를 중심에 두고 서로 대칭되도록 배치되어 있다. 제1 곡선 영역(541)들은 메사 홈(113c) 형성과정에서 노출되는 반도체 적층(110)의 측면에 인접하여 위치할 수 있다. 각각의 제1 곡선 영역(541)은 곡률 반경 R1 값을 가지며, 직선 영역에 연결될 수 있다.First, the edge of the first connection pad 520 may include a straight region and a first curved region 541. For example, referring to the planar shape of the first connection pad 520 disclosed in FIG. 16, two first curved areas 541 are arranged to be symmetrical with respect to the lower extension 520-1. . The first curved regions 541 may be located adjacent to a side surface of the semiconductor stack 110 that is exposed during the formation of the mesa groove 113c. Each first curved region 541 has a radius of curvature R 1 and may be connected to a straight region.
제1 전류 차단층(540)은 제1 접속 패드(520)와 제1 도전형 반도체층(111c) 사이에 개재되며, 제1 전류 차단층(540)의 테두리는 직선 영역 및 제2 곡선 영역(521)을 포함할 수 있다. 제2 곡선 영역(521)은 곡률 반경 R2 값을 가지며, 제1 곡선 영역(541) 내측에 위치할 수 있다. 여기서, R2 값은 R1 값보다 작다. 또한, 제1 곡선 영역(541)과 제2 곡선 영역(521) 사이의 간격(G1)은 균일하게 유지될 수 있다. 또한, 제1 곡선 영역(541)과 제2 곡선 영역(521) 사이의 간격(G1)은 제1 접속 패드(520)의 직선 영역과 제1 전류 차단층(540)의 직선 영역 사이의 간격과 동일할 수 있다. 이에 따라, 제1 전류 차단층(540)에 의해 정의되는, 제1 접속 패드(520)와 제1 도전형 반도체층(111c)이 접하는 영역의 폭이 균일하게 형성될 수 있다. 특히, 노출된 반도체 적층(110)과 인접한 부분에서, 제1 접속 패드(520)와 제1 도전형 반도체층(111c)이 접하는 영역의 폭이 균일하게 형성될 수 있다. 이를 통해, 제1 접속 패드(520)를 통해 주입되는 전류의 균일한 분배가 이루어 질 수 있다.The first current blocking layer 540 is interposed between the first connection pad 520 and the first conductive semiconductor layer 111c, and the edge of the first current blocking layer 540 has a straight region and a second curved region ( 521). The second curved area 521 has a radius of curvature R 2 and may be located inside the first curved area 541. Here, the R 2 value is smaller than the R 1 value. In addition, the gap G1 between the first curved area 541 and the second curved area 521 may be maintained uniformly. In addition, the interval G1 between the first curved region 541 and the second curved region 521 is equal to the interval between the linear region of the first connection pad 520 and the linear region of the first current blocking layer 540. May be the same. Accordingly, the width of the region defined by the first current blocking layer 540 and the first connection pad 520 and the first conductivity type semiconductor layer 111c may be uniformly formed. In particular, in a portion adjacent to the exposed semiconductor stack 110, a width of a region where the first connection pad 520 and the first conductive semiconductor layer 111c contact each other may be uniformly formed. Through this, uniform distribution of the current injected through the first connection pad 520 may be achieved.
각각의 하부 연장부(520-1)들은 연결부(520-1a) 및 메인 연장부(520-1b)를 포함할 수 있다. 연결부(520-1a)는 메인 연장부(520-1b)를 제1 접속 패드(520)에 연결할 수 있다. 도 16에 개시된 연결부(520-1a)의 평면 형상을 참조하면, 연결부(520-1a)의 테두리는 제3 곡선 영역(521-1)을 포함할 수 있다. 이때, 제3 곡선 영역(521-1)은 곡률 반경 R3 값을 가질 수 있다. Each of the lower extensions 520-1 may include a connecting portion 520-1a and a main extension 520-1b. The connection part 520-1a may connect the main extension part 520-1b to the first connection pad 520. Referring to the planar shape of the connector 520-1a disclosed in FIG. 16, the edge of the connector 520-1a may include a third curved area 521-1. At this time, the third curve area (521-1) may have a radius of curvature R 3 values.
연결부(520-1a)가 제3 곡선 영역(521-1)을 포함하는 것에 따라, 연결부(520-1a)의 폭(G2)은 제1 접속 패드(520)로부터 멀어질수록 감소할 수 있다. 다만, 제1 접속 패드(520)에 인접하는 연결부(520-1a)의 폭(G2)은 제1 곡선 영역(541)과 제2 곡선 영역(521) 사이의 간격(G1)보다 크게 형성될 수 있다. 그에 따라, 제1 접속 패드(520)를 통해 주입되는 전류 중 비교적 큰 비율이, 비교적 큰 넓이를 갖는 연결부(520-1a) 쪽으로 주입될 수 있다. 여기서, R3 값은 R1 값 및 R2 값에 비해 작게 형성될 수 있다. As the connection part 520-1a includes the third curved area 521-1, the width G2 of the connection part 520-1a may decrease as the distance from the first connection pad 520 increases. However, the width G2 of the connection portion 520-1a adjacent to the first connection pad 520 may be larger than the gap G1 between the first curved area 541 and the second curved area 521. have. Accordingly, a relatively large proportion of the current injected through the first connection pad 520 may be injected toward the connection portion 520-1a having a relatively large area. Here, the R3 value may be formed smaller than the R1 value and the R2 value.
메인 연장부(520-1b)의 일단은 상기 연결부(520-1a)에 접속된다. 메인 연장부(520-1b)의 폭(G3)은 상기 제1 곡선 영역(541) 및 제2 곡선 영역(521) 사이의 간격(G1)보다 크거나 같을 수 있다.One end of the main extension part 520-1b is connected to the connection part 520-1a. The width G3 of the main extension part 520-1b may be greater than or equal to the gap G1 between the first curved area 541 and the second curved area 521.
도 17 및 18은 본 발명의 또 다른 실시예에 따른 발광 소자를 설명하기 위한 평면도들이다. 구체적으로, 도 17는 본 실시예에 따른 발광 소자의 평면도를 나타내고, 도 18은 도 17의 영역 Χ를 확대 도시한 것이다.17 and 18 are plan views illustrating light emitting devices according to still another exemplary embodiment of the present invention. Specifically, FIG. 17 is a plan view of the light emitting device according to the present embodiment, and FIG. 18 is an enlarged view of the area Χ in FIG.
본 실시예에 따른 발광 소자는 도 8 내지 도 10에 개시된 발광 소자와 대부분의 구성이 동일하며, 다만, 서로 연결되는 복수의 발광셀들을 포함하는 것과, 제1 접속 패드(620), 하부 연장부(620-1), 제1 전류 차단층(640), 제2 접속 패드(530), 상부 연장부(530-1)의 형상에 있어서 다소 차이가 존재한다. 이하 동일한 구성에 대한 설명은 생략하며, 그 차이점을 중심으로 기술 된다. The light emitting device according to the present embodiment has the same configuration as that of the light emitting device disclosed in FIGS. 8 to 10, but includes a plurality of light emitting cells connected to each other, and the first connection pad 620 and the lower extension part. There is a slight difference in the shape of 620-1, the first current blocking layer 640, the second connection pad 530, and the upper extension 530-1. Hereinafter, the description of the same configuration will be omitted, and will be described based on the difference.
도 17을 참조하면, 본 실시예에 따른 발광 소자는 제1 내지 제4 발광셀(C1, C2, D1, D2)를 포함할 수 있다. 또한, 발광 소자는 제1 접속 패드(620) 및 제2 접속 패드(530)를 포함하며, 상부 연장부(530-1)들과 하부 연장부(620-1)들을 포함할 수 있다. 상부 연장부(530-1)는 보조 상부 연장부(530-1) 및 주 상부 연장부(530-1)로 구분될 수 있다.Referring to FIG. 17, the light emitting device according to the present embodiment may include first to fourth light emitting cells C1, C2, D1, and D2. In addition, the light emitting device may include a first connection pad 620 and a second connection pad 530, and may include upper extension parts 530-1 and lower extension parts 620-1. The upper extension 530-1 may be divided into an auxiliary upper extension 530-1 and a main upper extension 530-1.
제1 내지 제4 발광셀들(C1, C2, D1, D2)은 제1 도전형 반도체층(111a, 111b)을 노출시키는 메사 홈(113a, 113b)을 통해 분리될 수 있다. 제1 발광셀(C1)과 제2 발광셀(C2), 그리고 제3 발광셀(D1)과 제4 발광셀(D2)은 제1 접속 패드(620)와 제2 접속 패드(530)를 연결한 가상선을 기준으로 대칭되는 형상을 가질 수 있다.The first to fourth light emitting cells C1, C2, D1, and D2 may be separated through mesa grooves 113a and 113b exposing the first conductive semiconductor layers 111a and 111b. The first light emitting cell C1 and the second light emitting cell C2, and the third light emitting cell D1 and the fourth light emitting cell D2 connect the first connection pad 620 and the second connection pad 530. It may have a shape symmetrical with respect to one virtual line.
한편, 제1 접속 패드(620)는 발광 소자의 제4 측면(100d) 근처에 배치되고, 제2 접속 패드(530)는 발광 소자의 제2 측면(100b) 근처에 배치될 수 있다. 도 17에 도시된 것처럼, 제1 접속 패드(620)와 제2 접속 패드(530)는 서로 대향하여 배치될 수 있다. Meanwhile, the first connection pad 620 may be disposed near the fourth side surface 100d of the light emitting device, and the second connection pad 530 may be disposed near the second side surface 100b of the light emitting device. As illustrated in FIG. 17, the first connection pad 620 and the second connection pad 530 may be disposed to face each other.
제1 접속 패드(620)는 메사 홈(113c) 상에 배치될 수 있다. 즉, 제1 접속 패드(620) 형성을 위해, 발광 소자의 제4 측면(100d) 근처에서, 제3 발광셀(D1) 및 제4 발광셀(D2)의 하단 일부가 메사 식각되어, 메사 홈(113c)이 형성될 수 있다. 메사 홈(113c)을 통해 반도체 적층(110)의 측면이 노출될 수 있다. 제1 접속 패드(620)는 메사 홈(113c) 내에 배치되어 제1 도전형 반도체층(111c)에 전기적으로 접속될 수 있다. 제1 전류 차단층(640)은 제1 접속 패드(620)와 제1 도전형 반도체층(111b) 사이의 일부 영역에 개재되어, 전류의 수평 분산을 원활하게 할 수 있다. The first connection pad 620 may be disposed on the mesa groove 113c. That is, in order to form the first connection pad 620, near the fourth side surface 100d of the light emitting device, a portion of the lower end of the third light emitting cell D1 and the fourth light emitting cell D2 is mesa-etched to form a mesa groove. 113c may be formed. Side surfaces of the semiconductor stack 110 may be exposed through the mesa groove 113c. The first connection pad 620 may be disposed in the mesa groove 113c and electrically connected to the first conductivity type semiconductor layer 111c. The first current blocking layer 640 is interposed in a partial region between the first connection pad 620 and the first conductive semiconductor layer 111b to smoothly distribute currents.
절연층(665)이 제1 접속 패드(620)가 배치된 메사 홈(113c)의 측면을 덮을 수 있다. 도 15 및 16에 도시된 바와 같이, 절연층(665)은 메사 홈(113c)의 측면을 덮고, 또한 하부 연장부(620-1)가 지나는 부분에도 형성되어 전체적으로 연결된 하나의 곡선 형상을 가질 수 있다.The insulating layer 665 may cover the side surface of the mesa groove 113c on which the first connection pad 620 is disposed. As shown in FIGS. 15 and 16, the insulating layer 665 may cover a side surface of the mesa groove 113c and may also be formed at a portion through which the lower extension 620-1 passes to have a single curved shape. have.
제1 및 제2 발광셀들(C1, C2)에서, 하부 연장부(620-1)들의 일단은 메사 홈(113b) 내에 배치되는 연결 유닛(620-2)과 전기적으로 연결되고, 타단은 주 상부 연장부(530-1b)와 이격되되, 주 상부 연장부(530-1b)로 둘러 싸여 질 수 있다. 다만, 연결 유닛(620-2) 아래에는 제2 전류 차단층(150)(150)으로부터 연장된 절연층(151)이 위치할 수 있다. 상기 절연층(151)은 메사 홈(113b)에서 노출될 수 있는 반도체 적층(110)의 측면을 덮을 수 있고, 그에 따라 연결 유닛(620-2)이 반도체 적층(110)의 측면과 접속되는 것을 방지하여, 발광 소자의 신뢰성을 높일 수 있다.In the first and second light emitting cells C1 and C2, one end of the lower extension parts 620-1 is electrically connected to the connection unit 620-2 disposed in the mesa groove 113b, and the other end thereof is the main part. It may be spaced apart from the upper extension 530-1b, and may be surrounded by the main upper extension 530-1b. However, an insulating layer 151 extending from the second current blocking layers 150 and 150 may be positioned below the connection unit 620-2. The insulating layer 151 may cover the side surface of the semiconductor stack 110, which may be exposed in the mesa groove 113b, so that the connection unit 620-2 may be connected to the side surface of the semiconductor stack 110. It can prevent and improve the reliability of a light emitting element.
제3 및 제4 발광셀들(D1, D2)에서, 하부 연장부(620-1)들은 제1 접속 패드(620)에 접속되며 직선 영역 및 곡선 영역을 포함한다. 곡선 영역은 직선 영역을 제1 접속 패드(620)에 연결할 수 있다. 제3 및 제4 발광셀들(D1, D2)에서, 하부 연장부(620-1)의 형상은 제1 접속 패드(620) 및 제2 접속 패드(530)를 연결하는 가상의 선을 기준으로 서로 대칭될 수 있다.In the third and fourth light emitting cells D1 and D2, the lower extension parts 620-1 are connected to the first connection pad 620 and include a straight area and a curved area. The curved area may connect the straight area to the first connection pad 620. In the third and fourth light emitting cells D1 and D2, the shape of the lower extension part 620-1 is based on an imaginary line connecting the first connection pad 620 and the second connection pad 530. Can be symmetrical to each other.
제2 접속 패드(530)는 메사 홈(113a) 상에 배치되되, 제1 발광셀(C1) 및 제2 발광셀(C2)에 걸쳐서 배치될 수 있다. 제2 접속 패드(530) 아래에는 제2 접속 패드(530)보다 폭이 넓은 제2 전류 차단층(150)이 배치된다. 따라서, 제2 접속 패드(530)는 메사 홈(113a)에서 제2 전류 차단층(150)에 의해 제1 도전형 반도체층(111a)과 접속이 차단될 수 있다. 제2 접속 패드(530)와 제2 전류 차단층(150) 사이에는 투명 전극층(160)이 개재될 수 있고, 제2 접속 패드(530)는 투명 전극층(160)을 통해 제2 도전형 반도체층(113)에 접속될 수 있다.The second connection pad 530 is disposed on the mesa groove 113a and may be disposed over the first light emitting cell C1 and the second light emitting cell C2. A second current blocking layer 150 that is wider than the second connection pad 530 is disposed below the second connection pad 530. Accordingly, the second connection pad 530 may be disconnected from the first conductivity type semiconductor layer 111a by the second current blocking layer 150 in the mesa groove 113a. The transparent electrode layer 160 may be interposed between the second connection pad 530 and the second current blocking layer 150, and the second connection pad 530 is formed of the second conductive semiconductor layer through the transparent electrode layer 160. And may be connected to 113.
한편, 투명 전극층(160) 상에 보조 상부 연장부(530-1a)들 및 주 상부 연장부(530-1b)들이 배치될 수 있다. Meanwhile, auxiliary upper extensions 530-1a and main upper extensions 530-1b may be disposed on the transparent electrode layer 160.
보조 상부 연장부(530-1a)는 제1 및 제2 발광셀(C1, C2) 상에서, 주 상부 연장부(530-1b)를 제2 접속 패드(530)에 연결할 수 있다. 이에 따라, 제1 발광셀(C1)과 제2 발광셀(C2)이 전기적으로 연결될 수 있다. The auxiliary upper extension 530-1a may connect the main upper extension 530-1b to the second connection pad 530 on the first and second light emitting cells C1 and C2. Accordingly, the first light emitting cell C1 and the second light emitting cell C2 may be electrically connected to each other.
또한, 제3 및 제4 발광셀들(D1, D2)에서, 보조 상부 연장부(530-1a)는 주 상부 연장부(530-1b)를 제1 및 제2 발광셀(C1, C2)의 하부 연장부(620-1)와 연결할 수 있다. 제3 및 제4 발광셀들(D1, D2)에서 보조 상부 연장부(530-1a)의 일단은 주 상부 연장부(530-1b)에 연결되고, 타단은 연결 유닛(620-2)에 연결될 수 있다.In addition, in the third and fourth light emitting cells D1 and D2, the auxiliary upper extension 530-1a connects the main upper extension 530-1b to the first and second light emitting cells C1 and C2. It may be connected to the lower extension 620-1. In the third and fourth light emitting cells D1 and D2, one end of the auxiliary upper extension 530-1a is connected to the main upper extension 530-1b, and the other end is connected to the connection unit 620-2. Can be.
주 상부 연장부(530-1b)는 하부 연장부(620-1)의 단부 및 측면 일부를 감싸도록 배치될 수 있다. 따라서, 주 상부 연장부(530-1b)의 일부는 하부 연장부(620-1)의 일측에 배치되고, 또 다른 일부는 하부 연장부(620-1)의 일측에 대향하는 타측에 배치될 수 있다.The main upper extension 530-1b may be disposed to surround a portion of the end and side surfaces of the lower extension 620-1. Therefore, a part of the main upper extension 530-1b may be disposed on one side of the lower extension 620-1, and another part may be disposed on the other side opposite to one side of the lower extension 620-1. have.
도 18을 통해, 제1 접속 패드(620), 제1 전류 차단층(640) 및 하부 연장부(620-1)에 대한 평면도가 확대 도시되어 있다. 도 18을 참조하면 이들의 평면 형상에 대해 검토한다.18 is an enlarged plan view of the first connection pad 620, the first current blocking layer 640, and the lower extension 620-1. Referring to Fig. 18, these planar shapes will be examined.
먼저, 도 18에 개시된 제1 접속 패드(620)의 평면 형상을 참조하면, 제1 접속 패드(620)의 테두리는 직선 영역 및 제1 곡선 영역(621)을 포함할 수 있다. 제1 곡선 영역(621)은 메사 홈(113c) 형성과정에서 노출되는 반도체 적층(110)의 측면에 인접하여 위치할 수 있다. 제1 곡선 영역(621)은 곡률 반경 R1 값을 갖는다. First, referring to the planar shape of the first connection pad 620 illustrated in FIG. 18, the edge of the first connection pad 620 may include a straight region and a first curved region 621. The first curved area 621 may be located adjacent to the side surface of the semiconductor stack 110 exposed during the formation of the mesa groove 113c. The first curved area 621 has a radius of curvature R 1 .
제1 전류 차단층(640)은 제1 접속 패드(620)와 제1 도전형 반도체층(111b) 사이에 개재되며, 제1 전류 차단층(640)의 테두리는 직선 영역 및 제2 곡선 영역(641)을 포함할 수 있다. 제2 곡선 영역(641)은 곡률 반경 R2 값을 가지며, 제1 곡선 영역(621) 내측에 위치할 수 있다. 즉, 제2 곡선 영역(641)은 제1 곡선 영역(621)과 동일한 중심을 공유하며, 제1 곡선 영역(621)과 상기 중심을 통해 형성되는 부채꼴 내에 위치할 수 있다. 여기서, R2 값은 R1 값보다 작다. 또한, 제1 곡선 영역(621)과 제2 곡선 영역(641) 사이의 간격(G1)은 균일하게 유지될 수 있다. 또한, 제1 곡선 영역(621)과 제2 곡선 영역(641) 사이의 간격(G1)은 제1 접속 패드(620)의 직선 영역과 제1 전류 차단층(640)의 직선 영역 사이의 간격과 동일할 수 있다. The first current blocking layer 640 is interposed between the first connection pad 620 and the first conductive semiconductor layer 111b, and the edge of the first current blocking layer 640 has a straight region and a second curved region ( 641). The second curved area 641 has a radius of curvature R 2 and may be located inside the first curved area 621. That is, the second curved area 641 may share the same center as the first curved area 621, and may be located in a sector formed through the center and the first curved area 621. Here, the R 2 value is smaller than the R 1 value. In addition, the interval G1 between the first curved area 621 and the second curved area 641 may be maintained uniformly. In addition, the interval G1 between the first curved region 621 and the second curved region 641 is equal to the interval between the linear region of the first connection pad 620 and the linear region of the first current blocking layer 640. May be the same.
각각의 하부 연장부(620-1)들은 연결부(620-1a) 및 메인 연장부(620-1b)를 포함할 수 있다. 연결부(620-1a)는 메인 연장부(620-1b)를 제1 접속 패드(620)에 연결할 수 있다. 연결부(620-1a) 아래에는 절연층(665)이 배치될 수 있다. 도 18에 개시된 연결부(620-1a)의 평면 형상을 참조하면, 연결부(620-1a)의 테두리는 제3 곡선 영역(621-1)을 포함할 수 있다. 이때, 제3 곡선 영역(621-1)은 곡률 반경 R3 값을 가질 수 있다. Each lower extension 620-1 may include a connection 620-1a and a main extension 620-1b. The connection part 620-1a may connect the main extension part 620-1b to the first connection pad 620. An insulating layer 665 may be disposed below the connection portion 620-1a. Referring to the planar shape of the connector 620-1a illustrated in FIG. 18, the edge of the connector 620-1a may include a third curved area 621-1. In this case, the third curved area 621-1 may have a radius of curvature R 3 .
연결부(620-1a)가 제3 곡선 영역(621-1)을 포함하는 것에 따라, 연결부(620-1a)의 폭(G2)은 제1 접속 패드(620)로부터 멀어질수록 감소할 수 있다. 다만, 제1 접속 패드(620)에 인접하는 연결부(620-1a)의 폭(G2)은 제1 곡선 영역(621)과 제2 곡선 영역(641) 사이의 간격(G1)보다 크게 형성될 수 있다. 그에 따라, 제1 접속 패드(620)를 통해 주입되는 전류 중 비교적 큰 비율이, 비교적 큰 넓이를 갖는 연결부(620-1a) 쪽으로 주입될 수 있다. 여기서, R3 값은 R1 값 및 R2 값에 비해 작게 형성될 수 있다. As the connection portion 620-1a includes the third curved area 621-1, the width G2 of the connection portion 620-1a may decrease as the distance from the first connection pad 620 increases. However, the width G2 of the connection portion 620-1a adjacent to the first connection pad 620 may be larger than the gap G1 between the first curved area 621 and the second curved area 641. have. Accordingly, a relatively large proportion of the current injected through the first connection pad 620 may be injected toward the connection portion 620-1a having a relatively large width. Here, the R 3 value may be formed smaller than the R 1 value and the R 2 value.
메인 연장부(620-1b)의 일단은 상기 연결부(620-1a)에 접속된다. 메인 연장부(620-1b)의 폭(G3)은 상기 제1 곡선 영역(621) 및 제2 곡선 영역(641) 사이의 간격(G1)보다 크거나 같을 수 있다.One end of the main extension part 620-1b is connected to the connection part 620-1a. The width G3 of the main extension 620-1b may be greater than or equal to the gap G1 between the first curved area 621 and the second curved area 641.
도 19은 본 발명의 일 실시예에 따른 발광소자를 조명 장치에 적용한 예를 설명하기 위한 분해 사시도이다.19 is an exploded perspective view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a lighting device.
도 19을 참조하면, 본 실시예에 따른 조명 장치는, 확산 커버(1010), 발광소자 모듈(1020) 및 바디부(1030)를 포함한다. 바디부(1030)는 발광소자 모듈(1020)을 수용할 수 있고, 확산 커버(1010)는 발광소자 모듈(1020)의 상부를 커버할 수 있도록 바디부(1030) 상에 배치될 수 있다.Referring to FIG. 19, the lighting apparatus according to the present embodiment includes a diffusion cover 1010, a light emitting device module 1020, and a body portion 1030. The body portion 1030 may accommodate the light emitting device module 1020, and the diffusion cover 1010 may be disposed on the body portion 1030 to cover the upper portion of the light emitting device module 1020.
바디부(1030)는 발광소자 모듈(1020)을 수용 및 지지하여, 발광소자 모듈(1020)에 전기적 전원을 공급할 수 있는 형태이면 제한되지 않는다. 예를 들어, 도시된 바와 같이, 바디부(1030)는 바디 케이스(1031), 전원 공급 장치(1033), 전원 케이스(1035), 및 전원 접속부(1037)를 포함할 수 있다. The body part 1030 is not limited as long as it can receive and support the light emitting device module 1020 and supply electric power to the light emitting device module 1020. For example, as shown, the body portion 1030 may include a body case 1031, a power supply device 1033, a power case 1035, and a power connection portion 1037.
전원 공급 장치(1033)는 전원 케이스(1035) 내에 수용되어 발광소자 모듈(1020)과 전기적으로 연결되며, 적어도 하나의 IC칩을 포함할 수 있다. 상기 IC칩은 발광소자 모듈(1020)로 공급되는 전원의 특성을 조절, 변환 또는 제어할 수 있다. 전원 케이스(1035)는 전원 공급 장치(1033)를 수용하여 지지할 수 있고, 전원 공급 장치(1033)가 그 내부에 고정된 전원 케이스(1035)는 바디 케이스(1031)의 내부에 위치할 수 있다. 전원 접속부(115)는 전원 케이스(1035)의 하단에 배치되어, 전원 케이스(1035)와 결속될 수 있다. 이에 따라, 전원 접속부(1037)는 전원 케이스(1035) 내부의 전원 공급 장치(1033)와 전기적으로 연결되어, 외부 전원이 전원 공급 장치(1033)에 공급될 수 있는 통로 역할을 할 수 있다.The power supply device 1033 is accommodated in the power case 1035 and electrically connected to the light emitting device module 1020 and may include at least one IC chip. The IC chip may adjust, convert, or control the characteristics of the power supplied to the light emitting device module 1020. The power case 1035 may receive and support the power supply 1033, and the power case 1035 to which the power supply 1033 is fixed may be located inside the body case 1031. . The power connection unit 115 may be disposed at a lower end of the power case 1035 and may be coupled to the power case 1035. Accordingly, the power connection unit 1037 may be electrically connected to the power supply device 1033 inside the power case 1035 to serve as a path through which external power may be supplied to the power supply device 1033.
발광소자 모듈(1020)은 기판(1023) 및 기판(1023) 상에 배치된 발광소자(1021)를 포함한다. 발광소자 모듈(1020)은 바디 케이스(1031) 상부에 마련되어 전원 공급 장치(1033)에 전기적으로 연결될 수 있다.The light emitting device module 1020 includes a substrate 1023 and a light emitting device 1021 disposed on the substrate 1023. The light emitting device module 1020 may be provided on the body case 1031 and electrically connected to the power supply device 1033.
기판(1023)은 발광소자(1021)를 지지할 수 있는 기판이면 제한되지 않으며, 예를 들어, 배선을 포함하는 인쇄회로기판일 수 있다. 기판(1023)은 바디 케이스(1031)에 안정적으로 고정될 수 있도록, 바디 케이스(1031) 상부의 고정부에 대응하는 형태를 가질 수 있다. 발광소자(1021)는 상술한 본 발명의 실시예들에 따른 발광소자들 중 적어도 하나를 포함할 수 있다. The substrate 1023 is not limited as long as it can support the light emitting device 1021. For example, the substrate 1023 may be a printed circuit board including wiring. The substrate 1023 may have a shape corresponding to the fixing portion of the upper portion of the body case 1031 so as to be stably fixed to the body case 1031. The light emitting device 1021 may include at least one of the light emitting devices according to the embodiments of the present invention described above.
확산 커버(1010)는 발광소자(1021) 상에 배치되되, 바디 케이스(1031)에 고정되어 발광소자(1021)를 커버할 수 있다. 확산 커버(1010)는 투광성 재질을 가질 수 있으며, 확산 커버(1010)의 형태 및 광 투과성을 조절하여 조명 장치의 지향 특성을 조절할 수 있다. 따라서 확산 커버(1010)는 조명 장치의 이용 목적 및 적용 태양에 따라 다양한 형태로 변형될 수 있다.The diffusion cover 1010 may be disposed on the light emitting device 1021, and may be fixed to the body case 1031 to cover the light emitting device 1021. The diffusion cover 1010 may have a translucent material and may adjust the directivity of the lighting device by adjusting the shape and the light transmittance of the diffusion cover 1010. Therefore, the diffusion cover 1010 may be modified in various forms according to the purpose of use of the lighting device and the application aspect.
도 20은 본 발명의 일 실시예에 따른 발광소자를 디스플레이 장치에 적용한 예를 설명하기 위한 단면도이다. 20 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a display device.
본 실시예의 디스플레이 장치는 표시패널(2110), 표시패널(2110)에 광을 제공하는 백라이트 유닛 및, 상기 표시패널(2110)의 하부 가장자리를 지지하는 패널 가이드를 포함한다.The display device according to the present exemplary embodiment includes a display panel 2110, a backlight unit providing light to the display panel 2110, and a panel guide supporting a lower edge of the display panel 2110.
표시패널(2110)은 특별히 한정되지 않고, 예컨대, 액정층을 포함하는 액정표시패널일 수 있다. 표시패널(2110)의 가장자리에는 상기 게이트 라인으로 구동신호를 공급하는 게이트 구동 PCB가 더 위치할 수 있다. 여기서, 게이트 구동 PCB는 별도의 PCB에 구성되지 않고, 박막 트랜지스터 기판상에 형성될 수도 있다.The display panel 2110 is not particularly limited and may be, for example, a liquid crystal display panel including a liquid crystal layer. A gate driving PCB for supplying a driving signal to the gate line may be further located at the edge of the display panel 2110. Here, the gate driving PCB is not configured in a separate PCB, but may be formed on the thin film transistor substrate.
백라이트 유닛은 적어도 하나의 기판 및 복수의 발광소자(2160)를 포함하는 광원 모듈을 포함한다. 나아가, 백라이트 유닛은 바텀커버(2180), 반사 시트(2170), 확산 플레이트(2131) 및 광학 시트들(2130)을 더 포함할 수 있다.The backlight unit includes a light source module including at least one substrate and a plurality of light emitting devices 2160. In addition, the backlight unit may further include a bottom cover 2180, a reflective sheet 2170, a diffusion plate 2131, and optical sheets 2130.
바텀커버(2180)는 상부로 개구되어, 기판, 발광소자(2160), 반사 시트(2170), 확산 플레이트(2131) 및 광학 시트들(2130)을 수납할 수 있다. 또한, 바텀커버(2180)는 패널 가이드와 결합될 수 있다. 기판은 반사 시트(2170)의 하부에 위치하여, 반사 시트(2170)에 둘러싸인 형태로 배치될 수 있다. 다만, 이에 한정되지 않고, 반사 물질이 표면에 코팅된 경우에는 반사 시트(2170) 상에 위치할 수도 있다. 또한, 기판은 복수로 형성되어, 복수의 기판들이 나란히 배치된 형태로 배치될 수 있으나, 이에 한정되지 않고, 단일의 기판으로 형성될 수도 있다.The bottom cover 2180 may be opened upward to accommodate the substrate, the light emitting device 2160, the reflective sheet 2170, the diffusion plate 2131, and the optical sheets 2130. In addition, the bottom cover 2180 may be combined with the panel guide. The substrate may be disposed under the reflective sheet 2170 and be surrounded by the reflective sheet 2170. However, the present invention is not limited thereto, and when the reflective material is coated on the surface, the reflective material may be positioned on the reflective sheet 2170. In addition, a plurality of substrates may be formed, and the plurality of substrates may be arranged in a side-by-side arrangement, but is not limited thereto and may be formed of a single substrate.
발광소자(2160)는 상술한 본 발명의 실시예들에 따른 발광소자들 중 적어도 하나를 포함할 수 있다. 발광소자(2160)들은 기판 상에 일정한 패턴으로 규칙적으로 배열될 수 있다. 또한, 각각의 발광소자(2160) 상에는 렌즈(2210)가 배치되어, 복수의 발광소자(2160)들로부터 방출되는 광을 균일성을 향상시킬 수 있다.The light emitting device 2160 may include at least one of the light emitting devices according to the embodiments of the present invention described above. The light emitting devices 2160 may be regularly arranged in a predetermined pattern on the substrate. In addition, a lens 2210 may be disposed on each light emitting device 2160 to improve uniformity of light emitted from the plurality of light emitting devices 2160.
확산 플레이트(2131) 및 광학 시트들(2130)은 발광소자(2160) 상에 위치한다. 발광소자(2160)로부터 방출된 광은 확산 플레이트(2131) 및 광학 시트들(2130)을 거쳐 면 광원 형태로 표시패널(2110)로 공급될 수 있다. The diffusion plate 2131 and the optical sheets 2130 are positioned on the light emitting device 2160. Light emitted from the light emitting device 2160 may be supplied to the display panel 2110 in the form of a surface light source through the diffusion plate 2131 and the optical sheets 2130.
이와 같이, 본 발명의 실시예들에 따른 발광소자는 본 실시예와 같은 직하형 디스플레이 장치에 적용될 수 있다.As such, the light emitting device according to the embodiments of the present invention may be applied to the direct type display device as the present embodiment.
도 21은 일 실시예에 따른 발광소자를 디스플레이 장치에 적용한 예를 설명하기 위한 단면도이다. 21 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment is applied to a display device.
본 실시예에 따른 백라이트 유닛이 구비된 디스플레이 장치는 영상이 디스플레이되는 표시패널(3210), 표시패널(3210)의 배면에 배치되어 광을 조사하는 백라이트 유닛을 포함한다. 나아가, 상기 디스플레이 장치는, 표시패널(3210)을 지지하고 백라이트 유닛이 수납되는 프레임(240) 및 상기 표시패널(3210)을 감싸는 커버(3240, 3280)를 포함한다.The display device including the backlight unit according to the present exemplary embodiment includes a display panel 3210 on which an image is displayed and a backlight unit disposed on a rear surface of the display panel 3210 to irradiate light. In addition, the display apparatus includes a frame 240 that supports the display panel 3210 and accommodates the backlight unit, and covers 3240 and 3280 that surround the display panel 3210.
표시패널(3210)은 특별히 한정되지 않고, 예컨대, 액정층을 포함하는 액정표시패널일 수 있다. 표시패널(3210)의 가장자리에는 상기 게이트 라인으로 구동신호를 공급하는 게이트 구동 PCB가 더 위치할 수 있다. 여기서, 게이트 구동 PCB는 별도의 PCB에 구성되지 않고, 박막 트랜지스터 기판상에 형성될 수도 있다. 표시패널(3210)은 그 상하부에 위치하는 커버(3240, 3280)에 의해 고정되며, 하부에 위치하는 커버(3280)는 백라이트 유닛과 결속될 수 있다.The display panel 3210 is not particularly limited and may be, for example, a liquid crystal display panel including a liquid crystal layer. A gate driving PCB for supplying a driving signal to the gate line may be further located at an edge of the display panel 3210. Here, the gate driving PCB is not configured in a separate PCB, but may be formed on the thin film transistor substrate. The display panel 3210 may be fixed by covers 3240 and 3280 positioned at upper and lower portions thereof, and the cover 3280 positioned at lower portions thereof may be coupled to the backlight unit.
표시패널(3210)에 광을 제공하는 백라이트 유닛은 상면의 일부가 개구된 하부 커버(3270), 하부 커버(3270)의 내부 일 측에 배치된 광원 모듈 및 상기 광원 모듈과 나란하게 위치되어 점광을 면광으로 변환하는 도광판(3250)을 포함한다. 또한, 본 실시예의 백라이트 유닛은 도광판(3250) 상에 위치되어 광을 확산 및 집광시키는 광학 시트들(3230), 도광판(3250)의 하부에 배치되어 도광판(3250)의 하부방향으로 진행하는 광을 표시패널(3210) 방향으로 반사시키는 반사시트(3260)를 더 포함할 수 있다.The backlight unit for providing light to the display panel 3210 may include a lower cover 3270 having a portion of an upper surface thereof, a light source module disposed on one side of the lower cover 3270, and positioned in parallel with the light source module to provide point light. And a light guide plate 3250 for converting to surface light. In addition, the backlight unit according to the present exemplary embodiment is disposed on the light guide plate 3250 and is disposed below the light guide plate 3250 and the optical sheets 3230 for diffusing and condensing light. The display apparatus may further include a reflective sheet 3260 reflecting in the direction of the display panel 3210.
광원 모듈은 기판(3220) 및 상기 기판(3220)의 일면에 일정 간격으로 이격되어 배치된 복수의 발광소자(3110)를 포함한다. 기판(3220)은 발광소자(3110)를 지지하고 발광소자(3110)에 전기적으로 연결된 것이면 제한되지 않으며, 예컨대, 인쇄회로기판일 수 있다. 발광소자(3110)는 상술한 본 발명의 실시예들에 따른 발광소자를 적어도 하나 포함할 수 있다. 광원 모듈로부터 방출된 광은 도광판(3250)으로 입사되어 광학 시트들(3230)을 통해 표시패널(3210)로 공급된다. 도광판(3250) 및 광학 시트들(3230)을 통해, 발광소자(3110)들로부터 방출된 점 광원이 면 광원으로 변형될 수 있다.The light source module includes a substrate 3220 and a plurality of light emitting devices 3110 spaced apart from each other by a predetermined interval on one surface of the substrate 3220. The substrate 3220 is not limited as long as it supports the light emitting device 3110 and is electrically connected to the light emitting device 3110. For example, the substrate 3220 may be a printed circuit board. The light emitting device 3110 may include at least one light emitting device according to the embodiments of the present invention described above. Light emitted from the light source module is incident to the light guide plate 3250 and is supplied to the display panel 3210 through the optical sheets 3230. Through the light guide plate 3250 and the optical sheets 3230, the point light sources emitted from the light emitting devices 3110 may be transformed into surface light sources.
이와 같이, 본 발명의 실시예들에 따른 발광소자는 본 실시예와 같은 에지형 디스플레이 장치에 적용될 수 있다.As such, the light emitting device according to the embodiments of the present invention may be applied to the edge type display device as the present embodiment.
도 22는 본 발명의 일 실시예에 따른 발광소자를 헤드 램프에 적용한 예를 설명하기 위한 단면도이다.22 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a head lamp.
도 22를 참조하면, 상기 헤드 램프는, 램프 바디(4070), 기판(4020), 발광소자(4010) 및 커버 렌즈(4050)를 포함한다. 나아가, 상기 헤드 램프는, 방열부(4030), 지지랙(4060) 및 연결 부재(4040)를 더 포함할 수 있다.Referring to FIG. 22, the head lamp includes a lamp body 4070, a substrate 4020, a light emitting device 4010, and a cover lens 4050. Furthermore, the head lamp may further include a heat dissipation unit 4030, a support rack 4060, and a connection member 4040.
기판(4020)은 지지랙(4060)에 의해 고정되어 램프 바디(4070) 상에 이격 배치된다. 기판(4020)은 발광소자(4010)를 지지할 수 있는 기판이면 제한되지 않으며, 예컨대, 인쇄회로기판과 같은 도전 패턴을 갖는 기판일 수 있다. 발광소자(4010)는 기판(4020) 상에 위치하며, 기판(4020)에 의해 지지 및 고정될 수 있다. 또한, 기판(4020)의 도전 패턴을 통해 발광소자(4010)는 외부의 전원과 전기적으로 연결될 수 있다. 또한, 발광소자(4010)는 상술한 본 발명의 실시예들에 따른 발광소자를 적어도 하나 포함할 수 있다. The substrate 4020 is fixed by the support rack 4060 and spaced apart from the lamp body 4070. The substrate 4020 is not limited as long as it is a substrate capable of supporting the light emitting device 4010. For example, the substrate 4020 may be a substrate having a conductive pattern such as a printed circuit board. The light emitting device 4010 is positioned on the substrate 4020 and may be supported and fixed by the substrate 4020. In addition, the light emitting device 4010 may be electrically connected to an external power source through the conductive pattern of the substrate 4020. In addition, the light emitting device 4010 may include at least one light emitting device according to the embodiments of the present invention described above.
커버 렌즈(4050)는 발광소자(4010)로부터 방출되는 광이 이동하는 경로 상에 위치한다. 예컨대, 도시된 바와 같이, 커버 렌즈(4050)는 연결 부재(4040)에 의해 발광소자(4010)로부터 이격되어 배치될 수 있고, 발광소자(4010)로부터 방출된 광을 제공하고자하는 방향에 배치될 수 있다. 커버 렌즈(4050)에 의해 헤드 램프로부터 외부로 방출되는 광의 지향각 및/또는 색상이 조절될 수 있다. 한편, 연결 부재(4040)는 커버 렌즈(4050)를 기판(4020)과 고정시킴과 아울러, 발광소자(4010)를 둘러싸도록 배치되어 발광 경로(4045)를 제공하는 광 가이드 역할을 할 수도 있다. 이때, 연결 부재(4040)는 광 반사성 물질로 형성되거나, 광 반사성 물질로 코팅될 수 있다. 한편, 방열부(4030)는 방열핀(4031) 및/또는 방열팬(4033)을 포함할 수 있고, 발광소자(4010) 구동 시 발생하는 열을 외부로 방출시킨다.The cover lens 4050 is positioned on a path along which light emitted from the light emitting device 4010 travels. For example, as shown, the cover lens 4050 may be disposed to be spaced apart from the light emitting device 4010 by the connecting member 4040, and to be disposed in a direction to provide light emitted from the light emitting device 4010. Can be. By the cover lens 4050, the direction angle and / or color of the light emitted from the head lamp to the outside may be adjusted. Meanwhile, the connection member 4040 may fix the cover lens 4050 with the substrate 4020 and may be disposed to surround the light emitting device 4010 to serve as a light guide for providing the light emitting path 4045. In this case, the connection member 4040 may be formed of a light reflective material or coated with a light reflective material. Meanwhile, the heat dissipation unit 4030 may include a heat dissipation fin 4031 and / or a heat dissipation fan 4033, and dissipate heat generated when the light emitting device 4010 is driven to the outside.
이와 같이, 본 발명의 실시예들에 따른 발광소자는 본 실시예와 같은 헤드 램프, 특히, 차량용 헤드 램프에 적용될 수 있다.As such, the light emitting device according to the embodiments of the present invention may be applied to the head lamp, in particular, a vehicle head lamp as in the present embodiment.
이상에서는 본 발명의 실시예를 중심으로 설명하였지만, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 기술자의 수준에서 다양한 변경이나 변형을 가할 수 있다. 이러한 변경과 변형은 본 발명이 제공하는 기술 사상의 범위를 벗어나지 않는 한 본 발명에 속한다고 할 수 있다. 따라서 본 발명의 권리범위는 이하에 기재되는 청구범위에 의해 판단되어야 할 것이다.Although the above has been described with reference to the embodiments of the present invention, various changes and modifications can be made at the level of those skilled in the art. Such changes and modifications can be said to belong to the present invention without departing from the scope of the technical idea provided by the present invention. Therefore, the scope of the present invention will be determined by the claims described below.

Claims (34)

  1. 제1 도전형 반도체층, 제2 도전형 반도체층 및 상기 제1 및 제2 도전형 반도체층 사이에 위치하는 활성층을 포함하고, 상기 제2 도전형 반도체층 및 활성층을 관통하여 상기 제1 도전형 반도체층을 노출시키는 노출 영역을 포함하는 질화물계 반도체 적층;A first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer positioned between the first and second conductive semiconductor layers, and penetrating the second conductive semiconductor layer and the active layer to form the first conductive type. A nitride based semiconductor laminate including an exposed region exposing the semiconductor layer;
    상기 노출 영역을 통해 상기 제1 도전형 반도체층에 전기적으로 연결되는 제1 접속 패드;A first connection pad electrically connected to the first conductivity type semiconductor layer through the exposed region;
    상기 제1 도전형 반도체층과 상기 제1 접속 패드 사이에 개재된 제1 전류 차단층;A first current blocking layer interposed between the first conductive semiconductor layer and the first connection pad;
    상기 제2 도전형 반도체층 상에 배치된 제2 접속 패드; 및Second connection pads disposed on the second conductive semiconductor layer; And
    상기 제2 접속 패드로부터 연장된 상부 연장부를 포함하고, An upper extension extending from the second connection pad,
    상기 상부 연장부는 2개 이상이며, 상기 제1 접속 패드는 상기 상부 연장부들 사이에 위치하고,The upper extension is two or more, and the first connection pad is located between the upper extensions,
    상기 제1 전류 차단층은 상기 제1 도전형 반도체층과 상기 제1 접속 패드 사이의 영역에서는, 일부 영역에 한정되어 개재되는 발광소자.The first current blocking layer is limited to a part of the light emitting device in the region between the first conductive semiconductor layer and the first connection pad.
  2. 청구항 1에 있어서,The method according to claim 1,
    상기 제1 전류 차단층의 영역은 상기 제1 도전형 반도체층과 상기 제1 접속 패드 사이 영역의 90%를 초과하지 않는 발광소자.The region of the first current blocking layer does not exceed 90% of the region between the first conductive semiconductor layer and the first connection pad.
  3. 청구항 1에 있어서, The method according to claim 1,
    상기 제1 전류 차단층은 SiO2층 또는 분포 브래그 반사층을 포함하는 발광소자.The first current blocking layer includes a SiO 2 layer or a distributed Bragg reflective layer.
  4. 청구항 3에 있어서,The method according to claim 3,
    상기 분포 브래그 반사층은 SiO2층과 TiO2층 또는 SiO2층과 Nb2O5층이 교대로 적층된 구조를 가지는 발광소자.The distributed Bragg reflective layer has a structure in which an SiO 2 layer and a TiO 2 layer or an SiO 2 layer and an Nb 2 O 5 layer are alternately stacked.
  5. 청구항 1에 있어서,The method according to claim 1,
    상기 제1 전류 차단층의 형상은 상기 제1 접속 패드의 형상과 동일한 발광소자.The shape of the first current blocking layer is the same as the shape of the first connection pad.
  6. 청구항 1에 있어서, The method according to claim 1,
    상기 제2 접속 패드의 하부 및 상기 복수의 상부 연장부들 하부에 배치된 제2 전류 차단층을 더 포함하는 발광소자.And a second current blocking layer disposed below the second connection pad and below the plurality of upper extensions.
  7. 청구항 1에 있어서,The method according to claim 1,
    상기 제1 접속 패드로부터 연장되며, 상기 제1 도전형 반도체층에 콘택하는 하부 연장부를 더 포함하는 발광소자.And a lower extension part extending from the first connection pad and contacting the first conductivity type semiconductor layer.
  8. 청구항 1에 있어서,The method according to claim 1,
    상기 제2 도전형 반도체층 상에 위치하며, 상기 제2 도전형 반도체층에 오믹 콘택하는 오믹 전극층을 더 포함하는 발광소자.And an ohmic electrode layer disposed on the second conductive semiconductor layer and ohmic contacting the second conductive semiconductor layer.
  9. 청구항 1에 있어서,The method according to claim 1,
    상기 노출 영역을 통해 노출되는 질화물계 반도체 적층을 덮는 절연층을 더 포함하는 발광소자.The light emitting device further comprises an insulating layer covering the nitride-based semiconductor layer exposed through the exposed area.
  10. 청구항 1에 있어서,The method according to claim 1,
    상기 발광 소자는 복수개의 측면을 포함하는 다각형의 평면 형상이고,The light emitting device has a polygonal planar shape including a plurality of side surfaces,
    상기 제1 접속 패드는 상기 발광 소자의 일 측면으로부터 이격되어 위치하는 발광 소자.The first connection pad is a light emitting device spaced apart from one side of the light emitting device.
  11. 청구항 10에 있어서,The method according to claim 10,
    상기 상부 연장부는 상기 발광 소자의 일 측면과 상기 제1 접속 패드 사이의 영역까지 연장되는 위치하는 발광 소자.And the upper extension portion extending to an area between one side of the light emitting element and the first connection pad.
  12. 청구항 1에 있어서,The method according to claim 1,
    상기 질화물계 반도체 적층은 복수개의 노출 영역을 포함하고, The nitride based semiconductor laminate includes a plurality of exposed regions,
    상기 노출 영역은 적어도 하나의 제1 홀 및 적어도 하나의 제2 홀을 포함하는 제1 노출 영역, 적어도 하나의 제3 홀을 포함하는 제2 노출영역을 포함하는 발광소자.The exposure area includes a first exposure area including at least one first hole and at least one second hole, and a second exposure area including at least one third hole.
  13. 청구항 12에 있어서,The method according to claim 12,
    상기 적어도 하나의 제1 홀 및 적어도 하나의 제2홀은 원형 또는 다각형의 평면 형상이고, 상기 적어도 하나의 제3홀은 상기 적어도 하나의 제2 홀로부터 임의의 방향으로 연장되는 형상인 발광소자.The at least one first hole and the at least one second hole have a circular or polygonal planar shape, and the at least one third hole has a shape extending in an arbitrary direction from the at least one second hole.
  14. 청구항 13에 있어서,The method according to claim 13,
    상기 제1 접속 패드는 상기 제1 노출 영역을 통해 상기 제1 도전형 반도체층과 접하고, 상기 하부 연장부는 상기 제2 노출 영역을 통해 상기 제2 도전형 반도체층과 접하는 발광소자. The first connection pad is in contact with the first conductive semiconductor layer through the first exposed region, and the lower extension part is in contact with the second conductive semiconductor layer through the second exposed region.
  15. 청구항 14에 있어서,The method according to claim 14,
    상기 제1 전류 차단층은 상기 제1 노출 영역에 한정되어, 상기 제1 도전형 반도체층과 상기 제1 접속 패드 사이의 일부 영역에 한정되어 개재되는 발광소자.The first current blocking layer is limited to the first exposed region, and is limited to a partial region between the first conductive semiconductor layer and the first connection pad.
  16. 청구항 13에 있어서,The method according to claim 13,
    상기 제3 홀의 폭은 상기 제1 홀 및 제2 홀의 폭보다 작은 발광소자.The width of the third hole is smaller than the width of the first hole and the second hole.
  17. 청구항 12에 있어서,The method according to claim 12,
    상기 제1 접속 패드와 전기적으로 연결되는 제1 본딩 패드 및 상기 제2 접속 패드와 전기적으로 연결되는 제2 본딩 패드를 더 포함하는 발광소자.And a second bonding pad electrically connected to the first connection pad and a second bonding pad electrically connected to the second connection pad.
  18. 청구항 17에 있어서,The method according to claim 17,
    상기 제1 본딩 패드 및 상기 제2 본딩 패드와 상기 질화물계 반도체 적층 사이에 위치하는 절연층을 더 포함하는 발광소자.And a dielectric layer disposed between the first bonding pad and the second bonding pad and the nitride-based semiconductor stack.
  19. 청구항 18에 있어서,The method according to claim 18,
    상기 제1 본딩 패드 상기 제2 본딩 패드는 상기 절연층에 형성된 홀들을 통해 각각 제1 접속 패드 및 제2 접속 패드와 전기적으로 연결되는 발광소자.The first bonding pads The second bonding pads are electrically connected to the first connection pads and the second connection pads through holes formed in the insulating layer, respectively.
  20. 청구항 19에 있어서,The method according to claim 19,
    상기 절연층은 SiO2층 또는 분포 브래그 반사층을 포함하는 발광소자.The insulating layer includes a SiO 2 layer or a distributed Bragg reflective layer.
  21. 제1 도전형 반도체층, 활성층 및 제2 도전형 반도체층을 포함하되, 상기 제1 도전형 반도체층을 노출시키는 노출 영역을 포함하는 반도체 적층;A semiconductor stack including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer, the semiconductor stack including an exposed region exposing the first conductivity type semiconductor layer;
    상기 노출 영역을 통해 상기 제1 도전형 반도체층에 접속하는 제1 접속 패드 및 상기 제1 접속 패드로부터 연장되는 하부 연장부; 및A first connection pad connected to the first conductive semiconductor layer through the exposed area and a lower extension part extending from the first connection pad; And
    상기 제1 접속 패드와 제1 도전형 반도체층 사이에 위치하는 제1 전류 차단층을 포함하고,A first current blocking layer positioned between the first connection pad and the first conductivity type semiconductor layer,
    상기 제1 접속 패드는 곡률 반경 R1 값을 갖는 제1 곡선 영역을 포함하되, The first connection pad includes a first curved area having a radius of curvature R 1 value,
    상기 제1 전류 차단층은 곡률 반경 R2 값을 갖는 제2 곡선 영역을 포함하되, 상기 제2 곡선 영역은 상기 제1 곡선 영역의 내측에 인접하여 배치되며,The first current blocking layer includes a second curved area having a radius of curvature R 2 value, wherein the second curved area is disposed adjacent to the inside of the first curved area,
    상기 하부 연장부는 상기 제1 접속 패드와 접하는 연결부 및 상기 연결부에서 연장하는 메인 연장부를 포함하고, 상기 연결부는 곡률 반경 R3 값을 갖는 제3 곡선 영역을 포함하는 발광 소자.The lower extension part includes a connection part in contact with the first connection pad and a main extension part extending from the connection part, and the connection part includes a third curved area having a radius of curvature R 3 value.
  22. 청구항 21에 있어서,The method according to claim 21,
    상기 곡률 반경 R1, R2 및 R3는 아래와 같은 수학식을 만족하는 발광 소자.The radii of curvature R 1 , R 2 and R 3 satisfy the following equation.
    R3 < R2 < R1 R 3 <R 2 <R 1
  23. 청구항 21에 있어서,The method according to claim 21,
    제1 곡선 영역 및 제2 곡선 영역 사이의 간격은 균일하게 유지되는 발광 소자.The light emitting device of claim 1, wherein a distance between the first curved area and the second curved area is kept uniform.
  24. 청구항 21에 있어서,The method according to claim 21,
    상기 제1 곡선 영역 및 제2 곡선 영역은 동일한 중심을 공유하고,The first curved region and the second curved region share the same center,
    상기 제2 곡선 영역은, 상기 제1 곡선 영역과 상기 제1 곡선 영역의 양단과 상기 중심을 연결하는 가상의 직선에 의해 형성되는 영역 내에 위치하는 발광 소자.The second curved area is positioned in an area formed by an imaginary straight line connecting the first curved area, both ends of the first curved area, and the center.
  25. 청구항 21에 있어서,The method according to claim 21,
    상기 하부 연장부의 연결부의 폭은 상기 제1 곡선 영역 및 제2 곡선 영역 사이의 간격보다 크고, 상기 제1 접속 패드로부터 멀어질수록 감소하는 발광 소자.The width of the connecting portion of the lower extension is greater than the distance between the first curved area and the second curved area, the light emitting device that decreases away from the first connection pad.
  26. 청구항 25에 있어서,The method according to claim 25,
    상기 메인 연장부의 폭은 상기 제1 곡선 영역 및 제2 곡선 영역 사이의 간격보다 크거나 같은 발광 소자.Wherein the width of the main extension is greater than or equal to a distance between the first curved area and the second curved area.
  27. 청구항 21에 있어서,The method according to claim 21,
    상기 제1 전류 차단층은 상기 제1 도전형 반도체층과 상기 제1 접속 패드 사이의 영역에서는, 일부 영역에 한정되어 개재되는 발광소자.The first current blocking layer is limited to a part of the light emitting device in the region between the first conductive semiconductor layer and the first connection pad.
  28. 청구항 27에 있어서,The method of claim 27,
    상기 제1 전류 차단층의 영역은 상기 제1 도전형 반도체층과 상기 제1 접속 패드 사이 영역의 90%를 초과하지 않는 발광소자.The region of the first current blocking layer does not exceed 90% of the region between the first conductive semiconductor layer and the first connection pad.
  29. 청구항 28에 있어서,The method according to claim 28,
    상기 제1 전류 차단층은 단일층 또는 다층인 분포 브래그 반사층을 포함하고,The first current blocking layer comprises a distributed Bragg reflective layer that is single or multilayer;
    상기 분포 브래그 반사층은 SiO2층과 TiO2층 또는 SiO2층과 Nb2O5층이 교대로 적층된 구조를 가지는 발광소자.The distributed Bragg reflective layer has a structure in which an SiO 2 layer and a TiO 2 layer or an SiO 2 layer and an Nb 2 O 5 layer are alternately stacked.
  30. 청구항 21에 있어서,The method according to claim 21,
    상기 하부 연장부 아래 위치하는 제3 전류 차단층을 더 포함하고,Further comprising a third current blocking layer positioned below the lower extension,
    상기 제3 전류 차단층은 서로 이격된 복수의 도트를 포함하는 발광 소자.The third current blocking layer includes a plurality of dots spaced apart from each other.
  31. 청구항 30에 있어서,The method of claim 30,
    상기 제3 전류 차단층의 폭은 상기 메인 연장부의 폭보다 크고,The width of the third current blocking layer is greater than the width of the main extension,
    상기 메인 연장부는 상기 복수의 도트들 사이의 영역에서 상기 제1 도전형 반도체층에 접속되는 발광 소자.The main extension part is connected to the first conductivity type semiconductor layer in a region between the plurality of dots.
  32. 청구항 31에 있어서,The method according to claim 31,
    상기 메인 연장부는 상기 제3 전류 차단층에 의해 불연속적으로 상기 제1 도전형 반도체층에 접속되는 발광 소자.The main extension part is connected to the first conductivity type semiconductor layer discontinuously by the third current blocking layer.
  33. 청구항 21에 있어서,The method according to claim 21,
    상기 제2 도전형 반도체층 상에 배치되는 제2 접속 패드; 및A second connection pad disposed on the second conductive semiconductor layer; And
    상기 제2 접속 패드로부터 연장되는 상부 연장부를 더 포함하는 발광 소자.The light emitting device further comprises an upper extension extending from the second connection pad.
  34. 청구항 33에 있어서,The method according to claim 33,
    상기 제2 도전형 반도체층 상에 위치하며, 상기 제2 도전형 반도체층에 오믹 콘택하는 오믹 전극층을 더 포함하고,An ohmic electrode layer disposed on the second conductivity type semiconductor layer and ohmic contacting the second conductivity type semiconductor layer,
    상기 제2 접속 패드 및 상기 상부 연장부는 상기 오믹 전극층 상에 위치하는 발광 소자.The second connection pad and the upper extension part are disposed on the ohmic electrode layer.
PCT/KR2017/008337 2016-08-05 2017-08-02 Light emitting device WO2018026191A1 (en)

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CN201780048307.0A CN109564958A (en) 2016-08-05 2017-08-02 Light-emitting component
US16/264,866 US10840409B2 (en) 2016-08-05 2019-02-01 Light emitting diode

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Citations (5)

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Publication number Priority date Publication date Assignee Title
JP2008210900A (en) * 2007-02-24 2008-09-11 Nichia Chem Ind Ltd Semiconductor light emitting element and light emitting device provided with the same
KR20150097990A (en) * 2014-02-19 2015-08-27 엘지이노텍 주식회사 Light emitting device and lighting apparatus
KR20160041142A (en) * 2014-10-06 2016-04-18 주식회사 세미콘라이트 Semiconductor light emitting device
JP2016100510A (en) * 2014-11-25 2016-05-30 泰谷光電科技股▲ふん▼有限公司 Light emitting diode having current diffusion structure
KR20160081392A (en) * 2014-12-31 2016-07-08 서울바이오시스 주식회사 Light emitting diode

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Publication number Priority date Publication date Assignee Title
JP2008210900A (en) * 2007-02-24 2008-09-11 Nichia Chem Ind Ltd Semiconductor light emitting element and light emitting device provided with the same
KR20150097990A (en) * 2014-02-19 2015-08-27 엘지이노텍 주식회사 Light emitting device and lighting apparatus
KR20160041142A (en) * 2014-10-06 2016-04-18 주식회사 세미콘라이트 Semiconductor light emitting device
JP2016100510A (en) * 2014-11-25 2016-05-30 泰谷光電科技股▲ふん▼有限公司 Light emitting diode having current diffusion structure
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