WO2018023363A1 - Système de simulation de défaillance - Google Patents

Système de simulation de défaillance Download PDF

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Publication number
WO2018023363A1
WO2018023363A1 PCT/CN2016/092795 CN2016092795W WO2018023363A1 WO 2018023363 A1 WO2018023363 A1 WO 2018023363A1 CN 2016092795 W CN2016092795 W CN 2016092795W WO 2018023363 A1 WO2018023363 A1 WO 2018023363A1
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WO
WIPO (PCT)
Prior art keywords
control
fault
module
power supply
chip
Prior art date
Application number
PCT/CN2016/092795
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English (en)
Chinese (zh)
Inventor
邹霞
钟玲珑
Original Assignee
邹霞
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 邹霞 filed Critical 邹霞
Priority to PCT/CN2016/092795 priority Critical patent/WO2018023363A1/fr
Publication of WO2018023363A1 publication Critical patent/WO2018023363A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]

Definitions

  • the present invention relates to a fault simulation system, and more particularly to a fault simulation system for implementing a link and a transfer relationship model, and belongs to the field of laser ranging. Background technique
  • the fault detection-based detection technology acquires the response output of the fault state under the test conditions, and designs the system to complete the automatic detection of the fault unit. It has the characteristics of high detection efficiency and accurate fault location.
  • Equipment based on hardware-in-the-loop simulation The guarantee method uses a certain method to realize the simulation of various faults, solves the difficulties in setting the faults in the actual training, and the lack of troubleshooting opportunities for the maintenance personnel. It has the characteristics of strong sense of reality, close proximity to the installation, and low cost. Modeling is the basis of simulation.
  • Simulation is one of the important purposes of modeling, and the two are inseparable.
  • System modeling is a mathematical or physical method based on the analysis or observation of the actual system, ignoring the secondary factors, to obtain a model that approximates or simplifies the actual system.
  • the established model is actually a model established according to the purpose of the research, and is an abstract description of the essential attributes of a certain aspect of the system.
  • the simulation is to use the model to reproduce the essential process occurring in the actual system. The essence is the operation of the model, which is applied to the testing, analysis or training of the system.
  • the system can be a real system or a real and conceptual system realized by the model.
  • Fault modeling was originally a concept proposed in fault diagnosis, and is a process of establishing a fault model for various failure modes in the system.
  • fault modeling technology has been developed with the development of fault diagnosis technology, and the application object has been gradually expanded.
  • the existing basic models mainly include quantitative models, qualitative models, causal dependence models, structural models, and multi-signal flow graph models.
  • System modeling and simulation technology is based on similar principles, model theory, system technology, information technology, and related professional technologies in modeling and simulation applications.
  • Computer systems, application-related physical effects devices, and simulators are Tools, using models to study, analyze, and design actual or envisioned systems A multidisciplinary and comprehensive technology for processing, production, testing, operation, evaluation and maintenance activities.
  • a fault simulation system is mainly composed of a bus control circuit, an FPGA digital system, a single chip controller, a program control conditioning circuit, an interface adaptation circuit, a serial communication module, a power supply system, and various types of equipment cables, and the FPGA digital system
  • the utility model comprises a universal fault control module, which is mainly composed of a SOPC control system, a power supply system, a single chip controller, a serial communication module, an I/O driving module, a debugging button, an LED indicating module and a socket, wherein the SOPC control system is mainly composed of an FPGA.
  • the serial communication module is mainly composed of ATmegaS MCU, MAX485 chip, ⁇ , crystal oscillator and related sockets;
  • the I/O driver module is composed of driver chip 74ALVC164245 ;
  • the button and LED indicator module are mainly Debugging buttons, DIP Jian OFF and a light emitting diode.
  • the above FPGA digital system can implement various state registration and state control, and combines design-related program-controlled peripheral conditioning circuit and control bus to realize multi-modal flexible conversion of signals.
  • the above SOPC control system can realize various types of sequence, logic and state control through corresponding VHDL programming design.
  • the power supply system has an anti-reverse protection function.
  • the serial communication module is mainly used for receiving a fault code sent by the control end of the PC, and sending the parsed fault code to the SOPC control system.
  • the above I/O driving module is used to drive various types of control signals output by the SOPC system, and reduce the output impedance thereof to improve the driving capability.
  • the above button and LED indication module are used for system debugging and various status display.
  • the present invention starts from the structure and working principle of the stable aiming control combination, and can be found by comparing the stable aiming control combination link and the transfer relationship model with the fault model and the fault conditioning board: Under normal conditions, according to the definition in the basic model The mapping effect and the transmission process, various types of simulation signals are sequentially applied and propagated in the corresponding physical simulation circuit model to simulate the function realization of the simulation object under normal working conditions; in the fault state, according to the definition in the fault model The fault link mapping mode, the general fault control module sends various state control signals according to the fault code, thereby controlling the fault mapping effect of various fault conditioning circuit models, and the generated fault signals are sequentially propagated according to the transmission relationship, eventually leading to fault phenomena.
  • the occurrence of the simulated fault is through multiple mapping and transmission of the signal, forming a fault with an indefinite number of dimensions occurring inside and outside, meeting the requirements of the fault simulation.
  • FIG. 1 is a schematic structural diagram of a fault simulation system according to the present invention.
  • FIG. 2 is a general block diagram of a general control module of the present invention
  • FIG. 3 is a circuit diagram of a power supply system of the present invention.
  • FIG. 5 is a circuit diagram of an I/O driving module of the present invention.
  • the present invention provides a fault simulation system.
  • the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
  • the fault simulation system of the present invention is mainly composed of a bus control circuit, an FPGA digital system, a single chip controller, a program control conditioning circuit, an interface adaptation circuit, a serial communication module, a power supply system, and various types of equipment cables, as shown in the figure. 1 is shown.
  • the core of the simulation design of the stable aiming control component is the FPGA digital system.
  • various state registration and state control can be realized, and the design related program-controlled peripheral conditioning circuit and control bus are realized.
  • the multi-modal flexible conversion of the signal can not only complete the stable image control combination
  • various fault modes can be set by fault injection, that is, the hardware-in-the-loop simulation of the fault link and the transfer relationship model is completed.
  • the simulation principle of the steady-motion control combination is: After the computer simulated by the single-chip controller and the adaptation circuit issues a control signal, a mode signal, and a power-on signal, the FPGA control module generates an operation required for the stabilization control process on the one hand.
  • the sequence control signal receives the fault code sent by the serial communication module, adjusts the state of the status register (normal/fault) according to the fault code, and converts the corresponding logic, and finally issues various state control signals.
  • the control program-controlled peripheral conditioning circuit outputs a corresponding electrical signal, and is connected to the equipment cable through the interface adaptation, so that the stable control combination generates various port signals for maintenance detection.
  • the stable aiming control combined simulation system not only simulates the stable tracking control function of the components, but also simulates various fault states of the stable steering control combination to meet the requirements of maintenance training fault simulation.
  • the control module is mainly composed of a SOPC control system, a power supply system, a single chip controller, a serial communication module, an I/O driving module, a debugging button, an LED indicating module, and a socket, and the block diagram thereof is shown in FIG. 2 .
  • the system uses an external DC 24V power supply to supply power uniformly, and converts the power supply voltage to ⁇ 15V, 5V, 3.3V and 1.5V required by the system through the DC/DC power supply module and the LM1117 power supply chip.
  • the power supply system has anti-reverse protection. Function, its circuit structure is shown in Figure 3.
  • the SOPC control system is mainly composed of an FPGA digital chip 1C6PQ240C8, a serial configuration chip EPCS4, a 50 MHz crystal oscillator, a filter capacitor, and related sockets.
  • the SOPC control system through the corresponding VHDL programming design, can realize various types of sequencing, logic and state control, which is the core part of the general control module.
  • the serial communication module is mainly composed of ATmega8 single chip microcomputer, MAX485 chip, Shaoguan, crystal oscillator and related sockets, and its circuit structure is shown in FIG. It is mainly used to receive the fault code sent by the PC control terminal, and send the parsed fault code to the SOPC control system.
  • the I/O driving module is composed of a driving chip 74ALVC164245, and its circuit structure is as shown in FIG. 5. It is used to drive various types of control signals output from the SOPC system, reducing its output impedance to improve drive capability.
  • the button and the LED indicating module are mainly composed of a debugging button, a dialing switch and an LED, and are used for system debugging and various status displays.
  • the fault simulation system compares the control link and the transfer relationship model by The obstacle model and the fault conditioning board can be found:
  • various types of simulation signals are sequentially applied and propagated in the corresponding physical simulation circuit model to simulate the simulation.
  • the function realization of the object under normal working conditions in the fault state, according to the fault link mapping mode defined in the fault model, the universal fault control module sends various state control signals according to the fault code, thereby controlling various fault conditioning circuit models.
  • the fault mapping effect, the generated fault signal propagates in turn according to the transmission relationship, and finally leads to the occurrence of the fault phenomenon.
  • the simulated fault is the multiple mapping and transmission of the signal, forming the dimension occurring from the inside and the outside.
  • Indefinite faults meet the requirements of fault simulation.
  • the construction of link and transfer relationship model and fault model provides a reliable way for the design and implementation of the fixed-motion control combined maintenance training fault simulation system.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

L'invention concerne un système de simulation de défaillance principalement constitué d'un circuit de commande de bus, d'un système numérique FPGA, d'un contrôleur de microordinateur monopuce, d'un circuit de conditionnement de commande par programme, d'un circuit d'adaptateur d'interface, d'un module de communication à port série, d'un système d'alimentation électrique et de divers types de câbles d'équipement. Le système numérique FPGA comprend un module de commande de défaillance général, qui est principalement constitué d'un système de commande SOPC, du système d'alimentation électrique, du contrôleur de microordinateur monopuce, du module de communication à port série, d'un module pilote d'E/S, d'un bouton de débogage, d'un module indicateur à LED, d'une prise, etc. Le système de commande SOPC est principalement constitué d'une puce numérique FPGA 1C6PQ240C8, d'une puce de configuration série EPCS4, d'un oscillateur à quartz de 50 MHz, d'un condensateur de filtrage, d'une prise associée, etc. Le système de simulation de défaillance forme, au moyen de multiples mappages et transmissions de signaux, une défaillance qui se produit de l'intérieur vers l'extérieur et qui a une dimension incertaine, satisfaisant ainsi aux exigences de la simulation de défaillance.
PCT/CN2016/092795 2016-08-02 2016-08-02 Système de simulation de défaillance WO2018023363A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/092795 WO2018023363A1 (fr) 2016-08-02 2016-08-02 Système de simulation de défaillance

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Application Number Priority Date Filing Date Title
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109948306A (zh) * 2019-05-05 2019-06-28 无锡矽杰微电子有限公司 集成化的仿真系统

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101720464A (zh) * 2007-05-09 2010-06-02 新思公司 从仿真器状态至hdl模拟器的转换
CN101877019A (zh) * 2009-04-29 2010-11-03 新思科技有限公司 符合硬件语义的逻辑模拟和/或仿真
US8121818B2 (en) * 2008-11-10 2012-02-21 Mitek Analytics Llc Method and system for diagnostics of apparatus
CN103559112A (zh) * 2013-11-05 2014-02-05 北京经纬恒润科技有限公司 一种软件故障注入方法及系统
CN105302950A (zh) * 2015-10-19 2016-02-03 北京精密机电控制设备研究所 一种软、硬件协同的可编程逻辑器件交联仿真测试方法
CN106250628A (zh) * 2016-08-02 2016-12-21 邹霞 稳瞄控制组合故障仿真系统

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101720464A (zh) * 2007-05-09 2010-06-02 新思公司 从仿真器状态至hdl模拟器的转换
US8121818B2 (en) * 2008-11-10 2012-02-21 Mitek Analytics Llc Method and system for diagnostics of apparatus
CN101877019A (zh) * 2009-04-29 2010-11-03 新思科技有限公司 符合硬件语义的逻辑模拟和/或仿真
CN103559112A (zh) * 2013-11-05 2014-02-05 北京经纬恒润科技有限公司 一种软件故障注入方法及系统
CN105302950A (zh) * 2015-10-19 2016-02-03 北京精密机电控制设备研究所 一种软、硬件协同的可编程逻辑器件交联仿真测试方法
CN106250628A (zh) * 2016-08-02 2016-12-21 邹霞 稳瞄控制组合故障仿真系统

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109948306A (zh) * 2019-05-05 2019-06-28 无锡矽杰微电子有限公司 集成化的仿真系统
CN109948306B (zh) * 2019-05-05 2024-02-02 无锡矽杰微电子有限公司 集成化的仿真系统

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