WO2018018878A1 - 像素排列结构、像素电路、显示面板及驱动方法 - Google Patents

像素排列结构、像素电路、显示面板及驱动方法 Download PDF

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Publication number
WO2018018878A1
WO2018018878A1 PCT/CN2017/073790 CN2017073790W WO2018018878A1 WO 2018018878 A1 WO2018018878 A1 WO 2018018878A1 CN 2017073790 W CN2017073790 W CN 2017073790W WO 2018018878 A1 WO2018018878 A1 WO 2018018878A1
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transistor
pixel
sub
signal
circuit
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PCT/CN2017/073790
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English (en)
French (fr)
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吴渊
蒋璐霞
代弘伟
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to EP17761174.6A priority Critical patent/EP3493188B1/en
Priority to US15/557,721 priority patent/US10565918B2/en
Publication of WO2018018878A1 publication Critical patent/WO2018018878A1/zh

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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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    • H10K59/30—Devices specially adapted for multicolour light emission
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    • H—ELECTRICITY
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Definitions

  • Embodiments of the present disclosure relate to a pixel arrangement structure, a pixel circuit, a display panel, and a driving method.
  • organic light-emitting diode (OLED) display panels have self-illumination, high contrast, thin thickness, wide viewing angle, fast response speed, can be used for flexible panels, wide temperature range, simple manufacturing, etc., and have broad development. prospect.
  • the organic light emitting diode (OLED) display panel can be applied to a device having a display function such as a mobile phone, a display, a notebook computer, a digital camera, an instrument meter, and the like.
  • An embodiment of the present disclosure provides a pixel arrangement structure, including: a first pixel unit including a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, wherein a center of the first sub-pixel Coinciding with a first vertex of the first virtual diamond, a center of the second sub-pixel coincides with a second vertex of the first virtual diamond, a center of the third sub-pixel and a third of the first virtual diamond The vertices coincide, and the center of the fourth sub-pixel coincides with the fourth vertice of the first virtual diamond.
  • the first vertex, the second vertex, the third vertex, and the fourth vertex of the first virtual diamond are sequentially adjacent to each other, and the first sub-pixel and the first The three sub-pixels are rectangular, and the second sub-pixel and the fourth sub-pixel are triangular.
  • the rectangle is a square
  • the triangle is an isosceles triangle
  • a vertical line of one side of the rectangle passes through a center of the first virtual diamond, and a vertical line of one side of the triangle passes through the first virtual diamond center.
  • the first sub-pixel emits light of a first color when in operation
  • the second sub-pixel emits light of a second color when in operation
  • the The three sub-pixels emit light of a third color when in operation
  • the fourth sub-pixel emits light of a fourth color when in operation.
  • the mixed color of the second color and the fourth color is a first color or a third color.
  • the mixed color of the first color and the third color is white.
  • the first color is blue
  • the second color is green
  • the third color is yellow
  • the fourth color is red.
  • the pixel arrangement structure provided by the embodiment of the present disclosure further includes: a second pixel unit, including a fifth sub-pixel, a sixth sub-pixel, a seventh sub-pixel, and an eighth sub-pixel, wherein a center of the fifth sub-pixel Coincident with a first vertex of the second virtual diamond, a center of the sixth sub-pixel coincides with a second vertex of the second virtual diamond, a center of the seventh sub-pixel and a third of the second virtual diamond a vertex coincides, a center of the eighth sub-pixel coincides with a fourth vertex of the second virtual diamond; and a third pixel unit includes a ninth sub-pixel, a tenth sub-pixel, an eleventh sub-pixel, and a twelfth sub-pixel a pixel, wherein a center of the ninth sub-pixel coincides with a first vertex of the third virtual diamond, and a center of the tenth sub-pixel coincides with a second vertex of the third virtual diamond, the eleventh sub-
  • the virtual triangle is an acute triangle.
  • the virtual triangle is an isosceles acute triangle.
  • the virtual triangle is an equilateral triangle.
  • the shapes of the first dummy diamond, the second dummy diamond, and the third dummy diamond are the same.
  • the first vertex, the second vertex, the third vertex, and the fourth vertex of the first virtual diamond are sequentially adjacent to each other, and the second virtual diamond a vertex, a second vertex, a third vertex, and a fourth vertex are sequentially adjacent to each other, and the first vertex, the second vertex, the third vertex, and the fourth vertex of the third virtual diamond are sequentially adjacent to each other, the first sub-pixel
  • the fifth sub-pixel and the ninth sub-pixel have the same shape
  • the second sub-pixel, the sixth sub-pixel, and the tenth sub-pixel have the same shape
  • the seventh sub-pixel and the eleventh sub-pixel have the same shape
  • the fourth sub-pixel, the eighth sub-pixel, and the twelfth sub-pixel have the same shape.
  • the first sub-pixel, the third sub-pixel, the fifth sub-pixel, the seventh sub-pixel, the ninth sub-pixel, and the eleventh sub-pixel are rectangular
  • the second sub-pixel, the fourth sub-pixel, the sixth sub-pixel, the eighth sub-pixel, the tenth sub-pixel, and the twelfth sub-pixel are triangular.
  • the rectangle is a square
  • the triangle is an isosceles triangle
  • a vertical line of one side of the rectangle passes through a center of one of the virtual diamonds
  • a vertical line of one side of the triangle passes through a center of one of the virtual diamonds.
  • the first sub-pixel, the fifth sub-pixel, and the ninth sub-pixel emit light of a first color when in operation
  • the second sub-pixel The sixth sub-pixel and the tenth sub-pixel emit light of a second color when in operation
  • the third sub-pixel, the seventh sub-pixel, and the eleventh sub-pixel emit a first
  • the three-color light, the fourth sub-pixel, the eighth sub-pixel, and the twelfth sub-pixel emit light of a fourth color when in operation.
  • the mixed color of the second color and the fourth color is a first color or a third color.
  • the mixed color of the first color and the third color is white.
  • the first color is blue
  • the second color is green
  • the third color is yellow
  • the fourth color is red.
  • An embodiment of the present disclosure further provides a pixel circuit, including: a first lighting circuit for emitting light during operation; a first driving circuit for driving the first lighting circuit; and a first compensation circuit for compensating a first driving circuit; a first data writing circuit for writing to the first driving circuit Input data; a first reset circuit for resetting the first driving circuit; a first storage circuit for storing a driving voltage of the first driving circuit; and a first initializing circuit for using the first light emitting a first lighting control circuit for controlling operation and shutdown of the first lighting circuit; a first power terminal for providing a first lighting voltage to the first lighting circuit; and a second power terminal for Providing a second lighting voltage to the first lighting circuit; a third power terminal for providing a reset voltage to the first reset circuit; and a first data signal terminal for providing the first data writing circuit a first data signal or a standby signal; a first control terminal for providing a first control signal for controlling operation and shutdown of the first reset circuit; and a second control terminal for providing control of the first data write circuit
  • the first data writing circuit includes a first transistor
  • the first lighting control circuit includes a second transistor and a fifth transistor
  • the first compensation circuit includes a first a third transistor
  • the first driving circuit includes a fourth transistor
  • the first reset circuit includes a sixth transistor
  • the first initialization circuit includes a seventh transistor
  • the first storage circuit includes a first storage capacitor
  • the first lighting circuit includes a first organic light emitting diode.
  • a source of the first transistor is electrically connected to the first data signal end, a gate of the first transistor, a gate of the third transistor, and The second control terminal is electrically connected, and a drain of the first transistor, a drain of the second transistor, a source of the third transistor, and a source of the fourth transistor are electrically connected; a gate of the second transistor, a gate of the fifth transistor, and the fourth control terminal are electrically connected, a source of the second transistor, a first end of the first storage capacitor, and the first power terminal Electrically connecting; a drain of the third transistor and a first node are electrically connected; a gate of the fourth transistor is electrically connected to the first node, a drain of the fourth transistor, and a drain of the fifth transistor a source electrically connected; a drain of the fifth transistor, a drain of the seventh transistor, and a first end of the first organic light emitting diode are electrically connected; a source of the sixth transistor, the
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the The seventh transistor is a thin film transistor.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the The seventh transistor is a P-type transistor.
  • An embodiment of the present disclosure further provides a pixel circuit, including: a second lighting circuit for emitting light during operation; a second driving circuit for driving the second lighting circuit; and a second compensation circuit for compensating a second driving circuit; a second data writing circuit for writing data to the second driving circuit; a second reset circuit for resetting the second driving circuit; and a second storage circuit for storing a driving voltage of the second driving circuit; a second initializing circuit for initializing the second lighting circuit; and a second lighting control circuit for controlling operation and shutdown of the second lighting circuit; For transmitting the second data signal or the third data signal to the second data writing circuit; the first power terminal is configured to provide the first lighting voltage to the second lighting circuit; and the second power terminal is used Providing a second lighting voltage to the second lighting circuit; a third power terminal for providing a reset voltage to the second reset circuit; and a second data signal terminal for providing the second data writing circuit First a data signal or a standby signal; a third data signal end, configured to provide a third data signal or a stand
  • the second data writing circuit includes an eighth transistor
  • the second lighting control circuit includes a ninth transistor and a twelfth transistor
  • the second compensation circuit includes a tenth transistor
  • the second driving circuit includes an eleventh transistor
  • the second reset circuit includes a thirteenth transistor
  • the second initialization circuit includes a fourteenth transistor
  • the second storage circuit includes a second storage And a second light emitting circuit comprising a second organic light emitting diode, a third organic light emitting diode, a fifteenth transistor and a sixteenth transistor, wherein the gate circuit comprises a seventeenth transistor and an eighteenth transistor.
  • the source and the source of the eighth transistor The drain of the seventeenth transistor is electrically connected to the drain of the eighteenth transistor, the gate of the eighth transistor, the gate of the tenth transistor, and the second control terminal are electrically connected, a drain of the eighth transistor, a drain of the ninth transistor, a source of the tenth transistor, and a source of the eleventh transistor; a gate of the ninth transistor, the tenth a gate of the second transistor and the fourth control terminal are electrically connected, a source of the ninth transistor, a first end of the second storage capacitor and the first power terminal are electrically connected; the tenth transistor The drain and the second node are electrically connected; the gate of the eleventh transistor is electrically connected to the second node, and the drain of the eleventh transistor and the source of the twelfth transistor are electrically connected; a drain of the twelfth transistor, a drain of the fourteenth transistor, a source of the fifteenth transistor,
  • the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth The transistor, the fourteenth transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, and the eighteenth transistor are all thin film transistors.
  • the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth The transistor, the fourteenth transistor, the fifteenth transistor, and the sixteenth transistor are all P-type transistors, and the seventeenth transistor and the eighteenth transistor are both N-type transistors.
  • Embodiments of the present disclosure also provide a display panel including the image according to any embodiment of the present disclosure. Prime arrangement.
  • Embodiments of the present disclosure also provide a display panel including the pixel circuit of any of the embodiments of the present disclosure.
  • a pixel circuit according to an embodiment of the present disclosure includes a pixel arrangement structure according to any one of the embodiments of the present disclosure, and a pixel circuit according to any one of the embodiments of the present disclosure.
  • a light-emitting circuit emits blue or yellow light during operation; the second light-emitting circuit in the pixel circuit provided by the embodiment of the present disclosure emits red or green light during operation.
  • An embodiment of the present disclosure further provides a driving method of a pixel circuit, including: a reset phase, a compensation phase, an initialization phase, and an illumination phase, wherein, in the reset phase, the first control terminal outputs a valid signal, where the The second control terminal outputs an invalid signal, the third control terminal outputs an invalid signal, the fourth control terminal outputs an invalid signal, and the first data signal terminal outputs a standby signal; in the compensation phase, the first control terminal Outputting an invalid signal, the second control terminal outputs a valid signal, the third control terminal outputs an invalid signal, the fourth control terminal outputs an invalid signal, and the first data signal terminal outputs a first data signal; In the initialization phase, the first control terminal outputs an invalid signal, the second control terminal outputs an invalid signal, the third control terminal outputs a valid signal, and the fourth control terminal outputs an invalid signal, and the first data signal end Outputting a first data signal; in the lighting phase, the first control terminal outputs an invalid signal, and the second control terminal outputs an invalid signal,
  • the driving method provided by the above embodiment of the present disclosure may further include: a pre-reset phase and a pre-lighting phase, wherein the pre-reduction phase is after the lighting phase and before the reset phase, the pre-lighting phase is After the initialization phase and before the lighting phase, in the pre-reset phase, the first control terminal outputs an invalid signal, the second control terminal outputs an invalid signal, and the third control terminal outputs an invalid signal, the first The fourth control terminal outputs an invalid signal, the first data signal terminal outputs a standby signal; in the pre-lighting phase, the first control terminal outputs an invalid signal, and the second control terminal outputs an invalid signal, the third control The terminal outputs an invalid signal, the fourth control terminal outputs an invalid signal, and the first data signal terminal outputs the first data signal.
  • An embodiment of the present disclosure further provides a driving method of a pixel circuit, including: a reset phase, a compensation phase, an initialization phase, and an illumination phase, wherein, in the reset phase, the first control terminal outputs a valid signal, where the The second control terminal outputs an invalid signal, and the third control terminal outputs an invalid signal.
  • the fourth control terminal outputs an invalid signal, the second data signal terminal outputs a standby signal, and the third data signal terminal outputs a standby signal; in the compensation phase, the first control terminal outputs an invalid signal, The second control terminal outputs an effective signal, the third control terminal outputs an invalid signal, the fourth control terminal outputs an invalid signal, and the second data signal terminal outputs a second data signal, and the third data signal end Outputting a standby signal; in the initializing phase, the first control terminal outputs an invalid signal, the second control terminal outputs an invalid signal, the third control terminal outputs an effective signal, and the fourth control terminal outputs an invalid signal, The second data signal end outputs a second data signal, and the third data signal end outputs a standby signal; in the lighting stage, the first control end outputs an invalid signal, and the second control end outputs an invalid signal, The third control terminal outputs an invalid signal, the fourth control terminal outputs a valid signal, and the second data signal terminal outputs a second data signal, the third data The number terminal outputs
  • the driving method provided by the above embodiment of the present disclosure may further include: a pre-reset phase and a pre-lighting phase, wherein the pre-reduction phase is after the lighting phase and before the reset phase, the pre-lighting phase is After the initialization phase and before the lighting phase, in the pre-reset phase, the first control terminal outputs an invalid signal, the second control terminal outputs an invalid signal, and the third control terminal outputs an invalid signal, the first The fourth control terminal outputs an invalid signal, the second data signal terminal outputs a standby signal, and the third data signal terminal outputs a standby signal; in the pre-lighting phase, the first control terminal outputs an invalid signal, and the second The control terminal outputs an invalid signal, and the third control The terminal outputs an invalid signal, the fourth control terminal outputs an invalid signal, the second data signal terminal outputs a second data signal, and the third data signal terminal outputs a standby signal; or the second data signal terminal outputs a standby signal, the third data signal terminal outputs a third data signal, the
  • the pixel arrangement structure, the pixel circuit, the display panel and the driving method can reduce the distance between the sub-pixels, and can also reduce the area occupied by the pixel circuit, thereby improving the resolution of the display panel, and can be in the process of being driven.
  • the organic light emitting diode performs initializing discharge to ensure the accuracy of low gray scale and the total black under the full dark state image, thereby effectively improving the contrast of the entire display panel.
  • FIG. 1 is a schematic diagram of a pixel arrangement structure according to an embodiment of the present disclosure
  • FIG. 2 is a second schematic diagram of a pixel arrangement structure according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 4 is a second schematic view of a display panel according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 6 is a second schematic diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 7 is a driving timing diagram of the pixel circuit shown in FIG. 6 according to an embodiment of the present disclosure.
  • FIG. 8A is a schematic diagram of a conductive state in a pre-reset phase when the pixel circuit shown in FIG. 6 is driven by the driving timing shown in FIG. 7 according to an embodiment of the present disclosure
  • FIG. 8B is a schematic diagram of a conductive state in a reset phase when the pixel circuit shown in FIG. 6 is driven by the driving timing shown in FIG. 7 according to an embodiment of the present disclosure
  • FIG. 8C is a schematic diagram of a conductive state in a compensation phase when the pixel circuit shown in FIG. 6 is driven by the driving timing shown in FIG. 7 according to an embodiment of the present disclosure
  • FIG. 8D is a schematic diagram of a conductive state in an initialization phase when the pixel circuit shown in FIG. 6 is driven by the driving timing shown in FIG. 7 according to an embodiment of the present disclosure
  • FIG. 8E is a schematic diagram of a conductive state in a pre-lighting phase when the pixel circuit shown in FIG. 6 is driven by the driving timing shown in FIG. 7 according to an embodiment of the present disclosure
  • FIG. 8F is a diagram showing the pixel circuit shown in FIG. 6 as shown in FIG. Schematic diagram of the conduction state of the light-emitting phase during dynamic timing driving;
  • FIG. 9 is a schematic diagram of still another pixel circuit according to an embodiment of the present disclosure.
  • FIG. 10 is a second schematic diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 11 is a timing chart of driving when the second organic light emitting diode is separately illuminated in the pixel circuit shown in FIG. 10 according to an embodiment of the present disclosure
  • FIG. 12A is a schematic diagram of a conductive state in a pre-reset phase when the pixel circuit shown in FIG. 10 is driven by the driving timing shown in FIG. 11 according to an embodiment of the present disclosure
  • FIG. 12B is a schematic diagram of a conductive state in a reset phase when the pixel circuit shown in FIG. 10 is driven by the driving timing shown in FIG. 11 according to an embodiment of the present disclosure
  • FIG. 12C is a schematic diagram of a conductive state in a compensation phase when the pixel circuit shown in FIG. 10 is driven by the driving timing shown in FIG. 11 according to an embodiment of the present disclosure
  • FIG. 12D is a schematic diagram of a conductive state in an initialization phase when the pixel circuit shown in FIG. 10 is driven by the driving timing shown in FIG. 11 according to an embodiment of the present disclosure
  • FIG. 12E is a schematic diagram of a conductive state in a pre-lighting phase when the pixel circuit shown in FIG. 10 is driven by the driving timing shown in FIG. 11 according to an embodiment of the present disclosure
  • FIG. 12F is a schematic diagram showing a conductive state of the pixel circuit shown in FIG. 10 in the light emitting phase when the pixel circuit shown in FIG. 10 is driven by the driving timing shown in FIG. 11;
  • FIG. 13 is a schematic diagram of still another display panel according to an embodiment of the present disclosure.
  • An organic light emitting diode (OLED) display panel generally includes a plurality of pixel units, each of which includes a plurality of sub-pixels of an OLED capable of emitting light of different colors, and the OLEDs in each sub-pixel can be driven by respective pixel circuits, however, the pixel circuits The occupied area is large, so that the area of the sub-pixel cannot be further reduced, which affects the resolution of the display panel.
  • Embodiments of the present disclosure provide a pixel arrangement structure, a pixel circuit, a display panel, and a driving method, which can reduce the distance between sub-pixels while reducing the area occupied by the pixel circuit, thereby improving the resolution of the display panel, and
  • the OLED can be initialized and discharged, ensuring the accuracy of the low gray level and the total black under the full dark state picture, effectively improving the contrast of the entire display panel.
  • an embodiment of the present disclosure provides a pixel arrangement structure 10 including: a first pixel unit 100 including a first sub-pixel 110 , a second sub-pixel 120 , and a third sub-pixel
  • the pixel 130, the fourth sub-pixel 140, the center of the first sub-pixel 110 coincides with the first vertex of the first virtual diamond 150
  • the center of the second sub-pixel 120 coincides with the second vertex of the first virtual diamond 150
  • the third sub- The center of the pixel 130 coincides with the third vertex of the first virtual diamond 150
  • the center of the fourth sub-pixel 140 coincides with the fourth vertex of the first virtual diamond 150.
  • first virtual diamond 150 is only used to explain the positional relationship of the first sub-pixel 110, the second sub-pixel 120, the third sub-pixel 130, and the fourth sub-pixel 140. In the actual pixel arrangement structure 10, the actual structure of the first dummy diamond 150 does not exist.
  • the first vertex, the second vertex, the third vertex, and the fourth vertex of the first virtual diamond 150 are sequentially adjacent. That is, the first sub-pixel 110, the second sub-pixel 120, the third sub-pixel 130, and the fourth sub-pixel 140 are sequentially adjacent.
  • the first sub-pixel 110 and the second sub-pixel 120 are The third sub-pixel 130 and the fourth sub-pixel 140 are arranged in a clockwise direction.
  • first sub-pixel 110 and the third sub-pixel 130 are rectangular, and the second sub-pixel 120 and the fourth sub-pixel 140 are triangular.
  • the first sub-pixel 110 and the third sub-pixel 130 are square, and the second sub-pixel 120 and the fourth sub-pixel 140 are isosceles triangles.
  • the vertical line L1 of one side of the first sub-pixel 110 passes through the center of the first dummy diamond 150, and the second sub-pixel 120
  • the vertical line L2 of the bottom edge passes through the center of the first dummy diamond 150
  • the vertical line (not shown) of one side of the third sub-pixel 130 passes through the center of the first dummy diamond 150
  • the bottom edge of the fourth sub-pixel 140 The mid-perpendicular line (not shown) passes through the center of the first virtual diamond 150. That is, the first sub-pixel 110, the second sub-pixel 120, the third sub-pixel 130, and the fourth sub-pixel 140 are disposed opposite the center of the first dummy diamond 150.
  • the arrangement manner of the first sub-pixel 110, the second sub-pixel 120, the third sub-pixel 130, and the fourth sub-pixel 140 includes but is not limited to the case shown in FIG. 1, and may be other arrangements. the way.
  • one vertex of the first sub-pixel is disposed opposite the center of the first virtual diamond
  • one vertex of the second sub-pixel is disposed opposite the center of the first virtual diamond
  • one vertex of the third sub-pixel is opposite to the first virtual diamond Centered
  • one vertex of the fourth sub-pixel is set to the center of the first virtual diamond.
  • the pixel arrangement structure provided by the embodiment of the present disclosure can reduce the distance between sub-pixels, and more sub-pixels can be set in a unit area, that is, the display resolution is improved.
  • the first sub-pixel 110 emits light of a first color when in operation
  • the second sub-pixel 120 emits light of a second color when in operation
  • the third sub-pixel 130 The third color of light is emitted during operation
  • the fourth sub-pixel 140 emits a fourth color of light during operation.
  • the mixed color of the second color and the fourth color may be the first color or the third color.
  • the mixed color of the first color and the third color may be white.
  • the first color is blue
  • the second color is green
  • the third color is yellow
  • the fourth color is red
  • the mixed color of the second color green and the fourth color red is the third color yellow
  • the mixed color of the first color blue and the third color yellow is white.
  • the third color light emitted by the third sub-pixel may be used instead of the second color light emitted by the second sub-pixel and the fourth color light of the fourth sub-pixel, and the fourth color
  • the sub-pixel emits light of the fourth color as a supplement, that is, only the first sub-pixel, the third sub-pixel, and the fourth sub-pixel emit light, and the second sub-pixel does not emit light;
  • the third color of the light emitted by the third sub-pixel and the light of the fourth color emitted by the fourth sub-pixel may be used instead of the second sub-pixel.
  • the light of the second color is emitted as a supplement, that is, only the first sub-pixel, the second sub-pixel, and the third sub-pixel emit light, and the fourth sub-pixel does not emit light.
  • the fourth sub-pixel does not emit light.
  • the pixel arrangement structure provided by the embodiment of the present disclosure uses four-color pixel display, which can ensure various picture pixel ratio equalization and wide color gamut.
  • embodiments of the present disclosure include, but are not limited to, the case where the first color is blue, the second color is green, the third color is yellow, and the fourth color is red.
  • the combination of display colors can be flexibly adjusted according to the actual needs of the display.
  • the pixel arrangement structure 10 provided by the embodiment of the present disclosure may further include a second pixel unit 200 and a third pixel unit 300 .
  • the second pixel unit 200 includes a fifth sub-pixel 210, a sixth sub-pixel 220, a seventh sub-pixel 230, and an eighth sub-pixel 240.
  • the center of the fifth sub-pixel 210 coincides with the first vertex of the second virtual diamond 250
  • the center of the sixth sub-pixel 220 coincides with the second vertex of the second virtual diamond 250
  • the third vertex of 250 coincides
  • the center of the eighth sub-pixel 240 coincides with the fourth vertex of the second virtual diamond 250.
  • the third pixel unit 300 includes a ninth sub-pixel 310, a tenth sub-pixel 320, an eleventh sub-pixel 330, and a twelfth sub-pixel 340.
  • the center of the ninth sub-pixel 310 coincides with the first vertex of the third virtual diamond 350
  • the center of the tenth sub-pixel 320 coincides with the second vertex of the third virtual diamond 350
  • the third vertex of the diamond 350 coincides
  • the center of the twelfth sub-pixel 340 coincides with the fourth vertex of the third virtual diamond 350.
  • the center of the first virtual diamond 150 coincides with the first vertex 410 of the virtual triangle 400
  • the center of the second virtual diamond 250 coincides with the second vertex 420 of the virtual triangle 400
  • the third vertex 430 coincides.
  • the second virtual diamond 250 and the third virtual diamond 350 are only used to describe the positional relationship of the corresponding sub-pixels, and the virtual triangle 400 is only used to describe the first pixel unit 100, the second pixel unit 200, and the third pixel unit. 300 positional relationship.
  • the actual structure of the second dummy diamond 250, the third dummy diamond 350, and the virtual triangle 400 does not exist.
  • the virtual triangle 400 is sharp. Angular triangle. That is, the third pixel unit 300 is not aligned with the first pixel unit 100 or the second pixel unit 200 in the vertical direction, but is located in the first pixel unit 100 and the second pixel unit 200 in the vertical direction. between. This arrangement can further reduce the distance between sub-pixels, thereby increasing the display resolution.
  • the virtual triangle 400 is an isosceles acute triangle.
  • the virtual triangle 400 is an equilateral triangle.
  • the shapes of the first dummy diamond 150, the second dummy diamond 250, and the third dummy diamond 350 are the same.
  • the first vertex, the second vertex, the third vertex, and the fourth vertex of the first virtual diamond 150 are adjacent to each other, and the first vertex of the second virtual diamond 250 is The second vertex, the third vertex, and the fourth vertex are sequentially adjacent to each other, and the first vertex, the second vertex, the third vertex, and the fourth vertex of the third virtual diamond 350 are sequentially adjacent to each other, and the first sub-pixel 110 and the fifth sub-pixel
  • the shape of the second sub-pixel 120, the sixth sub-pixel 220, and the tenth sub-pixel 320 are the same, and the third sub-pixel 130, the seventh sub-pixel 230, and the eleventh sub-pixel 330 are the same.
  • the shapes of the fourth sub-pixel 140, the eighth sub-pixel 240, and the twelfth sub-pixel 340 are the same.
  • the first sub-pixel 110, the third sub-pixel 130, the fifth sub-pixel 210, the seventh sub-pixel 230, the ninth sub-pixel 310, and the eleventh sub-pixel 330 is a rectangle
  • the second sub-pixel 120, the fourth sub-pixel 140, the sixth sub-pixel 220, the eighth sub-pixel 240, the tenth sub-pixel 320, and the twelfth sub-pixel 340 are triangular.
  • the first sub-pixel 110, the third sub-pixel 130, the fifth sub-pixel 210, the seventh sub-pixel 230, the ninth sub-pixel 310, and the eleventh sub-pixel 330 is a square
  • the second sub-pixel 120, the fourth sub-pixel 140, the sixth sub-pixel 220, the eighth sub-pixel 240, the tenth sub-pixel 320, and the twelfth sub-pixel 340 are isosceles triangles.
  • the vertical line of one side of the fifth sub-pixel 210 passes through the center of the second virtual diamond 250, and the vertical line of one side of the seventh sub-pixel 230 passes the second virtual At the center of the diamond 250, the mid-perpendicular line of one side of the ninth sub-pixel 310 passes through the center of the third virtual diamond 350, and the mid-perpendicular line of one side of the eleventh sub-pixel 330 passes through the third virtual diamond 350. center of.
  • the mid-perpendicular line of the bottom side of the sixth sub-pixel 220 passes through the center of the second virtual diamond 250
  • the mid-perpendicular line of the bottom side of the eighth sub-pixel 240 passes through the center of the second virtual diamond 250
  • the bottom of the tenth sub-pixel 320 The mid-perpendicular line passes through the center of the third virtual diamond 350
  • the mid-perpendicular line of the bottom edge of the twelfth sub-pixel 340 passes through the center of the third virtual diamond 350.
  • the first sub-pixel 110, the fifth sub-pixel 210, and the ninth sub-pixel 310 emit light of a first color when operating
  • the second sub-pixel 120, sixth The sub-pixel 220 and the tenth sub-pixel 320 emit light of a second color when in operation
  • the third sub-pixel 130, the seventh sub-pixel 230, and the eleventh sub-pixel 330 emit light of a third color when in operation
  • the pixel 140, the eighth sub-pixel 240, and the twelfth sub-pixel 340 emit light of a fourth color when in operation.
  • the mixed color of the second color and the fourth color is the first color or the third color.
  • the mixed color of the first color and the third color is white.
  • the first color is blue
  • the second color is green
  • the third color is yellow
  • the fourth color is red.
  • the ninth sub-pixel and the eleventh sub-pixel emit light; when displaying a colorful picture with a higher gray level of the fourth color, the light of the third color may be used instead of the combined color of the light of the second color and the fourth color. That is, the second sub-pixel, the sixth sub-pixel, and the tenth sub-pixel do not emit light; when the second color of the second color is displayed, the light of the third color may be used instead of the second color and the fourth color.
  • the combined color of the light that is, the fourth sub-pixel, the eighth sub-pixel, and the twelfth sub-pixel does not emit light.
  • the grayscale picture when displaying the grayscale picture, only two sub-pixels are illuminated in each pixel unit, and when displaying a colorful picture, only three sub-pixels are illuminated in each pixel unit, which can save power.
  • the pixel arrangement structure provided by the embodiment of the present disclosure uses four-color pixel display, which can ensure various picture pixel ratio equalization and wide color gamut.
  • the embodiment of the present disclosure further provides a display panel 1.
  • the display panel 1 includes a pixel arrangement structure provided by any embodiment of the present disclosure.
  • the display panel 1 includes m rows and n columns of pixels. As shown in FIG. 3, the display panel 1 includes a first sub-pixel 110, a second sub-pixel 120, a third sub-pixel 130, a fourth sub-pixel 140, and five sub-pixels.
  • the first sub-pixel 110, the second sub-pixel 120, the third sub-pixel 130, the fourth sub-pixel 140, the five-sub-pixel 210, the sixth sub-pixel 220, the seventh sub-pixel 230, and the eighth sub-pixel 240 are located on the display panel 1.
  • the ninth sub-pixel 310, the tenth sub-pixel 320, the eleventh sub-pixel 330, and the twelfth sub-pixel 340 are located in the second row of the display panel 1.
  • the pixel arrangement structure causes the even rows in the display panel 1 described in FIG. 3 to form a gap near the edge of the display panel, in order to fill the gap, the sub-pixels may be further supplemented at the edge of the display panel 1 according to actual conditions.
  • the second supplemental sub-pixel 320' is supplemented on the left edge of the second row, and the first supplemental sub-pixel 310', the third supplemental sub-pixel 330' and the The four sub-pixels 340' are complemented and similar processing is performed on other spaces.
  • the area of the display panel can be fully utilized to ensure uniform distribution of sub-pixels, and the influence of the edge gap of the display panel on the display effect can be reduced or avoided.
  • the pixels may be re-divided.
  • the first row of pixels are P11, P12, ..., P1n from left to right, respectively; From top to bottom are P11, P21, ..., Pm1.
  • FIG. 5 is one schematic diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • an embodiment of the present disclosure further provides a pixel circuit 500, including: a first lighting circuit 502 for emitting light during operation; and a first driving circuit 504 for driving the first lighting circuit 502; a compensation circuit 506 for compensating the first driving circuit 504; a first data writing circuit 508 for writing data to the first driving circuit 504; and a first reset circuit 510 for resetting the first driving circuit 504;
  • the first storage circuit 512 is configured to store the driving voltage of the first driving circuit 504;
  • the first initialization circuit 514 is configured to initialize the first lighting circuit 502; and the first lighting control circuit 516 is configured to control the first lighting circuit 502.
  • the first lighting control circuit 516 includes a first portion 516A and a second portion 516B; a first power terminal ELVDD for providing a first lighting voltage Velvdd to the first lighting circuit 502; a second power terminal ELVSS, The second lighting voltage Velvss is provided to the first lighting circuit 502; the third power terminal Vx is used to provide the first reset circuit 510 a first reset signal Vvx; a first data signal end Data1 for providing a first data signal or a standby signal to the first data write circuit 508; a first control terminal Sn-1 for providing control of the first reset circuit 510 and Turning off the first control signal; the second control terminal Sn is configured to provide a second control signal for controlling the first data writing circuit 508 and the first compensation circuit 506 to operate and turn off; the third control terminal Sn+1 is used Providing a third control signal for controlling the operation and shutdown of the first initialization circuit 514; and a fourth control terminal En for providing a fourth control signal for controlling the operation
  • FIG. 6 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure, and FIG. 6 is a specific implementation of the pixel circuit shown in FIG. 5.
  • the first data writing circuit 508 includes a first transistor T1
  • the first lighting control circuit 516 includes a second transistor T2 and a fifth transistor T5.
  • the first portion 516A of the first illumination control circuit 516 includes a second transistor T2
  • the second portion 516B of the first illumination control circuit 516 includes a fifth transistor T5
  • the first compensation circuit 506 includes a third transistor T3
  • the first driver The circuit 504 includes a fourth transistor T4
  • the first reset circuit 510 includes a sixth transistor T6
  • the first initialization circuit 514 includes a seventh transistor T7
  • the first storage circuit 512 includes a first storage capacitor C1
  • the first lighting circuit 502 includes a first Organic light emitting diode OLED1.
  • the third transistor T3 includes a first sub-transistor and a second sub-transistor connected in series.
  • the source of the first sub-transistor serves as the source of the third transistor T3, and the drain and the first sub-transistor
  • the source of the second sub-transistor is electrically connected, the drain of the second sub-transistor serves as the drain of the third transistor T3, and the gate of the first sub-transistor and the gate of the second sub-transistor are electrically connected together as a gate of the third transistor T3. pole.
  • the embodiment of the present disclosure includes, but is not limited to, the composition of the third transistor T3.
  • the third transistor T3 may also include only one transistor, or may be a dual gate transistor.
  • the source of the first transistor T1 is electrically connected to the first data signal terminal Data1, the gate of the first transistor T1, and the third transistor T3.
  • the gate and the second control terminal Sn are electrically connected, the drain of the first transistor T1, the drain of the second transistor T2, the source of the third transistor T3 and the source of the fourth transistor T4 are electrically connected;
  • the second transistor T2 The gate of the gate, the fifth transistor T5 and the fourth control terminal En are electrically connected, the source of the second transistor T2, the first end of the first storage capacitor C1 and the first power supply terminal ELVDD are electrically connected;
  • the third transistor T3 The drain is electrically connected to the first node N1; the gate of the fourth transistor T4 and the first The node N1 is electrically connected, the drain of the fourth transistor T4 and the source of the fifth transistor T5 are electrically connected; the drain of the fifth transistor T5, the drain of the seventh transistor T7 and the first end of the first organic
  • the first organic light emitting diode OLED1 emits blue light or yellow light during operation.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all Thin film transistor.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all P-type transistor.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other switching devices having the same characteristics.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain of the transistor can be physically indistinguishable.
  • one of the extreme source and the other is the drain. Therefore, the source and the drain of all or part of the transistor in the embodiment of the present disclosure. It is interchangeable as needed.
  • the transistors can be divided into N-type and P-type transistors according to the characteristics of the transistors.
  • Embodiments of the present disclosure also provide a driving method of a pixel circuit as shown in FIG. 6, which includes a reset phase, a compensation phase, an initialization phase, and an illumination phase.
  • the first control terminal Sn-1 outputs an effective signal
  • the second control terminal Sn outputs an invalid signal
  • the third control terminal Sn+1 outputs an invalid signal
  • the fourth control terminal En outputs an invalid signal
  • the first data signal terminal Data1 The standby signal is output; in the compensation phase, the first control terminal Sn-1 outputs an invalid signal, the second control terminal Sn outputs an effective signal, the third control terminal Sn+1 outputs an invalid signal
  • the first data signal end Data1 outputs a first data signal; in the initialization phase, the first control terminal Sn-1 outputs an invalid signal, the second control terminal Sn outputs an invalid signal, and the third control terminal Sn+1 outputs an effective signal, and the fourth control The terminal En outputs an invalid signal, and the first data signal end Data1 outputs a first data signal; in the light emitting phase, the first control terminal Sn-1 outputs an invalid signal, the second control terminal Sn outputs an invalid signal, and the third control terminal Sn+1 outputs The invalid signal, the fourth control terminal En outputs a valid signal, and the first data signal terminal Data1 outputs the first data signal.
  • the driving method provided by the embodiment of the present disclosure may further include: a pre-reset phase and a pre-lighting phase.
  • the pre-reset phase is after the illumination phase and before the reset phase
  • the pre-emission phase is after the initialization phase and before the illumination phase
  • the first control terminal Sn-1 outputs an invalid signal
  • the second control terminal Sn outputs an invalid signal
  • the third control terminal Sn+1 outputs an invalid signal
  • the fourth control terminal En outputs an invalid signal
  • the first data signal terminal Data1 outputs a standby signal
  • the first control terminal Sn-1 outputs an invalid signal
  • the second control terminal Sn The invalid signal is output, the third control terminal Sn+1 outputs an invalid signal, the fourth control terminal En outputs an invalid signal, and the first data signal terminal Data1 outputs the first data signal.
  • the effective signal (or enable signal) described in the embodiment of the present disclosure refers to a signal that enables the corresponding circuit or transistor to be turned on
  • the invalid signal refers to a signal that enables the corresponding circuit or transistor to be turned off, the first data.
  • the signal refers to a signal (eg, a low-level signal) including the first light-emitting circuit or the first organic light-emitting diode light-emitting luminance information
  • the standby signal refers to a signal that causes the first light-emitting circuit or the first organic light-emitting diode to not emit light (for example, high power) Flat signal).
  • the effective signal refers to a low-level signal
  • the invalid signal refers to a high-level signal
  • the specific voltage value of the low-level signal and the high-level signal can be correspondingly set according to the properties of the transistor.
  • the embodiment of the present disclosure takes the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 as P-type transistors as an example. Description.
  • FIG. 7 is a driving timing diagram of the pixel circuit shown in FIG. 6 according to an embodiment of the present disclosure.
  • the embodiment of the present disclosure further provides a driving method of the pixel circuit as shown in FIG. 6, comprising: a pre-reset phase t1, a reset phase t2, a compensation phase t3, an initialization phase t4, a pre-emission phase t5, and an illumination phase t6.
  • the first control terminal Sn-1 outputs a high-level signal
  • the second control terminal Sn outputs a high-level signal
  • the third control terminal Sn+1 outputs a high-level signal
  • the fourth control terminal En Lose A high level signal is output
  • the first data signal terminal Data1 outputs a high level signal.
  • FIG. 8A is a schematic diagram of a conducting state in a pre-reset phase t1 when the pixel circuit shown in FIG. 6 is driven by the driving timing shown in FIG. 7 according to an embodiment of the present disclosure.
  • the pre-reset phase t1 the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all in a closed state, and no path is formed in the pixel circuit; the fourth transistor
  • the conduction state of T4 is related to the voltage of the first node N1.
  • the pre-reset phase can provide a stable time for the pixel circuit to stabilize the voltage and current states of the various circuit components and prevent circuit anomalies from occurring.
  • the first control terminal Sn-1 outputs a low level signal
  • the second control terminal Sn outputs a high level signal
  • the third control terminal Sn+1 outputs a high level signal
  • the fourth control terminal En outputs A high level signal
  • the first data signal terminal Data1 outputs a high level signal.
  • FIG. 8B is a schematic diagram of a conductive state in the reset phase t2 when the pixel circuit shown in FIG. 6 is driven by the driving timing shown in FIG. 7 according to an embodiment of the present disclosure.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, and the seventh transistor T7 are all in a closed state; since the first control terminal Sn-1 outputs a low level signal, the sixth The transistor T6 is turned on, the voltage of the first node N1 is the reset voltage Vvx provided by the third power terminal Vx, and the reset voltage Vvx is, for example, a low level voltage that enables the P-type transistor to be turned on, and for example, the reset voltage Vvx is a negative voltage; At this time, since the voltage of the first node N1 is the reset voltage Vvx of the low level, the fourth transistor T4 is turned on but does not form a via.
  • the first reset circuit resets the first driving circuit.
  • the voltage difference between the first node N1 and the first data signal Vdata1 may be increased through the reset phase, and the charging time of the first storage capacitor C1 in the compensation phase t3 is reduced.
  • the first control terminal Sn-1 outputs a high level signal
  • the second control terminal Sn outputs a low level signal
  • the third control terminal Sn+1 outputs a high level signal
  • the fourth control terminal En outputs The high level signal
  • the first data signal terminal Data1 outputs a first data signal Vdata1 (eg, a low level signal).
  • FIG. 8C is a schematic diagram of a conducting state in the compensation phase t3 when the pixel circuit shown in FIG. 6 is driven by the driving timing shown in FIG. 7 according to an embodiment of the present disclosure.
  • the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all in a closed state; since the second control terminal Sn outputs a low level signal, the first transistor T1 and the third transistor T3 Turn on,
  • the first data signal Vdata1 outputted by the first data signal terminal Data1 is transmitted to the first node N1 through the first transistor T1 and the third transistor T3. After the first storage capacitor C1 is charged, the voltage of the first node N1 is Vdata1+Vth1.
  • Vth1 is the total voltage drop of the first transistor T1 and the third transistor T3
  • the first data writing circuit writes data to the first driving circuit
  • the first compensation circuit compensates the first driving circuit.
  • the fourth transistor T4 is turned on but does not form a via.
  • the first control terminal Sn-1 outputs a high level signal
  • the second control terminal Sn outputs a high level signal
  • the third control terminal Sn+1 outputs a low level signal
  • the fourth control terminal En outputs The high level signal
  • the first data signal terminal Data1 outputs the first data signal Vdata1.
  • FIG. 8D is a schematic diagram of a conductive state in the initialization phase t4 when the pixel circuit shown in FIG. 6 is driven by the driving timing shown in FIG. 7 according to an embodiment of the present disclosure.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are all in a closed state; the fourth transistor T4 remains due to the storage voltage of the first storage capacitor C1.
  • the first end of the light emitting diode OLED1 (the first end is for example an anode), ie the fourth initialization circuit initializes the fourth lighting circuit.
  • the reset voltage Vvx is less than or equal to the second illuminating voltage Velvss provided by the second power supply terminal ELVSS, such that the initialization can prevent abnormal luminescence of the OLED, for example, the illuminating of the OLED in the non-emission phase can be prevented.
  • the organic light emitting diode is initialized and discharged to ensure the accuracy of the low gray level and the total black under the full dark state image, which can effectively improve the contrast of the entire display panel.
  • the first control terminal Sn-1 outputs a high level signal
  • the second control terminal Sn outputs a high level signal
  • the third control terminal Sn+1 outputs a high level signal
  • the fourth control terminal En The high level signal is output
  • the first data signal terminal Data1 outputs the first data signal Vdata1.
  • FIG. 8E is a schematic diagram of a conducting state in a pre-lighting phase t5 when the pixel circuit shown in FIG. 6 is driven by the driving timing shown in FIG. 7 according to an embodiment of the present disclosure.
  • the pre-emission phase t5 the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all in a closed state, and no path is formed in the pixel circuit;
  • the storage capacitor C1 stores the effect of the voltage, and the fourth transistor T4 maintains the same on state as the initialization phase t4.
  • the pre-lighting phase can provide a stable time for the pixel circuit to make the circuits
  • the voltage and current states of the components are stable to prevent circuit anomalies.
  • the first control terminal Sn-1 outputs a high level signal
  • the second control terminal Sn outputs a high level signal
  • the third control terminal Sn+1 outputs a high level signal
  • the fourth control terminal En outputs The low level signal
  • the first data signal terminal Data1 outputs the first data signal Vdata1.
  • FIG. 8F is a schematic diagram of a conductive state in the light emitting phase t6 when the pixel circuit shown in FIG. 6 is driven by the driving timing shown in FIG. 7 according to an embodiment of the present disclosure.
  • the first transistor T1, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are all in a closed state; the fourth transistor T4 remains and pre-emits in the t5 phase due to the storage voltage of the first storage capacitor C1.
  • the first organic light emitting diode OLED1 and the second power supply terminal ELVSS form a path, and the first organic light emitting diode OLED1 functions at the first light emitting voltage Velvdd provided by the first power supply terminal ELVDD and the second light emitting voltage Velvss provided by the second power supply terminal ELVSS.
  • the first lighting control circuit controls the operation of the first lighting circuit
  • the first power terminal supplies the first lighting voltage to the first lighting circuit
  • the second power source ends to the first lighting
  • the circuit provides a second illuminating voltage
  • the first driving circuit drives the first illuminating circuit, and the first illuminating circuit emits light during operation.
  • the driving method of the pixel circuit shown in FIG. 6 may include only the reset phase t2, the compensation phase t3, the initialization phase t4, and the illumination phase t6, and does not include the pre-reset phase t1 and the pre-emission phase t5, or includes a pre- One of the reset phase t1 and the pre-lighting phase t5 is not limited herein.
  • FIG. 9 is one schematic diagram of still another pixel circuit provided by an embodiment of the present disclosure.
  • an embodiment of the present disclosure further provides a pixel circuit 600, including: a second lighting circuit 602 for emitting light during operation; and a second driving circuit 604 for driving the second lighting circuit 602; a second compensation circuit 606 for compensating the second driving circuit 604; a second data writing circuit 608 for writing data to the second driving circuit 604; and a second reset circuit 610 for resetting the second driving circuit 604;
  • the second storage circuit 612 is configured to store the driving voltage of the second driving circuit 604;
  • the second initialization circuit 614 is configured to initialize the second lighting circuit 602; and the second lighting control circuit 616 is configured to control the second lighting circuit 602.
  • second illumination control circuit 616 includes first portion 616A and second portion 616B; gating circuit 618 for second data signal or third The data signal is transmitted to the second data writing circuit 608; the first power terminal ELVDD is configured to provide the first lighting voltage Velvdd to the second lighting circuit 602; and the second power terminal ELVSS is used to provide the second lighting circuit 602 with the second signal.
  • the third data signal terminal Data3 is configured to provide a third data signal or a standby signal to the second data writing circuit 608.
  • the first control terminal Sn-1 is configured to provide a first control for controlling the second reset circuit 610 to operate and turn off.
  • a second control terminal Sn for providing a second control signal for controlling the second data write circuit 608 and the second compensation circuit 606 to operate and turn off; a third control terminal Sn+1 for providing control of the second initialization A third control signal that operates and shuts down circuit 614; and a fourth control terminal En for providing a fourth control signal that controls operation and shutdown of second illumination control circuit 616.
  • FIG. 10 is a second schematic diagram of still another pixel circuit according to an embodiment of the present disclosure
  • FIG. 10 is a specific implementation of the pixel circuit shown in FIG.
  • the second data writing circuit 608 includes an eighth transistor T8, and the second lighting control circuit 616 includes a ninth transistor T9 and a twelfth transistor.
  • the first portion 616A of the second illumination control circuit 616 includes a ninth transistor T9
  • the second portion 616B of the second illumination control circuit 616 includes a twelfth transistor T12
  • the second compensation circuit 606 includes a tenth transistor T10
  • the second driving circuit 604 includes an eleventh transistor T11
  • the second reset circuit 610 includes a thirteenth transistor T13
  • the second initializing circuit 614 includes a fourteenth transistor T14
  • the second storage circuit 612 includes a second storage capacitor C2
  • the circuit 602 includes a second organic light emitting diode OLED2, a third organic light emitting diode OLED3, a fifteenth transistor T15, and a sixteenth transistor T16.
  • the gate circuit 618 includes a seventeenth transistor T17 and an eighteenth transistor T18.
  • the tenth transistor T10 includes a third sub-transistor and a fourth sub-transistor.
  • the source of the third sub-transistor serves as the source of the tenth transistor T10, and the drain and the fourth sub-transistor
  • the source of the transistor is electrically connected
  • the drain of the fourth sub-transistor serves as the drain of the tenth transistor T10
  • the gate of the third sub-transistor and the gate of the fourth sub-transistor are electrically connected together as the gate of the tenth transistor T10.
  • embodiments of the present disclosure include, but are not limited to, such a composition of the tenth transistor T10, and the tenth transistor T10 may also include only one transistor or, for example, a dual gate transistor.
  • the eighth crystal The source of the transistor T8, the drain of the seventeenth transistor T17 and the drain of the eighteenth transistor T18 are electrically connected, the gate of the eighth transistor T8, the gate of the tenth transistor T10 and the second control terminal Sn are electrically connected,
  • the drain of the eighth transistor T8, the drain of the ninth transistor T9, the source of the tenth transistor T10, and the source of the eleventh transistor T11 are electrically connected;
  • the pole is electrically connected to the fourth control terminal En
  • the source of the ninth transistor T9, the first end of the second storage capacitor C2 is electrically connected to the first power terminal ELVDD
  • the drain of the tenth transistor T10 is electrically connected to the second node N2.
  • the gate of the eleventh transistor T11 is electrically connected to the second node N2, the drain of the eleventh transistor T11 and the source of the twelfth transistor T12 are electrically connected; the drain of the twelfth transistor T12, the fourteenth transistor The drain of T14, the source of the fifteenth transistor T15, the source of the sixteenth transistor T16, and the third node are electrically connected; the source of the thirteenth transistor T13, the source of the fourteenth transistor T14, and the third power source
  • the terminal Vx is electrically connected, and the gate of the thirteenth transistor T13 is electrically connected to the first control terminal Sn-1.
  • the drain of the thirteenth transistor T13 is electrically connected to the second node N2; the gate of the fourteenth transistor T14 is electrically connected to the third control terminal Sn+1; the gate of the fifteenth transistor T15 and the second data signal terminal Data2 Electrically connected, the drain of the fifteenth transistor T15 and the first end of the second organic light emitting diode OLED2 are electrically connected; the gate of the sixteenth transistor T16 is electrically connected to the third data signal end Data3, and the drain of the sixteenth transistor T16 The first end of the seventh organic light emitting diode OLED3 is electrically connected; the source of the seventeenth transistor T17 is electrically connected to the second data signal end Data2, and the gate of the seventeenth transistor T17 is electrically connected to the third data signal end Data3.
  • the source of the eighteenth transistor T18 is electrically connected to the third data signal terminal Data3, the gate of the eighteenth transistor T18 is electrically connected to the second data signal terminal Data2; the second end of the second storage capacitor C2 and the second node
  • the second end of the second organic light emitting diode OLED2, the second end of the third organic light emitting diode OLED3, and the second power supply terminal ELVSS are electrically connected.
  • the transistor T14, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, and the eighteenth transistor T18 are all thin film transistors.
  • the transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16 are all P-type transistors, and the seventeenth transistor T17 and the eighteenth transistor T18 are both N-type transistors.
  • the pixel circuit 600 simultaneously controls the second organic light emitting diode OLED2 and the third organic light emitting diode OLED3, thereby saving the number of pixel circuits as a whole, thereby reducing the area occupied by the pixel circuit and improving the resolution of the display panel.
  • the second organic light emitting diode OLED2 may emit light alone, or the third organic light emitting diode OLED3 may emit light alone.
  • Embodiments of the present disclosure also provide a driving method of a pixel circuit as shown in FIG. 10, the driving method including: a reset phase, a compensation phase, an initialization phase, and an illumination phase.
  • the first control terminal Sn-1 outputs an effective signal
  • the second control terminal Sn outputs an invalid signal
  • the third control terminal Sn+1 outputs an invalid signal
  • the fourth control terminal En outputs an invalid signal
  • the standby signal is output, and the third data signal end Data3 outputs a standby signal
  • the first control terminal Sn-1 outputs an invalid signal
  • the second control terminal Sn outputs an effective signal
  • the third control terminal Sn+1 outputs an invalid signal
  • the fourth control terminal En outputs an invalid signal
  • the second data signal terminal Data2 outputs a second data signal
  • the third data signal terminal Data3 outputs a standby signal
  • the first control terminal Sn-1 outputs an invalid signal
  • the second control terminal Sn Outputting an invalid signal
  • the first control terminal Sn-1 outputs an effective signal
  • the second control terminal Sn outputs an invalid signal
  • the third control terminal Sn+1 outputs an invalid signal
  • the fourth control terminal En outputs an invalid signal
  • the terminal Data2 outputs a standby signal
  • the third data signal terminal Data3 outputs a standby signal
  • the first control terminal Sn-1 outputs an invalid signal
  • the second control terminal Sn outputs an effective signal
  • the third control terminal Sn+1 outputs an invalid signal.
  • the fourth control terminal En outputs an invalid signal, the second data signal terminal Data2 outputs a standby signal, and the third data signal terminal Data3 outputs a third data signal; in the initialization phase, the first control terminal Sn-1 outputs an invalid signal, and the second control The terminal Sn outputs an invalid signal, the third control terminal Sn+1 outputs an effective signal, the fourth control terminal En outputs an invalid signal, the second data signal terminal Data2 outputs a standby signal, and the third data signal terminal Data3 outputs a third data signal; In the stage, the first control terminal Sn-1 outputs an invalid signal, and the second control terminal Sn outputs an invalid signal.
  • the third control terminal Sn+1 outputs an invalid signal
  • the fourth control terminal En outputs a valid signal
  • the second data signal terminal Data2 outputs a standby signal
  • the third data signal terminal Data3 outputs a third data signal; in this case, the third organic light emitting diode OLED 3 emits light alone.
  • the driving method provided by the embodiment of the present disclosure may further include: a pre-reset phase and a pre-lighting phase.
  • the pre-reset phase is after the illumination phase and before the reset phase
  • the pre-emission phase is after the initialization phase and before the illumination phase
  • the first control terminal Sn-1 outputs an invalid signal
  • the second control terminal Sn outputs an invalid signal
  • the third control terminal Sn+1 outputs an invalid signal
  • the second data signal terminal Data2 outputs a standby signal
  • the third data signal terminal Data3 outputs a standby signal
  • the first control terminal Sn- 1 output invalid signal
  • the second control terminal Sn outputs an invalid signal
  • the third control terminal Sn+1 outputs an invalid signal
  • the fourth control terminal En outputs an invalid signal
  • the second data signal terminal Data2 outputs a second data signal
  • the terminal Data3 outputs a standby signal
  • the second data signal terminal Data2 outputs a standby signal
  • the second data signal terminal Data2 outputs the second data signal
  • the third data signal terminal Data3 outputs the standby signal.
  • the second organic light emitting diode OLED2 emits light separately, and the second data signal is used to control the brightness of the second organic light emitting diode OLED2; when the second data signal end Data2 outputs the standby signal, and the third data signal end Data3 outputs the third data signal.
  • the third organic light emitting diode OLED3 emits light alone, and the third data signal is used to control the luminance of the third organic light emitting diode OLED3.
  • the second organic light emitting diode OLED2 emits red light during operation
  • the third organic light emitting diode OLED3 emits green light during operation.
  • the effective signal in the embodiment of the present disclosure refers to a signal that enables the corresponding circuit or transistor to be turned on
  • the invalid signal refers to a signal that enables the corresponding circuit or transistor to be turned off, the first data signal and the second data signal. It refers to a signal (such as a low-level signal) that contains information on the luminance of the corresponding light-emitting circuit or organic light-emitting diode.
  • the standby signal refers to a signal (such as a high-level signal) that can cause the corresponding light-emitting circuit or the organic light-emitting diode to not emit light.
  • the effective signal refers to a low-level signal
  • the invalid signal refers to a high-level signal
  • the specific voltage value of the low-level signal and the high-level signal can be correspondingly set according to the properties of the transistor.
  • the embodiment of the present disclosure adopts an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and an eleventh transistor.
  • T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15 and the sixteenth transistor T16 are all P-type transistors, and the seventeenth transistor T17 and the eighteenth transistor T18 are both An N-type transistor and a second organic light-emitting diode are separately illuminated as an example.
  • FIG. 11 is a driving timing diagram of the pixel circuit shown in FIG. 10 according to an embodiment of the present disclosure.
  • the embodiment of the present disclosure further provides a driving method of the pixel circuit as shown in FIG. 10, including: a pre-reset phase t1, a reset phase t2, a compensation phase t3, an initialization phase t4, a pre-emission phase t5, and an illumination phase t6.
  • the first control terminal Sn-1 outputs a high-level signal
  • the second control terminal Sn outputs a high-level signal
  • the third control terminal Sn+1 outputs a high-level signal
  • the high level signal is output
  • the second data signal end Data2 outputs a high level signal
  • the third data signal end Data3 outputs a high level signal.
  • FIG. 12A is a schematic diagram of a conducting state in a pre-reset phase t1 when the pixel circuit shown in FIG. 10 is driven by the driving timing shown in FIG. 11 according to an embodiment of the present disclosure.
  • the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16 All of them are in a closed state, and the seventeenth transistor T17 (N-type transistor) and the eighteenth transistor T18 (N-type transistor) are turned on; the conduction state of the eleventh transistor T11 is related to the voltage of the second node N2.
  • the pre-reset phase can provide a stable time for the pixel circuit to stabilize the voltage and current states of the various circuit components and prevent circuit anomalies from occurring.
  • the first control terminal Sn-1 outputs a low level signal
  • the second control terminal Sn outputs a high level signal
  • the third control terminal Sn+1 outputs a high level signal
  • the fourth control terminal En outputs The high level signal
  • the second data signal end Data2 outputs a high level signal
  • the third data signal end Data3 outputs a high level signal.
  • FIG. 12B is a schematic diagram of a conductive state in the reset phase t2 when the pixel circuit shown in FIG. 10 is driven by the driving timing shown in FIG. 11 according to an embodiment of the present disclosure.
  • the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the twelfth transistor T12, the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16 are all in a closed state, tenth The seven transistor T17 and the eighteenth transistor T18 are turned on; since the first control terminal Sn-1 outputs a low level signal, the thirteenth transistor T13 is turned on, and the voltage of the second node N2 is a reset voltage provided by the third power terminal Vx.
  • the reset voltage Vvx is, for example, a low level voltage that enables the P-type transistor to be turned on, and for example, The reset voltage Vvx is a negative voltage; at this time, since the voltage of the second node N2 is the reset voltage Vvx of the low level, the eleventh transistor T11 is turned on but does not form a path. This realizes resetting the eleventh transistor T11 through the thirteenth transistor T13, that is, the second reset circuit resets the second driving circuit. For example, the voltage difference between the second node N2 and the second data signal Vdata2 can be increased through the reset phase, reducing the charging time of the second storage capacitor C2 in the compensation phase t3.
  • the first control terminal Sn-1 outputs a high level signal
  • the second control terminal Sn outputs a low level signal
  • the third control terminal Sn+1 outputs a high level signal
  • the second data signal terminal Data2 outputs a second data signal Vdata2 (for example, a low level signal)
  • the third data signal terminal Data3 outputs a high level signal.
  • FIG. 12C is a schematic diagram of a conductive state in the compensation phase t3 when the pixel circuit shown in FIG. 10 is driven by the driving timing shown in FIG. 11 according to an embodiment of the present disclosure.
  • the ninth transistor T9, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the sixteenth transistor T16 and the eighteenth transistor T18 are all in a closed state;
  • Data2 outputs a second data signal Vdata2 (for example, a low level signal), and the fifteenth transistor T15 is turned on; since the third data signal terminal Data3 outputs a high level signal, the seventeenth transistor T17 is turned on; since the second control terminal Sn The low level signal is output, and the eighth transistor T8 and the tenth transistor T10 are turned on.
  • Vdata2 for example, a low level signal
  • the second data signal Vdata2 outputted by the second data signal terminal Data2 is transmitted to the second node N2 through the seventeenth transistor T17, the eighth transistor T8, and the tenth transistor T10.
  • the voltage is Vdata1+Vth2 (Vth2 is the total voltage drop of the seventeenth transistor T17, the eighth transistor T8, and the tenth transistor T10). That is, the gating circuit transmits the second data signal to the second data writing circuit, the second data writing circuit writes data to the second driving circuit, and the second compensation circuit compensates the second driving circuit.
  • the eleventh transistor T11 is turned on but does not form a via.
  • the first control terminal Sn-1 outputs a high level signal
  • the second control terminal Sn outputs a high level signal
  • the third control terminal Sn+1 outputs a low level signal
  • the second data signal terminal Data2 outputs a second data signal Vdata2 (for example, a low level signal)
  • the third data signal terminal Data3 outputs a high level signal.
  • FIG. 12D is a schematic diagram of a conductive state in the initialization phase t4 when the pixel circuit shown in FIG. 10 is driven by the driving timing shown in FIG. 11 according to an embodiment of the present disclosure.
  • the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the twelfth transistor T12, and the thirteenth crystal The body tube T13, the sixteenth transistor T16 and the eighteenth transistor T18 are all in a closed state; the eleventh transistor T11 maintains the same on state as the compensation phase t3 due to the storage voltage of the second storage capacitor C2;
  • the signal terminal Data2 outputs a second data signal Vdata2 (for example, a low level signal), and the fifteenth transistor T15 is turned on; since the third data signal terminal Data3 outputs a high level signal, the seventeenth transistor T17 is turned on;
  • the terminal Sn+1 outputs a low level signal, the fourteenth transistor T14 is turned on, and the reset voltage Vvx provided by the third power terminal V
  • the source that is, the second initialization circuit initializes the second lighting circuit.
  • the reset voltage Vvx is less than or equal to the second illuminating voltage Velvss provided by the second power supply terminal ELVSS, such that the initialization can prevent abnormal luminescence of the OLED, for example, the illuminating of the OLED in the non-emission phase can be prevented.
  • the initial discharge of the organic light emitting diode ensures the accuracy of the low gray scale and the total black under the full dark state image, which can effectively improve the contrast of the entire display panel.
  • the first control terminal Sn-1 outputs a high level signal
  • the second control terminal Sn outputs a high level signal
  • the third control terminal Sn+1 outputs a high level signal
  • the high level signal is output
  • the second data signal end Data2 outputs the second data signal Vdata2
  • the third data signal end Data3 outputs a high level signal.
  • FIG. 12E is a schematic diagram of a conducting state in a pre-lighting phase t5 when the pixel circuit shown in FIG. 10 is driven by the driving timing shown in FIG. 11 according to an embodiment of the present disclosure.
  • the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the sixteenth transistor T16 and the eighteenth transistor T18 Both are in the off state, and the fifteenth transistor T15 and the seventeenth transistor T17 are turned on; the eleventh transistor T11 maintains the same on state as the initialization phase t4 due to the storage voltage of the second storage capacitor C2.
  • the pre-lighting phase can provide a stable time for the pixel circuit to stabilize the voltage and current states of the various circuit components and prevent circuit anomalies from occurring.
  • the first control terminal Sn-1 outputs a high level signal
  • the second control terminal Sn outputs a high level signal
  • the third control terminal Sn+1 outputs a high level signal
  • the second data signal end Data2 outputs the second data signal Vdata2
  • the third data signal end Data3 outputs a high level signal.
  • FIG. 12F is a schematic diagram of a conductive state in the light emitting phase t6 when the pixel circuit shown in FIG. 10 is driven by the driving timing shown in FIG. 11 according to an embodiment of the present disclosure.
  • the eighth crystal The tube T8 the tenth transistor T10, the thirteenth transistor T13, the fourteenth transistor T14, the sixteenth transistor T16 and the eighteenth transistor T18 are all in a closed state, and the fifteenth transistor T15 and the seventeenth transistor T17 are turned on;
  • the second storage capacitor C2 stores the voltage.
  • the eleventh transistor T11 maintains the same on-state as the pre-emission phase t5.
  • the ninth transistor T9 and the twelfth transistor T12 are turned on.
  • a first power supply terminal ELVDD, a ninth transistor T9, an eleventh transistor T11, a twelfth transistor T12, a fifteenth transistor T15, a second organic light emitting diode OLED2, and a second power supply terminal ELVSS form a path, and the second organic light emitting
  • the diode OLED2 emits light under the action of the first illuminating voltage Velvdd provided by the first power supply terminal ELVDD and the second illuminating voltage Velvss provided by the second power supply terminal ELVSS, and is driven by the eleventh transistor T11, that is, the second illuminating control circuit Controlling the operation of the second lighting circuit, the first power terminal provides a first lighting voltage to the second lighting circuit, and the second power terminal provides a second transmission to the second lighting circuit Voltage, the second drive circuit drives the second light emitting circuit, a light emitting circuit emit
  • the driving method of the pixel circuit shown in FIG. 10 may include only the reset phase t2, the compensation phase t3, the initialization phase t4, and the lighting phase t6, and does not include the pre-reset phase t1 and the pre-lighting phase t5, or includes a pre- One of the reset phase t1 and the pre-lighting phase t5 is not limited herein.
  • the case where the third organic light emitting diode OLED 3 emits light alone is similar to the case where the second organic light emitting diode OLED 2 emits light alone, and details are not described herein again.
  • Embodiments of the present disclosure also provide a driving method including a driving method of a pixel circuit as shown in FIG. 6 and a driving method of a pixel circuit as shown in FIG.
  • An embodiment of the present disclosure further provides a display panel including the pixel circuit provided by any of the foregoing embodiments of the present disclosure.
  • the display panel provided by the embodiment of the present disclosure may further include the pixel arrangement structure provided by any of the foregoing embodiments of the present disclosure, and the pixel arrangement structure adopts a corresponding pixel circuit.
  • the display panel 2 includes the pixel arrangement structure 10, the pixel circuit 500, and the pixel circuit 600 provided by any of the embodiments of the present disclosure.
  • two pixel circuits 500 and one pixel circuit 600 constitute one pixel circuit group.
  • the first organic light emitting diode in one of the pixel circuits 500 emits blue light
  • the first organic light emitting diode in the other pixel circuit 500 emits yellow light
  • the second organic light in the pixel circuit 600 LED emits red light
  • pixel The third organic light emitting diode in the path 600 emits green light.
  • the OLEDs in the pixel circuit 500 in the display panel 2 and the OLEDs in the pixel circuit 600 are used for the sub-pixels in the pixel arrangement structure 10 to emit light during operation.
  • the display panel provided by the embodiment of the present disclosure can be used for any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the pixel arrangement structure, the pixel circuit, the display panel and the driving method provided by the embodiments of the present disclosure can reduce the distance between the sub-pixels, reduce the area occupied by the pixel circuit, thereby improving the resolution of the display panel, and can
  • the organic light emitting diode performs initializing discharge to ensure the accuracy of low gray scale and the total black under the full dark state image, thereby effectively improving the contrast of the entire display panel.

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Abstract

一种像素排列结构、像素电路、显示面板及驱动方法。该像素排列结构(10)包括：第一像素单元(100)，包括第一子像素(110)、第二子像素(120)、第三子像素(130)、第四子像素(140)。第一子像素(110)的中心与第一虚拟菱形(150)的第一顶点重合，第二子像素(120)的中心与第一虚拟菱形(150)的第二顶点重合，第三子像素(130)的中心与第一虚拟菱形(150)的第三顶点重合，第四子像素(140)的中心与第一虚拟菱形(150)的第四顶点重合。该像素排列结构、像素电路、显示面板及驱动方法可以减小子像素之间的距离，还可以减小像素电路占用的面积，进而提高显示面板的分辨率，并在被驱动的过程中可以对有机发光二极管进行初始化放电，保证了低灰阶的准确性及全暗态画面下的全黑，有效改善整个显示面板的对比度。

Description

像素排列结构、像素电路、显示面板及驱动方法 技术领域
本公开的实施例涉及一种像素排列结构、像素电路、显示面板及驱动方法。
背景技术
在显示领域，有机发光二极管(OLED)显示面板具有自发光、对比度高、厚度薄、视角广、反应速度快、可用于挠曲性面板、使用温度范围广、制造简单等特点，具有广阔的发展前景。
由于上述特点，有机发光二极管(OLED)显示面板可以适用于手机、显示器、笔记本电脑、数码相机、仪器仪表等具有显示功能的装置。
发明内容
本公开的实施例提供一种像素排列结构，包括：第一像素单元，包括第一子像素、第二子像素、第三子像素、第四子像素，其中，所述第一子像素的中心与第一虚拟菱形的第一顶点重合，所述第二子像素的中心与所述第一虚拟菱形的第二顶点重合，所述第三子像素的中心与所述第一虚拟菱形的第三顶点重合，所述第四子像素的中心与所述第一虚拟菱形的第四顶点重合。
例如，在本公开实施例提供的像素排列结构中，所述第一虚拟菱形的第一顶点、第二顶点、第三顶点和第四顶点依次相邻，所述第一子像素和所述第三子像素为矩形，所述第二子像素和所述第四子像素为三角形。
例如，在本公开实施例提供的像素排列结构中，所述矩形为正方形，所述三角形为等腰三角形。
例如，在本公开实施例提供的像素排列结构中，所述矩形一条边的中垂线经过所述第一虚拟菱形的中心，所述三角形一条边的中垂线经过所述第一虚拟菱形的中心。
例如，在本公开实施例提供的像素排列结构中，所述第一子像素在工作时发出第一颜色的光，所述第二子像素在工作时发出第二颜色的光，所述第 三子像素在工作时发出第三颜色的光，所述第四子像素在工作时发出第四颜色的光。
例如，在本公开实施例提供的像素排列结构中，所述第二颜色和所述第四颜色的混合色为第一颜色或第三颜色。
例如，在本公开实施例提供的像素排列结构中，所述第一颜色和所述第三颜色的混合色为白色。
例如，在本公开实施例提供的像素排列结构中，所述第一颜色为蓝色，所述第二颜色为绿色，所述第三颜色为黄色，所述第四颜色为红色。
例如，本公开实施例提供的像素排列结构还包括：第二像素单元，包括第五子像素、第六子像素、第七子像素、第八子像素，其中，所述第五子像素的中心与第二虚拟菱形的第一顶点重合，所述第六子像素的中心与所述第二虚拟菱形的第二顶点重合，所述第七子像素的中心与所述第二虚拟菱形的第三顶点重合，所述第八子像素的中心与所述第二虚拟菱形的第四顶点重合；第三像素单元，包括第九子像素、第十子像素、第十一子像素、第十二子像素，其中，所述第九子像素的中心与第三虚拟菱形的第一顶点重合，所述第十子像素的中心与所述第三虚拟菱形的第二顶点重合，所述第十一子像素的中心与所述第三虚拟菱形的第三顶点重合，所述第十二子像素的中心与所述第三虚拟菱形的第四顶点重合；所述第一虚拟菱形的中心与虚拟三角形的第一顶点重合，所述第二虚拟菱形的中心与所述虚拟三角形的第二顶点重合，所述第三虚拟菱形的中心与所述虚拟三角形的第三顶点重合。
例如，在本公开实施例提供的像素排列结构中，所述虚拟三角形为锐角三角形。
例如，在本公开实施例提供的像素排列结构中，所述虚拟三角形为等腰锐角三角形。
例如，在本公开实施例提供的像素排列结构中，所述虚拟三角形为等边三角形。
例如，在本公开实施例提供的像素排列结构中，所述第一虚拟菱形、所述第二虚拟菱形和所述第三虚拟菱形的形状相同。
例如，在本公开实施例提供的像素排列结构中，所述第一虚拟菱形的第一顶点、第二顶点、第三顶点和第四顶点依次相邻，所述第二虚拟菱形的第 一顶点、第二顶点、第三顶点和第四顶点依次相邻，所述第三虚拟菱形的第一顶点、第二顶点、第三顶点和第四顶点依次相邻，所述第一子像素、所述第五子像素和所述第九子像素的形状相同，所述第二子像素、所述第六子像素和所述第十子像素的形状相同，所述第三子像素、所述第七子像素和所述第十一子像素的形状相同，所述第四子像素、所述第八子像素和所述第十二子像素的形状相同。
例如，在本公开实施例提供的像素排列结构中，所述第一子像素、第三子像素、第五子像素、第七子像素、第九子像素和第十一子像素为矩形，所述第二子像素、所述第四子像素、所述第六子像素、所述第八子像素、所述第十子像素和所述第十二子像素为三角形。
例如，在本公开实施例提供的像素排列结构中，所述矩形为正方形，所述三角形为等腰三角形。
例如，在本公开实施例提供的像素排列结构中，所述矩形一条边的中垂线经过一个所述虚拟菱形的中心，所述三角形一条边的中垂线经过一个所述虚拟菱形的中心。
例如，在本公开实施例提供的像素排列结构中，所述第一子像素、所述第五子像素和所述第九子像素在工作时发出第一颜色的光，所述第二子像素、所述第六子像素和所述第十子像素在工作时发出第二颜色的光，所述第三子像素、所述第七子像素和所述第十一子像素在工作时发出第三颜色的光，所述第四子像素、所述第八子像素和所述第十二子像素在工作时发出第四颜色的光。
例如，在本公开实施例提供的像素排列结构中，所述第二颜色和所述第四颜色的混合色为第一颜色或第三颜色。
例如，在本公开实施例提供的像素排列结构中，所述第一颜色和所述第三颜色的混合色为白色。
例如，在本公开实施例提供的像素排列结构中，所述第一颜色为蓝色，所述第二颜色为绿色，所述第三颜色为黄色，所述第四颜色为红色。
本公开的实施例还提供一种像素电路，包括：第一发光电路，用于在工作时发光；第一驱动电路，用于驱动所述第一发光电路；第一补偿电路，用于补偿所述第一驱动电路；第一数据写入电路，用于向所述第一驱动电路写 入数据；第一复位电路，用于将所述第一驱动电路复位；第一存储电路，用于存储所述第一驱动电路的驱动电压；第一初始化电路，用于将所述第一发光电路初始化；第一发光控制电路，用于控制所述第一发光电路的工作和关断；第一电源端，用于向所述第一发光电路提供第一发光电压；第二电源端，用于向所述第一发光电路提供第二发光电压；第三电源端，用于向所述第一复位电路提供复位电压；第一数据信号端，用于向所述第一数据写入电路提供第一数据信号或待机信号；第一控制端，用于提供控制所述第一复位电路工作和关断的第一控制信号；第二控制端，用于提供控制所述第一数据写入电路和所述第一补偿电路工作和关断的第二控制信号；第三控制端，用于提供控制所述第一初始化电路工作和关断的第三控制信号；以及第四控制端，用于提供控制所述第一发光控制电路工作和关断的第四控制信号。
例如，在本公开实施例提供的像素电路中，所述第一数据写入电路包括第一晶体管，所述第一发光控制电路包括第二晶体管和第五晶体管，所述第一补偿电路包括第三晶体管，所述第一驱动电路包括第四晶体管，所述第一复位电路包括第六晶体管，所述第一初始化电路包括第七晶体管，所述第一存储电路包括第一存储电容，所述第一发光电路包括第一有机发光二极管。
例如，在本公开实施例提供的像素电路中，所述第一晶体管的源极与所述第一数据信号端电连接，所述第一晶体管的栅极、所述第三晶体管的栅极和所述第二控制端电连接，所述第一晶体管的漏极、所述第二晶体管的漏极、所述第三晶体管的源极和所述第四晶体管的源极电连接；所述第二晶体管的栅极、所述第五晶体管的栅极和所述第四控制端电连接，所述第二晶体管的源极、所述第一存储电容的第一端和所述第一电源端电连接；所述第三晶体管的漏极和第一节点电连接；所述第四晶体管的栅极和所述第一节点电连接，所述第四晶体管的漏极和所述第五晶体管的源极电连接；所述第五晶体管的漏极、所述第七晶体管的漏极和所述第一有机发光二极管的第一端电连接；所述第六晶体管的源极、所述第七晶体管的源极和所述第三电源端电连接，所述第六晶体管的栅极和所述第一控制端电连接，第六晶体管的漏极和所述第一节点电连接；所述第七晶体管的栅极和所述第三控制端电连接；所述第一存储电容的第二端和所述第一节点电连接；所述第一有机发光二极管的第二端和所述第二电源端电连接。
例如，在本公开实施例提供的像素电路中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管以及所述第七晶体管均为薄膜晶体管。
例如，在本公开实施例提供的像素电路中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管以及所述第七晶体管均为P型晶体管。
本公开的实施例还提供一种像素电路，包括：第二发光电路，用于在工作时发光；第二驱动电路，用于驱动所述第二发光电路；第二补偿电路，用于补偿所述第二驱动电路；第二数据写入电路，用于向所述第二驱动电路写入数据；第二复位电路，用于将所述第二驱动电路复位；第二存储电路，用于存储所述第二驱动电路的驱动电压；第二初始化电路，用于将所述第二发光电路初始化；第二发光控制电路，用于控制所述第二发光电路的工作和关断；选通电路，用于将第二数据信号或第三数据信号传输给所述第二数据写入电路；第一电源端，用于向所述第二发光电路提供第一发光电压；第二电源端，用于向所述第二发光电路提供第二发光电压；第三电源端，用于向所述第二复位电路提供复位电压；第二数据信号端，用于向所述第二数据写入电路提供第二数据信号或待机信号；第三数据信号端，用于向所述第二数据写入电路提供第三数据信号或待机信号；第一控制端，用于提供控制所述第二复位电路工作和关断的第一控制信号；第二控制端，用于提供控制所述第二数据写入电路和所述第二补偿电路工作和关断的第二控制信号；第三控制端，用于提供控制所述第二初始化电路工作和关断的第三控制信号；以及第四控制端，用于提供控制所述第二发光控制电路工作和关断的第四控制信号。
例如，在本公开实施例提供的像素电路中，所述第二数据写入电路包括第八晶体管，所述第二发光控制电路包括第九晶体管和第十二晶体管，所述第二补偿电路包括第十晶体管，所述第二驱动电路包括第十一晶体管，所述第二复位电路包括第十三晶体管，所述第二初始化电路包括第十四晶体管，所述第二存储电路包括第二存储电容，所述第二发光电路包括第二有机发光二极管、第三有机发光二极管、第十五晶体管和第十六晶体管，所述选通电路包括第十七晶体管和第十八晶体管。
例如，在本公开实施例提供的像素电路中，所述第八晶体管的源极、所 述第十七晶体管的漏极和所述第十八晶体管的漏极电连接，所述第八晶体管的栅极、所述第十晶体管的栅极和所述第二控制端电连接，所述第八晶体管的漏极、所述第九晶体管的漏极、所述第十晶体管的源极和所述第十一晶体管的源极电连接；所述第九晶体管的栅极、所述第十二晶体管的栅极和所述第四控制端电连接，所述第九晶体管的源极、所述第二存储电容的第一端和所述第一电源端电连接；所述第十晶体管的漏极和第二节点电连接；所述第十一晶体管的栅极和所述第二节点电连接，所述第十一晶体管的漏极和所述第十二晶体管的源极电连接；所述第十二晶体管的漏极、所述第十四晶体管的漏极、所述第十五晶体管的源极、所述第十六晶体管的源极和第三节点电连接；所述第十三晶体管的源极、所述第十四晶体管的源极和所述第三电源端电连接，所述第十三晶体管的栅极和所述第一控制端电连接，第十三晶体管的漏极和所述第二节点电连接；所述第十四晶体管的栅极和所述第三控制端电连接；所述第十五晶体管的栅极和所述第二数据信号端电连接，所述第十五晶体管的漏极和所述第二有机发光二极管的第一端电连接；所述第十六晶体管的栅极和所述第三数据信号端电连接，所述第十六晶体管的漏极和所述第三有机发光二极管的第一端电连接；所述第十七晶体管的源极和所述第二数据信号端电连接，所述第十七晶体管的栅极和所述第三数据信号端电连接；所述第十八晶体管的源极和所述第三数据信号端电连接，所述第十八晶体管的栅极和所述第二数据信号端电连接；所述第二存储电容的第二端和所述第二节点电连接；所述第二有机发光二极管的第二端、所述第三有机发光二极管的第二端和所述第二电源端电连接。
例如，在本公开实施例提供的像素电路中，所述第八晶体管、所述第九晶体管、所述第十晶体管、所述第十一晶体管、所述第十二晶体管、所述第十三晶体管、所述第十四晶体管、所述第十五晶体管、所述第十六晶体管、所述第十七晶体管和所述第十八晶体管均为薄膜晶体管。
例如，在本公开实施例提供的像素电路中，所述第八晶体管、所述第九晶体管、所述第十晶体管、所述第十一晶体管、所述第十二晶体管、所述第十三晶体管、所述第十四晶体管、所述第十五晶体管和所述第十六晶体管均为P型晶体管，所述第十七晶体管和所述第十八晶体管均为N型晶体管。
本公开的实施例还提供一种显示面板，包括本公开任一实施例所述的像 素排列结构。
本公开的实施例还提供一种显示面板，包括本公开任一实施例所述的像素电路。
例如，本公开实施例提供的像素电路，包括本公开任一实施例所述的像素排列结构以及本公开任一实施例所述的像素电路，其中，本公开实施例提供的像素电路中的第一发光电路在工作时发出蓝色或黄色的光；本公开实施例提供的像素电路中的第二发光电路在工作时发出红色或绿色的光。
本公开的实施例还提供一种像素电路的驱动方法，包括：复位阶段、补偿阶段、初始化阶段和发光阶段，其中，在所述复位阶段，所述第一控制端输出有效信号，所述第二控制端输出无效信号，所述第三控制端输出无效信号，所述第四控制端输出无效信号，所述第一数据信号端输出待机信号；在所述补偿阶段，所述第一控制端输出无效信号，所述第二控制端输出有效信号，所述第三控制端输出无效信号，所述第四控制端输出无效信号，所述第一数据信号端输出第一数据信号；在所述初始化阶段，所述第一控制端输出无效信号，所述第二控制端输出无效信号，所述第三控制端输出有效信号，所述第四控制端输出无效信号，所述第一数据信号端输出第一数据信号；在所述发光阶段，所述第一控制端输出无效信号，所述第二控制端输出无效信号，所述第三控制端输出无效信号，所述第四控制端输出有效信号，所述第一数据信号端输出第一数据信号。
例如，本公开上述实施例提供的驱动方法，还可以包括：预复位阶段和预发光阶段，其中，预复位阶段在所述发光阶段之后和所述复位阶段之前，所述预发光阶段在所述初始化阶段之后和所述发光阶段之前，在所述预复位阶段，所述第一控制端输出无效信号，所述第二控制端输出无效信号，所述第三控制端输出无效信号，所述第四控制端输出无效信号，所述第一数据信号端输出待机信号；在所述预发光阶段，所述第一控制端输出无效信号，所述第二控制端输出无效信号，所述第三控制端输出无效信号，所述第四控制端输出无效信号，所述第一数据信号端输出第一数据信号。
本公开的实施例还提供一种像素电路的驱动方法，包括：复位阶段、补偿阶段、初始化阶段和发光阶段，其中，在所述复位阶段，所述第一控制端输出有效信号，所述第二控制端输出无效信号，所述第三控制端输出无效信 号，所述第四控制端输出无效信号，所述第二数据信号端输出待机信号，所述第三数据信号端输出待机信号；在所述补偿阶段，所述第一控制端输出无效信号，所述第二控制端输出有效信号，所述第三控制端输出无效信号，所述第四控制端输出无效信号，所述第二数据信号端输出第二数据信号，所述第三数据信号端输出待机信号；在所述初始化阶段，所述第一控制端输出无效信号，所述第二控制端输出无效信号，所述第三控制端输出有效信号，所述第四控制端输出无效信号，所述第二数据信号端输出第二数据信号，所述第三数据信号端输出待机信号；在所述发光阶段，所述第一控制端输出无效信号，所述第二控制端输出无效信号，所述第三控制端输出无效信号，所述第四控制端输出有效信号，所述第二数据信号端输出第二数据信号，所述第三数据信号端输出待机信号；或者，在所述复位阶段，所述第一控制端输出有效信号，所述第二控制端输出无效信号，所述第三控制端输出无效信号，所述第四控制端输出无效信号，所述第二数据信号端输出待机信号，所述第三数据信号端输出待机信号；在所述补偿阶段，所述第一控制端输出无效信号，所述第二控制端输出有效信号，所述第三控制端输出无效信号，所述第四控制端输出无效信号，所述第二数据信号端输出待机信号，所述第三数据信号端输出第三数据信号；在所述初始化阶段，所述第一控制端输出无效信号，所述第二控制端输出无效信号，所述第三控制端输出有效信号，所述第四控制端输出无效信号，所述第二数据信号端输出待机信号，所述第三数据信号端输出第三数据信号；在所述发光阶段，所述第一控制端输出无效信号，所述第二控制端输出无效信号，所述第三控制端输出无效信号，所述第四控制端输出有效信号，所述第二数据信号端输出待机信号，所述第三数据信号端输出第三数据信号。
例如，本公开上述实施例提供的驱动方法，还可以包括：预复位阶段和预发光阶段，其中，预复位阶段在所述发光阶段之后和所述复位阶段之前，所述预发光阶段在所述初始化阶段之后和所述发光阶段之前，在所述预复位阶段，所述第一控制端输出无效信号，所述第二控制端输出无效信号，所述第三控制端输出无效信号，所述第四控制端输出无效信号，所述第二数据信号端输出待机信号，所述第三数据信号端输出待机信号；在所述预发光阶段，所述第一控制端输出无效信号，所述第二控制端输出无效信号，所述第三控 制端输出无效信号，所述第四控制端输出无效信号，所述第二数据信号端输出第二数据信号，所述第三数据信号端输出待机信号；或者，所述第二数据信号端输出待机信号，所述第三数据信号端输出第三数据信号。
该像素排列结构、像素电路、显示面板及驱动方法可以减小子像素之间的距离，还可以减小像素电路占用的面积，进而提高显示面板的分辨率，并在被驱动的过程中可以对有机发光二极管进行初始化放电，保证了低灰阶的准确性及全暗态画面下的全黑，有效改善整个显示面板的对比度。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，并非对本公开的限制。
图1是本公开实施例提供的一种像素排列结构的示意图之一；
图2是本公开实施例提供的一种像素排列结构的示意图之二；
图3是本公开实施例提供的一种显示面板的示意图之一；
图4是本公开实施例提供的一种显示面板的示意图之二；
图5是本公开实施例提供的一种像素电路的示意图之一；
图6是本公开实施例提供的一种像素电路的示意图之二；
图7是本公开实施例提供的如图6所示的像素电路的驱动时序图；
图8A是本公开实施例提供的如图6所示的像素电路被如图7所示的驱动时序驱动时在预复位阶段的导通状态示意图；
图8B是本公开实施例提供的如图6所示的像素电路被如图7所示的驱动时序驱动时在复位阶段的导通状态示意图；
图8C是本公开实施例提供的如图6所示的像素电路被如图7所示的驱动时序驱动时在补偿阶段的导通状态示意图；
图8D是本公开实施例提供的如图6所示的像素电路被如图7所示的驱动时序驱动时在初始化阶段的导通状态示意图；
图8E是本公开实施例提供的如图6所示的像素电路被如图7所示的驱动时序驱动时在预发光阶段的导通状态示意图；
图8F是本公开实施例提供的如图6所示的像素电路被如图7所示的驱 动时序驱动时在发光阶段的导通状态示意图；
图9是本公开实施例提供的又一种像素电路的示意图之一；
图10是本公开实施例提供的又一种像素电路的示意图之二；
图11是本公开实施例提供的如图10所示的像素电路中第二有机发光二极管单独发光时的驱动时序图；
图12A是本公开实施例提供的如图10所示的像素电路被如图11所示的驱动时序驱动时在预复位阶段的导通状态示意图；
图12B是本公开实施例提供的如图10所示的像素电路被如图11所示的驱动时序驱动时在复位阶段的导通状态示意图；
图12C是本公开实施例提供的如图10所示的像素电路被如图11所示的驱动时序驱动时在补偿阶段的导通状态示意图；
图12D是本公开实施例提供的如图10所示的像素电路被如图11所示的驱动时序驱动时在初始化阶段的导通状态示意图；
图12E是本公开实施例提供的如图10所示的像素电路被如图11所示的驱动时序驱动时在预发光阶段的导通状态示意图；
图12F是本公开实施例提供的如图10所示的像素电路被如图11所示的驱动时序驱动时在发光阶段的导通状态示意图；以及
图13是本公开实施例提供的又一种显示面板的示意图。
具体实施方式
下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述参考在附图中示出并在以下描述中详述的非限制性示例实施例，更加全面地说明本公开的示例实施例和它们的多种特征及有利细节。应注意的是，图中示出的特征不是必须按照比例绘制。本公开省略了已知材料、组件和工艺技术的描述，从而不使本公开的示例实施例模糊。所给出的示例仅旨在有利于理解本公开示例实施例的实施，以及进一步使本领域技术人员能够实施示例实施例。因而，这些示例不应被理解为对本公开的实施例的范围的限制。
除非另外特别定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区 分不同的组成部分。此外，在本公开各个实施例中，相同或类似的参考标号表示相同或类似的构件。
有机发光二极管(OLED)显示面板一般包括多个像素单元，每个像素单元中包括多个能发出不同颜色光的OLED的子像素，每个子像素中的OLED可由各自的像素电路驱动，然而像素电路占用的面积较大，导致子像素的面积不能进一步被减小，影响了显示面板的分辨率。
本公开的实施例提供了一种像素排列结构、像素电路、显示面板及驱动方法，可以减小子像素之间的距离，同时减小像素电路占用的面积，进而提高显示面板的分辨率，并可以对OLED进行初始化放电，保证了低灰阶的准确性及全暗态画面下的全黑，有效改善整个显示面板的对比度。
例如，如图1所示，本公开的实施例提供一种像素排列结构10，包括：第一像素单元100，第一像素单元100包括第一子像素110、第二子像素120、第三子像素130、第四子像素140，第一子像素110的中心与第一虚拟菱形150的第一顶点重合，第二子像素120的中心与第一虚拟菱形150的第二顶点重合，第三子像素130的中心与第一虚拟菱形150的第三顶点重合，第四子像素140的中心与第一虚拟菱形150的第四顶点重合。
需要说明的是，第一虚拟菱形150仅用于说明第一子像素110、第二子像素120、第三子像素130和第四子像素140的位置关系。在实际的像素排列结构10中，并不存在第一虚拟菱形150的实际结构。
例如，在本公开实施例提供的像素排列结构10中，第一虚拟菱形150的第一顶点、第二顶点、第三顶点和第四顶点依次相邻。也就是说，第一子像素110、第二子像素120、第三子像素130和第四子像素140依次相邻，例如，如图1所示，第一子像素110、第二子像素120、第三子像素130和第四子像素140按顺时针方向排列。
例如，第一子像素110和第三子像素130为矩形，第二子像素120和第四子像素140为三角形。
例如，在本公开实施例提供的像素排列结构10中，第一子像素110和第三子像素130为正方形，第二子像素120和第四子像素140为等腰三角形。
例如，在本公开实施例提供的像素排列结构10中，如图1所示，第一子像素110一条边的中垂线L1经过第一虚拟菱形150的中心，第二子像素120 底边的中垂线L2经过第一虚拟菱形150的中心，第三子像素130一条边的中垂线(图中未示出)经过第一虚拟菱形150的中心，第四子像素140底边的中垂线(图中未示出)经过第一虚拟菱形150的中心。也就是说，第一子像素110、第二子像素120、第三子像素130和第四子像素140正对第一虚拟菱形150的中心设置。
需要说明的是，第一子像素110、第二子像素120、第三子像素130和第四子像素140的排布方式包括但不局限于图1所示的情形，也可以是其它排布方式。例如，第一子像素的一个顶点正对第一虚拟菱形的中心设置，第二子像素的一个顶点正对第一虚拟菱形的中心设置，第三子像素的一个顶点正对第一虚拟菱形的中心设置，第四子像素的一个顶点正对第一虚拟菱形的中心设置。
例如，本公开实施例提供的像素排列结构可以减小子像素之间的距离，在单位面积内可以设置更多的子像素，即提高了显示分辨率。
例如，在本公开实施例提供的像素排列结构10中，第一子像素110在工作时发出第一颜色的光，第二子像素120在工作时发出第二颜色的光，第三子像素130在工作时发出第三颜色的光，第四子像素140在工作时发出第四颜色的光。
例如，在本公开实施例提供的像素排列结构10中，第二颜色和第四颜色的混合色可以为第一颜色或第三颜色。例如，第一颜色和第三颜色的混合色可以为白色。
例如，在本公开实施例提供的像素排列结构10中，第一颜色为蓝色，第二颜色为绿色，第三颜色为黄色，第四颜色为红色。第二颜色绿色和第四颜色红色的混合色为第三颜色黄色，第一颜色蓝色和第三颜色黄色的混合色为白色。
例如，在显示单色画面时，相应颜色的子像素单独发光；在显示灰阶画面(例如白色画面)时，只需第一子像素和第三子像素发光；在显示第四颜色灰阶较高的多彩画面时，可以借用第三子像素发出的第三颜色的光替代第二子像素发出的第二颜色的光和第四子像素发出的第四颜色的光的组合色，同时第四子像素发出第四颜色的光作为补充，即只有第一子像素、第三子像素和第四子像素发光，第二子像素不发光；在显示第二颜色灰阶较高的多彩 画面时，也可以借用第三子像素发出的第三颜色的光替代第二子像素发出的第二颜色的光和第四子像素发出的第四颜色的光的组合色，同时第二子像素发出第二颜色的光作为补充，即只有第一子像素、第二子像素和第三子像素发光，第四子像素不发光。这样，在显示灰阶画面时仅有两个子像素发光，在显示多彩画面时，仅有三个子像素发光，可以节省电能。
例如，本公开的实施例提供的像素排列结构使用四色像素显示，能够保证各种画面像素配比均衡及色域的宽广。
需要说明的是，本公开的实施例包括但不仅限于第一颜色为蓝色，第二颜色为绿色，第三颜色为黄色，第四颜色为红色的情形。可以根据显示的实际需要灵活调整显示颜色的组合。
例如，如图2所示，本公开实施例提供的像素排列结构10还可以进一步包括第二像素单元200和第三像素单元300。第二像素单元200包括第五子像素210、第六子像素220、第七子像素230和第八子像素240。第五子像素210的中心与第二虚拟菱形250的第一顶点重合，第六子像素220的中心与第二虚拟菱形250的第二顶点重合，第七子像素230的中心与第二虚拟菱形250的第三顶点重合，第八子像素240的中心与第二虚拟菱形250的第四顶点重合。第三像素单元300包括第九子像素310、第十子像素320、第十一子像素330和第十二子像素340。第九子像素310的中心与第三虚拟菱形350的第一顶点重合，第十子像素320的中心与第三虚拟菱形350的第二顶点重合，第十一子像素330的中心与第三虚拟菱形350的第三顶点重合，第十二子像素340的中心与第三虚拟菱形350的第四顶点重合。例如，第一虚拟菱形150的中心与虚拟三角形400的第一顶点410重合，第二虚拟菱形250的中心与虚拟三角形400的第二顶点420重合，第三虚拟菱形350的中心与虚拟三角形400的第三顶点430重合。
需要说明的是，第二虚拟菱形250、第三虚拟菱形350仅用于说明相应子像素的位置关系，虚拟三角形400仅用于说明第一像素单元100、第二像素单元200和第三像素单元300的位置关系。在实际的像素排列结构10中，并不存在第二虚拟菱形250、第三虚拟菱形350和虚拟三角形400的实际结构。
例如，在本公开实施例提供的像素排列结构10中，虚拟三角形400为锐 角三角形。也就是说，第三像素单元300在竖直方向上并未与第一像素单元100或第二像素单元200对齐，而是在竖直方向上位于第一像素单元100和第二像素单元200之间。这种排布方式可以进一步减小子像素之间的距离，进而提高显示分辨率。
例如，在本公开实施例提供的像素排列结构10中，虚拟三角形400为等腰锐角三角形。
进一步地，又例如，在本公开实施例提供的像素排列结构10中，虚拟三角形400为等边三角形。
例如，在本公开实施例提供的像素排列结构10中，第一虚拟菱形150、第二虚拟菱形250和第三虚拟菱形350的形状相同。
例如，在本公开实施例提供的像素排列结构10中，第一虚拟菱形150的第一顶点、第二顶点、第三顶点和第四顶点依次相邻，第二虚拟菱形250的第一顶点、第二顶点、第三顶点和第四顶点依次相邻，第三虚拟菱形350的第一顶点、第二顶点、第三顶点和第四顶点依次相邻，第一子像素110、第五子像素210和第九子像素310的形状相同，第二子像素120、第六子像素220和第十子像素320的形状相同，第三子像素130、第七子像素230和第十一子像素330的形状相同，第四子像素140、第八子像素240和第十二子像素340的形状相同。
例如，在本公开实施例提供的像素排列结构10中，第一子像素110、第三子像素130、第五子像素210、第七子像素230、第九子像素310和第十一子像素330为矩形，第二子像素120、第四子像素140、第六子像素220、第八子像素240、第十子像素320和第十二子像素340为三角形。
例如，在本公开实施例提供的像素排列结构10中，第一子像素110、第三子像素130、第五子像素210、第七子像素230、第九子像素310和第十一子像素330为正方形，第二子像素120、第四子像素140、第六子像素220、第八子像素240、第十子像素320和第十二子像素340为等腰三角形。
例如，在本公开实施例提供的像素排列结构10中，第五子像素210一条边的中垂线经过第二虚拟菱形250的中心，第七子像素230一条边的中垂线经过第二虚拟菱形250的中心，第九子像素310一条边的中垂线经过第三虚拟菱形350的中心，第十一子像素330一条边的中垂线经过第三虚拟菱形350 的中心。
例如，第六子像素220底边的中垂线经过第二虚拟菱形250的中心，第八子像素240底边的中垂线经过第二虚拟菱形250的中心，第十子像素320底边的中垂线经过第三虚拟菱形350的中心，第十二子像素340底边的中垂线经过第三虚拟菱形350的中心。
例如，在本公开实施例提供的像素排列结构10中，第一子像素110、第五子像素210和第九子像素310在工作时发出第一颜色的光，第二子像素120、第六子像素220和第十子像素320在工作时发出第二颜色的光，第三子像素130、第七子像素230和第十一子像素330在工作时发出第三颜色的光，第四子像素140、第八子像素240和第十二子像素340在工作时发出第四颜色的光。
例如，在本公开实施例提供的像素排列结构10中，第二颜色和第四颜色的混合色为第一颜色或第三颜色。
例如，在本公开实施例提供的像素排列结构10中，第一颜色和第三颜色的混合色为白色。
例如，在本公开实施例提供的像素排列结构10中，第一颜色为蓝色，第二颜色为绿色，第三颜色为黄色，第四颜色为红色。
例如，在显示单色画面时，相应颜色的子像素单独发光；在显示灰阶画面(例如白色画面)时，只需第一子像素、第三子像素、第五子像素、第七子像素、第九子像素和第十一子像素发光；在显示第四颜色灰阶较高的多彩画面时，可以借用第三颜色的光替代第二颜色的光和第四颜色的光的组合色，即第二子像素、第六子像素和第十子像素不发光；在显示第二颜色灰阶较高的多彩画面时，也可以借用第三颜色的光替代第二颜色的光和第四颜色的光的组合色，即第四子像素、第八子像素和第十二子像素不发光。这样，在显示灰阶画面时每个像素单元内仅有两个子像素发光，在显示多彩画面时，每个像素单元内仅有三个子像素发光，可以节省电能。
例如，本公开的实施例提供的像素排列结构使用四色像素显示，能够保证各种画面像素配比均衡及色域的宽广。
本公开的实施例还提供一种显示面板1，如图3所示，显示面板1包括本公开任一实施例提供的像素排列结构。
例如，以显示面板1包括m行n列像素进行说明，如图3所示，显示面板1包括第一子像素110、第二子像素120、第三子像素130、第四子像素140、五子像素210、第六子像素220、第七子像素230、第八子像素240、第九子像素310、第十子像素320、第十一子像素330、第十二子像素340......。第一子像素110、第二子像素120、第三子像素130、第四子像素140、五子像素210、第六子像素220、第七子像素230和第八子像素240位于显示面板1的第一行，第九子像素310、第十子像素320、第十一子像素330和第十二子像素340位于显示面板1的第二行。
例如，由于像素排列结构会造成图3所述的显示面板1中的偶数行接近显示面板边缘处形成空隙，为了填补该空隙，还可以进一步根据实际情况在显示面板1的边缘补充子像素。
例如，如图4所示，在第二行的左侧边缘补充第二补充子像素320’，在第二行右侧边缘补充第一补充子像素310’、第三补充子像素330’和第四补充子像素340’，对其它空隙也进行类似处理。这样，可以充分利用显示面板的面积，保证子像素分布均匀，减小或避免显示面板边缘空隙对显示效果的影响。
例如，在填补补充子像素这一示例中，还可对像素进行重新划分，如图4所示，第一行像素从左到右分别为P11，P12，……，P1n；第一列像素从上到下分别为P11，P21，……，Pm1。
例如，图5是本公开实施例提供的一种像素电路的示意图之一。如图5所示，本公开的实施例还提供一种像素电路500，包括：第一发光电路502，用于在工作时发光；第一驱动电路504，用于驱动第一发光电路502；第一补偿电路506，用于补偿第一驱动电路504；第一数据写入电路508，用于向第一驱动电路504写入数据；第一复位电路510，用于将第一驱动电路504复位；第一存储电路512，用于存储第一驱动电路504的驱动电压；第一初始化电路514，用于将第一发光电路502初始化；第一发光控制电路516，用于控制第一发光电路502的工作和关断，例如，第一发光控制电路516包括第一部分516A和第二部分516B；第一电源端ELVDD，用于向第一发光电路502提供第一发光电压Velvdd；第二电源端ELVSS，用于向第一发光电路502提供第二发光电压Velvss；第三电源端Vx，用于向第一复位电路510提 供复位电压Vvx；第一数据信号端Data1，用于向第一数据写入电路508提供第一数据信号或待机信号；第一控制端Sn-1，用于提供控制第一复位电路510工作和关断的第一控制信号；第二控制端Sn，用于提供控制第一数据写入电路508和第一补偿电路506工作和关断的第二控制信号；第三控制端Sn+1，用于提供控制第一初始化电路514工作和关断的第三控制信号；以及第四控制端En，用于提供控制第一发光控制电路516工作和关断的第四控制信号。
例如，图6是本公开实施例提供的一种像素电路的示意图之二，图6是图5中所示像素电路的一种具体实施方式。如图5和图6所示，在本公开实施例提供的像素电路500中，第一数据写入电路508包括第一晶体管T1，第一发光控制电路516包括第二晶体管T2和第五晶体管T5，例如，第一发光控制电路516的第一部分516A包括第二晶体管T2，第一发光控制电路516的第二部分516B包括第五晶体管T5，第一补偿电路506包括第三晶体管T3，第一驱动电路504包括第四晶体管T4，第一复位电路510包括第六晶体管T6，第一初始化电路514包括第七晶体管T7，第一存储电路512包括第一存储电容C1，第一发光电路502包括第一有机发光二极管OLED1。
例如，如图6所示，第三晶体管T3包括串联的第一子晶体管和第二子晶体管，第一子晶体管的源极作为第三晶体管T3的源极，第一子晶体管的漏极与第二子晶体管的源极电连接，第二子晶体管的漏极作为第三晶体管T3的漏极，第一子晶体管的栅极和第二子晶体管的栅极电连接共同作为第三晶体管T3的栅极。需要说明的是，本公开的实施例包括但不仅限于第三晶体管T3的这种组成方式，第三晶体管T3也可以仅包括一个晶体管，或者可以为双栅晶体管。
例如，如图6所示，在本公开实施例提供的像素电路500中，第一晶体管T1的源极与第一数据信号端Data1电连接，第一晶体管T1的栅极、第三晶体管T3的栅极和第二控制端Sn电连接，第一晶体管T1的漏极、第二晶体管T2的漏极、第三晶体管T3的源极和第四晶体管T4的源极电连接；第二晶体管T2的栅极、第五晶体管T5的栅极和第四控制端En电连接，第二晶体管T2的源极、第一存储电容C1的第一端和第一电源端ELVDD电连接；第三晶体管T3的漏极和第一节点N1电连接；第四晶体管T4的栅极和第一 节点N1电连接，第四晶体管T4的漏极和第五晶体管T5的源极电连接；第五晶体管T5的漏极、第七晶体管T7的漏极和第一有机发光二极管OLED1的第一端电连接；第六晶体管T6的源极、第七晶体管T7的源极和第三电源端Vx电连接，第六晶体管T6的栅极和第一控制端Sn-1电连接，第六晶体管T6的漏极和第一节点N1电连接；第七晶体管T7的栅极和第三控制端Sn+1电连接；第一存储电容C1的第二端和第一节点N1电连接；第一有机发光二极管OLED1的第二端和第二电源端ELVSS电连接。
例如，第一有机发光二极管OLED1在工作时发出蓝色的光或黄色的光。
例如，在本公开实施例提供的像素电路500中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6以及第七晶体管T7均为薄膜晶体管。
例如，在本公开实施例提供的像素电路500中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6以及第七晶体管T7均为P型晶体管。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为源极，另一极为漏极，所以本公开实施例中全部或部分晶体管的源极和漏极根据需要是可以互换的。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。基于本公开对P型晶体管实现方式的描述和教导，本领域普通技术人员在没有做出创造性劳动前提下能够容易想到本公开实施例采用N型晶体管的实现方式，因此，这些实现方式也是在本公开的保护范围内的。
本公开的实施例还提供一种如图6所示像素电路的驱动方法，该驱动方法包括：复位阶段、补偿阶段、初始化阶段和发光阶段。在复位阶段，第一控制端Sn-1输出有效信号，第二控制端Sn输出无效信号，第三控制端Sn+1输出无效信号，第四控制端En输出无效信号，第一数据信号端Data1输出待机信号；在补偿阶段，第一控制端Sn-1输出无效信号，第二控制端Sn输出有效信号，第三控制端Sn+1输出无效信号，第四控制端En输出无效信号， 第一数据信号端Data1输出第一数据信号；在初始化阶段，第一控制端Sn-1输出无效信号，第二控制端Sn输出无效信号，第三控制端Sn+1输出有效信号，第四控制端En输出无效信号，第一数据信号端Data1输出第一数据信号；在发光阶段，第一控制端Sn-1输出无效信号，第二控制端Sn输出无效信号，第三控制端Sn+1输出无效信号，第四控制端En输出有效信号，第一数据信号端Data1输出第一数据信号。
例如，本公开实施例提供的驱动方法，还可以包括：预复位阶段和预发光阶段。预复位阶段在发光阶段之后和复位阶段之前，预发光阶段在初始化阶段之后和发光阶段之前，在预复位阶段，第一控制端Sn-1输出无效信号，第二控制端Sn输出无效信号，第三控制端Sn+1输出无效信号，第四控制端En输出无效信号，第一数据信号端Data1输出待机信号；在预发光阶段，第一控制端Sn-1输出无效信号，第二控制端Sn输出无效信号，第三控制端Sn+1输出无效信号，第四控制端En输出无效信号，第一数据信号端Data1输出第一数据信号。
需要说明的是，本公开实施例中所述的有效信号(或使能信号)是指能使相应电路或晶体管开启的信号，无效信号是指能使相应电路或晶体管关闭的信号，第一数据信号是指包含着第一发光电路或第一有机发光二极管发光亮度信息的信号(例如低电平信号)，待机信号是指使第一发光电路或第一有机发光二极管不发光的信号(例如高电平信号)。例如，当晶体管为P型晶体管时，有效信号是指低电平信号，无效信号是指高电平信号，低电平信号和高电平信号的具体电压值可根据晶体管的属性进行相应设置。以下，本公开的实施例以第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6以及第七晶体管T7均为P型晶体管为例进行说明。
例如，图7是本公开实施例提供的如图6所示的像素电路的驱动时序图。本公开的实施例还提供一种如图6所示像素电路的驱动方法，包括：预复位阶段t1、复位阶段t2、补偿阶段t3、初始化阶段t4、预发光阶段t5和发光阶段t6。
例如，在预复位阶段t1，第一控制端Sn-1输出高电平信号，第二控制端Sn输出高电平信号，第三控制端Sn+1输出高电平信号，第四控制端En输 出高电平信号，第一数据信号端Data1输出高电平信号。
例如，图8A是本公开实施例提供的如图6所示的像素电路被如图7所示的驱动时序驱动时在预复位阶段t1的导通状态示意图。在预复位阶段t1，第一晶体管T1、第二晶体管T2、第三晶体管T3、第五晶体管T5、第六晶体管T6和第七晶体管T7均处于关闭状态，像素电路中没有形成通路；第四晶体管T4的导通状态与第一节点N1的电压有关。例如，预复位阶段可以给像素电路提供一个稳定的时间，使各电路元件的电压和电流状态稳定，防止电路异常情况发生。
例如，在复位阶段t2，第一控制端Sn-1输出低电平信号，第二控制端Sn输出高电平信号，第三控制端Sn+1输出高电平信号，第四控制端En输出高电平信号，第一数据信号端Data1输出高电平信号。
图8B是本公开实施例提供的如图6所示的像素电路被如图7所示的驱动时序驱动时在复位阶段t2的导通状态示意图。在复位阶段t2，第一晶体管T1、第二晶体管T2、第三晶体管T3、第五晶体管T5和第七晶体管T7均处于关闭状态；由于第一控制端Sn-1输出低电平信号，第六晶体管T6导通，第一节点N1的电压为第三电源端Vx提供的复位电压Vvx，复位电压Vvx例如为能使P型晶体管开启的低电平电压，又例如，复位电压Vvx为负电压；此时，由于第一节点N1的电压为低电平的复位电压Vvx，第四晶体管T4开启但不会形成通路。这样就实现了通过第六晶体管T6将第四晶体管T4复位，即第一复位电路将第一驱动电路复位。例如，经过复位阶段可以增加第一节点N1和第一数据信号Vdata1之间的电压差，减小了在补偿阶段t3中，对第一存储电容C1的充电时间。
例如，在补偿阶段t3，第一控制端Sn-1输出高电平信号，第二控制端Sn输出低电平信号，第三控制端Sn+1输出高电平信号，第四控制端En输出高电平信号，第一数据信号端Data1输出第一数据信号Vdata1(例如低电平信号)。
图8C是本公开实施例提供的如图6所示的像素电路被如图7所示的驱动时序驱动时在补偿阶段t3的导通状态示意图。在补偿阶段t3，第二晶体管T2、第五晶体管T5、第六晶体管T6和第七晶体管T7均处于关闭状态；由于第二控制端Sn输出低电平信号，第一晶体管T1和第三晶体管T3导通， 第一数据信号端Data1输出的第一数据信号Vdata1通过第一晶体管T1和第三晶体管T3传输到第一节点N1，对第一存储电容C1充电完成后，第一节点N1的电压为Vdata1+Vth1(Vth1为第一晶体管T1和第三晶体管T3的总压降)，也就是说第一数据写入电路向第一驱动电路写入了数据，第一补偿电路对第一驱动电路进行了补偿，此时，第四晶体管T4开启但不会形成通路。
例如，在初始化阶段t4，第一控制端Sn-1输出高电平信号，第二控制端Sn输出高电平信号，第三控制端Sn+1输出低电平信号，第四控制端En输出高电平信号，第一数据信号端Data1输出第一数据信号Vdata1。
图8D是本公开实施例提供的如图6所示的像素电路被如图7所示的驱动时序驱动时在初始化阶段t4的导通状态示意图。在初始化阶段t4，第一晶体管T1、第二晶体管T2、第三晶体管T3、第五晶体管T5和第六晶体管T6均处于关闭状态；由于第一存储电容C1存储电压的作用，第四晶体管T4保持和补偿阶段t3一样的开启状态；由于第三控制端Sn+1输出低电平信号，第七晶体管T7导通，第三电源端Vx提供的复位电压Vvx通过第七晶体管T7传输给第一有机发光二极管OLED1的第一端(第一端例如为阳极)，即第四初始化电路将第四发光电路初始化。例如，复位电压Vvx小于或等于第二电源端ELVSS提供的第二发光电压Velvss，这样，经过初始化可以防止OLED的异常发光，例如可以防止OLED在非发光阶段的微亮发光。例如，在驱动过程中，对有机发光二极管进行初始化放电，保证了低灰阶的准确性及全暗态画面下的全黑，可以有效改善整个显示面板的对比度。
例如，在预发光阶段t5，第一控制端Sn-1输出高电平信号，第二控制端Sn输出高电平信号，第三控制端Sn+1输出高电平信号，第四控制端En输出高电平信号，第一数据信号端Data1输出第一数据信号Vdata1。
图8E是本公开实施例提供的如图6所示的像素电路被如图7所示的驱动时序驱动时在预发光阶段t5的导通状态示意图。在预发光阶段t5，第一晶体管T1、第二晶体管T2、第三晶体管T3、第五晶体管T5、第六晶体管T6和第七晶体管T7均处于关闭状态，像素电路中没有形成通路；由于第一存储电容C1存储电压的作用，第四晶体管T4保持和初始化阶段t4一样的开启状态。例如，预发光阶段可以给像素电路提供一个稳定的时间，使各电路 元件的电压和电流状态稳定，防止电路异常情况发生。
例如，在发光阶段t6，第一控制端Sn-1输出高电平信号，第二控制端Sn输出高电平信号，第三控制端Sn+1输出高电平信号，第四控制端En输出低电平信号，第一数据信号端Data1输出第一数据信号Vdata1。
图8F是本公开实施例提供的如图6所示的像素电路被如图7所示的驱动时序驱动时在发光阶段t6的导通状态示意图。在发光阶段t6，第一晶体管T1、第三晶体管T3、第六晶体管T6和第七晶体管T7均处于关闭状态；由于第一存储电容C1存储电压的作用，第四晶体管T4保持和预发光阶段t5一样的开启状态；由于第四控制端En输出低电平信号，第二晶体管T2和第五晶体管T5处于开启状态，第一电源端ELVDD、第二晶体管T2、第四晶体管T4、第五晶体管T5、第一有机发光二极管OLED1和第二电源端ELVSS形成通路，第一有机发光二极管OLED1在第一电源端ELVDD提供的第一发光电压Velvdd和第二电源端ELVSS提供的第二发光电压Velvss的作用下，并在第四晶体管T4的驱动下发光，即第一发光控制电路控制第一发光电路的工作，第一电源端向第一发光电路提供第一发光电压，第二电源端向第一发光电路提供第二发光电压，第一驱动电路驱动第一发光电路，第一发光电路在工作时发光。
需要说明的是，如图6所示像素电路的驱动方法可以仅包括复位阶段t2、补偿阶段t3、初始化阶段t4和发光阶段t6，而不包括预复位阶段t1和预发光阶段t5，或者包括预复位阶段t1和预发光阶段t5中的一个，在此不做限定。
例如，图9是本公开实施例提供的又一种像素电路的示意图之一。如图9所示，本公开的实施例还提供一种像素电路600，包括：第二发光电路602，用于在工作时发光；第二驱动电路604，用于驱动第二发光电路602；第二补偿电路606，用于补偿第二驱动电路604；第二数据写入电路608，用于向第二驱动电路604写入数据；第二复位电路610，用于将第二驱动电路604复位；第二存储电路612，用于存储第二驱动电路604的驱动电压；第二初始化电路614，用于将第二发光电路602初始化；第二发光控制电路616，用于控制第二发光电路602的工作和关断，例如，第二发光控制电路616包括第一部分616A和第二部分616B；选通电路618，用于将第二数据信号或第三 数据信号传输给第二数据写入电路608；第一电源端ELVDD，用于向第二发光电路602提供第一发光电压Velvdd；第二电源端ELVSS，用于向第二发光电路602提供第二发光电压Velvss；第三电源端Vx，用于向第二复位电路610提供复位电压Vvx；第二数据信号端Data2，用于向第二数据写入电路608提供第二数据信号或待机信号；第三数据信号端Data3，用于向第二数据写入电路608提供第三数据信号或待机信号；第一控制端Sn-1，用于提供控制第二复位电路610工作和关断的第一控制信号；第二控制端Sn，用于提供控制第二数据写入电路608和第二补偿电路606工作和关断的第二控制信号；第三控制端Sn+1，用于提供控制第二初始化电路614工作和关断的第三控制信号；以及第四控制端En，用于提供控制第二发光控制电路616工作和关断的第四控制信号。
例如，图10是本公开实施例提供的又一种像素电路的示意图之二，图10是图9中所示像素电路的一种具体实施方式。如图9和图10所示，在本公开实施例提供的像素电路600中，第二数据写入电路608包括第八晶体管T8，第二发光控制电路616包括第九晶体管T9和第十二晶体管T12，例如，第二发光控制电路616的第一部分616A包括第九晶体管T9，第二发光控制电路616的第二部分616B包括第十二晶体管T12，第二补偿电路606包括第十晶体管T10，第二驱动电路604包括第十一晶体管T11，第二复位电路610包括第十三晶体管T13，第二初始化电路614包括第十四晶体管T14，第二存储电路612包括第二存储电容C2，第二发光电路602包括第二有机发光二极管OLED2、第三有机发光二极管OLED3、第十五晶体管T15和第十六晶体管T16，选通电路618包括第十七晶体管T17和第十八晶体管T18。
例如，如图10所示，第十晶体管T10包括第三子晶体管和第四子晶体管，第三子晶体管的源极作为第十晶体管T10的源极，第三子晶体管的漏极与第四子晶体管的源极电连接，第四子晶体管的漏极作为第十晶体管T10的漏极，第三子晶体管的栅极和第四子晶体管的栅极电连接共同作为第十晶体管T10的栅极。需要说明的是，本公开的实施例包括但不仅限于第十晶体管T10的这种组成方式，第十晶体管T10也可以仅包括一个晶体管，或者例如为双栅晶体管。
例如，如图10所示，在本公开实施例提供的像素电路600中，第八晶体 管T8的源极、第十七晶体管T17的漏极和第十八晶体管T18的漏极电连接，第八晶体管T8的栅极、第十晶体管T10的栅极和第二控制端Sn电连接，第八晶体管T8的漏极、第九晶体管T9的漏极、第十晶体管T10的源极和第十一晶体管T11的源极电连接；第九晶体管T9的栅极、第十二晶体管T12的栅极和第四控制端En电连接，第九晶体管T9的源极、第二存储电容C2的第一端和第一电源端ELVDD电连接；第十晶体管T10的漏极和第二节点N2电连接；第十一晶体管T11的栅极和第二节点N2电连接，第十一晶体管T11的漏极和第十二晶体管T12的源极电连接；第十二晶体管T12的漏极、第十四晶体管T14的漏极、第十五晶体管T15的源极、第十六晶体管T16的源极和第三节点电连接；第十三晶体管T13的源极、第十四晶体管T14的源极和第三电源端Vx电连接，第十三晶体管T13的栅极和第一控制端Sn-1电连接，第十三晶体管T13的漏极和第二节点N2电连接；第十四晶体管T14的栅极和第三控制端Sn+1电连接；第十五晶体管T15的栅极和第二数据信号端Data2电连接，第十五晶体管T15的漏极和第二有机发光二极管OLED2的第一端电连接；第十六晶体管T16的栅极和第三数据信号端Data3电连接，第十六晶体管T16的漏极和第三有机发光二极管OLED3的第一端电连接；第十七晶体管T17的源极和第二数据信号端Data2电连接，第十七晶体管T17的栅极和第三数据信号端Data3电连接；第十八晶体管T18的源极和第三数据信号端Data3电连接，第十八晶体管T18的栅极和第二数据信号端Data2电连接；第二存储电容C2的第二端和第二节点N2电连接；第二有机发光二极管OLED2的第二端、第三有机发光二极管OLED3的第二端和第二电源端ELVSS电连接。
例如，在本公开实施例提供的像素电路600中，第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第十六晶体管T16、第十七晶体管T17和第十八晶体管T18均为薄膜晶体管。
例如，在本公开实施例提供的像素电路600中，第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15和第十六晶体管T16均为P型晶体管，第十七晶体管T17和第十八晶体管T18均为N型晶体管。
例如，像素电路600同时控制第二有机发光二极管OLED2和第三有机发光二极管OLED3，由此整体上节省了像素电路的数量，进而减小了像素电路占用的面积，提高了显示面板的分辨率。
例如，在像素电路600工作时，可以是第二有机发光二极管OLED2单独发光，也可以是第三有机发光二极管OLED3单独发光。
本公开的实施例还提供一种如图10所示像素电路的驱动方法，该驱动方法包括：复位阶段、补偿阶段、初始化阶段和发光阶段。在复位阶段，第一控制端Sn-1输出有效信号，第二控制端Sn输出无效信号，第三控制端Sn+1输出无效信号，第四控制端En输出无效信号，第二数据信号端Data2输出待机信号，第三数据信号端Data3输出待机信号；在补偿阶段，第一控制端Sn-1输出无效信号，第二控制端Sn输出有效信号，第三控制端Sn+1输出无效信号，第四控制端En输出无效信号，第二数据信号端Data2输出第二数据信号，第三数据信号端Data3输出待机信号；在初始化阶段，第一控制端Sn-1输出无效信号，第二控制端Sn输出无效信号，第三控制端Sn+1输出有效信号，第四控制端En输出无效信号，第二数据信号端Data2输出第二数据信号，第三数据信号端Data3输出待机信号；在发光阶段，第一控制端Sn-1输出无效信号，第二控制端Sn输出无效信号，第三控制端Sn+1输出无效信号，第四控制端En输出有效信号，第二数据信号端Data2输出第二数据信号，第三数据信号端Data3输出待机信号；这种情形下第二有机发光二极管OLED2单独发光。
或者，在复位阶段，第一控制端Sn-1输出有效信号，第二控制端Sn输出无效信号，第三控制端Sn+1输出无效信号，第四控制端En输出无效信号，第二数据信号端Data2输出待机信号，第三数据信号端Data3输出待机信号；在补偿阶段，第一控制端Sn-1输出无效信号，第二控制端Sn输出有效信号，第三控制端Sn+1输出无效信号，第四控制端En输出无效信号，第二数据信号端Data2输出待机信号，第三数据信号端Data3输出第三数据信号；在初始化阶段，第一控制端Sn-1输出无效信号，第二控制端Sn输出无效信号，第三控制端Sn+1输出有效信号，第四控制端En输出无效信号，第二数据信号端Data2输出待机信号，第三数据信号端Data3输出第三数据信号；在发光阶段，第一控制端Sn-1输出无效信号，第二控制端Sn输出无效信号，第 三控制端Sn+1输出无效信号，第四控制端En输出有效信号，第二数据信号端Data2输出待机信号，第三数据信号端Data3输出第三数据信号；这种情形下第三有机发光二极管OLED3单独发光。
例如，本公开实施例提供的驱动方法，还可以包括：预复位阶段和预发光阶段。预复位阶段在发光阶段之后和复位阶段之前，预发光阶段在初始化阶段之后和发光阶段之前，在预复位阶段，第一控制端Sn-1输出无效信号，第二控制端Sn输出无效信号，第三控制端Sn+1输出无效信号，第四控制端En输出无效信号，第二数据信号端Data2输出待机信号，第三数据信号端Data3输出待机信号；在预发光阶段，第一控制端Sn-1输出无效信号，第二控制端Sn输出无效信号，第三控制端Sn+1输出无效信号，第四控制端En输出无效信号，第二数据信号端Data2输出第二数据信号，第三数据信号端Data3输出待机信号；或者，第二数据信号端Data2输出待机信号，第三数据信号端Data3输出第三数据信号。
例如，在本公开实施例提供的驱动方法中，在补偿阶段、初始化阶段、预发光阶段和发光阶段，当第二数据信号端Data2输出第二数据信号，第三数据信号端Data3输出待机信号时，第二有机发光二极管OLED2单独发光，第二数据信号用于控制第二有机发光二极管OLED2的发光亮度；当第二数据信号端Data2输出待机信号，第三数据信号端Data3输出第三数据信号时，第三有机发光二极管OLED3单独发光，第三数据信号用于控制第三有机发光二极管OLED3的发光亮度。
例如，第二有机发光二极管OLED2在工作时发出红色的光，第三有机发光二极管OLED3在工作时发出绿色的光。
需要说明的是，本公开实施例中所述的有效信号是指能使相应电路或晶体管开启的信号，无效信号是指能使相应电路或晶体管关闭的信号，第一数据信号、第二数据信号是指包含着相应发光电路或有机发光二极管发光亮度信息的信号(例如低电平信号)，待机信号是指能使相应发光电路或有机发光二极管不发光的信号(例如高电平信号)。例如，当晶体管为P型晶体管时，有效信号是指低电平信号，无效信号是指高电平信号，低电平信号和高电平信号的具体电压值可根据晶体管的属性进行相应设置。以下，本公开的实施例以第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管 T11、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15和第十六晶体管T16均为P型晶体管，第十七晶体管T17和第十八晶体管T18均为N型晶体管，第二有机发光二极管单独发光为例进行说明。
例如，图11是本公开实施例提供的如图10所示的像素电路的驱动时序图。本公开的实施例还提供一种如图10所示像素电路的驱动方法，包括：预复位阶段t1、复位阶段t2、补偿阶段t3、初始化阶段t4、预发光阶段t5和发光阶段t6。
例如，在预复位阶段t1，第一控制端Sn-1输出高电平信号，第二控制端Sn输出高电平信号，第三控制端Sn+1输出高电平信号，第四控制端En输出高电平信号，第二数据信号端Data2输出高电平信号，第三数据信号端Data3输出高电平信号。
例如，图12A是本公开实施例提供的如图10所示的像素电路被如图11所示的驱动时序驱动时在预复位阶段t1的导通状态示意图。在预复位阶段t1，第八晶体管T8、第九晶体管T9、第十晶体管T10、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15和第十六晶体管T16均处于关闭状态，第十七晶体管T17(N型晶体管)和第十八晶体管T18(N型晶体管)导通；第十一晶体管T11的导通状态与第二节点N2的电压有关。例如，预复位阶段可以给像素电路提供一个稳定的时间，使各电路元件的电压和电流状态稳定，防止电路异常情况发生。
例如，在复位阶段t2，第一控制端Sn-1输出低电平信号，第二控制端Sn输出高电平信号，第三控制端Sn+1输出高电平信号，第四控制端En输出高电平信号，第二数据信号端Data2输出高电平信号，第三数据信号端Data3输出高电平信号。
图12B是本公开实施例提供的如图10所示的像素电路被如图11所示的驱动时序驱动时在复位阶段t2的导通状态示意图。在复位阶段t2，第八晶体管T8、第九晶体管T9、第十晶体管T10、第十二晶体管T12、第十四晶体管T14、第十五晶体管T15和第十六晶体管T16均处于关闭状态，第十七晶体管T17和第十八晶体管T18导通；由于第一控制端Sn-1输出低电平信号，第十三晶体管T13导通，第二节点N2的电压为第三电源端Vx提供的复位电压Vvx，复位电压Vvx例如为能使P型晶体管开启的低电平电压，又例如， 复位电压Vvx为负电压；此时，由于第二节点N2的电压为低电平的复位电压Vvx，第十一晶体管T11开启但不会形成通路。这样就实现了通过第十三晶体管T13将第十一晶体管T11复位，即第二复位电路将第二驱动电路复位。例如，经过复位阶段可以增加第二节点N2和第二数据信号Vdata2之间的电压差，减小了在补偿阶段t3中，对第二存储电容C2的充电时间。
例如，在补偿阶段t3，第一控制端Sn-1输出高电平信号，第二控制端Sn输出低电平信号，第三控制端Sn+1输出高电平信号，第四控制端En输出高电平信号，第二数据信号端Data2输出第二数据信号Vdata2(例如低电平信号)，第三数据信号端Data3输出高电平信号。
图12C是本公开实施例提供的如图10所示的像素电路被如图11所示的驱动时序驱动时在补偿阶段t3的导通状态示意图。在补偿阶段t3，第九晶体管T9、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十六晶体管T16和第十八晶体管T18均处于关闭状态；由于第二数据信号端Data2输出第二数据信号Vdata2(例如低电平信号)，第十五晶体管T15导通；由于第三数据信号端Data3输出高电平信号，第十七晶体管T17导通；由于第二控制端Sn输出低电平信号，第八晶体管T8和第十晶体管T10导通。第二数据信号端Data2输出的第二数据信号Vdata2通过第十七晶体管T17、第八晶体管T8和第十晶体管T10传输到第二节点N2，对第二存储电容C2充电完成后，第二节点N2的电压为Vdata1+Vth2(Vth2为第十七晶体管T17、第八晶体管T8和第十晶体管T10的总压降)。也就是说，选通电路将第二数据信号传输给第二数据写入电路，第二数据写入电路向第二驱动电路写入了数据，第二补偿电路对第二驱动电路进行了补偿，此时，第十一晶体管T11开启但不会形成通路。
例如，在初始化阶段t4，第一控制端Sn-1输出高电平信号，第二控制端Sn输出高电平信号，第三控制端Sn+1输出低电平信号，第四控制端En输出高电平信号，第二数据信号端Data2输出第二数据信号Vdata2(例如低电平信号)，第三数据信号端Data3输出高电平信号。
图12D是本公开实施例提供的如图10所示的像素电路被如图11所示的驱动时序驱动时在初始化阶段t4的导通状态示意图。在初始化阶段t4，第八晶体管T8、第九晶体管T9、第十晶体管T10、第十二晶体管T12、第十三晶 体管T13、第十六晶体管T16和第十八晶体管T18均处于关闭状态；由于第二存储电容C2存储电压的作用，第十一晶体管T11保持和补偿阶段t3一样的开启状态；由于第二数据信号端Data2输出第二数据信号Vdata2(例如低电平信号)，第十五晶体管T15导通；由于第三数据信号端Data3输出高电平信号，第十七晶体管T17导通；由于第三控制端Sn+1输出低电平信号，第十四晶体管T14导通，第三电源端Vx提供的复位电压Vvx通过第十四晶体管T14传输到第十五晶体管T15源极和第十六晶体管T16的源极，即第二初始化电路将第二发光电路初始化。例如，复位电压Vvx小于或等于第二电源端ELVSS提供的第二发光电压Velvss，这样，经过初始化可以防止OLED的异常发光，例如可以防止OLED在非发光阶段的微亮发光。例如，对有机发光二极管进行初始化放电，保证了低灰阶的准确性及全暗态画面下的全黑，可以有效改善整个显示面板的对比度。
例如，在预发光阶段t5，第一控制端Sn-1输出高电平信号，第二控制端Sn输出高电平信号，第三控制端Sn+1输出高电平信号，第四控制端En输出高电平信号，第二数据信号端Data2输出第二数据信号Vdata2，第三数据信号端Data3输出高电平信号。
图12E是本公开实施例提供的如图10所示的像素电路被如图11所示的驱动时序驱动时在预发光阶段t5的导通状态示意图。在预发光阶段t5，第八晶体管T8、第九晶体管T9、第十晶体管T10、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十六晶体管T16和第十八晶体管T18均处于关闭状态，第十五晶体管T15和第十七晶体管T17开启；由于第二存储电容C2存储电压的作用，第十一晶体管T11保持和初始化阶段t4一样的开启状态。例如，预发光阶段可以给像素电路提供一个稳定的时间，使各电路元件的电压和电流状态稳定，防止电路异常情况发生。
例如，在发光阶段t6，第一控制端Sn-1输出高电平信号，第二控制端Sn输出高电平信号，第三控制端Sn+1输出高电平信号，第四控制端En输出低电平信号，第二数据信号端Data2输出第二数据信号Vdata2，第三数据信号端Data3输出高电平信号。
图12F是本公开实施例提供的如图10所示的像素电路被如图11所示的驱动时序驱动时在发光阶段t6的导通状态示意图。在发光阶段t6，第八晶体 管T8、第十晶体管T10、第十三晶体管T13、第十四晶体管T14、第十六晶体管T16和第十八晶体管T18均处于关闭状态，第十五晶体管T15和第十七晶体管T17开启；由于第二存储电容C2存储电压的作用，第十一晶体管T11保持和预发光阶段t5一样的开启状态；由于第四控制端En输出低电平信号，第九晶体管T9和第十二晶体管T12处于开启状态，第一电源端ELVDD、第九晶体管T9、第十一晶体管T11、第十二晶体管T12、第十五晶体管T15、第二有机发光二极管OLED2和第二电源端ELVSS形成通路，第二有机发光二极管OLED2在第一电源端ELVDD提供的第一发光电压Velvdd和第二电源端ELVSS提供的第二发光电压Velvss的作用下，并在第十一晶体管T11的驱动下发光，即第二发光控制电路控制第二发光电路的工作，第一电源端向第二发光电路提供第一发光电压，第二电源端向第二发光电路提供第二发光电压，第二驱动电路驱动第二发光电路，第二发光电路在工作时发光。
需要说明的是，如图10所示像素电路的驱动方法可以仅包括复位阶段t2、补偿阶段t3、初始化阶段t4和发光阶段t6，而不包括预复位阶段t1和预发光阶段t5，或者包括预复位阶段t1和预发光阶段t5中的一个，在此不做限定。
例如，第三有机发光二极管OLED3单独发光的情形与上述第二有机发光二极管OLED2单独发光的情形类似，在此不再赘述。
本公开的实施例还提供一种驱动方法，包括如图6所示像素电路的驱动方法以及如图10所示像素电路的驱动方法。
本公开的实施例还提供一种显示面板，包括本公开前述任一实施例提供的像素电路。
例如，本公开实施例提供的显示面板，还可以包括本公开前述任一实施例提供的像素排列结构，这些像素排列结构采用相应的像素电路。
例如，如图13所示，显示面板2包括本公开任一实施例提供的像素排列结构10、像素电路500和像素电路600。
例如，在显示面板2中，两个像素电路500和一个像素电路600组成一个像素电路组。在一个像素电路组中，其中一个像素电路500中的第一有机发光二极管发出蓝色的光，另一个像素电路500中的第一有机发光二极管发出黄色的光，像素电路600中的第二有机发光二极管发出红色的光，像素电 路600中的第三有机发光二极管发出绿色的光。
例如，显示面板2中的像素电路500中的OLED和像素电路600中的OLED用于像素排列结构10中的子像素在工作时发光。
例如，本公开实施例提供的显示面板可以用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开的实施例提供的像素排列结构、像素电路、显示面板及驱动方法，可以减小子像素之间的距离，同时减小像素电路占用的面积，进而提高显示面板的分辨率，并可以对有机发光二极管进行初始化放电，保证了低灰阶的准确性及全暗态画面下的全黑，有效改善整个显示面板的对比度。
虽然上文中已经用一般性说明及具体实施方式，对本公开作了详尽的描述，但在本公开实施例基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本公开精神的基础上所做的这些修改或改进，均属于本公开要求保护的范围。
本专利申请要求于2016年7月26日递交的中国专利申请第201610596086.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (40)

  1. 一种像素排列结构，包括：
    第一像素单元，包括第一子像素、第二子像素、第三子像素、第四子像素，其中，所述第一子像素的中心与第一虚拟菱形的第一顶点重合，所述第二子像素的中心与所述第一虚拟菱形的第二顶点重合，所述第三子像素的中心与所述第一虚拟菱形的第三顶点重合，所述第四子像素的中心与所述第一虚拟菱形的第四顶点重合。
  2. 根据权利要求1所述的像素排列结构，其中，所述第一虚拟菱形的第一顶点、第二顶点、第三顶点和第四顶点依次相邻，所述第一子像素和所述第三子像素为矩形，所述第二子像素和所述第四子像素为三角形。
  3. 根据权利要求2所述的像素排列结构，其中，所述矩形为正方形，所述三角形为等腰三角形。
  4. 根据权利要求2所述的像素排列结构，其中，所述矩形一条边的中垂线经过所述第一虚拟菱形的中心，所述三角形一条边的中垂线经过所述第一虚拟菱形的中心。
  5. 根据权利要求1-4任一项所述的像素排列结构，其中，所述第一子像素在工作时发出第一颜色的光，所述第二子像素在工作时发出第二颜色的光，所述第三子像素在工作时发出第三颜色的光，所述第四子像素在工作时发出第四颜色的光。
  6. 根据权利要求5所述的像素排列结构，其中，所述第二颜色和所述第四颜色的混合色为第一颜色或第三颜色。
  7. 根据权利要求5所述的像素排列结构，其中，所述第一颜色和所述第三颜色的混合色为白色。
  8. 根据权利要求5所述的像素排列结构，其中，所述第一颜色为蓝色，所述第二颜色为绿色，所述第三颜色为黄色，所述第四颜色为红色。
  9. 根据权利要求1所述的像素排列结构，还包括：
    第二像素单元，包括第五子像素、第六子像素、第七子像素、第八子像素，其中，所述第五子像素的中心与第二虚拟菱形的第一顶点重合，所述第六子像素的中心与所述第二虚拟菱形的第二顶点重合，所述第七子像素的中 心与所述第二虚拟菱形的第三顶点重合，所述第八子像素的中心与所述第二虚拟菱形的第四顶点重合；
    第三像素单元，包括第九子像素、第十子像素、第十一子像素、第十二子像素，其中，所述第九子像素的中心与第三虚拟菱形的第一顶点重合，所述第十子像素的中心与所述第三虚拟菱形的第二顶点重合，所述第十一子像素的中心与所述第三虚拟菱形的第三顶点重合，所述第十二子像素的中心与所述第三虚拟菱形的第四顶点重合；
    其中，所述第一虚拟菱形的中心与虚拟三角形的第一顶点重合，所述第二虚拟菱形的中心与所述虚拟三角形的第二顶点重合，所述第三虚拟菱形的中心与所述虚拟三角形的第三顶点重合。
  10. 根据权利要求9所述的像素排列结构，其中，所述虚拟三角形为锐角三角形。
  11. 根据权利要求9所述的像素排列结构，其中，所述虚拟三角形为等腰锐角三角形。
  12. 根据权利要求9所述的像素排列结构，其中，所述虚拟三角形为等边三角形。
  13. 根据权利要求9-12任一项所述的像素排列结构，其中，所述第一虚拟菱形、所述第二虚拟菱形和所述第三虚拟菱形的形状相同。
  14. 根据权利要求9-12任一项所述的像素排列结构，其中，所述第一虚拟菱形的第一顶点、第二顶点、第三顶点和第四顶点依次相邻，所述第二虚拟菱形的第一顶点、第二顶点、第三顶点和第四顶点依次相邻，所述第三虚拟菱形的第一顶点、第二顶点、第三顶点和第四顶点依次相邻，所述第一子像素、所述第五子像素和所述第九子像素的形状相同，所述第二子像素、所述第六子像素和所述第十子像素的形状相同，所述第三子像素、所述第七子像素和所述第十一子像素的形状相同，所述第四子像素、所述第八子像素和所述第十二子像素的形状相同。
  15. 根据权利要求14所述的像素排列结构，其中，所述第一子像素、第三子像素、第五子像素、第七子像素、第九子像素和第十一子像素为矩形，所述第二子像素、所述第四子像素、所述第六子像素、所述第八子像素、所述第十子像素和所述第十二子像素为三角形。
  16. 根据权利要求15所述的像素排列结构，其中，所述矩形为正方形，所述三角形为等腰三角形。
  17. 根据权利要求15所述的像素排列结构，其中，所述矩形一条边的中垂线经过一个所述虚拟菱形的中心，所述三角形一条边的中垂线经过一个所述虚拟菱形的中心。
  18. 根据权利要求14所述的像素排列结构，其中，所述第一子像素、所述第五子像素和所述第九子像素在工作时发出第一颜色的光，所述第二子像素、所述第六子像素和所述第十子像素在工作时发出第二颜色的光，所述第三子像素、所述第七子像素和所述第十一子像素在工作时发出第三颜色的光，所述第四子像素、所述第八子像素和所述第十二子像素在工作时发出第四颜色的光。
  19. 根据权利要求18所述的像素排列结构，其中，所述第二颜色和所述第四颜色的混合色为第一颜色或第三颜色。
  20. 根据权利要求18所述的像素排列结构，其中，所述第一颜色和所述第三颜色的混合色为白色。
  21. 根据权利要求18所述的像素排列结构，其中，所述第一颜色为蓝色，所述第二颜色为绿色，所述第三颜色为黄色，所述第四颜色为红色。
  22. 一种像素电路，包括：
    第一发光电路，用于在工作时发光；
    第一驱动电路，用于驱动所述第一发光电路；
    第一补偿电路，用于补偿所述第一驱动电路；
    第一数据写入电路，用于向所述第一驱动电路写入数据；
    第一复位电路，用于将所述第一驱动电路复位；
    第一存储电路，用于存储所述第一驱动电路的驱动电压；
    第一初始化电路，用于将所述第一发光电路初始化；
    第一发光控制电路，用于控制所述第一发光电路的工作和关断；
    第一电源端，用于向所述第一发光电路提供第一发光电压；
    第二电源端，用于向所述第一发光电路提供第二发光电压；
    第三电源端，用于向所述第一复位电路提供复位电压；
    第一数据信号端，用于向所述第一数据写入电路提供第一数据信号或待 机信号；
    第一控制端，用于提供控制所述第一复位电路工作和关断的第一控制信号；
    第二控制端，用于提供控制所述第一数据写入电路和所述第一补偿电路工作和关断的第二控制信号；
    第三控制端，用于提供控制所述第一初始化电路工作和关断的第三控制信号；以及
    第四控制端，用于提供控制所述第一发光控制电路工作和关断的第四控制信号。
  23. 根据权利要求22所述的像素电路，其中，所述第一数据写入电路包括第一晶体管，所述第一发光控制电路包括第二晶体管和第五晶体管，所述第一补偿电路包括第三晶体管，所述第一驱动电路包括第四晶体管，所述第一复位电路包括第六晶体管，所述第一初始化电路包括第七晶体管，所述第一存储电路包括第一存储电容，所述第一发光电路包括第一有机发光二极管。
  24. 根据权利要求23所述的像素电路，其中，
    所述第一晶体管的源极与所述第一数据信号端电连接，所述第一晶体管的栅极、所述第三晶体管的栅极和所述第二控制端电连接，所述第一晶体管的漏极、所述第二晶体管的漏极、所述第三晶体管的源极和所述第四晶体管的源极电连接；
    所述第二晶体管的栅极、所述第五晶体管的栅极和所述第四控制端电连接，所述第二晶体管的源极、所述第一存储电容的第一端和所述第一电源端电连接；
    所述第三晶体管的漏极和第一节点电连接；
    所述第四晶体管的栅极和所述第一节点电连接，所述第四晶体管的漏极和所述第五晶体管的源极电连接；
    所述第五晶体管的漏极、所述第七晶体管的漏极和所述第一有机发光二极管的第一端电连接；
    所述第六晶体管的源极、所述第七晶体管的源极和所述第三电源端电连接，所述第六晶体管的栅极和所述第一控制端电连接，第六晶体管的漏极和所述第一节点电连接；
    所述第七晶体管的栅极和所述第三控制端电连接；
    所述第一存储电容的第二端和所述第一节点电连接；
    所述第一有机发光二极管的第二端和所述第二电源端电连接。
  25. 根据权利要求23或24所述的像素电路，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管以及所述第七晶体管均为薄膜晶体管。
  26. 根据权利要求23或24所述的像素电路，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管以及所述第七晶体管均为P型晶体管。
  27. 一种像素电路，包括：
    第二发光电路，用于在工作时发光；
    第二驱动电路，用于驱动所述第二发光电路；
    第二补偿电路，用于补偿所述第二驱动电路；
    第二数据写入电路，用于向所述第二驱动电路写入数据；
    第二复位电路，用于将所述第二驱动电路复位；
    第二存储电路，用于存储所述第二驱动电路的驱动电压；
    第二初始化电路，用于将所述第二发光电路初始化；
    第二发光控制电路，用于控制所述第二发光电路的工作和关断；
    选通电路，用于将第二数据信号或第三数据信号传输给所述第二数据写入电路；
    第一电源端，用于向所述第二发光电路提供第一发光电压；
    第二电源端，用于向所述第二发光电路提供第二发光电压；
    第三电源端，用于向所述第二复位电路提供复位电压；
    第二数据信号端，用于向所述第二数据写入电路提供第二数据信号或待机信号；
    第三数据信号端，用于向所述第二数据写入电路提供第三数据信号或待机信号；
    第一控制端，用于提供控制所述第二复位电路工作和关断的第一控制信号；
    第二控制端，用于提供控制所述第二数据写入电路和所述第二补偿电路 工作和关断的第二控制信号；
    第三控制端，用于提供控制所述第二初始化电路工作和关断的第三控制信号；以及
    第四控制端，用于提供控制所述第二发光控制电路工作和关断的第四控制信号。
  28. 根据权利要求27所述的像素电路，其中，所述第二数据写入电路包括第八晶体管，所述第二发光控制电路包括第九晶体管和第十二晶体管，所述第二补偿电路包括第十晶体管，所述第二驱动电路包括第十一晶体管，所述第二复位电路包括第十三晶体管，所述第二初始化电路包括第十四晶体管，所述第二存储电路包括第二存储电容，所述第二发光电路包括第二有机发光二极管、第三有机发光二极管、第十五晶体管和第十六晶体管，所述选通电路包括第十七晶体管和第十八晶体管。
  29. 根据权利要求28所述的像素电路，其中，
    所述第八晶体管的源极、所述第十七晶体管的漏极和所述第十八晶体管的漏极电连接，所述第八晶体管的栅极、所述第十晶体管的栅极和所述第二控制端电连接，所述第八晶体管的漏极、所述第九晶体管的漏极、所述第十晶体管的源极和所述第十一晶体管的源极电连接；
    所述第九晶体管的栅极、所述第十二晶体管的栅极和所述第四控制端电连接，所述第九晶体管的源极、所述第二存储电容的第一端和所述第一电源端电连接；
    所述第十晶体管的漏极和第二节点电连接；
    所述第十一晶体管的栅极和所述第二节点电连接，所述第十一晶体管的漏极和所述第十二晶体管的源极电连接；
    所述第十二晶体管的漏极、所述第十四晶体管的漏极、所述第十五晶体管的源极、所述第十六晶体管的源极和第三节点电连接；
    所述第十三晶体管的源极、所述第十四晶体管的源极和所述第三电源端电连接，所述第十三晶体管的栅极和所述第一控制端电连接，第十三晶体管的漏极和所述第二节点电连接；
    所述第十四晶体管的栅极和所述第三控制端电连接；
    所述第十五晶体管的栅极和所述第二数据信号端电连接，所述第十五晶 体管的漏极和所述第二有机发光二极管的第一端电连接；
    所述第十六晶体管的栅极和所述第三数据信号端电连接，所述第十六晶体管的漏极和所述第三有机发光二极管的第一端电连接；
    所述第十七晶体管的源极和所述第二数据信号端电连接，所述第十七晶体管的栅极和所述第三数据信号端电连接；
    所述第十八晶体管的源极和所述第三数据信号端电连接，所述第十八晶体管的栅极和所述第二数据信号端电连接；
    所述第二存储电容的第二端和所述第二节点电连接；
    所述第二有机发光二极管的第二端、所述第三有机发光二极管的第二端和所述第二电源端电连接。
  30. 根据权利要求28或29所述的像素电路，其中，所述第八晶体管、所述第九晶体管、所述第十晶体管、所述第十一晶体管、所述第十二晶体管、所述第十三晶体管、所述第十四晶体管、所述第十五晶体管、所述第十六晶体管、所述第十七晶体管和所述第十八晶体管均为薄膜晶体管。
  31. 根据权利要求28或29所述的像素电路，其中，所述第八晶体管、所述第九晶体管、所述第十晶体管、所述第十一晶体管、所述第十二晶体管、所述第十三晶体管、所述第十四晶体管、所述第十五晶体管和所述第十六晶体管均为P型晶体管，所述第十七晶体管和所述第十八晶体管均为N型晶体管。
  32. 一种显示面板，包括如权利要求1-21任一项所述的像素排列结构。
  33. 一种显示面板，包括如权利要求22-31任一项所述的像素电路。
  34. 根据权利要求33所述的显示面板，包括如权利要求22-26任一项所述的像素电路以及如权利要求27-31任一项所述的像素电路。
  35. 根据权利要求34所述的显示面板，还包括如权利要求1-21任一项所述的像素排列结构，其中，如权利要求22-26任一项所述的像素电路中的第一发光电路在工作时发出蓝色或黄色的光；如权利要求27-31任一项所述的像素电路中的第二发光电路在工作时发出红色或绿色的光。
  36. 一种如权利要求22-31任一项所述像素电路的驱动方法，包括：复位阶段、补偿阶段、初始化阶段和发光阶段，其中，
    在所述复位阶段，所述第一控制端输出有效信号，所述第二控制端输出 无效信号，所述第三控制端输出无效信号，所述第四控制端输出无效信号，所述第一数据信号端输出待机信号；
    在所述补偿阶段，所述第一控制端输出无效信号，所述第二控制端输出有效信号，所述第三控制端输出无效信号，所述第四控制端输出无效信号，所述第一数据信号端输出第一数据信号；
    在所述初始化阶段，所述第一控制端输出无效信号，所述第二控制端输出无效信号，所述第三控制端输出有效信号，所述第四控制端输出无效信号，所述第一数据信号端输出第一数据信号；
    在所述发光阶段，所述第一控制端输出无效信号，所述第二控制端输出无效信号，所述第三控制端输出无效信号，所述第四控制端输出有效信号，所述第一数据信号端输出第一数据信号。
  37. 根据权利要求36所述的驱动方法，还包括：预复位阶段和预发光阶段，其中，预复位阶段在所述发光阶段之后和所述复位阶段之前，所述预发光阶段在所述初始化阶段之后和所述发光阶段之前，
    在所述预复位阶段，所述第一控制端输出无效信号，所述第二控制端输出无效信号，所述第三控制端输出无效信号，所述第四控制端输出无效信号，所述第一数据信号端输出待机信号；
    在所述预发光阶段，所述第一控制端输出无效信号，所述第二控制端输出无效信号，所述第三控制端输出无效信号，所述第四控制端输出无效信号，所述第一数据信号端输出第一数据信号。
  38. 一种如权利要求27-31任一项所述像素电路的驱动方法，包括：复位阶段、补偿阶段、初始化阶段和发光阶段，其中，
    在所述复位阶段，所述第一控制端输出有效信号，所述第二控制端输出无效信号，所述第三控制端输出无效信号，所述第四控制端输出无效信号，所述第二数据信号端输出待机信号，所述第三数据信号端输出待机信号；
    在所述补偿阶段，所述第一控制端输出无效信号，所述第二控制端输出有效信号，所述第三控制端输出无效信号，所述第四控制端输出无效信号，所述第二数据信号端输出第二数据信号，所述第三数据信号端输出待机信号；
    在所述初始化阶段，所述第一控制端输出无效信号，所述第二控制端输出无效信号，所述第三控制端输出有效信号，所述第四控制端输出无效信号， 所述第二数据信号端输出第二数据信号，所述第三数据信号端输出待机信号；
    在所述发光阶段，所述第一控制端输出无效信号，所述第二控制端输出无效信号，所述第三控制端输出无效信号，所述第四控制端输出有效信号，所述第二数据信号端输出第二数据信号，所述第三数据信号端输出待机信号；或者，
    在所述复位阶段，所述第一控制端输出有效信号，所述第二控制端输出无效信号，所述第三控制端输出无效信号，所述第四控制端输出无效信号，所述第二数据信号端输出待机信号，所述第三数据信号端输出待机信号；
    在所述补偿阶段，所述第一控制端输出无效信号，所述第二控制端输出有效信号，所述第三控制端输出无效信号，所述第四控制端输出无效信号，所述第二数据信号端输出待机信号，所述第三数据信号端输出第三数据信号；
    在所述初始化阶段，所述第一控制端输出无效信号，所述第二控制端输出无效信号，所述第三控制端输出有效信号，所述第四控制端输出无效信号，所述第二数据信号端输出待机信号，所述第三数据信号端输出第三数据信号；
    在所述发光阶段，所述第一控制端输出无效信号，所述第二控制端输出无效信号，所述第三控制端输出无效信号，所述第四控制端输出有效信号，所述第二数据信号端输出待机信号，所述第三数据信号端输出第三数据信号。
  39. 根据权利要求38所述的驱动方法，还包括：预复位阶段和预发光阶段，其中，预复位阶段在所述发光阶段之后和所述复位阶段之前，所述预发光阶段在所述初始化阶段之后和所述发光阶段之前，
    在所述预复位阶段，所述第一控制端输出无效信号，所述第二控制端输出无效信号，所述第三控制端输出无效信号，所述第四控制端输出无效信号，所述第二数据信号端输出待机信号，所述第三数据信号端输出待机信号；
    在所述预发光阶段，所述第一控制端输出无效信号，所述第二控制端输出无效信号，所述第三控制端输出无效信号，所述第四控制端输出无效信号，所述第二数据信号端输出第二数据信号，所述第三数据信号端输出待机信号；或者，所述第二数据信号端输出待机信号，所述第三数据信号端输出第三数据信号。
  40. 一种驱动方法，包括如权利要求36所述的驱动方法以及如权利要求38所述的驱动方法。
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