WO2018014249A1 - 低密度奇偶校验码基矩阵生成方法及装置 - Google Patents

低密度奇偶校验码基矩阵生成方法及装置 Download PDF

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WO2018014249A1
WO2018014249A1 PCT/CN2016/090646 CN2016090646W WO2018014249A1 WO 2018014249 A1 WO2018014249 A1 WO 2018014249A1 CN 2016090646 W CN2016090646 W CN 2016090646W WO 2018014249 A1 WO2018014249 A1 WO 2018014249A1
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matrix
ring
group
length characteristic
replaced
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PCT/CN2016/090646
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English (en)
French (fr)
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郑晨
魏岳军
马亮
曾歆
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华为技术有限公司
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Priority to EP16909178.2A priority Critical patent/EP3471275B1/en
Priority to CN201680073765.5A priority patent/CN108370254B/zh
Priority to PCT/CN2016/090646 priority patent/WO2018014249A1/zh
Priority to JP2019502091A priority patent/JP6798754B2/ja
Publication of WO2018014249A1 publication Critical patent/WO2018014249A1/zh
Priority to US16/251,182 priority patent/US10879931B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/1157—Low-density generator matrices [LDGM]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/1177—Regular LDPC codes with parity-check matrices wherein all rows and columns have the same row weight and column weight, respectively
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6516—Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the present application relates to the field of wireless communications, and in particular, to a method and an apparatus for generating a low density parity check code base matrix.
  • a quasi cycle low density parity check code (QC-LDPC) is a type of linear block coding with a sparse check matrix. Because QC-LDPC not only has good performance close to the Shannon limit, but also has the characteristics of flexible structure and low decoding complexity, it can be widely used in various communication systems.
  • QC-LDPC check matrix For the wireless communication device, different sizes of radio resource blocks (RBs) may be allocated to the wireless communication devices according to different transmission requirements, and QCs supported by the wireless communication devices under different RBs of different sizes.
  • the code length of LDPC is also different.
  • n, k are all positive integers, and are preset in accordance with the spreading factors corresponding to the code lengths of the respective QC-LDPCs.
  • the data transmission device After the code length of the QC-LDPC is determined, the data transmission device first acquires a spreading factor corresponding to the code length, and then performs expansion using the base matrix of the spreading factor, thereby obtaining a check matrix corresponding to the code length. . In this manner, different check matrices can be obtained on the basis of the base matrix when the code lengths of the QC-LDPC are different, so that the wireless communication device can support QC-LDPCs of different code lengths.
  • each of the check matrices formed has good loop length characteristics.
  • the loop length characteristics of some check matrices are poor, the error level of these check matrices is high, which affects the reliability of data transmission using QC-LDPC with the corresponding code length.
  • the present application provides a low density parity check code base matrix generation method and apparatus to reduce the problem that the base matrix has a higher error level under a partial spreading factor.
  • the present application provides a method for generating a low density parity check code base matrix, the method comprising: acquiring a low density parity check code matrix; generating a first matrix to a qth matrix one by one, q being a preset positive integer; For any of the first matrix to the qth matrix, the P matrix is generated by selecting a matrix element to be replaced in the P-1 matrix, and the replacement matrix element is in the P-1 matrix.
  • the ring length characteristic determines that the P-th matrix group includes a matrix formed by expanding the P-th matrix respectively under each preset spreading factor; and the ring length characteristic of the P-1 matrix is determined by the P-1 matrix group
  • the ring length characteristic of each matrix included is determined, and the P-1 matrix group includes The P-1 matrix expands the formed matrix separately under each predetermined spreading factor.
  • the base matrix is generated by the method provided by the aspect, and since the shift factor setting of the base matrix considers the loop length characteristic of the expansion matrix formed under all the expansion factors, the base matrix can be expanded under each preset expansion factor.
  • the average loop length characteristic of the check matrix is superior, so that the check matrix obtained under each preset expansion factor has a good loop length characteristic, so that the base matrix can be expanded according to all preset expansion factors.
  • the resulting check matrix has a lower error leveling layer, which avoids the high level of error leveling of some check matrixes.
  • a loop length characteristic of the P-th matrix is better than a loop length characteristic of the P-1 matrix, and the approximate external information degree ACE in the P-th matrix group is smaller than
  • the number of 4 loops to L loops in which the ACE of the first preset value is smaller than the first preset value in the 4th loop to the L loop and the P-1 matrix group is the same, and the 4th loop to the L loop and the Pth in the P matrix group.
  • the number of 4 rings to L rings in the matrix group is also the same, and the L+2 ring in which the ACE is smaller than the second preset value in the P matrix group is smaller than the ACE in the P-1 matrix group is less than the second preset value.
  • L+2 ring where L is an even number less than a preset value.
  • a loop length characteristic of the P-th matrix is better than a loop length characteristic of the P-1 matrix, including: a 4-ring to an L-ring in the P-th matrix group
  • the number of 4 loops to L loops in the P-1 matrix group is the same, and the approximate external information degree ACE in the P matrix group is smaller than the second preset value of the 4 loop to the L+2 loop and the ACE in the P-1 matrix group.
  • the number of 4 ring to L+2 rings smaller than the second preset value is also the same, and the L+2 ring in the Pth matrix group is smaller than the L+2 ring in the P-1 matrix group; wherein L is smaller than The even number of preset values.
  • the P shift factor includes: acquiring a Pk shift factor corresponding to the matrix element to be replaced; replacing the matrix element to be replaced in the P-1 matrix with the Pk shift factor Thereby generating a Pk matrix; if the loop length characteristic of the Pk matrix is better than the loop length characteristic of the P-1 matrix, the Pk shift factor is taken as the Pth shift factor.
  • the method further includes: if a loop length characteristic of the P k matrix is not better than a loop length characteristic of the P-1 matrix, Obtaining a P k+ 1th shift factor corresponding to the matrix element to be replaced; replacing the matrix element to be replaced in the P-1 matrix with the P k+ 1th shift factor, thereby Generating a Pk+1 matrix; if the ring length characteristic of the Pk+1 matrix is better than the ring length characteristic of the P-1 matrix, then using the Pk+1 shift factor as the Pth Shift factor.
  • the present application further provides a low density parity check code base matrix generating apparatus, and the apparatus may comprise means for performing the first aspect and the method steps in the various implementation manners of the first aspect.
  • the present application further provides a generating device, where the generating device may be composed of a processor, a memory, and a component of a communication interface, where the processor may be configured to perform the foregoing first aspect and various implementations of the first aspect. All or part of the method steps in the way.
  • the check matrix formed according to the base matrix expanded under all preset expansion factors has a lower error leveling layer, and the error level of some check matrix is avoided. appear.
  • the base matrix is generated by the method provided by the present application, and the average loop length characteristic of each check matrix obtained by expanding the base matrix generated by each of the preset expansion factors is superior, thereby avoiding a certain preset expansion factor.
  • the problem that the resulting check matrix has poor ring length characteristics ensures that the check matrix obtained under each preset expansion factor has a good loop length characteristic, so that the error level of some check matrices can be avoided. The situation arises.
  • FIG. 1 is a schematic flow chart of an embodiment of a method for generating a low density parity check code base matrix according to the present application
  • FIG. 2 is a schematic flow chart of an embodiment of a method for generating a P matrix of the present application
  • FIG. 3 is a schematic flowchart diagram of an embodiment of a method for determining a P-th shift factor according to the present application
  • FIG. 4 is a schematic structural diagram of an embodiment of a low density parity check code base matrix generating apparatus according to the present application.
  • FIG. 5 is a schematic structural diagram of an embodiment of a low density parity check code base matrix generating apparatus generating unit according to the present application
  • FIG. 6 is a schematic structural diagram of an embodiment of a generating device of the present application.
  • the ring in the matrix refers to the ring in the Tanner graph corresponding to the matrix when the matrix is used as the check matrix of the low density parity check code.
  • the L-ring refers to a ring composed of L nodes.
  • the characteristics of the Tanner graph can be known as L-even, and the minimum value of L is 4, and the maximum value is the number of rows and columns of the matrix and the complexity of the matrix. Decide. It should be noted here that since there is no ring with a vertex of 2 in the Tanner graph, the number of the two rings can be considered to be zero.
  • a matrix group refers to a group of matrices formed by expanding a matrix as a base matrix under respective preset spreading factors.
  • the matrix group contains the same number of matrices as the preset spreading factor, and each matrix in the matrix group uniquely corresponds to one spreading factor.
  • the ring length characteristic of the matrix group may refer to the total number of rings that meet the predetermined condition in all the matrices included in the matrix group, and the better ring length characteristic refers to the total number of rings that meet the predetermined condition. less.
  • the loop length characteristic of the matrix group is also the loop length characteristic of the matrix corresponding to the matrix group.
  • a set of matrices formed by expanding the A matrix under each preset expansion factor is an A matrix group
  • a set of matrices formed by expanding the B matrix under each preset expansion factor is a B matrix group.
  • the ring length characteristic of the A matrix group is the total number of rings in the respective matrix included in the A matrix group that meet the predetermined condition
  • the ring length characteristic of the B matrix group is the ring that meets the predetermined condition in each matrix included in the B matrix group. The total number. If the total number of eligible rings in each matrix included in the A matrix group is less than the total number of rings in the respective matrix included in the B matrix group that meet the predetermined condition, then the ring length characteristic of the A matrix group can be considered to be superior.
  • the loop length characteristics of the B matrix group is the total number of rings in the respective matrix included in the A matrix group that meet the predetermined condition
  • the ring length characteristic of the A matrix group is considered to be better than the ring length of the B matrix group. characteristic.
  • the preset condition can be:
  • the number of the 4 ring to the L ring in the 4 ring to the L ring and the B matrix group is smaller than the first preset value.
  • the number of 4-ring to L-rings in the 4-ring to L-ring and B-group in the A matrix group are also the same, and the ACE in the A matrix group If the L+2 ring smaller than the B preset value is less than the L+2 ring in the second matrix group where the ACE is smaller than the second preset value, then the ring length characteristic of the A matrix may be considered to be superior to the ring length characteristic of the B matrix.
  • the approximate external information degree ACE in the A matrix group is smaller than the second predetermined value of the 4-ring to L+2 ring.
  • the number of 4 ring to L+2 rings in which the ACE is smaller than the second preset value in the B matrix group is also the same, and the L+2 ring in the A matrix group is less than the L+2 ring in the B matrix group, then It is considered that the loop length characteristic of the matrix is superior to the loop length characteristic of the matrix.
  • the number of 4 rings to L rings in which the ACE is smaller than the first preset value in the A matrix group and the ACE is smaller than the first preset value in the B matrix group may mean: for not less than 4 and not more than L Any even number X, which satisfies the ACE in the A matrix, is smaller than the Y and X rings, and the ACE of the B matrix is less than the number of Y and X rings, where Y is a positive integer.
  • the value of Y is determined by the value of X. In general, the value of Y is half of the value of X.
  • the number of the 4th ring to the L ring in the B matrix group in the A matrix group is the same, respectively. It can mean that for any even number X of not less than 4 and not more than L, the X ring in the A matrix is satisfied, and The number of X rings in the B matrix group is the same.
  • the predetermined condition is that the number of 4 rings with ACE less than 2 is less, then if the total number of 4 rings of ACE ⁇ 2 in the A matrix group is less than the total number of 4 rings of ACE ⁇ 2 in the B matrix group, It is said that the loop length characteristic of the A matrix is superior to the loop length characteristic of the B matrix.
  • the predetermined condition is that the number of 4 rings is small, if the total number of 4 rings in the A matrix group is less than the total number of 4 rings in the B matrix group, it can be said that the ring length characteristic of the A matrix is excellent.
  • the ring length characteristic of the B matrix is that the number of 4 rings with ACE less than 2 is less, then if the total number of 4 rings of ACE ⁇ 2 in the A matrix group is less than the total number of 4 rings of ACE ⁇ 2 in the B matrix group, It is said that the loop length characteristic of the A matrix is superior to the loop length characteristic of the B matrix.
  • the predetermined condition is that the number of 4 rings is small, if the total
  • the value of L may be very large in actual use, when the value of L is large, the comparison process of the loop length characteristics of the A matrix group and the B matrix group is complicated, so a limit value can be set in actual use.
  • L is equal to the limit value, the number of 4-ring to L-rings in the 4-ring to L-ring and B-matrix groups in the A matrix group are respectively the same, and the approximate external information degree ACE in the A matrix group is less than the second preset value 4
  • the number of 4-ring to L-rings in the ring-to-L-ring and B-matrix groups is smaller than the second preset value, so that the ring length of the A matrix group is not particularly better than the ring length of the B matrix group, and B
  • the loop length characteristics of the matrix group are also not specific due to the loop length of the A matrix group.
  • the generating device may be a wireless communication device, a server in a wireless communication system, or other device dedicated to generating a base matrix, and the low density parity check matrix generated by the generating device is used to perform data. transmission.
  • FIG. 1 is a schematic flowchart of an embodiment of a method for generating a low density parity check code base matrix according to the present application. The method comprises the following steps:
  • Step 101 Acquire a low density parity check code matrix.
  • the generating device When generating the base matrix, the generating device needs to first acquire a mother matrix.
  • the mother matrix includes m rows and n columns of matrix elements, and the code rate is (n-m)/n.
  • the parent matrix may be generated by the generating device or may be acquired by the generating device from other devices.
  • the generating device may construct a matrix of m rows and n columns according to the density evolution theory and the PEG method as the mother matrix.
  • the code rate of the mother matrix may be (n-m)/n, and the value of each matrix element in the matrix is 0 or -1.
  • Step 102 Generate a first matrix to a qth matrix one by one, where q is a preset positive integer.
  • the mother matrix may be used as the 0th matrix, and then the first to qth matrices are generated one by one according to a preset generation manner, where q is a preset positive integer.
  • any P matrix of the first matrix to the qth matrix may be generated on the basis of the P-1 matrix, and the loop length characteristic of the P matrix is better than the loop length of the P-1 matrix. characteristic.
  • the value of q can be set in advance according to actual needs. Since the value of q is larger, the loop length characteristic of the parity matrix obtained by expanding the base matrix under each expansion factor is generally better, but the resource overhead for generating the base matrix is also larger; The smaller the value is, the smaller the resource overhead caused by generating the base matrix is. However, the loop length characteristics of each check matrix generated according to the base matrix are generally worse. Therefore, in actual use, according to the The requirement of the loop length characteristic of each check matrix and the limitation of the resource overhead are used to determine the value of q.
  • the P matrix may be generated as follows:
  • Step 201 Select a matrix element to be replaced in the P-1 matrix.
  • the generating device may first determine the matrix elements to be replaced in the P-1 matrix.
  • the matrix element to be replaced in the P-1 matrix may be represented as the P-1th matrix element to be replaced.
  • the 0th to-be-replaced matrix element represents the to-be-replaced matrix element in the 0th matrix
  • the 5th to-be-replaced matrix element represents the matrix element to be replaced in the 5th matrix.
  • the generating device may determine, by matrix search, a matrix element having a non--1 value in the P-1 matrix, and then selecting one of the matrix elements having a value other than -1 as the P-1 to be replaced matrix element. .
  • the generating device may directly use the matrix element that is searched by the matrix search and whose value is non-1 as the P-1 to be replaced matrix element.
  • Step 202 Determine a Pth shift factor corresponding to the matrix element to be replaced.
  • the generating device may determine a shift factor for the P-1th to be replaced matrix element.
  • the shift factor generated for the P-1th to be replaced matrix element may be referred to as a Pth shift factor.
  • the P-th shift factor may be such that the ring length characteristic of the P-th matrix is better than the ring length characteristic of the P-1 matrix, wherein the P-matrix is the P-1 matrix and the P-matrix A matrix formed by replacing the Pth shift factor corresponding to the matrix element.
  • Step 203 Replace the matrix element to be replaced in the P-1 matrix with the Pth shift factor to obtain a Pth matrix.
  • the matrix element to be replaced in the P-1 matrix may be replaced by the Pth shift factor to obtain a Pth matrix.
  • the base matrix is generated by using the method provided in this embodiment, and the average loop length characteristic of each check matrix obtained by expanding the base matrix obtained under each preset expansion factor is superior, thereby avoiding a preset expansion factor.
  • the check matrix formed by the expansion factor has a lower error leveling layer, which avoids the high level of error leveling of some check matrix.
  • FIG. 3 it is a schematic flowchart of an embodiment of a method for determining a P-th shift factor of the present application.
  • the Pth shift factor in the foregoing embodiment can be determined in the following manner.
  • Step 301 Acquire a Pk shift factor corresponding to the matrix element to be replaced.
  • the Pk shift factor can be obtained in multiple ways, and the generating device can generate a random number as the Pk shift factor within the preset random number generation range, or can also be preset in multiple candidate shifts. One of the factors is selected as the Pk shift factor according to a predetermined selection rule.
  • the generating device may acquire the Pk shift factor when the loop length characteristic of the Pk-1 matrix is not better than the loop length characteristic of the P-1 matrix, where The Pk-1 matrix is formed by replacing the matrix element to be replaced in the P-1 matrix with a Pk-1 shift factor.
  • Step 302 Replace the matrix element to be replaced in the P-1 matrix with the Pk shift factor, thereby generating a Pk matrix.
  • the generating device may replace the to-be-replaced matrix element in the P-1 matrix with the P k shift factor to obtain a P k matrix.
  • Step 303 if the loop length characteristic of the Pk matrix is better than the loop length characteristic of the P-1 matrix, then the Pk shift factor is used as the Pth shift factor.
  • the Pk shift factor is the Pth shift factor.
  • the Pk matrix group can be considered as The loop length characteristic is superior to the loop length characteristic of the P-1 matrix group, and the Pk shift factor can be the Pth shift factor.
  • L L
  • the number of 4 rings with ACE less than 2 is the same, and the number of 4 rings is also the same, but the 6 rings with ACE less than 3 in the P k matrix group are less than the P-th. 1
  • the ACE of the ACE is less than 3 then it can be considered that the loop length characteristic of the Pk matrix is better than the loop length characteristic of the P-1 matrix, and the Pk shift factor can be said to be Pth shift factor.
  • L L
  • the number of 4 rings with ACE less than 2 is the same, the number of 4 rings is the same, and the number of 6 rings with ACE less than 3 is the same, but 6 rings in the P k matrix group. If the number of rings in the P-1 matrix is less than 6 rings, then the ring length characteristic of the Pk matrix is better than the ring length characteristic of the P-1 matrix, and the Pk shift factor can be The Pth shift factor.
  • the Pth shift factor corresponding to the matrix element to be replaced can be determined, so that the Pth matrix can be generated.
  • the Pk shift factor is a shift factor randomly generated by the generating device within a preset random number range, or may be a shift factor arbitrarily selected by the generating device from the preset shift factor.
  • the loop length characteristics of the P k matrix are not necessarily better than the loop length characteristics of the P-1 matrix.
  • the method may further include:
  • Step 304 If the loop length characteristic of the Pk matrix is not better than the loop length characteristic of the P-1 matrix, obtain a Pk+1 shift factor corresponding to the matrix element to be replaced.
  • Step 305 Replace the matrix element to be replaced in the P-1 matrix with the Pk+1 shift factor, thereby generating a Pk+1 matrix.
  • Step 306 if the loop length characteristic of the P k+1 matrix is better than the loop length characteristic of the P-1 matrix, the P k+1 shift factor is used as the Pth shift factor.
  • the P k+1 shift factor can be used as the Pth shift factor.
  • the value of k may be large, but the loop length characteristic of the P k+1 matrix is still not superior to the loop length characteristic of the P-1 matrix, resulting in a long P matrix. Unable to generate. To avoid this, a maximum value b can be set in advance for k+1, where the value of b can be a positive integer greater than one. If the generating device has generated a total of b shifting factors from P 1 to P b , but the loop length characteristics of the P 1 matrix group to the P b matrix are not superior to the loop length characteristics of the P-1 matrix, then The P-1 matrix may be directly used as the Pth matrix.
  • FIG. 4 is a schematic structural diagram of an embodiment of a low density parity check code base matrix generating apparatus according to the present application.
  • the apparatus may include: an obtaining unit 401 and a generating unit 402.
  • the obtaining unit 401 is configured to obtain a low density parity check code matrix.
  • the generating unit 402 is configured to generate the first matrix to the qth matrix one by one, where q is a preset positive integer; for any of the first matrix to the qth matrix, the generating unit 402 may adopt Generated as follows:
  • the replacement matrix element is a matrix element whose value in the P-1 matrix is not -1; determining that the matrix element to be replaced corresponds to the matrix element to be replaced a Pth shift factor; replacing the matrix element to be replaced in the P-1 matrix with the Pth shift factor to obtain a Pth matrix.
  • the generating unit 402 may include: an obtaining subunit 4021, a replacing subunit 4022, and a determining subunit 4023.
  • the obtaining sub-unit 4021 is configured to acquire a Pk shift factor corresponding to the matrix element to be replaced.
  • the replacement subunit 4022 is configured to replace the to-be-replaced matrix element in the P-1 matrix with the Pk shift factor, thereby generating a Pk matrix.
  • the determining subunit 4023 is configured to use the Pk shift factor as the Pth shift factor if a loop length characteristic of the Pk matrix is better than a loop length characteristic of the P-1 matrix .
  • the obtaining sub-unit 4021 is further configured to: if the ring length characteristic of the P k matrix is not better than the ring length characteristic of the P-1 matrix, obtain the first corresponding to the matrix element to be replaced P k+1 shift factor.
  • the replacement subunit 4022 is further configured to replace the to-be-replaced matrix element in the P-1 matrix with the Pk+ 1th shift factor, thereby generating a Pk+1 matrix.
  • the determining subunit 4023 is further configured to: if the ring length characteristic of the P k+1 matrix is better than a ring length characteristic of the P-1 matrix, use the P k+ 1th shift factor as the Pth shift factor.
  • FIG. 6 a schematic structural diagram of an embodiment of a generating device of the present application is shown.
  • the generating device may include at least one processor 601 and at least one memory 602.
  • at least one communication interface 603 may be included.
  • 601 and the storage and the communication interface 603 can be connected by one or more buses 604.
  • the bus 604 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. According to the usage, the bus 604 can be divided into an address bus, a data bus, a control bus, and the like.
  • PCI peripheral component interconnect
  • EISA extended industry standard architecture
  • the processor 601 may be a central processing unit (CPU), a network processor (NP), or a combination of a CPU and an NP.
  • the processor may further include a hardware chip.
  • the hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof.
  • the PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), and a general array logic (GAL). Or any combination thereof.
  • the memory 602 may include a volatile memory, such as a random access memory (RAM), and may also include a non-volatile memory, such as a flash memory ( A flash memory, a hard disk drive (HDD) or a solid-state drive (SSD); the memory may also include a combination of the above types of memories.
  • RAM random access memory
  • non-volatile memory such as a flash memory ( A flash memory, a hard disk drive (HDD) or a solid-state drive (SSD); the memory may also include a combination of the above types of memories.
  • the communication interface 603 is used to communicate with other devices.
  • the communication interface may be a wired communication access port, a wireless communication interface or a combination thereof, wherein the wired communication interface may be, for example, an Ethernet interface.
  • the Ethernet interface can be an optical interface, an electrical interface, or a combination thereof.
  • the wireless communication interface may be a wireless local area networks (WLAN) interface, a cellular network communication interface, or a combination thereof.
  • WLAN wireless local area networks
  • the processor 601 is configured to obtain a low density parity check code matrix matrix; generate a first matrix to a qth matrix one by one, q is a preset positive integer; for the first matrix to the qth matrix Any of the Pth matrices, the processor 601 may be generated by: selecting a matrix element to be replaced in the P-1 matrix, Determining that the replacement matrix element is a matrix element whose value in the first P-1 matrix is not -1; determining a Pth shift factor corresponding to the matrix element to be replaced; and the P-1 The matrix element to be replaced in the matrix is replaced by the Pth shift factor to obtain a Pth matrix.
  • the processor 601 may acquire the mother matrix from other devices through the communication interface, or the processor 601 may obtain the mother matrix from the memory, or The processor 601 may also generate the mother matrix according to a predetermined generation rule.
  • the processor 601 is further configured to acquire a Pk shift factor corresponding to the matrix element to be replaced, and replace the matrix element to be replaced in the P-1 matrix with The Pk shift factor, thereby generating a Pk matrix; if the loop length characteristic of the Pk matrix is better than the loop length characteristic of the P-1 matrix, then the Pk shift factor is taken as The Pth shift factor.
  • the processor 601 is further configured to: if the ring length characteristic of the P k matrix is not better than the ring length characteristic of the P-1 matrix, obtain a corresponding to the matrix element to be replaced a P k+1 shift factor; replacing the matrix element to be replaced in the P-1 matrix with the P k+ 1th shift factor, thereby generating a P k+1 matrix; if the Pk The loop length characteristic of the +1 matrix is better than the loop length characteristic of the first P-1 matrix, and then the Pk+1 shift factor is used as the Pth shift factor.
  • the generating device may communicate with other devices by using the base matrix, or may send the base matrix to other devices for other devices to use the base matrix for data transmission.
  • the present application further provides a computer storage medium, wherein the computer storage medium may store a program, and the program may include some or all of the steps of the low density parity check code base matrix generation method of the present application.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (English: read-only memory, abbreviated as: ROM) or a random access memory (English: random access memory, abbreviation: RAM).
  • the technology in the embodiments of the present application can be implemented by means of software plus a necessary general hardware platform.
  • the technical solution in the embodiments of the present application may be embodied in the form of a software product in essence or in the form of a software product, and the computer software product may be stored in a storage medium such as a ROM/RAM. , a diskette, an optical disk, etc., including instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform the methods described in various embodiments of the present application or portions of the embodiments.
  • a computer device which may be a personal computer, server, or network device, etc.

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Abstract

一种低密度奇偶校验码基矩阵生成方法及装置。所述方法包括：获取低密度奇偶校验码母矩阵（101）；逐一生成第1矩阵至第q矩阵，q为预设正整数（102）。对于第1矩阵至第q矩阵中的任一第P矩阵采用如下方式生成：选取第P-1矩阵中的一个待替换矩阵元素，所述待替换矩阵元素为第P-1矩阵中任意一个取值不为-1的矩阵元素；确定与待替换矩阵元素相对应的第P移位因子；将第P-1矩阵中待替换矩阵元素替换为第P移位因子，得到环长特性优于第P-1矩阵的环长特性的第P矩阵。采用该方法生成基矩阵，由于最终生成的基矩阵在各个预设展开因子下展开所得的各个校验矩阵的平均环长特性较优，因此可以避免某些校验矩阵的错误平层较高的情况出现。

Description

低密度奇偶校验码基矩阵生成方法及装置 技术领域
本申请涉及无线通信领域，尤其涉及低密度奇偶校验码基矩阵生成方法及装置。
背景技术
准循环低密度奇偶校验码(quasi cycle low density parity check code，简称QC-LDPC)是一类具有稀疏校验矩阵的线性分组编码。由于QC-LDPC不仅具有逼近香农极限的良好性能，而且具有结构灵活译码复杂度较低的特点，因此可以被广泛应用于各种通信系统中。
在使用QC-LDPC进行数据传输时，首先需要为无线通信设备构造一个QC-LDPC校验矩阵。由于在无线通信系统中，根据传输需求的不同可能会为无线通信设备分配不同大小的无线资源块(resource block，简称RB)，而在不同大小的RB下，无线通信设备所能支持的QC-LDPC的码长也各不相同。为使无线通信设备能够兼容不同码长的QC-LDPC，可以预先生成一个由m行n列矩阵元素所构成的基矩阵，其中，m＝n-k，k为QC-LDPC中信息序列的长度，m，n，k的取值均为正整数，并预先设置于各个QC-LDPC的码长相对应的扩展因子。在QC-LDPC的码长确定之后，数据传输设备首先获取与所述码长对应的扩展因子，然后使用所述扩展因子所述基矩阵进行展开，从而得到与所述码长对应的校验矩阵。采用该方式，可以在QC-LDPC的码长不同时，在基矩阵的基础上得到不同的校验矩阵，从而使得无线通信设备能够支持不同码长的QC-LDPC。
但是当使用多个不同的扩展因子对同一个基矩阵进行展开时，通常很难保证所形成的每一个校验矩阵都具有良好的环长特性。当某些校验矩阵的环长特性较差时，会导致这些校验矩阵的错误平层较高，从而会影响采用相应码长的QC-LDPC进行数据传输的可靠性。
发明内容
本申请提供了低密度奇偶校验码基矩阵生成方法及装置，以减少基矩阵在部分扩展因子下错误平层较高的问题。
第一方面，本申请提供了低密度奇偶校验码基矩阵生成方法，该方法包括：获取低密度奇偶校验码母矩阵；逐一生成第1矩阵至第q矩阵，q为预设正整数；对于所述第1矩阵至第q矩阵中的任一第P矩阵采用如下方式生成：选取第P-1矩阵中的一个待替换矩阵元素，述待替换矩阵元素为所述第P-1矩阵中任意一个取值不为-1的矩阵元素；确定与所述待替换矩阵元素相对应的第P移位因子；将所述第P-1矩阵中待替换矩阵元素替换为所述第P移位因子，得到第P矩阵；其中，第P矩阵的环长特性优于所述第P-1矩阵的环长特性；所述第P矩阵的环长特性由第P矩阵组所包含的各个矩阵的环长特性决定，所述第P矩阵组包含所述第P矩阵在各个预设扩展因子下分别展开所形成的矩阵；所述第P-1矩阵的环长特性由第P-1矩阵组所包含的各个矩阵的环长特性决定，所述第P-1矩阵组包含所述第P-1矩阵在各个预设扩展因子下分别展开所形成的矩阵。
采用本方面所提供的方法生成基矩阵，由于基矩阵的移位因子设置考虑了所有扩展因子下所形成展开矩阵的环长特性，因而可以使得基矩阵在各个预设展开因子下展开所得的各个校验矩阵的平均环长特性较优，从而保证在每一个预设展开因子下所得的校验矩阵均具有较好的环长特性，因此可以使根据该基矩阵在所有预设扩展因子下展开所形成的校验矩阵都有较低的错误平层，避免了某些校验矩阵的错误平层较高的情况出现。
结合第一方面，在第一方面第一种可能实现方式中，第P矩阵的环长特性优于所述第P-1矩阵的环长特性包括：第P矩阵组中近似外部信息度ACE小于第一预设值的4环至L环与第P-1矩阵组中ACE小于第一预设值的4环至L环数量分别相同，第P矩阵组中4环至L环与第P-1矩阵组中4环至L环的数量也分别相同，且第P矩阵组中ACE小于第二预设值的L+2环少于第P-1矩阵组中ACE小于第二预设值的L+2环；其中，L为小于预设值的偶数。
结合第一方面，在第一方面第二种可能实现方式中，第P矩阵的环长特性优于所述第P-1矩阵的环长特性包括：第P矩阵组中4环至L环与第P-1矩阵组中4环至L环的数量分别相同，第P矩阵组中近似外部信息度ACE小于第二预设值的4环至L+2环与第P-1矩阵组中ACE小于第二预设值的4环至L+2环数量也分别相同，且第P矩阵组中的L+2环少于第P-1矩阵组中的L+2环；其中，L为小于预设值的偶数。
结合第一方面或第一方面第一至二种实现方式其中任意一种，在第一方面第三种可能的实现方式中，确定与第P-1矩阵中的待替换矩阵元素相对应的第P移位因子包括：获取与所述待替换矩阵元素相对应的第Pk移位因子；将所述第P-1矩阵中的所 述待替换矩阵元素替换为所述第Pk移位因子，从而生成第Pk矩阵；如果第Pk矩阵的环长特性优于所述第P-1矩阵的环长特性，那么将所述第Pk移位因子作为所述第P移位因子。
结合第一方面第三种实现方式，在第一方面第四种可能的实现方式中，还包括：如果第Pk矩阵的环长特性不优于所述第P-1矩阵的环长特性，获取与所述待替换矩阵元素相对应的第Pk+1移位因子；将所述第P-1矩阵中的所述待替换矩阵元素替换为所述第Pk+1移位因子，从而生成第Pk+1矩阵；如果第Pk+1矩阵的环长特性优于所述第P-1矩阵的环长特性，那么将所述第Pk+1移位因子作为所述第P移位因子。
第二方面，本申请还提供了一种低密度奇偶校验码基矩阵生成装置，所述装置可以包括用于执行前述第一方面及第一方面各种实现方式中方法步骤的单元。
第三方面，本申请还提供了一种生成设备，所述生成设备可以由处理器，存储器及通信接口的组件组成，所述处理器可以用于执行前述第一方面及第一方面各种实现方式中的全部或部分方法步骤。
采用本实现方式，因此可以使根据该基矩阵在所有预设扩展因子下展开所形成的校验矩阵都有较低的错误平层，避免了某些校验矩阵的错误平层较高的情况出现。
采用本申请所提供的方法生成基矩阵，由于最终生成的基矩阵在各个预设展开因子下展开所得的各个校验矩阵的平均环长特性较优，从而可以避免在某个预设展开因子下所得的校验矩阵环长特性较差的问题，保证在每一个预设展开因子下所得的校验矩阵均具有较好的环长特性，因此可以避免某些校验矩阵的错误平层较高的情况出现。
附图说明
为了更清楚地说明本申请的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，对于本领域普通技术人员而言，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本申请低密度奇偶校验码基矩阵生成方法一个实施例的流程示意图；
图2为本申请第P矩阵生成方法一个实施例的流程示意图；
图3为本申请第P移位因子确定方法一个实施例的流程示意图；
图4为本申请低密度奇偶校验码基矩阵生成装置一个实施例的结构示意图；
图5为本申请低密度奇偶校验码基矩阵生成装置生成单元一个实施例的结构示意图；
图6为本申请生成设备一个实施例的结构示意图。
具体实施方式
在本申请各个实施例中，矩阵中的环是指将矩阵作为低密度奇偶校验码的校验矩阵时，矩阵所对应Tanner图中的环。其中，L环是指由L个节点所构成的环，从Tanner图的特征可知L偶数，且L最小的取值为4，最大取值则由矩阵的行数与列数及矩阵的复杂度决定。在此需要说明的是，由于Tanner图中不存在顶点为2的环，因此可以认为2环的数量为0。
在本申请各个实施例中，矩阵组是指将一个矩阵作为基矩阵分别在各个预设的扩展因子下展开所形成的一组矩阵。矩阵组所包含的矩阵数量与预设扩展因子的数量相同，并且矩阵组中每一个矩阵与一个扩展因子唯一对应。
在本申请各个实施例中，矩阵组的环长特性可以是指该矩阵组所包含全部矩阵中，符合预定条件的环的总数量，环长特性较优是指符合预定条件的环的总数量较少。矩阵组的环长特性也即为矩阵组所对应矩阵的环长特性。
例如，A矩阵在各个预设展开因子下展开所形成的一组矩阵即为A矩阵组，B矩阵在各个预设展开因子下展开所形成的一组矩阵即为B矩阵组。A矩阵组的环长特性即为A矩阵组所包含的各个矩阵中符合预定条件的环的总数量，B矩阵组的环长特性即为B矩阵组所包含的各个矩阵中符合预定条件的环的总数量。如果A矩阵组所包含的各个矩阵中符合条件的环的总数量少于B矩阵组所包含的各个矩阵中符合预定条件的环的总数量，那么就可以认为A矩阵组的环长特性优于B矩阵组的环长特性。
如果A矩阵组所包含的各个矩阵中4环的总数量少于B矩阵组所包含的各个矩阵中4环的总数量，那么可以认为A矩阵组的环长特性优于B矩阵组的环长特性。但是在实际使用中，很可能会出现如果A矩阵组所包含的各个矩阵中4环的总数量与B矩阵组所包含的各个矩阵中4环的总数量相同的情况。因此所述预设条件可以为：
如果A矩阵组中近似外部信息度(approximate circle EMD,简称ACE)小于第一预设值的4环至L环与B矩阵组中ACE小于第一预设值的4环至L环数量分别相同，A矩阵组中4环至L环与B阵组中4环至L环的数量也分别相同，且A矩阵组中ACE 小于B预设值的L+2环少于第二矩阵组中ACE小于第二预设值的L+2环，那么可以认为A矩阵的环长特性优于所述B矩阵的环长特性。
或者，如果A矩阵组中4环至L环与B矩阵组中4环至L环的数量分别相同，A矩阵组中近似外部信息度ACE小于第二预设值的4环至L+2环与B矩阵组中ACE小于第二预设值的4环至L+2环数量也分别相同，且A矩阵组中的L+2环少于B矩阵组中的L+2环，那么也可以认为甲矩阵的环长特性优于所述乙矩阵的环长特性。
A矩阵组中ACE小于第一预设值的4环至L环与B矩阵组中ACE小于第一预设值的4环至L环数量分别相同可以是指：对于不小于4且不大于L的任意偶数X，都满足A矩阵中ACE小于Y与X环，与B矩阵组种ACE小于Y与X环数量相同，其中，Y为正整数。Y的取值由X的取值决定，通常情况下Y的取值为X的取值的一半。A矩阵组中4环至L环与B矩阵组中4环至L环的数量分别相同可以是指：对于不小于4且不大于L的任意偶数X，都满足A矩阵中的X环，与B矩阵组中的X环数量相同。
例如，如果所述预定条件为ACE小于2的4环较少，那么若A矩阵组中ACE＜2的4环的总数量少于B矩阵组中ACE＜2的4环的总数量，就可以说所述A矩阵的环长特性优于所述B矩阵的环长特性。又如，如果所述预定条件为4环数量较少，那么若A矩阵组中4环的总数量少于B矩阵组中4环的总数量，就可以说所述A矩阵的环长特性优于所述B矩阵的环长特性。
由于在实际使用中L的取值可能会非常大，当L的取值很大时，会造成A矩阵组与B矩阵组环长特性的比较过程复杂，因此在实际使用中可以设置一个限度值，当L等于该限度值时，A矩阵组中4环至L环与B矩阵组中4环至L环的数量分别相同，A矩阵组中近似外部信息度ACE小于第二预设值的4环至L环与B矩阵组中ACE小于第二预设值的4环至L环数量也分别相同，那么就可以认为A矩阵组环长特定不优于B矩阵组的环长特定，并且B矩阵组的环长特性也不由于A矩阵组的环长特定。
在本申请各个实施例中，所述生成设备可以是无线通信设备、无线通信系统中的服务器或其他专门用于生成基矩阵的设备，生成设备所生成的低密度奇偶校验矩阵用于进行数据传输。
参见图1，为本申请低密度奇偶校验码基矩阵生成方法一个实施例的流程示意图。该方法包括如下步骤：
步骤101，获取低密度奇偶校验码母矩阵。
生成设备在生成基矩阵时，需要首先获取一个母矩阵，通常情况下所述母矩阵包含m行n列矩阵元素，且码率为(n-m)/n。所述母矩阵可以由所述生成设备生成，也可以由所述生成设备从其他设备获取。
例如，生成设备可以根据密度进化理论和PEG方法所构造一个m行n列的矩阵作为所述母矩阵。所述母矩阵的码率可以为(n-m)/n，且所述矩阵中各个矩阵元素的取值为0或-1。
步骤102，逐一生成第1矩阵至第q矩阵，q为预设正整数。
在获取到母矩阵之后，可以将所述母矩阵作为第0矩阵，然后按照预设生成方式逐一生成第1至第q矩阵，其中，q为预设正整数。其中，对于所述第1矩阵至第q矩阵中的任一第P矩阵都可以在第P-1矩阵的基础上生成，并且第P矩阵的环长特性优于第P-1矩阵的环长特性。
q的取值可以根据实际需要预先设置。由于q的取值越大，最终生成的基矩阵在各个展开因子下展开所得的校验矩阵的环长特性通常也会越好，但是生成所述基矩阵的资源开销也会越大；q的取值越小时，生成所述基矩阵所带来的资源开销也越小，但是根据基矩阵所生成的各个校验矩阵的环长特性通常也会越差，因此在实际使用中，可以根据所述各个校验矩阵环长特性的需求与所述资源开销的限制来确定q的取值。
参见图2，为本申请第P矩阵生成方法一个实施例的流程示意图，对于所述第1矩阵至第q矩阵中的任一第P矩阵可以采用如下方式生成：
步骤201，选取第P-1矩阵中的一个待替换矩阵元素。
在第P-1矩阵生成后，生成设备可以首先确定所述第P-1矩阵中待替换矩阵元素。其中，第P-1矩阵中的所述待替换矩阵元素可以表示为第P-1待替换矩阵元素。例如，第0待替换矩阵元素表示第0矩阵中的所述待替换矩阵元素，第5待替换矩阵元素表示第5矩阵中的待替换矩阵元素。
第P-1待替换矩阵元素的确定方式有多种。例如，生成设备可以通过矩阵搜索确定第P-1矩阵中取值为非-1的矩阵元素，然后从取值为非-1的矩阵元素中选择一个作为所述第P-1待替换矩阵元素。或者，生成设备也可以直接将通过矩阵搜索搜索到的第一个取值为非-1的矩阵元素作为所述第P-1待替换矩阵元素。
步骤202，确定与所述待替换矩阵元素相对应的第P移位因子。
在第P-1待替换矩阵元素确定后，生成设备可以为所述第P-1待替换矩阵元素确定一个移位因子。为所述第P-1待替换矩阵元素生成的移位因子可以被称作第P移位因子。并且该第P移位因子可以使得第P矩阵的环长特性优于所述第P-1矩阵的环长特性，其中，所述P矩阵为将所述第P-1矩阵中与所述待替换矩阵元素相对应的第P移位因子所形成的矩阵。第P移位因子的确定方法可以参见图3所对应实施例。
步骤203，将所述第P-1矩阵中待替换矩阵元素替换为所述第P移位因子，得到第P矩阵。
在所述第P移位因子确定后，可以将所述第P-1矩阵中待替换矩阵元素替换为所述第P移位因子，得到第P矩阵。
采用本实施例所提供的方法生成基矩阵，由于最终生成的基矩阵在各个预设展开因子下展开所得的各个校验矩阵的平均环长特性较优，从而可以避免在某个预设展开因子下所得的校验矩阵环长特性较差的问题，从而可以保证在每一个预设展开因子下所得的校验矩阵均具有较好的环长特性，因此可以使根据该基矩阵在所有预设扩展因子下展开所形成的校验矩阵都有较低的错误平层，避免了某些校验矩阵的错误平层较高的情况出现。
参见图3，为本申请第P移位因子确定方法一个实施例的流程示意图。前述实施例中的第P移位因子可以采用如下方式确定。
步骤301，获取与所述待替换矩阵元素相对应的第Pk移位因子。
第Pk移位因子的获取方式有多种，生成设备可以在预设的随机数生成范围之内生成一个随机数作为第Pk移位因子，或者也可以在预设的多个候选移位因子中按照预定选取规则选取一个作为第Pk移位因子。
在此需要说明的是，所述生成设备可以在所述第Pk-1矩阵环长特性不优于第P-1矩阵的环长特性时，再获取所述第Pk移位因子，其中，所述第Pk-1矩阵为将所述第P-1矩阵中的所述待替换矩阵元素替换为第Pk-1移位因子所形成。
步骤302，将所述第P-1矩阵中的所述待替换矩阵元素替换为所述第Pk移位因子，从而生成第Pk矩阵。
在第Pk移位因子生成后，生成设备可以将所述第P-1矩阵中的所述待替换矩阵元素替换为所述第Pk移位因子得到第Pk矩阵。
步骤303，如果第Pk矩阵的环长特性优于所述第P-1矩阵的环长特性，那么将所 述第Pk移位因子作为所述第P移位因子。
在第Pk矩阵生成后，可以比较第Pk矩阵组的环长特性是否优于第P-1矩阵组的环长特性，如果第Pk矩阵组的环长特性优于第P-1矩阵组的环长特性，所述第Pk移位因子即为所述第P移位因子。
以L的取值为6为例，如果第Pk矩阵组中ACE小于2的4环数量小于第P-1矩阵组中ACE小于2的4环的数量，那么可以认为第Pk矩阵组的环长特性优于第P-1矩阵组的环长特性，进而可以将所述第Pk移位因子即为所述第P移位因子。
仍以L的取值为6为例。如果第Pk矩阵组与第P-1矩阵组相比较，ACE小于2的4环数量相同，并且4环数量也相同，但是第Pk矩阵组中ACE小于3的6环少于第P-1矩阵组中ACE小于3的6环，那么也可以认为第Pk矩阵的环长特性优于第P-1矩阵的环长特性，进而可以将所述第Pk移位因子即为所述第P移位因子。
仍以L的取值为6为例。如果第Pk矩阵组与第P-1矩阵组相比较，ACE小于2的4环数量相同，4环数量也相同，并且ACE小于3的6环数量相同，但是第Pk矩阵组中6环少于第P-1矩阵组中的6环，那么也可以认为第Pk矩阵的环长特性优于第P-1矩阵的环长特性，进而可以将所述第Pk移位因子即为所述第P移位因子。
采用本实施例，可以确定与待替换矩阵元素相对应的第P移位因子，从而可以生成第P矩阵。
由于第Pk移位因子是生成设备在预设的随机数范围内随机生成的一个移位因子，或者也可以是生成设备从预设移位因子中任意选取的一个一个移位因子，因此第Pk矩阵的环长特性并不一定会优于第P-1矩阵的环长特性。
因此如果第Pk矩阵的环长特性不优于第P-1矩阵的环长特性，那么在步骤303之后还可以包括：
步骤304，如果第Pk矩阵的环长特性不优于所述第P-1矩阵的环长特性，获取与所述待替换矩阵元素相对应的第Pk+1移位因子。
步骤305，将所述第P-1矩阵中的所述待替换矩阵元素替换为所述第Pk+1移位因子，从而生成第Pk+1矩阵。
步骤306，如果第Pk+1矩阵的环长特性优于所述第P-1矩阵的环长特性，那么将所述第Pk+1移位因子作为所述第P移位因子。
其中，第Pk+1移位因子的获取方式与第Pk移位因子
当第Pk+1矩阵的环长特性优于第P-1矩阵的环长特性，可以将所述第Pk+1移位因子作为第P移位因子。
由于在实际使用中，可能会出现k的取值已经很大，但是第Pk+1矩阵的环长特性仍然不优于第P-1矩阵的环长特性的情况，导致第P矩阵长时间无法生成。为避免此情况的出现，可以预先为k+1设置一个最大值b，其中，b的取值可以为大于1的正整数。如果生成设备已经生成了第P1至第Pb共b个移位因子，但是第P1矩阵组至第Pb矩阵的环长特性均不优于第P-1矩阵的环长特性，那么可以直接将所述第P-1矩阵作为所述第P矩阵。
参见图4为本申请低密度奇偶校验码基矩阵生成装置一个实施例的结构示意图。
参见图4，所述装置可以包括：获取单元401与生成单元402。
其中，所述获取单元401，用于获取低密度奇偶校验码母矩阵。
所述生成单元402，用于逐一生成第1矩阵至第q矩阵，q为预设正整数；对于所述第1矩阵至第q矩阵中的任一第P矩阵，所述生成单元402可以采用如下方式生成：
选取第P-1矩阵中的一个待替换矩阵元素，述待替换矩阵元素为所述第P-1矩阵中任意一个取值不为-1的矩阵元素；确定与所述待替换矩阵元素相对应的第P移位因子；将所述第P-1矩阵中待替换矩阵元素替换为所述第P移位因子，得到第P矩阵。
可选的，如图5所示，所述生成单元402可以包括：获取子单元4021，替换子单元4022及确定子单元4023。
其中，所述获取子单元4021，用于获取与所述待替换矩阵元素相对应的第Pk移位因子。所述替换子单元4022，用于将所述第P-1矩阵中的所述待替换矩阵元素替换为所述第Pk移位因子，从而生成第Pk矩阵。所述确定子单元4023，用于如果第Pk矩阵的环长特性优于所述第P-1矩阵的环长特性，那么将所述第Pk移位因子作为所述第P移位因子。
可选的，所述获取子单元4021，还用于如果第Pk矩阵的环长特性不优于所述第P-1矩阵的环长特性，获取与所述待替换矩阵元素相对应的第Pk+1移位因子。所述替换子单元4022，还用于将所述第P-1矩阵中的所述待替换矩阵元素替换为所述第Pk+1移位因子，从而生成第Pk+1矩阵。所述确定子单元4023，还用于如果第Pk+1矩阵的环长特性优于所述第P-1矩阵的环长特性，那么将所述第Pk+1移位因子作为所述第P移 位因子。
参见图6，为本申请生成设备一个实施例的结构示意图。
如图6所示，所述生成设备可以包含至少一个处理器601与至少一个存储器602，除所述处理器601及所述存储器602之外，还可以包含至少一个通信接口603，所述处理器601与所述存储及所述通信接口603之间可以通过一条或多条总线604连接。
其中，总线604可以是外设部件互连标准(peripheral component interconnect，简称：PCI)总线或扩展工业标准结构(extended industry standard architecture，简称：EISA)总线等。按照用途划分，所述总线604可以分为地址总线、数据总线、控制总线等。
所述处理器601可以是中央处理器(central processing unit，简称：CPU)，网络处理器(network processor，简称：NP)或者CPU和NP的组合。处理器还可以进一步包括硬件芯片。上述硬件芯片可以是专用集成电路(application-specific integrated circuit，简称：ASIC)，可编程逻辑器件(programmable logic device，简称：PLD)或其组合。上述PLD可以是复杂可编程逻辑器件(complex programmable logic device，简称：CPLD)，现场可编程逻辑门阵列(field-programmable gate array，简称：FPGA)，通用阵列逻辑(generic array logic,简称：GAL)或其任意组合。
所述存储器602可以包括易失性存储器(volatile memory)，例如随机存取内存(random access memory，简称：RAM)；还可以包括非易失性存储器(non-volatile memory)，例如快闪存储器(flash memory)，硬盘(hard disk drive，简称：HDD)或固态硬盘(solid-state drive，简称：SSD)；存储器还可以包括上述种类的存储器的组合。
所述通信接口603用于与其他设备进行通信。所述通信接口可以为有线通信接入口，无线通信接口或其组合，其中，有线通信接口例如可以为以太网接口。以太网接口可以是光接口，电接口或其组合。无线通信接口可以为无线局域网(wireless local area networks，简称：WLAN)接口，蜂窝网络通信接口或其组合等。
在本申请中，所述处理器601用于获取低密度奇偶校验码母矩阵；逐一生成第1矩阵至第q矩阵，q为预设正整数；对于所述第1矩阵至第q矩阵中的任一第P矩阵，所述处理器601可以采用如下方式生成：选取第P-1矩阵中的一个待替换矩阵元素， 述待替换矩阵元素为所述第P-1矩阵中任意一个取值不为-1的矩阵元素；确定与所述待替换矩阵元素相对应的第P移位因子；将所述第P-1矩阵中待替换矩阵元素替换为所述第P移位因子，得到第P矩阵。
其中，在获取所述母矩阵时，所述处理器601可以通过所述通信接口从其他设备获取所述母矩阵，或者所述处理器601也可以从所述存储器中获取所述母矩阵，或者所述处理器601也可以根据预定的生成规则，生成所述母矩阵。
可选的，所述处理器601，还可以用于获取与所述待替换矩阵元素相对应的第Pk移位因子；将所述第P-1矩阵中的所述待替换矩阵元素替换为所述第Pk移位因子，从而生成第Pk矩阵；如果第Pk矩阵的环长特性优于所述第P-1矩阵的环长特性，那么将所述第Pk移位因子作为所述第P移位因子。
可选的，所述处理器601，还可以用于如果第Pk矩阵的环长特性不优于所述第P-1矩阵的环长特性，获取与所述待替换矩阵元素相对应的第Pk+1移位因子；将所述第P-1矩阵中的所述待替换矩阵元素替换为所述第Pk+1移位因子，从而生成第Pk+1矩阵；如果第Pk+1矩阵的环长特性优于所述第P-1矩阵的环长特性，那么将所述第Pk+1移位因子作为所述第P移位因子。
在所述基矩阵生成后，所述生成设备可以使用所苏基矩阵与其他设备进行通信，或者也可以将所述基矩阵发送给其他设备，以供其他设备使用所述基矩阵进行数据传输。
具体实现中，本申请还提供一种计算机存储介质，其中，该计算机存储介质可存储有程序，该程序执行时可包括本申请低密度奇偶校验码基矩阵生成方法部分或全部步骤。所述的存储介质可为磁碟、光盘、只读存储记忆体(英文：read-only memory，简称：ROM)或随机存储记忆体(英文：random access memory，简称：RAM)等。
本领域的技术人员可以清楚地了解到本申请实施例中的技术可借助软件加必需的通用硬件平台的方式来实现。基于这样的理解，本申请实施例中的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品可以存储在存储介质中，如ROM/RAM、磁碟、光盘等，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例或者实施例的某些部分所述的方法。
本说明书中各个实施例之间相同相似的部分互相参见即可。尤其，对于装置及设备实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例中的说明即可。
以上所述的本申请实施方式并不构成对本申请保护范围的限定。

Claims (10)

  1. 一种低密度奇偶校验码基矩阵生成方法，其特征在于，包括：
    获取低密度奇偶校验码母矩阵；
    逐一生成第1矩阵至第q矩阵，q为预设正整数；
    对于所述第1矩阵至第q矩阵中的任一第P矩阵采用如下方式生成：
    选取第P-1矩阵中的一个待替换矩阵元素，述待替换矩阵元素为所述第P-1矩阵中任意一个取值不为-1的矩阵元素；
    确定与所述待替换矩阵元素相对应的第P移位因子；
    将所述第P-1矩阵中待替换矩阵元素替换为所述第P移位因子，得到第P矩阵；
    其中，第P矩阵的环长特性优于所述第P-1矩阵的环长特性；
    所述第P矩阵的环长特性由第P矩阵组所包含的各个矩阵的环长特性决定，所述第P矩阵组包含所述第P矩阵在各个预设扩展因子下分别展开所形成的矩阵；
    所述第P-1矩阵的环长特性由第P-1矩阵组所包含的各个矩阵的环长特性决定，所述第P-1矩阵组包含所述第P-1矩阵在各个预设扩展因子下分别展开所形成的矩阵。
  2. 如权利要求1所述的方法，其特征在于，第P矩阵的环长特性优于所述第P-1矩阵的环长特性包括：
    第P矩阵组中近似外部信息度ACE小于第一预设值的4环至L环与第P-1矩阵组中ACE小于第一预设值的4环至L环数量分别相同，第P矩阵组中4环至L环与第P-1矩阵组中4环至L环的数量也分别相同，且第P矩阵组中ACE小于第二预设值的L+2环少于第P-1矩阵组中ACE小于第二预设值的L+2环；其中，L为小于预设值的偶数。
  3. 如权利要求1所述的方法，其特征在于，第P矩阵的环长特性优于所述第P-1矩阵的环长特性包括：
    第P矩阵组中4环至L环与第P-1矩阵组中4环至L环的数量分别相同，第P矩阵组中近似外部信息度ACE小于第二预设值的4环至L+2环与第P-1矩阵组中ACE小于第二预设值的4环至L+2环数量也分别相同，且第P矩阵组中的L+2 环少于第P-1矩阵组中的L+2环；其中，L为小于预设值的偶数。
  4. 如权利要求1至3任一项所述的方法，其特征在于，确定与第P-1矩阵中的待替换矩阵元素相对应的第P移位因子包括：
    获取与所述待替换矩阵元素相对应的第Pk移位因子；
    将所述第P-1矩阵中的所述待替换矩阵元素替换为所述第Pk移位因子，从而生成第Pk矩阵；
    如果第Pk矩阵的环长特性优于所述第P-1矩阵的环长特性，那么将所述第Pk移位因子作为所述第P移位因子。
  5. 如权利要求4所述的方法，其特征在于，还包括：
    如果第Pk矩阵的环长特性不优于所述第P-1矩阵的环长特性，获取与所述待替换矩阵元素相对应的第Pk+1移位因子；
    将所述第P-1矩阵中的所述待替换矩阵元素替换为所述第Pk+1移位因子，从而生成第Pk+1矩阵；
    如果第Pk+1矩阵的环长特性优于所述第P-1矩阵的环长特性，那么将所述第Pk+1移位因子作为所述第P移位因子。
  6. 一种低密度奇偶校验码基矩阵生成装置，其特征在于，包括：
    获取单元，用于获取低密度奇偶校验码母矩阵；
    生成单元，用于逐一生成第1矩阵至第q矩阵，q为预设正整数；对于所述第1矩阵至第q矩阵中的任一第P矩阵采用如下方式生成：
    选取第P-1矩阵中的一个待替换矩阵元素，述待替换矩阵元素为所述第P-1矩阵中任意一个取值不为-1的矩阵元素；确定与所述待替换矩阵元素相对应的第P移位因子；将所述第P-1矩阵中待替换矩阵元素替换为所述第P移位因子，得到第P矩阵；
    其中，第P矩阵的环长特性优于所述第P-1矩阵的环长特性；所述第P矩阵的环长特性由第P矩阵组所包含的各个矩阵的环长特性决定，所述第P矩阵组包含所述第P矩阵在各个预设扩展因子下分别展开所形成的矩阵；所述第P-1矩阵的环长特性由第P-1矩阵组所包含的各个矩阵的环长特性决定，所述第P-1矩阵组包含所述第P-1矩阵在各个预设扩展因子下分别展开所形成的矩阵。
  7. 如权利要求6所述的装置，其特征在于，第P矩阵的环长特性优于所述第P-1矩阵的环长特性包括：
    第P矩阵组中近似外部信息度ACE小于第一预设值的4环至L环与第P-1矩阵组中ACE小于第一预设值的4环至L环数量分别相同，第P矩阵组中4环至L环与第P-1矩阵组中4环至L环的数量也分别相同，且第P矩阵组中ACE小于第二预设值的L+2环少于第P-1矩阵组中ACE小于第二预设值的L+2环；其中，L为小于预设值的偶数。
  8. 如权利要求6所述的装置，其特征在于，第P矩阵的环长特性优于所述第P-1矩阵的环长特性包括：
    第P矩阵组中4环至L环与第P-1矩阵组中4环至L环的数量分别相同，第P矩阵组中近似外部信息度ACE小于第二预设值的4环至L+2环与第P-1矩阵组中ACE小于第二预设值的4环至L+2环数量也分别相同，且第P矩阵组中的L+2环少于第P-1矩阵组中的L+2环；其中，L为小于预设值的偶数。
  9. 如权利要求5至8任一项所述的装置，其特征在于，所述生成单元包括：
    获取子单元，用于获取与所述待替换矩阵元素相对应的第Pk移位因子；
    替换子单元，用于将所述第P-1矩阵中的所述待替换矩阵元素替换为所述第Pk移位因子，从而生成第Pk矩阵；
    确定子单元，用于如果第Pk矩阵的环长特性优于所述第P-1矩阵的环长特性，那么将所述第Pk移位因子作为所述第P移位因子。
  10. 如权利要求9所述的装置，其特征在于，
    所述获取子单元，还用于如果第Pk矩阵的环长特性不优于所述第P-1矩阵的环长特性，获取与所述待替换矩阵元素相对应的第Pk+1移位因子；
    所述替换子单元，还用于将所述第P-1矩阵中的所述待替换矩阵元素替换为所述第Pk+1移位因子，从而生成第Pk+1矩阵；
    所述确定子单元，还用于如果第Pk+1矩阵的环长特性优于所述第P-1矩阵的环长特性，那么将所述第Pk+1移位因子作为所述第P移位因子。
PCT/CN2016/090646 2016-07-20 2016-07-20 低密度奇偶校验码基矩阵生成方法及装置 WO2018014249A1 (zh)

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