WO2016168991A1 - 一种低密度校验码生成方法及装置 - Google Patents

一种低密度校验码生成方法及装置 Download PDF

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Publication number
WO2016168991A1
WO2016168991A1 PCT/CN2015/077122 CN2015077122W WO2016168991A1 WO 2016168991 A1 WO2016168991 A1 WO 2016168991A1 CN 2015077122 W CN2015077122 W CN 2015077122W WO 2016168991 A1 WO2016168991 A1 WO 2016168991A1
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information bit
shortened
information
column
columns
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PCT/CN2015/077122
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English (en)
French (fr)
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陈州辉
马征
林伟
林英沛
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华为技术有限公司
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Priority to PCT/CN2015/077122 priority Critical patent/WO2016168991A1/zh
Publication of WO2016168991A1 publication Critical patent/WO2016168991A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a method and an apparatus for generating a low density check code.
  • the optional channel coding scheme of the WLAN (English: Wireless Local Area Networks) standard (IEEE 802.11n/ac) is: using LDPC (Chinese: Low Density Parity; English: Low-density parity-check)
  • LDPC Choinese: Low Density Parity; English: Low-density parity-check
  • the following illustrates the process of LDPC encoding the data bits to be encoded.
  • the code length is 648 bits and the bit rate is
  • the LDPC code check matrix H encodes the coded data bits, as shown in FIG. 1 is a 12 ⁇ 24 check matrix schematic, each element in the check matrix represents a 27 ⁇ 27 cyclic shift square matrix.
  • FIG. 2 is a schematic diagram of a 27 ⁇ 27 all-zero square matrix, a schematic diagram of a 27 ⁇ 27 unit array, and Schematic diagram.
  • the check matrix shown in Figure 1 due to the bit rate Therefore, the first 12 columns are information bit columns, and the last 12 columns are parity bit columns.
  • the data bit to be encoded is used to correspond to the information bit column of the check matrix, and the check bit is generated by using the check relationship in the matrix.
  • the information bit column corresponding to the data bits to be encoded in the check matrix is the information bit sequence that needs to be shortened. Since the order of the information bit columns corresponding to the check matrix of the data to be encoded is sequentially performed from the first column to the last column of the information bit column, the information bit string that needs to be shortened is usually back, and the short operation is performed in the backward direction. The previous order is performed, that is, the priority is shortened from the last column to the first column of the information bit column.
  • the data bits to be encoded correspond to the first column to the tenth column in the information bit column of the check matrix, and the number of bits of the data bit to be encoded is limited, and the number 11 of the information bit column is limited.
  • the 11th column and the 12th column in the information bit column become information bit columns to be shortened, and the 12th column and the 11th column in the information bit column need to be sequentially Perform a shortening operation.
  • Figures 3 and 4 are a 4 ⁇ 8 LDPC code check matrix H and its factor diagram, respectively.
  • Each column in the LDPC code check matrix H in FIG. 3 corresponds to one variable node, and each row corresponds to one check node.
  • the LDPC code check matrix shown in FIG. 3 has eight variable nodes: V 1 to V 8 , and 4 check nodes: C 1 to C 4 .
  • variable nodes there are three parameters: variable node degrees, external information, and Total ACE (Chinese: Total Approximate Cycle Extrinsic Message Degree).
  • variable node V 1 As can be seen from FIG. 4, the check nodes connected to the variable node V 1 have: C 1 and C 2 , the number is 2, or as can be seen from FIG. 3, the information corresponding to the variable node V 1 If the column weight of the bit column (that is, the number of non-zero elements in the column) is 2, it can be determined that the variable node degree of the variable node V 1 is 2.
  • the shortening scheme in the prior art does not take into account the specific structure of the LDPC code check matrix and its factor graph, that is, does not take into account the variable node degree of the variable node corresponding to the information bit column of the LDPC code check matrix, External information and Total ACE, only the information bit column is shortened from the back to the front without screening. Therefore, it is impossible to provide superior shortening performance, and performance loss is particularly serious when the number of bits to be shortened is large.
  • Embodiments of the present invention provide a method and an apparatus for generating an LDPC code, which are used to improve shortening performance and reduce performance loss of an LDPC code.
  • a first aspect of the embodiments of the present invention provides a low-density check code generating method, including:
  • the shortening priority pattern includes Shorten one or more columns of information bits arranged in order of priority from high to low
  • the shortening priority of the information bit column is increased as the Total ACE of the variable node corresponding to the information bit column is decreased, and the external information sum of the variable node corresponding to the information bit column is increased;
  • the information bit string that needs to be shortened is sequentially shortened in order of shortening the priority from high to low, and the information bit sequence of the generated low density check code is obtained.
  • the total ACE and the outer information sum of the variable node corresponding to each information bit column in the LDPC code check matrix are used to generate a shortened priority pattern ,include:
  • the information bit column is selected and stored in the shortened priority pattern until the shortening
  • the number of columns of the information bit column included in the priority pattern is not less than the number of columns corresponding to the number of information bits to be shortened by the LDPC code check matrix, wherein the information bit column has a shortened priority level and the information bit column is stored.
  • the sequence of entering the shortened priority pattern corresponds to:
  • the process ends, and the final shortened priority pattern is obtained; otherwise
  • the selecting a partial information bit column from each information bit column in the LDPC code check matrix Into the first collection including:
  • the performing the LDPC code check matrix Updates including:
  • the information bit column includes N sub-columns, and N is an integer greater than or equal to 1;
  • the determined information bit columns that need to be shortened are sequentially shortened, including:
  • the other information bit columns except the information bit column with the lowest priority are shortened in sequence for the determined information bit string that needs to be shortened;
  • M sub-columns are randomly selected from the N sub-columns included in the information bit column with the lowest priority, and M is the remainder of the number of information bits to be shortened by the LDPC code check matrix divided by N, and M is greater than An integer equal to 1.
  • a second aspect of the embodiments of the present invention provides a low-density check code generating apparatus, including:
  • a generating unit configured to generate a shortened priority pattern by using a total progressive acyclic information degree Total ACE and/or an external information sum of the variable nodes corresponding to each information bit column in the low density check LDPC code check matrix, the shortening
  • the priority pattern includes one or more columns of information bits arranged in descending order of priority from high to low.
  • the shortening priority of the information bit column is increased as the Total ACE of the variable node corresponding to the information bit column is decreased, and the external information sum of the variable node corresponding to the information bit column is increased;
  • a processing unit configured to determine, according to the number of information bits that need to be shortened according to the LDPC code check matrix, use a shortened priority pattern to determine an information bit sequence that needs to be shortened;
  • the shortening unit is configured to sequentially shorten the determined information bit sequence that needs to be shortened in order of shortening the priority from high to low, and obtain an information bit sequence of the generated low density check code.
  • the generating unit includes:
  • the information bit column is stored in the shortened priority pattern until the number of columns of the information bit column included in the shortened priority pattern is not less than the number of columns corresponding to the number of information bits to be shortened by the LDPC code check matrix And wherein the shortening priority level of the information bit column corresponds to a sequence in which the information bit column is stored in the shortened priority pattern:
  • a first selection module configured to select all information bit columns or partial information bit columns from each information bit column in the LDPC code check matrix to be stored in the first set;
  • a second selection module configured to select, from the first set, an information bit column corresponding to the variable node having the largest outer information sum, to be stored in the second set;
  • a third selection module configured to select, from the second set, an information bit column corresponding to a variable node having a minimum Total ACE, to store the shortened priority pattern
  • a processing module configured to: if the number of columns of information bit columns included in the shortened priority pattern is not less than a number of columns corresponding to the number of information bits to be shortened by the LDPC code check matrix, end processing, and obtain the final shortening Priority pattern; otherwise
  • an updating module configured to update the LDPC code check matrix, and return the execution selection information bit sequence to the first set in the updated LDPC code check matrix.
  • the first selection module is configured to:
  • the update module is configured to:
  • the information bit column includes N sub-columns, and N is an integer greater than or equal to 1;
  • the shortening unit is used to:
  • the other information bit columns except the information bit column with the lowest priority are shortened in sequence for the determined information bit string that needs to be shortened;
  • M sub-columns are randomly selected from the N sub-columns included in the information bit column with the lowest priority, and M is the remainder of the number of information bits to be shortened by the LDPC code check matrix divided by N, and M is greater than An integer equal to 1.
  • a total priority progressive out-of-loop information degree Total ACE and/or an external information sum of a variable node corresponding to each information bit column in the low-density parity check LDPC code check matrix is used to generate a shortened priority pattern, that is, According to the order of shortening the priority from high to low, one or more columns of information bit rows are arranged; then, according to the number of information bits that need to be shortened according to the LDPC code check matrix, the shortened priority pattern is used to determine the information bit column that needs to be shortened; In order of priority from high to low, the identified information bitstreams that need to be shortened are sequentially shortened to obtain information bitstreams of the generated low-density check codes.
  • the embodiment of the present invention utilizes the information.
  • the Total ACE and/or external information of the variable node corresponding to the bit string and the shortening priority of the information bit column are improved, the performance of the LDPC code is shortened, and the performance loss due to the shortening is reduced.
  • 1 is a schematic diagram of a check matrix of 12 ⁇ 24
  • Figure 2 is a schematic diagram of a 27 ⁇ 27 all-zero square matrix, a schematic diagram of a 27 ⁇ 27 unit array, and Schematic diagram
  • FIG. 3 is a schematic diagram of a 4 ⁇ 8 LDPC code check matrix H
  • 4 is a factor diagram of the 4 ⁇ 8 LDPC code check matrix H shown in FIG. 3;
  • FIG. 5 is a schematic diagram of a ring having a partial length of 6 in an LDPC code check matrix
  • FIG. 6 is a partial schematic diagram of a factor graph of a variable node with a variable node degree of 4;
  • FIG. 7 is a schematic diagram of a VN3 external information sum of a variable node
  • FIG. 8 is a flowchart of a method for generating an LDPC code according to an embodiment of the present invention.
  • FIG. 9 is a flowchart of using a Total ACE and external information and generating a shortened priority pattern according to an embodiment of the present invention.
  • FIG. 10 is a diagram showing the use of variable node degrees, Total ACE, and external information and generation reduction in an embodiment of the present invention. Flow chart of short priority pattern;
  • FIG. 11 is a BLER performance comparison diagram of the shortening scheme provided by the embodiment of the present invention and the shortening scheme in the prior art, where the code length is 648 bits and the code rate is 1/2;
  • FIG. 12 is a BLER performance comparison diagram of the shortening scheme provided by the embodiment of the present invention and the shortening scheme in the prior art, where the code length is 1296 bits and the code rate is 1/2;
  • FIG. 13 is a comparison diagram of BLER performance of the shortening scheme provided by the embodiment of the present invention and the shortening scheme of the prior art when the code length is 1944 bits and the code rate is 1/2;
  • FIG. 14 is a block diagram of an LDPC code generating apparatus according to an embodiment of the present invention.
  • FIG. 15 is a hardware structural diagram of an LDPC code generating apparatus according to an embodiment of the present invention.
  • Embodiments of the present invention provide a method and an apparatus for generating an LDPC code, which are used to improve shortening performance and reduce performance loss of an LDPC code.
  • a total priority progressive out-of-loop information degree Total ACE and/or an external information sum of a variable node corresponding to each information bit column in the low-density parity check LDPC code check matrix is used to generate a shortened priority pattern, that is, According to the order of shortening the priority from high to low, one or more columns of information bit rows are arranged; then, according to the number of information bits that need to be shortened according to the LDPC code check matrix, the shortened priority pattern is used to determine the information bit column that needs to be shortened; In order of priority from high to low, the identified information bitstreams that need to be shortened are sequentially shortened to obtain information bitstreams of the generated low-density check codes.
  • the embodiment of the present invention utilizes the information.
  • the Total ACE and/or external information of the variable node corresponding to the bit string and the shortening priority of the information bit column are improved, the performance of the LDPC code is shortened, and the performance loss due to the shortening operation is reduced.
  • the embodiment of the invention provides a method for generating an LDPC (Chinese: Low-density parity-check) code, which is suitable for supporting IEEE WLAN standards (such as IEEE 802.11n/ac/ax). WiFi device.
  • LDPC Low-density parity-check
  • the LDPC code generation method provided by the embodiment of the present invention is based on the check matrix of the LDPC code and the corresponding structure of the corresponding factor graph: the variable node degree, the outer information, and the Total ACE, which are given in the check matrix of the LDPC code.
  • the method of shortening the priority of each information bitstream generates an information bitstream of the LDPC code in accordance with the shortening priority of each information bitstream.
  • variable node degree refers to the number of check nodes connected to the variable node in the factor graph of the LDPC code, that is, the column weight of the information bit column corresponding to the variable node in the check matrix of the LDPC code (column weight of one column) The number of non-zero elements in this column).
  • FIG. 6 is a partial schematic diagram of a factor graph of a variable node with a variable node degree of 4.
  • the number of check nodes connected to the variable node is four. Since each check node is equivalent to a check equation, when the variable node degree of the variable node is larger, the more the check node receives the check information from the remaining check equations in the iterative decoding process, the The verification information refers to the confidence message transmitted by the checkpoint to the variable node during the iterative decoding process of the LDPC code, so that the probability that the variable node is correctly decoded is larger. Therefore, the information bit column corresponding to the variable node with smaller variable node degree should be shortened preferentially, and the information bit column corresponding to the variable node with larger variable node degree should be retained as much as possible.
  • h i,j is any element in the check matrix of the LDPC code
  • M NK
  • N is the check of the LDPC code
  • K is the number of columns of information bit columns in the check matrix of the LDPC code, that is, ⁇ j is: a check node to which the variable node j is connected, or a check equation to which the variable node j participates.
  • ⁇ (i) represents the number of variable nodes connected to the check node i.
  • the step of determining the outer information sum of the variable node j is: first determining a set of check nodes connected to the variable node j, and then determining, for each check node in the set, the number of variable nodes connected to the check node, Finally, add all the numbers to get the outer information sum of the variable node j.
  • the information that the check node i passes to the variable node j is the confidence message of the remaining ⁇ (i)-1 check nodes. If the ⁇ (i)-1 is larger, the variable node j can receive more A lot of confidence messages from check node i, so that variable node j is more easily decoded correctly in the iterative decoding process, so the probability that variable node j is correctly decoded depends on: all the schools connected to variable node j Check the total number of sent messages sent by node i, that is, the sum of the outer information of variable node j.
  • the other variable nodes can receive the confidence from the check node.
  • the message will be reduced, which in turn will reduce the probability that other variable nodes will be correctly decoded. Therefore, in order to avoid shortening the operation, the degree of any check node is too sharp, and the information bit column corresponding to the outer information and the larger variable node should be shortened preferentially, while the information bits corresponding to the outer information and the smaller variable node are retained as much as possible. Column.
  • FIG. 7 is a schematic diagram of the VN3 external information sum of the variable node.
  • variable node degree of the variable node VN1 is 1, the variable node degree of the variable node VN2 is also 1, the variable node degree of the variable node VN1 and the variable node VN2 is the same, but the variable node VN1 is outside.
  • the shortening operation refers to the fact that a column in the information bit column is associated with 0 bit. In order to avoid shortening the operation, the degree of any check node is too sharp, which seriously affects the information transmission of the check node in iterative decoding.
  • the variable nodes with the same degree of variable nodes in the shortening process should preferentially shorten the outer information and the larger variable nodes of E(j).
  • d j is the variable node degree of the variable node V j in the ring.
  • the ACE value of the ring represents the connectivity of the ring to the remaining part in the factor graph of the LDPC code. The larger the ACE value of the ring, the more external ring from the ring can be received in the iterative decoding. Information, so that the various variable nodes contained in the ring are more easily decoded correctly. If the ACE value of the ring is small, the variable nodes included in the ring will not be able to adequately receive the external information from the ring in the iterative decoding, so that it is not easy to obtain correct decoding.
  • Each variable node in the factor graph of the LDPC code may participate in multiple rings, and the lengths of these rings are different.
  • the variable node V j there are multiple rings with the shortest length among the participating rings.
  • the set of the shortest rings in which the variable node V j participates is ⁇ V j
  • its Total ACE is defined as:
  • TotalACE j is the sum of the ACE values of all the shortest rings in which the variable node V j participates.
  • the variable node with a larger TotalACE value is more likely to receive more confidence information from the outside in the iterative decoding, so that it is easier to obtain correct decoding.
  • a variable node with a smaller TotalACE value is relatively incapable of being correctly decoded. Therefore, the information bit column corresponding to the smaller variable node of TotalACE should be shortened preferentially, and the information bit column corresponding to the larger variable node of TotalACE should be retained as much as possible.
  • the LDPC code shortening method provided by the embodiment of the present invention first utilizes any of the variable node degree, the external information, and the Total ACE, because the variable node degree, the outer information, and the Total ACE have an impact on the shortening priority of the information bit column.
  • the combination of the two or a combination of the three determines the shortening priority of each information bit column, and then shortens the information bit column according to the determined shortening priority.
  • FIG. 8 is a flowchart of a method for generating an LDPC code according to an embodiment of the present invention.
  • the LDPC code generating method provided by the embodiment of the present invention includes the following steps:
  • Step 81 Generate a shortened priority pattern by using a total progressive progressive out-of-information information Total ACE and/or external information sum of variable nodes corresponding to each information bit column in the LDPC code check matrix of the low-density check, the shortening priority
  • the pattern includes one or more columns of information bits arranged in descending order of priority from high to low.
  • the shortening priority of the information bit column is increased as the Total ACE of the variable node corresponding to the information bit column is decreased, and the external information sum of the variable node corresponding to the information bit column is increased;
  • Step 82 Determine, according to the LDPC code check matrix, the number of information bits to be shortened, and use the shortened priority pattern to determine the information bit column that needs to be shortened;
  • Step 83 shorten the determined need according to the order of shortening the priority from high to low.
  • the information bitstream is sequentially shortened to obtain an information bitstream of the generated low-density check code.
  • An LDPC code having a bit and a code rate R 1/2, whose check matrix H is composed of a 81 ⁇ 81 cyclic shift square matrix.
  • the shortening priority pattern in the existing WLAN standard is: 12, 11, that is, the shortening operation preferentially shortens the 12th column in the information bit column, and then shortens the 11th column in the information bit column.
  • the number of columns of the information bit column included in the shortened priority pattern may be equal to the total number of columns of the information bit column in the LDPC code check matrix. Since the check matrix used in the WLAN standard is fixed, the LDPC provided by the embodiment of the present invention may be utilized.
  • the code shortening method determines the shortening priority pattern in advance, and can shorten the priority pattern provided by the embodiment of the present invention, regardless of the number of columns of the information bit column that needs to be shortened, so the system hardware complexity is not increased, so the present invention
  • the LDPC code shortening scheme provided by the embodiment has strong competitiveness.
  • the number of columns of the information bit column included in the shortened priority pattern may be greater than or equal to the number of columns of the information bit column that needs to be shortened.
  • the number of columns of information bit columns that need to be shortened is M columns, and then a shortened priority pattern including N columns of information bit columns is determined, wherein N is greater than or equal to M, and N and M are positive integers. .
  • step 81 has the following three types:
  • the first specific implementation manner is: generating a shortened priority pattern by using a total progressive extra-cyclic information degree Total ACE of a variable node corresponding to each information bit column in the low-density parity check LDPC code check matrix.
  • the TotalACE of the variable node corresponding to each information bit column in the LDPC code check matrix is used to measure the shortening priority of the information bit column corresponding to the variable node.
  • the TotalACE should be shortened preferentially.
  • the second specific implementation manner is: generating a shortened priority pattern by using the low-density check LDPC code check matrix outer information of the variable node corresponding to each information bit column.
  • the LDPC code is used to check the outer information of the variable node corresponding to each information bit column in the matrix and the shortening priority of the information bit column corresponding to the variable node.
  • a third specific implementation manner is: generating, by using a low-density check LDPC code check matrix, a total progressive in-loop information degree Total ACE and a foreign information sum of a variable node corresponding to each information bit column, and generating a shortened priority pattern,
  • the shortening the priority pattern includes one or more columns of information bit columns arranged in descending order of priority from highest to lowest, wherein the shortening priority of the information bit column decreases with the Total ACE of the variable node corresponding to the information bit column The increase is small and increases as the sum of the outer information of the variable node corresponding to the information bit column increases.
  • the Total ACE and the outer information of the variable node corresponding to each information bit column in the LDPC code check matrix are used to measure the shortening priority of the information bit column corresponding to the variable node.
  • the Total ACE and the external information sum of the variable node corresponding to each information bit column in the LDPC code check matrix are used to generate a shortened priority pattern, which specifically includes:
  • FIG. 9 is a flowchart of generating a shortened priority pattern by using a Total ACE and a foreign information sum of a variable node corresponding to each information bit column in an LDPC code check matrix according to an embodiment of the present invention, including the following steps. :
  • Step 91 Select all information bit columns from each information bit column in the LDPC code check matrix to be stored in the first set;
  • Step 92 Select, from the first set, information bit columns corresponding to variable nodes having the largest outer information sum, to be stored in the second set;
  • Step 93 Select an information bit column corresponding to the variable node having the smallest Total ACE from the second set, and store the shortened priority pattern;
  • Step 94 If the number of columns of the information bit column included in the shortened priority pattern is not less than the number of columns corresponding to the number of information bits to be shortened by the LDPC code check matrix, the process ends, and the final shortened priority is obtained. Pattern; otherwise
  • the updating of the LDPC code check matrix includes:
  • initialization is performed first.
  • the set of information bit columns in the LDPC code check matrix H is the first set P, and for the variable node j corresponding to each information bit column in the first set P, the external information and E(j) are first calculated and recorded.
  • TotalACE j the number of columns corresponding to the number of information bits to be shortened in the LDPC code check matrix is SL;
  • step a is performed: selecting information bit columns corresponding to the variable nodes having the largest outer information sum from the first set P and storing them in the second set G 1 ;
  • Step b an information LEAST Total ACE node corresponding to a second selection from the set G into shorter bit string pattern priorities
  • step c is performed to determine whether the number of columns of the information bit column included in the current shortened priority pattern is less than SL, if not less, step d is performed, if not, step e is performed;
  • Step d End processing, and shorten the priority pattern as the final shortening priority pattern
  • Step e Update the LDPC code check matrix, and return to the updated LDPC code check matrix to perform step a.
  • each information bit column in the LDPC code check matrix H is: the first column to the eighth column
  • the first set P includes the first column to the eighth column.
  • the external information of the first column to the eighth column are: 1, 2, 3, 3, 3, 3, 2, 1. Since the maximum outer information sum in the first set P is 3, and the information bits of the outer information sum 3 are listed as the third to sixth columns, the third to sixth columns are first selected from the first set P. Into the second set G 1 .
  • the Total ACEs in columns 3 through 6 are: 1, 1, 3, and 4, respectively. Since the minimum Total ACE of the second set G 1 is 1, and the information bits of the Total ACE of 1 are listed as the third column and the fourth column, the third column and the fourth column are stored in the shortened priority pattern.
  • the processing ends and the The shortened priority pattern of the third column of information bits is used as the final shortened priority pattern.
  • the Total ACEs in columns 3 through 6 are: 1, 2, 3, and 4, respectively. Since the minimum Total ACE of the second set G 1 is 1, and the information bit of the Total ACE is 1 is the third column, the third column is stored in the shortened priority pattern.
  • the shortened priority pattern of the bitstream is used as the final shortened priority pattern.
  • the check matrix of the LDPC code is updated. Then, the updated LDPC code check matrix is returned to perform step a.
  • each information bit column in the updated LDPC code check matrix is: the first column to the second column, the third column, the fourth column to the eighth column, and the first set P includes: the first column to the second column Column, column 3', column 4 to column 8. Assuming that the information bit column having the largest outer information sum is selected from the first set P, and then the information bit column having the smallest Total ACE is selected from the information bit column having the largest outer information sum as the fourth column, the fourth column is stored. Enter Shorten the priority pattern.
  • the shortened priority pattern contains the information bits listed as: column 3 and column 4. Since the third column is stored in the shortened priority pattern before the fourth column, the shortening of the third column is prioritized. The level is higher than the shortening priority of the fourth column.
  • variable node degree of the variable node corresponding to each information bit column in the LDPC code check matrix, the Total ACE and the external information, and the shortening priority of the information bit column corresponding to the variable node may also be used.
  • variable node degree, the Total ACE, and the external information sum of the variable node corresponding to each information bit column in the LDPC code check matrix are used to generate a shortened priority pattern, which specifically includes:
  • FIG. 10 is a flowchart of generating a shortened priority pattern by using a variable node degree, a Total ACE, and an external information of a variable node corresponding to each information bit column in an LDPC code check matrix according to an embodiment of the present invention. Specifically, the following steps are included:
  • Step 101 Select a partial information bit column from each information bit column in the LDPC code check matrix to be stored in the first set, that is, select a minimum variable from each information bit column in the LDPC code check matrix.
  • the information bit column corresponding to the node node of the node degree is stored in the first set;
  • Step 102 Select, from the first set, information bit columns corresponding to variable nodes having the largest outer information sum, to be stored in the second set;
  • Step 103 Select, from the second set, an information bit column corresponding to a variable node having a minimum Total ACE, and store the shortened priority pattern;
  • Step 104 If the shortened priority pattern includes a number of columns of information bit columns not less than If the LDPC code check matrix needs to shorten the number of columns corresponding to the number of information bits, the process ends, and the final shortened priority pattern is obtained; otherwise
  • initialization is performed first.
  • the set of information bit columns in the LDPC code check matrix H is the zeroth set Q.
  • the variable node degree d j is first calculated and recorded.
  • Information and E(j) and TotalACE j the number of columns corresponding to the number of information bits to be shortened in the LDPC code check matrix is SL;
  • step Z selecting the information bit column corresponding to the variable node having the smallest variable node degree from the zeroth set Q to be stored in the first set P;
  • step A is performed: selecting information bit columns corresponding to the variable nodes having the largest outer information sum from the first set P and storing them in the second set G 1 ;
  • step B selecting a second set of G 1 having an information variable from a minimum Total ACE node into a bit sequence corresponding to the priority shortening pattern;
  • step C is performed to determine whether the number of columns of the information bit column included in the current shortened priority pattern is less than SL, if not less, step D is performed, if not, step E is performed;
  • Step D End the process, and shorten the priority pattern as the final shortening priority pattern
  • Step E Update the LDPC code check matrix, and return to the updated LDPC code check matrix to perform step Z.
  • updating the LDPC code check matrix includes:
  • each information bit column in the LDPC code check matrix H is: column 1 to column 10
  • the zeroth set Q includes the first column to the tenth column.
  • the variable node degrees of the first column to the tenth column are: 1, 1, 1, 1, 1, 1, 1, 1, 2, and 3. Since the minimum variable node degree in the zeroth set Q is 1, and the information bit column whose variable node degree is 1 is the first column to the eighth column, first, the first column to the eighth column are selected from the zeroth set Q.
  • the first set P Assume that the external information of the first column to the eighth column are: 1, 2, 3, 3, 3, 3, 2, 1. Since the maximum outer information sum in the first set P is 3, and the information bits of the outer information sum 3 are listed as the third to sixth columns, the third to sixth columns are first selected from the first set P.
  • the second set G 1 Into the second set G 1 .
  • the external information of the first column to the fourth column are: 1, 2, 3, 3, 3, 3, 2, 1. Since the maximum outer information sum in the first set P is 3, and the information bits of the outer information sum 3 are listed as the third to sixth columns, the third to sixth columns are first selected from the first set P. Into the second set G 1 .
  • the processing ends and the The shortened priority pattern of the third column of information bits is used as the final shortened priority pattern.
  • the Total ACEs in columns 3 through 6 are: 1, 2, 3, and 4, respectively. Since the minimum Total ACE of the second set G 1 is 1, and the information bit of the Total ACE is 1 is the third column, the third column is stored in the shortened priority pattern.
  • the shortened priority pattern of the bitstream is used as the final shortened priority pattern.
  • the check matrix of the LDPC code is updated. Then, the updated LDPC code check matrix is returned to perform step a.
  • each information bit column in the updated LDPC code check matrix is: column 1 to column 2, column 3, column 4 to column 10, Then, the zeroth set Q includes: the first column to the second column, the third column, and the fourth column to the tenth column.
  • the fourth column is stored in the shortened priority pattern.
  • the information bit column included in the shortened priority pattern is: column 3 and column 4. Since the third column is stored in the shortened priority pattern before the fourth column, the shortening priority of the third column is higher than the shortening priority of the fourth column.
  • the mother matrix refers to an LDPC code check matrix whose sub-matrices are not cyclically extended as shown in FIG. 1, wherein each element in the mother matrix represents a sub-matrix.
  • the WLAN existing standard IEEE 802.11n/ac defines three code lengths for LDPC codes: 648 bits, 1296 bits, 1944 bits, and 4 code rates: 1/2, 2/3, 3/4, 5/6, each An LDPC code check matrix is defined for both the code length and the code rate, so a total of 12 check matrices are included.
  • variable node degree Total ACE and external information sum of the variable node corresponding to each information bit column in the LDPC code check matrix as shown in FIG. 10, a method for shortening the priority pattern is generated, and the 12 checksums can be obtained.
  • the priority matrix of the matrix matrix is shortened, and the priority pattern is shortened to include each information bit column, and the shortening priority of the information bit column in each shortened priority pattern is gradually reduced from left to right:
  • the shortening priority pattern of the check matrix with a code length of 648 bits and a code rate of 1/2 is: 7 ⁇ 6 ⁇ 11 ⁇ 10 ⁇ 2 ⁇ 3 ⁇ 12 ⁇ 8 ⁇ 4 ⁇ 9 ⁇ 5 ⁇ 1;
  • the shortening priority pattern of the check matrix with a code length of 648 bits and a code rate of 2/3 is: 11 ⁇ 10 ⁇ 15 ⁇ 14 ⁇ 16 ⁇ 13 ⁇ 12 ⁇ 5 ⁇ 8 ⁇ 7 ⁇ 6 ⁇ 9 ⁇ 4 ⁇ 1 ⁇ 2 ⁇ 3;
  • the shortening priority pattern of the check matrix with a code length of 648 bits and a code rate of 3/4 is: 13 ⁇ 12 ⁇ 15 ⁇ 14 ⁇ 18 ⁇ 17 ⁇ 16 ⁇ 11 ⁇ 10 ⁇ 6 ⁇ 9 ⁇ 8 ⁇ 7 ⁇ 2 ⁇ 1 ⁇ 5 ⁇ 3 ⁇ 4;
  • the shortening priority pattern of the check matrix with a code length of 648 bits and a code rate of 5/6 is: 13 ⁇ 19 ⁇ 12 ⁇ 16 ⁇ 4 ⁇ 14 ⁇ 20 ⁇ 2 ⁇ 7 ⁇ 5 ⁇ 6 ⁇ 9 ⁇ 17 ⁇ 1 ⁇ 11 ⁇ 3 ⁇ 10 ⁇ 15 ⁇ 18 ⁇ 8;
  • the shortening priority pattern of the check matrix with a code length of 1296 bits and a code rate of 1/2 is: 7 ⁇ 6 ⁇ 4 ⁇ 3 ⁇ 8 ⁇ 11 ⁇ 12 ⁇ 10 ⁇ 2 ⁇ 1 ⁇ 9 ⁇ 5;
  • the shortening priority pattern of the check matrix with a code length of 1926 bits and a code rate of 2/3 is: 6 ⁇ 8 ⁇ 7 ⁇ 10 ⁇ 14 ⁇ 9 ⁇ 13 ⁇ 16 ⁇ 11 ⁇ 15 ⁇ 12 ⁇ 5 ⁇ 4 ⁇ 3 ⁇ 1 ⁇ 2;
  • the shortening priority pattern of the check matrix with a code length of 1926 bits and a code rate of 3/4 is: 8 ⁇ 9 ⁇ 10 ⁇ 17 ⁇ 12 ⁇ 15 ⁇ 18 ⁇ 13 ⁇ 14 ⁇ 11 ⁇ 16 ⁇ 2 ⁇ 7 ⁇ 5 ⁇ 3 ⁇ 1 ⁇ 4 ⁇ 6;
  • the shortening priority pattern of the check matrix with a code length of 1926 bits and a code rate of 5/6 is: 19 ⁇ 18 ⁇ 20 ⁇ 17 ⁇ 7 ⁇ 11 ⁇ 9 ⁇ 1 ⁇ 16 ⁇ 8 ⁇ 5 ⁇ 3 ⁇ 2 ⁇ 13 ⁇ 15 ⁇ 10 ⁇ 12 ⁇ 4 ⁇ 14 ⁇ 6;
  • the shortening priority pattern of the check matrix with a code length of 1944 bits and a code rate of 1/2 is: 3 ⁇ 4 ⁇ 7 ⁇ 6 ⁇ 8 ⁇ 10 ⁇ 11 ⁇ 12 ⁇ 2 ⁇ 1 ⁇ 9 ⁇ 5;
  • the shortening priority pattern of the check matrix with a code length of 1944 bits and a code rate of 2/3 is: 13 ⁇ 12 ⁇ 9 ⁇ 15 ⁇ 10 ⁇ 6 ⁇ 14 ⁇ 8 ⁇ 7 ⁇ 16 ⁇ 11 ⁇ 5 ⁇ 3 ⁇ 1 ⁇ 2 ⁇ 4;
  • the shortening priority pattern of the check matrix with a code length of 1944 bits and a code rate of 3/4 is: 9 ⁇ 16 ⁇ 17 ⁇ 14 ⁇ 18 ⁇ 8 ⁇ 10 ⁇ 13 ⁇ 12 ⁇ 15 ⁇ 7 ⁇ 11 ⁇ 4 ⁇ 5 ⁇ 3 ⁇ 2 ⁇ 6 ⁇ 1;
  • the shortening priority pattern of the check matrix with a code length of 1944 bits and a code rate of 5/6 is: 18 ⁇ 12 ⁇ 17 ⁇ 20 ⁇ 16 ⁇ 14 ⁇ 15 ⁇ 13 ⁇ 11 ⁇ 19 ⁇ 2 ⁇ 10 ⁇ 9 ⁇ 6 ⁇ 8 ⁇ 1 ⁇ 4 ⁇ 7 ⁇ 3 ⁇ 5.
  • step 82 and step 83 are performed. Before performing step 82, first determine the number of information bits that the LDPC code check matrix needs to be shortened. For example, the number of bits that need to be shortened currently is 54, 108, 216, 162, 324, and so on. Then, step 82 is performed to determine the information bit sequence that needs to be shortened by shortening the priority pattern according to the number of information bits that need to be shortened according to the LDPC code check matrix.
  • the check matrix H is composed of a 27 ⁇ 27 cyclic shift square matrix. Assume that the number of bits that need to be shortened is currently 54. In this case, the two columns of information bits in the mother matrix need to be shortened. When the number of bits to be shortened is 108, the four columns of information bits in the mother matrix need to be shortened.
  • the two columns of information bit columns in the mother matrix need to be shortened.
  • the number of bits to be shortened is 216
  • the four columns of information bits in the mother matrix need to be shortened.
  • the check matrix H is composed of a 81 ⁇ 81 cyclic shift square matrix. Assume that the number of bits that need to be shortened is 162. In this case, the two columns of information bits in the mother matrix need to be shortened. When the number of bits to be shortened is 324, the four columns of information bits in the mother matrix need to be shortened.
  • the shortening priority pattern of the check matrix with a code length of 648 bits and a code rate of 1/2 is: 7 ⁇ 6 ⁇ 11 ⁇ 10 ⁇ 2 ⁇ 3 ⁇ 12 ⁇ 8 ⁇ 4 ⁇ 9 ⁇ 5 ⁇ 1, so When it is necessary to shorten the information column of two columns, it is determined that the information bit columns that need to be shortened are the seventh column and the sixth column. When it is necessary to shorten the information column of four columns, the information bit column that needs to be shortened is determined to be the seventh column, Column 6, column 11, and column 12.
  • step 83 the determined information bitstreams that need to be shortened are sequentially shortened in order of shortening the priority from high to low, and the information bitstream of the generated LDPC code is obtained.
  • the information bits that need to be shortened are listed as the seventh column and the sixth column, and the shortening priority of the seventh column is higher than the shortening priority of the sixth column, the seventh column is shortened first, and then the sixth column is shortened. The column is shortened, and further, the information bit sequence of the generated LDPC code is obtained.
  • each information bit column included in the check matrix of the LDPC code includes N sub-columns, and N is an integer greater than or equal to 1.
  • the check matrix H is composed of a 27 ⁇ 27 cyclic shift square matrix, and each information bit The column contains 27 subcolumns.
  • the check matrix H is composed of a 54 ⁇ 54 cyclic shift square matrix, and each information bit column includes 54 sub-columns.
  • the check matrix H is composed of a 81 ⁇ 81 cyclic shift square matrix, and each information bit column includes 81 sub-columns.
  • the other information bit columns except the information bit column with the lowest priority are shortened in sequence for the determined information bit string that needs to be shortened;
  • M sub-columns are randomly selected from the N sub-columns included in the information bit column with the lowest priority, and M is the remainder of the number of information bits to be shortened by the LDPC code check matrix divided by N, and M is greater than An integer equal to 1.
  • each of the information bit columns included in the check matrix of the LDPC code includes N sub-columns, because the WLAN standard uses the quasi-cyclic LDPC code as shown in FIG. 1 and FIG. 2, so N sub-sub-subs The variable node degree, outer information, and Total ACE of the column are the same. Therefore, the shortening priorities of the N sub-columns are the same.
  • M sub-columns may be randomly selected from the N sub-columns included in the information bit column for shortening.
  • the check matrix H is composed of a 27 ⁇ 27 cyclic shift square matrix, each information.
  • the bit column contains 27 subcolumns.
  • the number of bits that need to be shortened is 30 at this time.
  • the shortening priority pattern of the check matrix is: 7 ⁇ 6 ⁇ 11 ⁇ 10 ⁇ 2 ⁇ 3 ⁇ 12 ⁇ 8 ⁇ 4 ⁇ 9 ⁇ 5 ⁇ 1, and the information bits that need to be shortened are determined to be the seventh column and the sixth column.
  • the shortening priority of the seventh column is higher than the shortening priority of the sixth column, first shortening the seventh column, and after shortening the entire column of the seventh column, randomly selecting 3 out of the 27 sub-columns included in the sixth column Sub-columns are shortened.
  • Table 1 shows that the code length is 648 bits and the code rate is 1/2.
  • Table 2 shows that the code length is 1296 bits and the code rate is 1/2.
  • Table 3 shows that the code length is 1944 bits and the code rate is 1/2.
  • Table 1 lists the comparison of the priority pattern with a code length of 648 bits and a code rate of 1/2.
  • Table 2 lists the comparison of the priority patterns with a code length of 1296 bits and a code rate of 1/2.
  • Table 3 lists the comparison of the shortened priority patterns with a code length of 1944 bits and a code rate of 1/2.
  • the channel is AWGN (Chinese: Additive White Gaussian Noise)
  • the modulation mode is BPSK (Chinese: Binary Phase Shift Keying; English: Binary Phase Shift Keying)
  • the decoding algorithm is LLR-BP.
  • the performance of the shortening scheme provided by the embodiment of the present invention and the BLER (Chinese: Block Error Rate) performance of the shortening scheme in the prior art are respectively simulated. Please refer to Figure 11, 12 and FIG. 13, FIG.
  • FIG. 11 is a comparison diagram of the BLER performance of the shortening scheme provided by the embodiment of the present invention and the shortening scheme of the prior art under the code length of 648 bits and a code rate of 1/2
  • FIG. 12 is a code length of FIG. 1296 bit and code rate is 1/2
  • FIG. 13 is the code length of 1944 bits and the code rate is 1/2.
  • the abscissa is Eb/No, that is, the ratio of signal power to noise power, the unit is decibel (ie, dB), and the ordinate is BLER.
  • the shortening scheme provided by the embodiment of the present invention has better performance than the shortening scheme in the prior art under various code lengths and code rates.
  • the performance advantages of the LDPC code generation scheme provided by the embodiment of the present invention are particularly obvious when the number of columns of information bit columns to be shortened is large.
  • the existing WLAN needs to perform a large number of shortening operations in the short packet service, and therefore the present invention has obvious advantages in the WLAN short packet service.
  • the check matrix used in the WLAN standard is fixed, the LDPC code shortening method provided by the embodiment of the present invention can be used to determine the shortened priority pattern in advance, without increasing the system hardware complexity.
  • the LDPC code generation scheme has strong competitiveness.
  • FIG. 14 is a block diagram of a low density check code generating apparatus.
  • the low density check code generating device includes:
  • a generating unit 1 configured to generate a shortened priority pattern by using a total progressive extra-cyclic information degree Total ACE and/or an external information sum of a variable node corresponding to each information bit column in the low-density check LDPC code check matrix,
  • the shortening of the priority pattern includes one or more columns of information bits arranged in descending order of priority from high to low.
  • the shortening priority of the information bit column is increased as the Total ACE of the variable node corresponding to the information bit column is decreased, and the external information sum of the variable node corresponding to the information bit column is increased;
  • the processing unit 2 is configured to determine, according to the number of information bits that need to be shortened according to the LDPC code check matrix, by using a shortened priority pattern to determine an information bit sequence that needs to be shortened;
  • the shortening unit 3 is configured to sequentially shorten the identified information bitstreams that need to be shortened in order of shortening the priority from high to low, and obtain information bitstreams of the generated low-density check codes.
  • the generating unit 1 includes:
  • the information bit column is stored in the shortened priority pattern until the number of columns of the information bit column included in the shortened priority pattern is not less than the number of columns corresponding to the number of information bits to be shortened by the LDPC code check matrix And wherein the shortening priority level of the information bit column corresponds to a sequence in which the information bit column is stored in the shortened priority pattern:
  • a first selection module configured to select all information bit columns or partial information bit columns from each information bit column in the LDPC code check matrix to be stored in the first set;
  • a second selection module configured to select, from the first set, an information bit column corresponding to the variable node having the largest outer information sum, to be stored in the second set;
  • a third selection module configured to select, from the second set, an information bit column corresponding to a variable node having a minimum Total ACE, to store the shortened priority pattern
  • a processing module configured to: if the number of columns of information bit columns included in the shortened priority pattern is not less than a number of columns corresponding to the number of information bits to be shortened by the LDPC code check matrix, end processing, and obtain the final shortening Priority pattern; otherwise
  • an updating module configured to update the LDPC code check matrix, and return the execution selection information bit sequence to the first set in the updated LDPC code check matrix.
  • the first selection module is used to:
  • the update module is used to:
  • the information bit column includes N sub-columns, and N is an integer greater than or equal to 1;
  • the shortening unit 3 is configured to:
  • the other information bit columns except the information bit column with the lowest priority are shortened in sequence for the determined information bit string that needs to be shortened;
  • M sub-columns are randomly selected from the N sub-columns included in the information bit column with the lowest priority, and M is the remainder of the number of information bits to be shortened by the LDPC code check matrix divided by N, and M is greater than An integer equal to 1.
  • FIG. 15 is a schematic diagram showing the hardware structure of the low-density check code generating apparatus in the embodiment.
  • the low-density check code generating apparatus includes: a processor 01, configured to use the low-density check LDPC code check matrix, the total progressive outer-out information degree Total ACE and/or the outer information of the variable node corresponding to each information bit column Generating a shortened priority pattern including one or more columns of information bit columns arranged in descending order of priority from high to low,
  • the shortening priority of the information bit column is increased as the Total ACE of the variable node corresponding to the information bit column is decreased, and the external information sum of the variable node corresponding to the information bit column is increased; Determining an information bit sequence that needs to be shortened by using a shortened priority pattern according to the number of information bits that need to be shortened according to the LDPC code check matrix;
  • the information bit string that needs to be shortened is sequentially shortened in order of shortening the priority from high to low, and the information bit sequence of the generated low density check code is obtained.
  • the processor 01 is configured to:
  • the information bit column is stored in the shortened priority pattern until the number of columns of the information bit column included in the shortened priority pattern is not less than the number of columns corresponding to the number of information bits to be shortened by the LDPC code check matrix And wherein the shortening priority level of the information bit column corresponds to a sequence in which the information bit column is stored in the shortened priority pattern:
  • the process ends, and the final shortened priority pattern is obtained; otherwise
  • the processor 01 is configured to:
  • the processor 01 is configured to:
  • the information bit column includes N sub-columns, and N is an integer greater than or equal to 1;
  • the processor 01 is configured to:
  • the other information bit columns except the information bit column with the lowest priority are shortened in sequence for the determined information bit string that needs to be shortened;
  • M sub-columns are randomly selected from the N sub-columns included in the information bit column with the lowest priority, and M is the remainder of the number of information bits to be shortened by the LDPC code check matrix divided by N, and M is greater than An integer equal to 1.
  • bus 00 can include any number of interconnected buses and bridges, bus 00 will include one or more processors and memory 02 represented by processor 01. The various circuits of the memory are connected together. Bus 00 can also connect various other circuits such as peripherals, voltage regulators, and power management circuits. These are well known in the art and, therefore, will not be further described herein.
  • the processor 01 is responsible for managing the bus 00 and the usual processing, and the memory 02 can be used to store the data used by the processor 01 when performing the operations.
  • a total priority progressive out-of-loop information degree Total ACE and/or an external information sum of a variable node corresponding to each information bit column in the low-density parity check LDPC code check matrix is used to generate a shortened priority pattern, that is, According to the order of shortening the priority from high to low, one or more columns of information bit rows are arranged; then, according to the number of information bits that need to be shortened according to the LDPC code check matrix, the shortened priority pattern is used to determine the information bit column that needs to be shortened; In order of priority from high to low, the identified information bitstreams that need to be shortened are sequentially shortened to obtain information bitstreams of the generated low-density check codes.
  • the embodiment of the present invention utilizes the information.
  • the Total ACE and/or external information of the variable node corresponding to the bit string and the shortening priority of the information bit column are improved, the performance of the LDPC code is shortened, and the performance loss due to the shortening is reduced.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the present invention is directed to a method, apparatus (system), and computer program according to an embodiment of the present invention.
  • the flow chart and/or block diagram of the product is described. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG.
  • These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

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Abstract

本发明提供一种低密度校验码生成方法及装置，所述方法包括：利用低密度校验LDPC码校验矩阵中的各个信息比特列对应的变量节点的总渐进环外信息度Total ACE和/或外信息和，生成缩短优先级图样，所述缩短优先级图样包括按照缩短优先级从高到低依次排列的一列或多列信息比特列，其中，所述信息比特列的缩短优先级随所述信息比特列对应的变量节点的Total ACE的减小而提升，随所述信息比特列对应的变量节点的外信息和的增大而提升；根据所述LDPC码校验矩阵需缩短的信息比特数，利用缩短优先级图样确定出需要缩短的信息比特列；按照缩短优先级从高到低的顺序，对确定出的所述需要缩短的信息比特列依次进行缩短，得到生成的低密度校验码的信息比特列。

Description

一种低密度校验码生成方法及装置 技术领域
本发明涉及通信技术领域，尤其涉及一种低密度校验码生成方法及装置。
背景技术
目前WLAN(中文：无线局域网；英文：Wireless Local Area Networks)标准(IEEE 802.11n/ac)的可选信道编码方案为：利用LDPC(中文：低密度校验；英文：Low-density parity-check)码进行编码。
下面举例说明对待编码数据比特进行LDPC编码的过程。假设采用的码长为648比特，码率为
Figure PCTCN2015077122-appb-000001
的LDPC码校验矩阵H对待编码数据比特进行编码，如图1所示为12×24的校验矩阵示意图，该校验矩阵中的每一个元素代表一个27×27的循环移位方阵，其中-代表27×27全零方阵(方阵中的元素均为0)，0代表27×27单位阵(方阵中对角线上的元素为1，其余均为0)，i(0≤i≤26)代表27×27单位阵各行循环右移i位得到的方阵
Figure PCTCN2015077122-appb-000002
图2分别为27×27全零方阵的示意图、27×27单位阵的示意图以及
Figure PCTCN2015077122-appb-000003
的示意图。对于如图1所示的校验矩阵，由于码率为
Figure PCTCN2015077122-appb-000004
所以前12列为信息比特列，后12列为校验比特列。
首先用待编码数据比特一一对应于校验矩阵的信息比特列，再利用矩阵中的校验关系生成校验比特。校验矩阵中没有待编码数据比特对应的信息比特列即为需要缩短的信息比特列。由于待编码数据比特对应校验矩阵的信息比特列的顺序是从信息比特列的第1列至最后一列依次进行，所以需要缩短的信息比特列通常靠后，在进行缩短操作时按照从后往前的顺序进行，即缩短优先级为从信息比特列的最后一列至第1列依次降低。
例如：如图1所示，待编码数据比特对应校验矩阵的信息比特列中的第1列至第10列，由于待编码数据比特的比特数量有限，信息比特列中的第11 列和第12列没有待编码数据比特与之对应，则信息比特列中的第11列和第12列成为需要缩短的信息比特列，需要对信息比特列中的第12列和第11列依次进行缩短操作。
然而，现有技术中的缩短方案没有考虑到LDPC码校验矩阵及其因子图的具体结构。图3和图4分别为一个4×8的LDPC码校验矩阵H及其因子图。图3中LDPC码校验矩阵H中的每一列对应一个变量节点，每一行对应一个校验节点，图3所示的LDPC码校验矩阵中有8个变量节点：V1至V8，以及4个校验节点：C1至C4。对于变量节点，有三个参数：变量节点度、外信息和以及Total ACE(中文：总渐进环外信息度；英文：Total Approximate Cycle Extrinsic Message Degree)。
以变量节点V1为例，从图4中可知，与变量节点V1相连的校验节点有：C1和C2，数目为2，或者从图3中可知，变量节点V1对应的信息比特列的列重(即该列非0元素的个数)为2，则可以确定变量节点V1的变量节点度为2。
由于与变量节点V1的相连的校验节点有：C1和C2，而与校验节点C1相连的变量节点数目为4，与校验节点C2相连的变量节点数目为4，则可确定变量节点V1的外信息和为(4-1)+(4-1)＝6。
首先借助图5说明ACE的计算方法。请参考图5，图5为一个LDPC码校验矩阵中局部长度为6的环的示意图，该环由图中加粗线条表示。由于参与该环的变量节点集为{V1,V2,V3}，所以该环的ACE为(3-2)+(3-2)+(3-2)＝3。
由于变量节点V1可能参与多个环，这些环的长度大小不同。对于变量节点V1，假设变量节点V1所参与的所有环中长度最短的环的ACE为3且有4个，则可确定变量节点V1的Total ACE为3+3+3+3＝12。
从图4中可知，节点集{V3,C3,V7,C1}构成了一个长度为4的环。由于参与该环的变量节点集为{V3,V7}，变量节点V3及变量节点V7的变量节点度分别为2 和2，所以该环的ACE为(2-2)+(2-2)＝0。
然而，现有技术中的缩短方案没有考虑到LDPC码校验矩阵及其因子图的具体结构，也就是说，没有考虑到LDPC码校验矩阵的信息比特列对应的变量节点的变量节点度、外信息和以及Total ACE，仅仅不加筛选地对信息比特列从后向前进行缩短。因此无法提供较优的缩短性能，当需要缩短的比特数目很多时性能损失尤为严重。
综上，现有技术中的缩短方案的缩短性能差，存在较大的性能损失。
发明内容
本发明实施例提供一种LDPC码生成方法及装置，用于改善对LDPC码进行缩短的缩短性能，减少性能损失。
本发明实施例第一方面提供了一种低密度校验码生成方法，包括：
利用低密度校验LDPC码校验矩阵中的各个信息比特列对应的变量节点的总渐进环外信息度Total ACE和/或外信息和，生成缩短优先级图样，所述缩短优先级图样包括按照缩短优先级从高到低依次排列的一列或多列信息比特列，
其中，所述信息比特列的缩短优先级随所述信息比特列对应的变量节点的Total ACE的减小而提升，随所述信息比特列对应的变量节点的外信息和的增大而提升；
根据所述LDPC码校验矩阵需缩短的信息比特数，利用缩短优先级图样确定出需要缩短的信息比特列；
按照缩短优先级从高到低的顺序，对确定出的所述需要缩短的信息比特列依次进行缩短，得到生成的低密度校验码的信息比特列。
结合第一方面，在第一方面的第一种可能的实现方式中，所述利用LDPC码校验矩阵中的各个信息比特列对应的变量节点的Total ACE和外信息和，生成缩短优先级图样，包括：
按照以下步骤选择信息比特列存入所述缩短优先级图样，直至所述缩短 优先级图样包含的信息比特列的列数不小于所述LDPC码校验矩阵需缩短的信息比特数对应的列数，其中，所述信息比特列的缩短优先级高低与所述信息比特列存入所述缩短优先级图样的先后顺序对应：
从所述LDPC码校验矩阵中的各个信息比特列中选择全部信息比特列或者部分信息比特列存入第一集合；
从所述第一集合中选择具有最大外信息和的变量节点对应的信息比特列存入第二集合；
从所述第二集合中选择具有最小Total ACE的变量节点对应的信息比特列存入所述缩短优先级图样；
若所述缩短优先级图样包含的信息比特列的列数不小于所述LDPC码校验矩阵需缩短的信息比特数对应的列数，则结束处理，得到最终的所述缩短优先级图样；否则
对所述LDPC码校验矩阵进行更新，并对更新后的LDPC码校验矩阵返回执行选择信息比特列存入第一集合的步骤。
结合第一方面的第一种可能的实现方式，在第一方面的第二种可能的实现方式中，所述从所述LDPC码校验矩阵中的各个信息比特列中选择部分信息比特列存入第一集合，包括：
从所述LDPC码校验矩阵中的各个信息比特列中选择具有最小变量节点度的变量节点对应的信息比特列存入所述第一集合。
结合第一方面的第一种可能的实现方式或第一方面的第二种可能的实现方式，在第一方面的第三种可能的实现方式中，所述对所述LDPC码校验矩阵进行更新，包括：
在所述LDPC码校验矩阵中，对存入所述缩短优先级图样的信息比特列中的所有元素置0。
结合第一方面的第三种可能的实现方式，在第一方面的第四种可能的实现方式中，所述信息比特列包含N个子列，N为大于等于1的整数；
当所述LDPC码校验矩阵需缩短的信息比特数不为N的整数倍时，所述 按照缩短优先级从高到低的顺序，对确定出的所述需要缩短的信息比特列依次进行缩短，包括：
按照缩短优先级从高到低的顺序，对确定出的所述需要缩短的信息比特列中除缩短优先级最低的信息比特列外的其他信息比特列依次进行缩短；
从所述缩短优先级最低的信息比特列包含的N个子列中随机选择M个子列进行缩短，M为所述LDPC码校验矩阵需缩短的信息比特数除以N所得的余数，M为大于等于1的整数。
本发明实施例第二方面提供了一种低密度校验码生成装置，包括：
生成单元，用于利用低密度校验LDPC码校验矩阵中的各个信息比特列对应的变量节点的总渐进环外信息度Total ACE和/或外信息和，生成缩短优先级图样，所述缩短优先级图样包括按照缩短优先级从高到低依次排列的一列或多列信息比特列，
其中，所述信息比特列的缩短优先级随所述信息比特列对应的变量节点的Total ACE的减小而提升，随所述信息比特列对应的变量节点的外信息和的增大而提升；
处理单元，用于根据所述LDPC码校验矩阵需缩短的信息比特数，利用缩短优先级图样确定出需要缩短的信息比特列；
缩短单元，用于按照缩短优先级从高到低的顺序，对确定出的所述需要缩短的信息比特列依次进行缩短，得到生成的低密度校验码的信息比特列。
结合第二方面，在第二方面的第一种可能的实现方式中，所述生成单元包括：
按照以下步骤选择信息比特列存入所述缩短优先级图样，直至所述缩短优先级图样包含的信息比特列的列数不小于所述LDPC码校验矩阵需缩短的信息比特数对应的列数，其中，所述信息比特列的缩短优先级高低与所述信息比特列存入所述缩短优先级图样的先后顺序对应：
第一选择模块，用于从所述LDPC码校验矩阵中的各个信息比特列中选择全部信息比特列或者部分信息比特列存入第一集合；
第二选择模块，用于从所述第一集合中选择具有最大外信息和的变量节点对应的信息比特列存入第二集合；
第三选择模块，用于从所述第二集合中选择具有最小Total ACE的变量节点对应的信息比特列存入所述缩短优先级图样；
处理模块，用于若所述缩短优先级图样包含的信息比特列的列数不小于所述LDPC码校验矩阵需缩短的信息比特数对应的列数，则结束处理，得到最终的所述缩短优先级图样；否则
更新模块，用于对所述LDPC码校验矩阵进行更新，并对更新后的LDPC码校验矩阵返回执行选择信息比特列存入第一集合的步骤。
结合第二方面的第一种可能的实现方式，在第二方面的第二种可能的实现方式中，所述第一选择模块用于：
从所述LDPC码校验矩阵中的各个信息比特列中选择具有最小变量节点度的变量节点对应的信息比特列存入所述第一集合。
结合第二方面的第一种可能的实现方式或第二方面的第二种可能的实现方式，在第二方面的第三种可能的实现方式中，所述更新模块用于：
在所述LDPC码校验矩阵中，对存入所述缩短优先级图样的信息比特列中的所有元素置0。
结合第二方面的第三种可能的实现方式，在第二方面的第四种可能的实现方式中，所述信息比特列包含N个子列，N为大于等于1的整数；
当所述LDPC码校验矩阵需缩短的信息比特数不为N的整数倍时，所述缩短单元用于：
按照缩短优先级从高到低的顺序，对确定出的所述需要缩短的信息比特列中除缩短优先级最低的信息比特列外的其他信息比特列依次进行缩短；
从所述缩短优先级最低的信息比特列包含的N个子列中随机选择M个子列进行缩短，M为所述LDPC码校验矩阵需缩短的信息比特数除以N所得的余数，M为大于等于1的整数。
本发明实施例中提供的一个或多个技术方案，至少具有如下技术效果或 优点：
本发明实施例中，首先利用低密度校验LDPC码校验矩阵中的各个信息比特列对应的变量节点的总渐进环外信息度Total ACE和/或外信息和，生成缩短优先级图样，即按照缩短优先级从高到低依次排列的一列或多列信息比特列；然后根据LDPC码校验矩阵需缩短的信息比特数，利用缩短优先级图样确定出需要缩短的信息比特列；最后按照缩短优先级从高到低的顺序，对确定出的需要缩短的信息比特列依次进行缩短，得到生成的低密度校验码的信息比特列。
由于信息比特列的缩短优先级随信息比特列对应的变量节点的Total ACE的减小而提升，随信息比特列对应的变量节点的外信息和的增大而提升，所以本发明实施例利用信息比特列对应的变量节点的Total ACE和/或外信息和确定信息比特列的缩短优先级，改善了对LDPC码进行缩短后的性能，减少了因缩短而造成的性能损失。
附图说明
图1为12×24的校验矩阵示意图；
图2分别为27×27全零方阵的示意图、27×27单位阵的示意图以及
Figure PCTCN2015077122-appb-000005
的示意图；
图3为一个4×8的LDPC码校验矩阵H示意图；
图4为图3所示的4×8的LDPC码校验矩阵H的因子图；
图5为一个LDPC码校验矩阵中局部长度为6的环的示意图；
图6为变量节点度为4的变量节点的因子图的局部示意图；
图7为变量节点的VN3外信息和的示意图；
图8为本发明实施例提供的LDPC码生成方法的流程图；
图9为本发明实施例中利用Total ACE和外信息和生成缩短优先级图样的流程图；
图10为本发明实施例中利用变量节点度、Total ACE和外信息和生成缩 短优先级图样的流程图；
图11为码长是648比特且码率为1/2下本发明实施例提供的缩短方案与现有技术中的缩短方案的BLER性能对比图；
图12为码长是1296比特且码率为1/2下本发明实施例提供的缩短方案与现有技术中的缩短方案的BLER性能对比图；
图13为码长是1944比特且码率为1/2下本发明实施例提供的缩短方案与现有技术中的缩短方案的BLER性能对比图；
图14为本发明实施例提供的LDPC码生成装置的模块图；
图15为本发明实施例提供的LDPC码生成装置的硬件结构图。
具体实施方式
本发明实施例提供一种LDPC码生成方法及装置，用于改善对LDPC码进行缩短的缩短性能，减少性能损失。
本发明实施例中，首先利用低密度校验LDPC码校验矩阵中的各个信息比特列对应的变量节点的总渐进环外信息度Total ACE和/或外信息和，生成缩短优先级图样，即按照缩短优先级从高到低依次排列的一列或多列信息比特列；然后根据LDPC码校验矩阵需缩短的信息比特数，利用缩短优先级图样确定出需要缩短的信息比特列；最后按照缩短优先级从高到低的顺序，对确定出的需要缩短的信息比特列依次进行缩短，得到生成的低密度校验码的信息比特列。
由于信息比特列的缩短优先级随信息比特列对应的变量节点的Total ACE的减小而提升，随信息比特列对应的变量节点的外信息和的增大而提升，所以本发明实施例利用信息比特列对应的变量节点的Total ACE和/或外信息和确定信息比特列的缩短优先级，改善了对LDPC码进行缩短后的性能，减少了因缩短操作而造成的性能损失。
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述， 显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
下面结合附图对本发明的实施方式进行详细说明。
本发明实施例提供了一种LDPC(中文：低密度校验；英文：Low-density parity-check)码生成方法，适用于支持IEEE WLAN各种标准(如IEEE 802.11n/ac/ax等标准)的WiFi设备。
本发明实施例提供的LDPC码生成方法根据LDPC码的校验矩阵及其相应的因子图的具体结构：变量节点度、外信息和以及Total ACE，给出了判断LDPC码的校验矩阵中的各个信息比特列的缩短优先级的方法，按照各个信息比特列的缩短优先级，生成LDPC码的信息比特列。
下面首先分析变量节点度对信息比特列的缩短优先级的影响。
变量节点度是指：LDPC码的因子图中与变量节点相连的校验节点的数目，即：在LDPC码的校验矩阵中变量节点对应的信息比特列的列重(一个列的列重指该列中非零元素的个数)。
请参考图6，图6为变量节点度为4的变量节点的因子图的局部示意图。从图6中可以看出，与该变量节点相连的校验节点的数目为4。由于每个校验节点等效为一个校验方程，所以当变量节点的变量节点度越大时，迭代译码过程中该变量节点可收到来自其余校验方程的校验信息越多，该校验信息指LDPC码迭代译码过程中校验检点向变量节点传递的置信消息，从而令该变量节点正确译码的概率越大。因此，应优先缩短变量节点度更小的变量节点对应的信息比特列，而尽可能保留变量节点度更大的变量节点对应的信息比特列。
接下来分析外信息和对信息比特列的缩短优先级的影响。
LDPC码的因子图中变量节点j的外信息和的定义如下：
Figure PCTCN2015077122-appb-000006
其中，ηj＝{i:hi,j＝1且1≤i≤M}，hi,j为LDPC码的校验矩阵中的任一元素，M＝N-K，N为LDPC码的校验矩阵的总列数，K为LDPC码的校验矩阵中信息比特列的列数，即ηj为：变量节点j相连的校验节点，或变量节点j所参与的校验方程。ρ(i)表示与校验节点i所相连的变量节点的数目。因此，确定变量节点j的外信息和的步骤为：首先确定与变量节点j相连的校验节点的集合，然后对于集合中的每个校验节点，确定与校验节点相连的变量节点数目，最后将所有的数目相加即可得到变量节点j的外信息和。
LDPC迭代译码中校验节点i传递给变量节点j的信息为其余ρ(i)-1个校验节点的置信消息，如果ρ(i)-1越大，则变量节点j可收到更多的来自校验节点i的置信消息，从而使变量节点j在迭代译码过程中更易被正确译码，所以，变量节点j被正确译码的概率取决于：与变量节点j相连的所有校验节点i传来的置信消息的总数，也即变量节点j的外信息和。如果对变量节点j对应的信息比特列进行缩短，即将变量节点j对应的信息比特列用0比特与之对应，那么对其他变量节点来说，其他变量节点可接收到的来自校验节点的置信消息将会减少，进而导致其他变量节点被正确译码的概率下降。因此，为了避免缩短操作导致任何校验节点的度下降过于尖锐，应优先缩短外信息和更大的变量节点对应的信息比特列，而尽可能保留外信息和更小的变量节点对应的信息比特列。
接下来分析外信息和对变量节点度相同的变量节点对应的信息比特列的缩短优先级的影响。
请参考图7，图7为变量节点的VN3外信息和的示意图。从图7中可以看出，与变量节点VN3相连的校验节点有：CAN、CNB、CNC。因此，根据上述外信息和的定义，变量节点VN3的外信息和为： E(3)＝(ρ(A)-1)+(ρ(B)-1)+(ρ(C)-1)＝(3-1)+(2-1)+(2-1)＝4。同理，变量节点VN1的外信息和E(1)＝(ρ(A)-1)＝(3-1)＝2，变量节点VN2的外信息和E(2)＝(ρ(B)-1)＝(2-1)＝1，变量节点VN4的外信息和E(4)＝(ρ(A)-1)＝(3-1)＝2，变量节点VN5的外信息和E(5)＝(ρ(C)-1)＝(2-1)＝1。由于除变量节点VN3外的其余变量节点的外信息和均小于4，所以优先对变量节点VN3对应的信息比特列进行缩短。
从图7中还可以看出，与变量节点VN1相连的校验节点为：CNA，与变量节点VN2相连的校验节点为：CNB。因此，根据前述变量节点度的定义，变量节点VN1的变量节点度为1，变量节点VN2的变量节点度也为1，变量节点VN1与变量节点VN2的变量节点度相同，但是变量节点VN1的外信息和大于变量节点VN2的外信息和。因此，在这种情况下，优先对变量节点VN1进行缩短。
缩短操作是指将信息比特列中某一列用0比特与之对应，为了避免缩短操作导致任何校验节点的度下降过于尖锐，从而严重影响该校验节点在迭代译码中的信息传递，在缩短过程中对变量节点度相同的变量节点应优先缩短外信息和E(j)更大的变量节点。
接下来分析Total ACE对信息比特列的缩短优先级的影响。
对于LDPC码的因子图中的一个环ξ，定义参与该环的变量节点集合为Vj∈ξ，则该环的ACE为：
Figure PCTCN2015077122-appb-000007
其中，dj为环ξ中变量节点Vj的变量节点度。环ξ的ACE值表示该环在LDPC码的因子图中与余留部分的连接性，环ξ的ACE值越大，该环在迭代译码中可接收更多的来自该环之外的外部信息，从而令该环所包含的各个变量节点更易得到正确译码。如果环ξ的ACE值很小，则该环所包含的各个变量节点在迭代译码中将无法充分接收来自该环之外的外信息，从而不易得到 正确译码。
LDPC码的因子图中每个变量节点可能参与多个环，这些环的长度大小不同。对于变量节点Vj，所参与的环中长度最短的环有多个。假设变量节点Vj所参与的最短环的集合为ξ∈Vj，定义其Total ACE为：
Figure PCTCN2015077122-appb-000008
即TotalACEj为变量节点Vj所参与所有最短环的ACE值之和。在LDPC码的所有变量节点中，TotalACE值更大的变量节点在迭代译码中更易收到更多来自外部的置信信息，从而更易得到正确译码。而TotalACE值较小的变量节点相对而言不易得到正确译码。因此，应优先缩短TotalACE更小的变量节点对应的信息比特列，而尽可能保留TotalACE更大的变量节点对应的信息比特列。
由于变量节点度、外信息和以及Total ACE对信息比特列的缩短优先级有影响，所以本发明实施例提供的LDPC码缩短方法首先利用变量节点度、外信息和以及Total ACE三者中任一、任两种的组合或者三者的组合，确定各个信息比特列的缩短优先级，然后按照确定出的缩短优先级对信息比特列进行缩短。
请参考图8，图8为本发明实施例提供的LDPC码生成方法的流程图。本发明实施例提供的LDPC码生成方法包括以下步骤：
步骤81：利用低密度校验LDPC码校验矩阵中的各个信息比特列对应的变量节点的总渐进环外信息度Total ACE和/或外信息和，生成缩短优先级图样，所述缩短优先级图样包括按照缩短优先级从高到低依次排列的一列或多列信息比特列，
其中，所述信息比特列的缩短优先级随所述信息比特列对应的变量节点的Total ACE的减小而提升，随所述信息比特列对应的变量节点的外信息和的增大而提升；
步骤82：根据所述LDPC码校验矩阵需缩短的信息比特数，利用缩短优先级图样确定出需要缩短的信息比特列；
步骤83：按照缩短优先级从高到低的顺序，对确定出的所述需要缩短的 信息比特列依次进行缩短，得到生成的低密度校验码的信息比特列。
本发明实施例中，缩短优先级图样是指：按照缩短优先级从高到低的顺序依次排列的一列或多列信息比特列，例如：对于现有WLAN标准中所采用的码长N＝1944比特、码率R＝1/2的LDPC码，其校验矩阵H是由81×81的循环移位方阵组成。现有WLAN标准中的缩短优先级图样为：12、11，即进行缩短操作时优先缩短信息比特列中的第12列，然后缩短信息比特列中的第11列。
缩短优先级图样包含的信息比特列的列数可以等于LDPC码校验矩阵中信息比特列的总列数，由于WLAN标准中所采用的校验矩阵固定，所以可以利用本发明实施例提供的LDPC码缩短方法预先离线确定缩短优先级图样，无论需要缩短的信息比特列的列数是多少，都能够利用本发明实施例提供的缩短优先级图样，因此并不增加系统硬件复杂度，故本发明实施例提供的LDPC码缩短方案具有较强的竞争力。
当然，为了提高缩短操作的效率，缩短优先级图样包含的信息比特列的列数可以大于或等于需要缩短的信息比特列的列数。在具体实现过程中，首先确定需要缩短的信息比特列的列数是M列，然后确定包含N列信息比特列的缩短优先级图样，其中，N大于等于M，且N和M均为正整数。
本发明实施例中，步骤81的具体实施方式有以下三种：
第一种具体实施方式为：利用低密度校验LDPC码校验矩阵中的各个信息比特列对应的变量节点的总渐进环外信息度Total ACE，生成缩短优先级图样。
具体来讲，利用LDPC码校验矩阵中的各个信息比特列对应的变量节点的TotalACE衡量该变量节点所对应的信息比特列的缩短优先级。通过前述分析Total ACE对信息比特列的缩短优先级的影响，可以获知：信息比特列的缩短优先级随该信息比特列对应的变量节点的Total ACE的减小而提升，因此，应优先缩短TotalACE更小的变量节点对应的信息比特列，而尽可能保留TotalACE更大的变量节点对应的信息比特列。
第二种具体实施方式为：利用低密度校验LDPC码校验矩阵中的各个信息比特列对应的变量节点的外信息和，生成缩短优先级图样。
具体来讲，利用LDPC码校验矩阵中的各个信息比特列对应的变量节点的外信息和衡量该变量节点所对应的信息比特列的缩短优先级。通过前述分析外信息和对信息比特列的缩短优先级的影响，可以获知：信息比特列的缩短优先级随该信息比特列对应的变量节点的外信息和的增大而提升，因此，因此，应优先缩短外信息和更大的变量节点对应的信息比特列，而尽可能保留外信息和更小的变量节点对应的信息比特列。
第三种具体实施方式为：利用低密度校验LDPC码校验矩阵中的各个信息比特列对应的变量节点的总渐进环外信息度Total ACE和外信息和，生成缩短优先级图样，所述缩短优先级图样包括按照缩短优先级从高到低依次排列的一列或多列信息比特列，其中，所述信息比特列的缩短优先级随所述信息比特列对应的变量节点的Total ACE的减小而提升，随所述信息比特列对应的变量节点的外信息和的增大而提升。
具体来讲，利用LDPC码校验矩阵中的各个信息比特列对应的变量节点的Total ACE和外信息和衡量该变量节点所对应的信息比特列的缩短优先级。
本发明实施例中利用LDPC码校验矩阵中的各个信息比特列对应的变量节点的Total ACE和外信息和，生成缩短优先级图样，具体包括：
按照图9所示的步骤选择信息比特列存入所述缩短优先级图样，直至所述缩短优先级图样包含的信息比特列的列数不小于所述LDPC码校验矩阵需缩短的信息比特数对应的列数，其中，所述信息比特列的缩短优先级高低与所述信息比特列存入所述缩短优先级图样的先后顺序对应。
请参考图9，图9为本发明实施例中利用LDPC码校验矩阵中的各个信息比特列对应的变量节点的Total ACE和外信息和，生成缩短优先级图样的流程图，具体包括以下步骤：
步骤91：从所述LDPC码校验矩阵中的各个信息比特列中选择全部信息比特列存入第一集合；
步骤92：从所述第一集合中选择具有最大外信息和的变量节点对应的信息比特列存入第二集合；
步骤93：从所述第二集合中选择具有最小Total ACE的变量节点对应的信息比特列存入所述缩短优先级图样；
步骤94：若所述缩短优先级图样包含的信息比特列的列数不小于所述LDPC码校验矩阵需缩短的信息比特数对应的列数，则结束处理，得到最终的所述缩短优先级图样；否则
对所述LDPC码校验矩阵进行更新，并对更新后的LDPC码校验矩阵返回执行选择信息比特列存入第一集合的步骤。
其中，对所述LDPC码校验矩阵进行更新，包括：
在所述LDPC码校验矩阵中，对存入所述缩短优先级图样的信息比特列中的所有元素置0。具体来讲，假设存入缩短优先级图样的信息比特列为列c，则另hi,c＝0，其中，hi,c为LDPC码校验矩阵中列c的任一元素。
具体来讲，首先进行初始化。记LDPC码校验矩阵H中各个信息比特列的集合为第一集合P，对于第一集合P中的每一个信息比特列对应的变量节点j，首先计算并记录其外信息和E(j)以及TotalACEj，记该LDPC码校验矩阵需缩短的信息比特数对应的列数为SL；
接下来执行步骤a：从第一集合P中选择具有最大外信息和的变量节点对应的信息比特列存入第二集合G1；
然后执行步骤b：从第二集合G1中选择具有最小Total ACE的变量节点对应的信息比特列存入缩短优先级图样；
接着执行步骤c：判断当前缩短优先级图样包含的信息比特列的列数是否小于SL，如果不小于，则执行步骤d，如果小于，则执行步骤e；
步骤d：结束处理，将缩短优先级图样作为最终的缩短优先级图样；
步骤e：对LDPC码校验矩阵进行更新，并对更新后的LDPC码校验矩阵返回执行步骤a。
举例来讲，假设LDPC码校验矩阵H中各个信息比特列为：第1列至第8列，则第一集合P包括第1列至第8列。假设第1列至第8列的外信息和分别为：1、2、3、3、3、3、2、1。由于第一集合P中最大外信息和为3，且外信息和为3的信息比特列为：第3列至第6列，所以首先从第一集合P中选择第3列至第6列存入第二集合G1。
假设第3列至第6列的Total ACE分别为：1、1、3、4。由于第二集合G1中最小Total ACE为1，且Total ACE为1的信息比特列为第3列和第4列，所以将第3列和第4列存入缩短优先级图样。
如果LDPC码校验矩阵需缩短的信息比特数对应的列数为1列，而当前缩短优先级图样包含的信息比特列为2列，即第3列和第4列，则结束处理，将包含第3列信息比特列的缩短优先级图样作为最终的缩短优先级图样。
或者假设第3列至第6列的Total ACE分别为：1、2、3、4。由于第二集合G1中最小Total ACE为1，且Total ACE为1的信息比特列为第3列，所以将第3列存入缩短优先级图样。
如果LDPC码校验矩阵需缩短的信息比特数对应的列数为1列，而当前缩短优先级图样包含的信息比特列为1列，即第3列，则结束处理，将包含第3列信息比特列的缩短优先级图样作为最终的缩短优先级图样。
如果LDPC码校验矩阵需缩短的信息比特数对应的列数为3列，而当前缩短优先级图样包含的信息比特列为1列，即第3列，则对LDPC码校验矩阵进行更新，然后对更新后的LDPC码校验矩阵返回执行步骤a。
由于存入缩短优先级图样的信息比特列为第3列，所以对第3列进行更新，将第3列中的所有元素置0，第3列变为第3’列。则更新后的LDPC码校验矩阵中各个信息比特列为：第1列至第2列、第3’列、第4列至第8列，则第一集合P包括：第1列至第2列、第3’列、第4列至第8列。假设从第一集合P中选择具有最大外信息和的信息比特列，然后从具有最大外信息和的信息比特列中选择具有最小Total ACE的信息比特列为第4列，则将第4列存入 缩短优先级图样，此时，缩短优先级图样包含的信息比特列为：第3列和第4列，由于第3列先于第4列存入缩短优先级图样，所以第3列的缩短优先级高于第4列的缩短优先级。
如果LDPC码校验矩阵需缩短的信息比特数对应的列数为2列，而当前缩短优先级图样包含的信息比特列为2列，即第3列和第4列，则结束处理，将包含第3列信息比特列和第4列信息比特列的缩短优先级图样作为最终的缩短优先级图样。
本发明实施例中，还可以利用LDPC码校验矩阵中的各个信息比特列对应的变量节点的变量节点度、Total ACE和外信息和衡量该变量节点所对应的信息比特列的缩短优先级。
本发明实施例中利用LDPC码校验矩阵中的各个信息比特列对应的变量节点的变量节点度、Total ACE和外信息和，生成缩短优先级图样，具体包括：
按照图10所示的步骤选择信息比特列存入所述缩短优先级图样，直至所述缩短优先级图样包含的信息比特列的列数不小于所述LDPC码校验矩阵需缩短的信息比特数对应的列数，其中，所述信息比特列的缩短优先级高低与所述信息比特列存入所述缩短优先级图样的先后顺序对应。
请参考图10，图10为本发明实施例中利用LDPC码校验矩阵中的各个信息比特列对应的变量节点的变量节点度、Total ACE和外信息和，生成缩短优先级图样的流程图，具体包括以下步骤：
步骤101：从所述LDPC码校验矩阵中的各个信息比特列中选择部分信息比特列存入第一集合，即：从所述LDPC码校验矩阵中的各个信息比特列中选择具有最小变量节点度的变量节点对应的信息比特列存入所述第一集合；
步骤102：从所述第一集合中选择具有最大外信息和的变量节点对应的信息比特列存入第二集合；
步骤103：从所述第二集合中选择具有最小Total ACE的变量节点对应的信息比特列存入所述缩短优先级图样；
步骤104：若所述缩短优先级图样包含的信息比特列的列数不小于所述 LDPC码校验矩阵需缩短的信息比特数对应的列数，则结束处理，得到最终的所述缩短优先级图样；否则
对所述LDPC码校验矩阵进行更新，并对更新后的LDPC码校验矩阵返回执行选择信息比特列存入第一集合的步骤。
具体来讲，首先进行初始化。记LDPC码校验矩阵H中各个信息比特列的集合为第零集合Q，对于第零集合Q中的每一个信息比特列对应的变量节点j，首先计算并记录其变量节点度dj、外信息和E(j)以及TotalACEj，记该LDPC码校验矩阵需缩短的信息比特数对应的列数为SL；
然后执行步骤Z：从第零集合Q中选择具有最小变量节点度的变量节点对应的信息比特列存入第一集合P；
接下来执行步骤A：从第一集合P中选择具有最大外信息和的变量节点对应的信息比特列存入第二集合G1；
然后执行步骤B：从第二集合G1中选择具有最小Total ACE的变量节点对应的信息比特列存入缩短优先级图样；
接着执行步骤C：判断当前缩短优先级图样包含的信息比特列的列数是否小于SL，如果不小于，则执行步骤D，如果小于，则执行步骤E；
步骤D：结束处理，将缩短优先级图样作为最终的缩短优先级图样；
步骤E：对LDPC码校验矩阵进行更新，并对更新后的LDPC码校验矩阵返回执行步骤Z。
如前述，对所述LDPC码校验矩阵进行更新，包括：
在所述LDPC码校验矩阵中，对存入所述缩短优先级图样的信息比特列中的所有元素置0。具体来讲，假设存入缩短优先级图样的信息比特列为列c，则另hi,c＝0，其中，hi,c为LDPC码校验矩阵中列c的任一元素。
举例来讲，假设LDPC码校验矩阵H中各个信息比特列为：第1列至第10列，则第零集合Q包括第1列至第10列。假设第1列至第10列的变量节点度分别为：1、1、1、1、1、1、1、1、2、3。由于第零集合Q中最小变量节 点度为1，且变量节点度为1的信息比特列为第1列至第8列，所以首先从第零集合Q中选择第1列至第8列存入第一集合P。假设第1列至第8列的外信息和分别为：1、2、3、3、3、3、2、1。由于第一集合P中最大外信息和为3，且外信息和为3的信息比特列为：第3列至第6列，所以首先从第一集合P中选择第3列至第6列存入第二集合G1。
假设第1列至第4列的外信息和分别为：1、2、3、3、3、3、2、1。由于第一集合P中最大外信息和为3，且外信息和为3的信息比特列为：第3列至第6列，所以首先从第一集合P中选择第3列至第6列存入第二集合G1。
假设第3列至第6列的Total ACE分别为：1、1、3、4。由于第二集合G1中最小Total ACE为1，且Total ACE为1的信息比特列为第3列和第4列，所以将第3列和第4列存入缩短优先级图样。
如果LDPC码校验矩阵需缩短的信息比特数对应的列数为1列，而当前缩短优先级图样包含的信息比特列为2列，即第3列和第4列，则结束处理，将包含第3列信息比特列的缩短优先级图样作为最终的缩短优先级图样。
或者假设第3列至第6列的Total ACE分别为：1、2、3、4。由于第二集合G1中最小Total ACE为1，且Total ACE为1的信息比特列为第3列，所以将第3列存入缩短优先级图样。
如果LDPC码校验矩阵需缩短的信息比特数对应的列数为1列，而当前缩短优先级图样包含的信息比特列为1列，即第3列，则结束处理，将包含第3列信息比特列的缩短优先级图样作为最终的缩短优先级图样。
如果LDPC码校验矩阵需缩短的信息比特数对应的列数为3列，而当前缩短优先级图样包含的信息比特列为1列，即第3列，则对LDPC码校验矩阵进行更新，然后对更新后的LDPC码校验矩阵返回执行步骤a。
由于存入缩短优先级图样的信息比特列为第3列，所以对第3列进行更新，将第3列中的所有元素置0，第3列变为第3’列。则更新后的LDPC码校验矩阵中各个信息比特列为：第1列至第2列、第3’列、第4列至第10列， 则第零集合Q包括：第1列至第2列、第3’列、第4列至第10列。假设从第零集合Q中选择具有最小变量节点度的信息比特列，然后从具有最小变量节点度的信息比特列中选择具有最大外信息和的信息比特列，最后从具有最大外信息和的信息比特列中选择具有最小Total ACE的信息比特列为第4列，则将第4列存入缩短优先级图样，此时，缩短优先级图样包含的信息比特列为：第3列和第4列，由于第3列先于第4列存入缩短优先级图样，所以第3列的缩短优先级高于第4列的缩短优先级。
如果LDPC码校验矩阵需缩短的信息比特数对应的列数为2列，而当前缩短优先级图样包含的信息比特列为2列，即第3列和第4列，则结束处理，将包含第3列信息比特列和第4列信息比特列的缩短优先级图样作为最终的缩短优先级图样。
对于WLAN标准所采用的如图1和图2所示的准循环LDPC码，缩短优先级图样的生成可直接对如图1所示的母矩阵进行搜索即可。母矩阵指如图1所示的未经循环扩展其子矩阵的LDPC码校验矩阵，其中母矩阵中每一个元素代表一个子矩阵。WLAN现有标准IEEE 802.11n/ac针对LDPC码定义了3种码长：648比特、1296比特、1944比特和4种码率：1/2、2/3、3/4、5/6，每种码长和码率下均定义了一个LDPC码校验矩阵，因此总共包含12个校验矩阵。按照如图10所示的利用LDPC码校验矩阵中的各个信息比特列对应的变量节点的变量节点度、Total ACE和外信息和，生成缩短优先级图样的方法，可以得到这12个校验矩阵母矩阵的缩短优先级图样，缩短优先级图样中包含各个信息比特列，每个缩短优先级图样中的信息比特列的缩短优先级从左向右逐步降低：
1)码长为648比特且码率为1/2的校验母矩阵的缩短优先级图样为：7→6→11→10→2→3→12→8→4→9→5→1；
2)码长为648比特且码率为2/3的校验母矩阵的缩短优先级图样为：11→10→15→14→16→13→12→5→8→7→6→9→4→1→2→3；
3)码长为648比特且码率为3/4的校验母矩阵的缩短优先级图样为：13 →12→15→14→18→17→16→11→10→6→9→8→7→2→1→5→3→4；
4)码长为648比特且码率为5/6的校验母矩阵的缩短优先级图样为：13→19→12→16→4→14→20→2→7→5→6→9→17→1→11→3→10→15→18→8；
5)码长为1296比特且码率为1/2的校验母矩阵的缩短优先级图样为：7→6→4→3→8→11→12→10→2→1→9→5；
6)码长为1926比特且码率为2/3的校验母矩阵的缩短优先级图样为：6→8→7→10→14→9→13→16→11→15→12→5→4→3→1→2；
7)码长为1926比特且码率为3/4的校验母矩阵的缩短优先级图样为：8→9→10→17→12→15→18→13→14→11→16→2→7→5→3→1→4→6；
8)码长为1926比特且码率为5/6的校验母矩阵的缩短优先级图样为：19→18→20→17→7→11→9→1→16→8→5→3→2→13→15→10→12→4→14→6；
9)码长为1944比特且码率为1/2的校验母矩阵的缩短优先级图样为：3→4→7→6→8→10→11→12→2→1→9→5；
10)码长为1944比特且码率为2/3的校验母矩阵的缩短优先级图样为：13→12→9→15→10→6→14→8→7→16→11→5→3→1→2→4；
11)码长为1944比特且码率为3/4的校验母矩阵的缩短优先级图样为：9→16→17→14→18→8→10→13→12→15→7→11→4→5→3→2→6→1；
12)码长为1944比特且码率为5/6的校验母矩阵的缩短优先级图样为：18→12→17→20→16→14→15→13→11→19→2→10→9→6→8→1→4→7→3→5。
在执行完步骤81，生成缩短优先级图样后，执行步骤82和步骤83。在执行步骤82之前，首先要确定所述LDPC码校验矩阵需缩短的信息比特数。例如：当前需要缩短的比特数目为54个、108个、216个、162个、324个等。然后执行步骤82，根据所述LDPC码校验矩阵需缩短的信息比特数，利用缩短优先级图样确定出需要缩短的信息比特列。
具体来讲，对于WLAN标准中所采用的码长N＝648比特、码率R＝1/2的LDPC码，其校验矩阵H是由27×27的循环移位方阵组成。假设当前需要缩短的比特数目为54个，此时对应需缩短母矩阵中2列信息比特列；而当需要缩短的比特数目为108个时，需对母矩阵中4列信息比特列进行缩短。对于 WLAN标准中所采用的码长N＝1296比特、码率R＝1/2的LDPC码，其校验矩阵H是由54×54的循环移位方阵组成。假设当前需要缩短的比特数目为108个，此时对应需缩短母矩阵中2列信息比特列；而当需要缩短的比特数目为216个时，需对母矩阵中4列信息比特列进行缩短。对于WLAN标准中所采用的码长N＝1944比特、码率R＝1/2的LDPC码，其校验矩阵H是由81×81的循环移位方阵组成。假设当前需要缩短的比特数目为162个，此时对应需缩短母矩阵中2列信息比特列；而当需要缩短的比特数目为324个时，需对母矩阵中4列信息比特列进行缩短。
由于码长为648比特且码率为1/2的校验母矩阵的缩短优先级图样为：7→6→11→10→2→3→12→8→4→9→5→1，所以当需要缩短2列信息比特列时，确定出需要缩短的信息比特列为第7列和第6列，当需要缩短4列信息比特列时，确定出需要缩短的信息比特列为第7列、第6列、第11列和第12列。
最后执行步骤83，按照缩短优先级从高到低的顺序，对确定出的需要缩短的信息比特列依次进行缩短，得到生成的LDPC码的信息比特列。例如：确定出需要缩短的信息比特列为第7列和第6列，且第7列的缩短优先级高于第6列的缩短优先级，则首先对第7列进行缩短，然后对第6列进行缩短，进而，得到生成的LDPC码的信息比特列。
本发明实施例中，对LDPC码的校验矩阵包含的各个信息比特列来说，每个信息比特列包含N个子列，N为大于等于1的整数。例如：对于WLAN标准中所采用的码长N＝648比特、码率R＝1/2的LDPC码，其校验矩阵H是由27×27的循环移位方阵组成，则每个信息比特列包含27个子列。对于WLAN标准中所采用的码长N＝1296比特、码率R＝1/2的LDPC码，其校验矩阵H是由54×54的循环移位方阵组成，则每个信息比特列包含54个子列。对于WLAN标准中所采用的码长N＝1944比特、码率R＝1/2的LDPC码，其校验矩阵H是由81×81的循环移位方阵组成，则每个信息比特列包含81个子列。
当所述LDPC码校验矩阵需缩短的信息比特数不为N的整数倍时，步骤 81中的按照缩短优先级从高到低的顺序，对确定出的所述需要缩短的信息比特列依次进行缩短，包括：
按照缩短优先级从高到低的顺序，对确定出的所述需要缩短的信息比特列中除缩短优先级最低的信息比特列外的其他信息比特列依次进行缩短；
从所述缩短优先级最低的信息比特列包含的N个子列中随机选择M个子列进行缩短，M为所述LDPC码校验矩阵需缩短的信息比特数除以N所得的余数，M为大于等于1的整数。
具体来讲，LDPC码的校验矩阵包含的各个信息比特列中每个信息比特列包含N个子列，因为WLAN标准所采用的如图1和图2所示的准循环LDPC码，所以N个子列的变量节点度、外信息和以及Total ACE均相同。因此，该N个子列的缩短优先级相同。当需要对一个信息比特列中的M个子列进行缩短时，可以从该信息比特列包含的N个子列中随机选择M个子列进行缩短。
举例来讲，对于WLAN标准中所采用的码长N＝648比特、码率R＝1/2的LDPC码，其校验矩阵H是由27×27的循环移位方阵组成，每个信息比特列包含27个子列。假设当前需要缩短的比特数目为30个，此时对应需缩短母矩阵中1整列信息比特列和1个信息比特列中的3个子列，根据码长为648比特且码率为1/2的校验母矩阵的缩短优先级图样：7→6→11→10→2→3→12→8→4→9→5→1，确定出需要缩短的信息比特列为第7列和第6列，且第7列的缩短优先级高于第6列的缩短优先级，则首先对第7列进行缩短，在对第7列整列缩短之后，从第6列包含的27个子列中随机选择3个子列进行缩短。
表1 码长为648比特且码率为1/2下缩短优先级图样对比
Figure PCTCN2015077122-appb-000009
表2 码长为1296比特且码率为1/2下缩短优先级图样对比
Figure PCTCN2015077122-appb-000010
表3 码长为1944比特且码率为1/2下缩短优先级图样对比
Figure PCTCN2015077122-appb-000011
在需要缩短2列信息比特列和需要缩短4列信息比特列的情况下，本发明实施例提供的缩短优先级图样和现有技术中的缩短优先级图样对比可以参考表1、表2及表3。其中，表1列出了码长为648比特且码率为1/2下缩短优先级图样对比，表2列出了码长为1296比特且码率为1/2下缩短优先级图样对比，表3列出了码长为1944比特且码率为1/2下缩短优先级图样对比。
从表1、表2和表3中可以看出，现有技术中的缩短优先级图样为直接对信息比特列从后往前进行缩短，而发明实施例提供的缩短优先级图样为优化方案。对比表1和表2可知，对于码长N＝1296比特、码率R＝1/2的LDPC码的校验矩阵，当需要缩短4列信息比特列时，本发明实施例提供的缩短优先级图样为：7→6→4→3，而对于码长N＝648比特、码率R＝1/2的LDPC码的校验矩阵，当需要缩短4列信息比特列时，本发明实施例提供的缩短优先级图样为：7→6→11→10。可见，对于不同的校验矩阵，当需要缩短相同列数的信息比特列时，本发明实施例提供的缩短优先级图样不同。
在采用信道为AWGN(中文：加性高斯白噪声；英文：Additive White Gaussian Noise)信道、调制方式为BPSK(中文：二进制监控移相；英文：Binary Phase Shift Keying)、译码算法为LLR-BP算法、译码迭代次数为20次的情况下，对本发明实施例提供的缩短方案与现有技术中的缩短方案的BLER(中文：误块率；英文：Block Error Rate)性能分别进行了仿真。请参考图11、 图12和图13，图11为码长是648比特且码率为1/2下本发明实施例提供的缩短方案与现有技术中的缩短方案的BLER性能对比图，图12为码长是1296比特且码率为1/2下本发明实施例提供的缩短方案与现有技术中的缩短方案的BLER性能对比图，图13为码长是1944比特且码率为1/2下本发明实施例提供的缩短方案与现有技术中的缩短方案的BLER性能对比图。图11、图12和图13中，横坐标为Eb/No，即信号功率与噪声功率之比，单位为分贝(即dB)，纵坐标为BLER。
从图11、图12和图13中可以看出，本发明实施例提供的缩短方案在各种码长和码率下均具有优于现有技术中的缩短方案的性能。而在需缩短的信息比特列的列数较多时，本发明实施例提供的LDPC码生成方案的性能优势尤为明显。现有WLAN在短包业务时需要进行大量的缩短操作，因此本发明在WLAN短包业务时优势明显。同时，由于WLAN标准中所采用的校验矩阵固定，所以可以利用本发明实施例提供的LDPC码缩短方法预先离线确定缩短优先级图样，并不增加系统硬件复杂度，故本发明实施例提供的LDPC码生成方案具有较强的竞争力。
基于同一发明构思，本发明另一实施例中提供一种低密度校验码生成装置，请参考图14，图14为低密度校验码生成装置的模块图。图14所示的低密度校验码生成装置涉及到的术语的含义以及具体实现，可以参考前述图1至图13以及实施例的相关描述。低密度校验码生成装置包括：
生成单元1，用于利用低密度校验LDPC码校验矩阵中的各个信息比特列对应的变量节点的总渐进环外信息度Total ACE和/或外信息和，生成缩短优先级图样，所述缩短优先级图样包括按照缩短优先级从高到低依次排列的一列或多列信息比特列，
其中，所述信息比特列的缩短优先级随所述信息比特列对应的变量节点的Total ACE的减小而提升，随所述信息比特列对应的变量节点的外信息和的增大而提升；
处理单元2，用于根据所述LDPC码校验矩阵需缩短的信息比特数，利用缩短优先级图样确定出需要缩短的信息比特列；
缩短单元3，用于按照缩短优先级从高到低的顺序，对确定出的所述需要缩短的信息比特列依次进行缩短，得到生成的低密度校验码的信息比特列。
可选的，所述生成单元1包括：
按照以下步骤选择信息比特列存入所述缩短优先级图样，直至所述缩短优先级图样包含的信息比特列的列数不小于所述LDPC码校验矩阵需缩短的信息比特数对应的列数，其中，所述信息比特列的缩短优先级高低与所述信息比特列存入所述缩短优先级图样的先后顺序对应：
第一选择模块，用于从所述LDPC码校验矩阵中的各个信息比特列中选择全部信息比特列或者部分信息比特列存入第一集合；
第二选择模块，用于从所述第一集合中选择具有最大外信息和的变量节点对应的信息比特列存入第二集合；
第三选择模块，用于从所述第二集合中选择具有最小Total ACE的变量节点对应的信息比特列存入所述缩短优先级图样；
处理模块，用于若所述缩短优先级图样包含的信息比特列的列数不小于所述LDPC码校验矩阵需缩短的信息比特数对应的列数，则结束处理，得到最终的所述缩短优先级图样；否则
更新模块，用于对所述LDPC码校验矩阵进行更新，并对更新后的LDPC码校验矩阵返回执行选择信息比特列存入第一集合的步骤。
可选的，所述第一选择模块用于：
从所述LDPC码校验矩阵中的各个信息比特列中选择具有最小变量节点度的变量节点对应的信息比特列存入所述第一集合。
可选的，所述更新模块用于：
在所述LDPC码校验矩阵中，对存入所述缩短优先级图样的信息比特列中的所有元素置0。
可选的，所述信息比特列包含N个子列，N为大于等于1的整数；
当所述LDPC码校验矩阵需缩短的信息比特数不为N的整数倍时，所述缩短单元3用于：
按照缩短优先级从高到低的顺序，对确定出的所述需要缩短的信息比特列中除缩短优先级最低的信息比特列外的其他信息比特列依次进行缩短；
从所述缩短优先级最低的信息比特列包含的N个子列中随机选择M个子列进行缩短，M为所述LDPC码校验矩阵需缩短的信息比特数除以N所得的余数，M为大于等于1的整数。
前述图8实施例中的低密度校验码生成方法中的各种变化方式和具体实例同样适用于本实施例的低密度校验码生成装置，通过前述对低密度校验码生成方法的详细描述，本领域技术人员可以清楚的知道本实施例中低密度校验码生成装置的实施方法，所以为了说明书的简洁，在此不再详述。
请参考图15，图15为本实施例中低密度校验码生成装置的硬件结构示意图。低密度校验码生成装置包括：处理器01，用于利用低密度校验LDPC码校验矩阵中的各个信息比特列对应的变量节点的总渐进环外信息度Total ACE和/或外信息和，生成缩短优先级图样，所述缩短优先级图样包括按照缩短优先级从高到低依次排列的一列或多列信息比特列，
其中，所述信息比特列的缩短优先级随所述信息比特列对应的变量节点的Total ACE的减小而提升，随所述信息比特列对应的变量节点的外信息和的增大而提升；根据所述LDPC码校验矩阵需缩短的信息比特数，利用缩短优先级图样确定出需要缩短的信息比特列；
按照缩短优先级从高到低的顺序，对确定出的所述需要缩短的信息比特列依次进行缩短，得到生成的低密度校验码的信息比特列。
可选的，所述处理器01用于：
按照以下步骤选择信息比特列存入所述缩短优先级图样，直至所述缩短优先级图样包含的信息比特列的列数不小于所述LDPC码校验矩阵需缩短的信息比特数对应的列数，其中，所述信息比特列的缩短优先级高低与所述信息比特列存入所述缩短优先级图样的先后顺序对应：
从所述LDPC码校验矩阵中的各个信息比特列中选择全部信息比特列或者部分信息比特列存入第一集合；
从所述第一集合中选择具有最大外信息和的变量节点对应的信息比特列存入第二集合；
从所述第二集合中选择具有最小Total ACE的变量节点对应的信息比特列存入所述缩短优先级图样；
若所述缩短优先级图样包含的信息比特列的列数不小于所述LDPC码校验矩阵需缩短的信息比特数对应的列数，则结束处理，得到最终的所述缩短优先级图样；否则
对所述LDPC码校验矩阵进行更新，并对更新后的LDPC码校验矩阵返回执行选择信息比特列存入第一集合的步骤。
可选的，所述处理器01用于：
从所述LDPC码校验矩阵中的各个信息比特列中选择具有最小变量节点度的变量节点对应的信息比特列存入所述第一集合。
可选的，所述处理器01用于：
在所述LDPC码校验矩阵中，对存入所述缩短优先级图样的信息比特列中的所有元素置0。
可选的，所述信息比特列包含N个子列，N为大于等于1的整数；
当所述LDPC码校验矩阵需缩短的信息比特数不为N的整数倍时，所述处理器01用于：
按照缩短优先级从高到低的顺序，对确定出的所述需要缩短的信息比特列中除缩短优先级最低的信息比特列外的其他信息比特列依次进行缩短；
从所述缩短优先级最低的信息比特列包含的N个子列中随机选择M个子列进行缩短，M为所述LDPC码校验矩阵需缩短的信息比特数除以N所得的余数，M为大于等于1的整数。
其中，在图15中，总线架构(用总线00来代表)，总线00可以包括任意数量的互联的总线和桥，总线00将包括由处理器01代表的一个或多个处理器和存储器02代表的存储器的各种电路连接在一起。总线00还可以将诸如外围设备、稳压器和功率管理电路等之类的各种其他电路连接在一起，这 些都是本领域所公知的，因此，本文不再对其进行进一步描述。
处理器01负责管理总线00和通常的处理，而存储器02可以被用于存储处理器01在执行操作时所使用的数据。
前述图8实施例中的低密度校验码生成方法中的各种变化方式和具体实例同样适用于本实施例的低密度校验码生成装置，通过前述对低密度校验码生成方法的详细描述，本领域技术人员可以清楚的知道本实施例中低密度校验码生成装置的实施方法，所以为了说明书的简洁，在此不再详述。
本发明实施例中提供的一个或多个技术方案，至少具有如下技术效果或优点：
本发明实施例中，首先利用低密度校验LDPC码校验矩阵中的各个信息比特列对应的变量节点的总渐进环外信息度Total ACE和/或外信息和，生成缩短优先级图样，即按照缩短优先级从高到低依次排列的一列或多列信息比特列；然后根据LDPC码校验矩阵需缩短的信息比特数，利用缩短优先级图样确定出需要缩短的信息比特列；最后按照缩短优先级从高到低的顺序，对确定出的需要缩短的信息比特列依次进行缩短，得到生成的低密度校验码的信息比特列。
由于信息比特列的缩短优先级随信息比特列对应的变量节点的Total ACE的减小而提升，随信息比特列对应的变量节点的外信息和的增大而提升，所以本发明实施例利用信息比特列对应的变量节点的Total ACE和/或外信息和确定信息比特列的缩短优先级，改善了对LDPC码进行缩短后的性能，减少了因缩短而造成的性能损失。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产 品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (10)

  1. 一种低密度校验码生成方法，其特征在于，包括：
    利用低密度校验LDPC码校验矩阵中的各个信息比特列对应的变量节点的总渐进环外信息度Total ACE和/或外信息和，生成缩短优先级图样，所述缩短优先级图样包括按照缩短优先级从高到低依次排列的一列或多列信息比特列，
    其中，所述信息比特列的缩短优先级随所述信息比特列对应的变量节点的Total ACE的减小而提升，随所述信息比特列对应的变量节点的外信息和的增大而提升；
    根据所述LDPC码校验矩阵需缩短的信息比特数，利用缩短优先级图样确定出需要缩短的信息比特列；
    按照缩短优先级从高到低的顺序，对确定出的所述需要缩短的信息比特列依次进行缩短，得到生成的低密度校验码的信息比特列。
  2. 如权利要求1所述的方法，其特征在于，所述利用LDPC码校验矩阵中的各个信息比特列对应的变量节点的Total ACE和外信息和，生成缩短优先级图样，包括：
    按照以下步骤选择信息比特列存入所述缩短优先级图样，直至所述缩短优先级图样包含的信息比特列的列数不小于所述LDPC码校验矩阵需缩短的信息比特数对应的列数，其中，所述信息比特列的缩短优先级高低与所述信息比特列存入所述缩短优先级图样的先后顺序对应：
    从所述LDPC码校验矩阵中的各个信息比特列中选择全部信息比特列或者部分信息比特列存入第一集合；
    从所述第一集合中选择具有最大外信息和的变量节点对应的信息比特列存入第二集合；
    从所述第二集合中选择具有最小Total ACE的变量节点对应的信息比特列存入所述缩短优先级图样；
    若所述缩短优先级图样包含的信息比特列的列数不小于所述LDPC码校验矩阵需缩短的信息比特数对应的列数，则结束处理，得到最终的所述缩短优先级图样；否则
    对所述LDPC码校验矩阵进行更新，并对更新后的LDPC码校验矩阵返回执行选择信息比特列存入第一集合的步骤。
  3. 如权利要求2所述的方法，其特征在于，所述从所述LDPC码校验矩阵中的各个信息比特列中选择部分信息比特列存入第一集合，包括：
    从所述LDPC码校验矩阵中的各个信息比特列中选择具有最小变量节点度的变量节点对应的信息比特列存入所述第一集合。
  4. 如权利要求2或3所述的方法，其特征在于，所述对所述LDPC码校验矩阵进行更新，包括：
    在所述LDPC码校验矩阵中，对存入所述缩短优先级图样的信息比特列中的所有元素置0。
  5. 如权利要求4所述的方法，其特征在于，所述信息比特列包含N个子列，N为大于等于1的整数；
    当所述LDPC码校验矩阵需缩短的信息比特数不为N的整数倍时，所述按照缩短优先级从高到低的顺序，对确定出的所述需要缩短的信息比特列依次进行缩短，包括：
    按照缩短优先级从高到低的顺序，对确定出的所述需要缩短的信息比特列中除缩短优先级最低的信息比特列外的其他信息比特列依次进行缩短；
    从所述缩短优先级最低的信息比特列包含的N个子列中随机选择M个子列进行缩短，M为所述LDPC码校验矩阵需缩短的信息比特数除以N所得的余数，M为大于等于1的整数。
  6. 一种低密度校验码生成装置，其特征在于，包括：
    生成单元，用于利用低密度校验LDPC码校验矩阵中的各个信息比特列对应的变量节点的总渐进环外信息度Total ACE和/或外信息和，生成缩短优先级图样，所述缩短优先级图样包括按照缩短优先级从高到低依次排列的一 列或多列信息比特列，
    其中，所述信息比特列的缩短优先级随所述信息比特列对应的变量节点的Total ACE的减小而提升，随所述信息比特列对应的变量节点的外信息和的增大而提升；
    处理单元，用于根据所述LDPC码校验矩阵需缩短的信息比特数，利用缩短优先级图样确定出需要缩短的信息比特列；
    缩短单元，用于按照缩短优先级从高到低的顺序，对确定出的所述需要缩短的信息比特列依次进行缩短，得到生成的低密度校验码的信息比特列。
  7. 如权利要求6所述的装置，其特征在于，所述生成单元包括：
    按照以下步骤选择信息比特列存入所述缩短优先级图样，直至所述缩短优先级图样包含的信息比特列的列数不小于所述LDPC码校验矩阵需缩短的信息比特数对应的列数，其中，所述信息比特列的缩短优先级高低与所述信息比特列存入所述缩短优先级图样的先后顺序对应：
    第一选择模块，用于从所述LDPC码校验矩阵中的各个信息比特列中选择全部信息比特列或者部分信息比特列存入第一集合；
    第二选择模块，用于从所述第一集合中选择具有最大外信息和的变量节点对应的信息比特列存入第二集合；
    第三选择模块，用于从所述第二集合中选择具有最小Total ACE的变量节点对应的信息比特列存入所述缩短优先级图样；
    处理模块，用于若所述缩短优先级图样包含的信息比特列的列数不小于所述LDPC码校验矩阵需缩短的信息比特数对应的列数，则结束处理，得到最终的所述缩短优先级图样；否则
    更新模块，用于对所述LDPC码校验矩阵进行更新，并对更新后的LDPC码校验矩阵返回执行选择信息比特列存入第一集合的步骤。
  8. 如权利要求7所述的装置，其特征在于，所述第一选择模块用于：
    从所述LDPC码校验矩阵中的各个信息比特列中选择具有最小变量节点度的变量节点对应的信息比特列存入所述第一集合。
  9. 如权利要求7或8所述的装置，其特征在于，所述更新模块用于：
    在所述LDPC码校验矩阵中，对存入所述缩短优先级图样的信息比特列中的所有元素置0。
  10. 如权利要求9所述的装置，其特征在于，所述信息比特列包含N个子列，N为大于等于1的整数；
    当所述LDPC码校验矩阵需缩短的信息比特数不为N的整数倍时，所述缩短单元用于：
    按照缩短优先级从高到低的顺序，对确定出的所述需要缩短的信息比特列中除缩短优先级最低的信息比特列外的其他信息比特列依次进行缩短；
    从所述缩短优先级最低的信息比特列包含的N个子列中随机选择M个子列进行缩短，M为所述LDPC码校验矩阵需缩短的信息比特数除以N所得的余数，M为大于等于1的整数。
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