WO2018010581A1 - Power device and preparation method therefor - Google Patents

Power device and preparation method therefor Download PDF

Info

Publication number
WO2018010581A1
WO2018010581A1 PCT/CN2017/091823 CN2017091823W WO2018010581A1 WO 2018010581 A1 WO2018010581 A1 WO 2018010581A1 CN 2017091823 W CN2017091823 W CN 2017091823W WO 2018010581 A1 WO2018010581 A1 WO 2018010581A1
Authority
WO
WIPO (PCT)
Prior art keywords
trench
region
trenches
source
metal
Prior art date
Application number
PCT/CN2017/091823
Other languages
French (fr)
Chinese (zh)
Inventor
王培林
Original Assignee
王培林
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 王培林 filed Critical 王培林
Priority to GB1901361.4A priority Critical patent/GB2566895B/en
Publication of WO2018010581A1 publication Critical patent/WO2018010581A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7815—Vertical DMOS transistors, i.e. VDMOS transistors with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0865—Disposition

Definitions

  • the present disclosure relates to the field of semiconductors, and more particularly to power devices and methods of making same.
  • a scaling factor according to the amount of current in the main device this coefficient is generally expressed in CSR.
  • the current amount of current conducted by the device is measured at full scale to ensure the safety of the device. Reliable, for example in the field of automotive electronics.
  • a current sensor device such as a mirrored current device, can be selected throughout the device (referred to as the master device) to provide such measurements. The coupling and isolation of the current sensor device from the main device is very important.
  • a power device including: a first device having a plurality of first source regions and having a plurality of first trenches, wherein the plurality of first trenches are plurality of The first source regions are electrically isolated from each other; at least one second device having a plurality of second source regions and having a plurality of second trenches, the plurality of second trenches electrically isolating the plurality of second source regions from each other, Wherein the second device is embedded in the first device, and the second trench of the second device is in communication with the corresponding first trench of the first device, wherein the second source region of the second device is The first source region is electrically isolated by a metal pitch region, and wherein portions of the first device and the second device except the trench are active regions.
  • a method of fabricating a power device includes: providing a substrate; forming a body region of the first device and a body region of the at least one second device on the substrate; and a body region of the first device Forming a plurality of first trenches for the first device, and forming a plurality of second trenches for the second device in the body region of the second device, wherein the second trenches of the second device are first Corresponding first trenches of the device are in communication; forming a plurality of first source regions for the first device and for the second device a plurality of second source regions, wherein the plurality of first source regions are electrically isolated from each other by the plurality of first trenches, and the plurality of second source regions are electrically isolated from each other by the plurality of second trenches; wherein The second source region of the second device is electrically isolated from the first source region of the first device by a metal pitch region, and wherein the portions of the first device and the second device except the trench are
  • the first device and the second device are coupled and isolated in a unique manner, and since the portion of the second device embedded with the first device has no additional high concentration diffusion region (ie, no The source region), the embedding of the second device is smooth and does not cause structural changes to the first device, and thus does not adversely affect the current-voltage performance of the first device.
  • the second device since the second device is embedded in the portion of the first device, since there is no source region, this portion can still contribute to the current supply, so that there is no waste of any chip area.
  • FIG. 1 is a simplified plan view showing a power device in accordance with an exemplary embodiment of the present disclosure
  • FIG. 2 is a plan view showing details of a power device in accordance with an exemplary embodiment of the present disclosure
  • 3 to 5 respectively show cross-sectional views along A-A, B-B, and C-C in FIG. 2;
  • FIG. 6 is a plan view showing details of a power device according to an exemplary embodiment of the present disclosure.
  • Figure 9 is a cross-sectional view showing the position 601 to 603 in Figure 6;
  • FIG. 10 is a plan view showing details of a power device according to an exemplary embodiment of the present disclosure.
  • 11-13 are cross-sectional views along F-F, G-G, and H-H, respectively, of FIG. 10;
  • Figure 14 is a cross-sectional view showing the position 1001 in Figure 10;
  • FIG. 15 is a flowchart illustrating a method of fabricating a power device, according to an exemplary embodiment of the present disclosure.
  • MOSFET metal oxide semiconductor field effect transistors and insulated gate bipolar transistors, respectively.
  • the MOSFET and the IGBT have a conductor gate electrode, however it should be understood that the conductor material is not necessarily a metal material, but may be, for example, a metal alloy, a semimetal, a metal semiconductor alloy or compound, a doped semiconductor, or a combination thereof.
  • metal contacts and the like should be interpreted broadly to include the various conductor forms discussed above and is not intended to be merely limited to metallized conductors.
  • Non-limiting examples of insulating materials suitable for use in MOSFETs and IGBTs are oxides, nitrides, oxygen-nitrogen mixtures, organic insulating materials, and other dielectrics.
  • substrate may refer to a semiconductor substrate, whether used in single crystal, polycrystalline or amorphous, and includes Group IV semiconductors, non-IV semiconductors, compound semiconductors, and organic and inorganic semiconductors, and may For example, a film structure or a laminated structure.
  • silicon semiconductors are used herein to describe power devices and methods for their preparation, but those skilled in the art will appreciate that other semiconductor materials can also be used.
  • various device types and/or doped semiconductor regions may be labeled as N-type or P-type, but this is for convenience of illustration and is not intended to be limiting, and such markings may be "first conductivity type" or "second,”
  • the first conductivity type can be either N-type or P-type
  • the second conductivity type can also be P-type or N-type.
  • a power device including: a first device having a plurality of first source regions and having a plurality of first trenches, wherein the plurality of first trenches are plurality of first One source region is electrically isolated from each other; at least one second device having a plurality of second source regions and having a plurality of second trenches, the plurality of second trenches electrically isolating the plurality of second source regions from each other, wherein a second device is embedded in the first device, and a second trench of the second device is in communication with a corresponding first trench of the first device, wherein the second source region of the second device and the first device A source region is electrically isolated by a metal pitch region, and wherein portions of the first device and the second device except the trench are active regions.
  • the plurality of second source regions of the second device are collectively arranged.
  • the first device and the second device are formed on a P+N substrate and The rate device is an insulated gate bipolar transistor. In one embodiment, the first device and the second device are formed on an N+N substrate and the power device is a metal oxide semiconductor field effect transistor.
  • each second source region of the second device corresponds to a respective one of the first source regions of the first device, and each of the second trenches of the second device and the first one of the first device are first The trenches are in direct communication.
  • the power device further includes a plurality of third trenches, each of the third trenches corresponding to a second source region of the second device, and two second regions corresponding to the second source region The grooves are connected.
  • the first trench, the second trench, and the third trench are structurally identical.
  • the first source region of the first device has a first metal contact region
  • the second source region of the second device has a second metal contact region, the boundary of the first metal contact region being in contact with the corresponding second metal
  • the boundaries of the zones are at a distance so that the current can no longer flow laterally along the plane.
  • each second source region of the second device corresponds to a respective two first source regions of the first device
  • the power device further includes a plurality of fourth trenches, each of the fourth trenches a trilateral shape corresponding to a second source region of the second device and between the two second trenches corresponding to the second source region and the two first source regions corresponding to the second source region
  • the first grooves are connected.
  • the first trench, the second trench, and the fourth trench are structurally identical.
  • the first device and the second device are coupled and isolated in a unique manner, and there is no additional high concentration diffusion region due to the portion of the second device embedded with the first device (ie, no The source device), the embedding of the second device is smooth and does not cause structural changes to the first device, and thus does not adversely affect the current-voltage performance of the first device.
  • the second device since the second device is embedded in the portion of the first device, since there is no source region, this portion can still contribute to the current supply, so that there is no waste of any chip area.
  • FIG. 1 is a simplified plan view showing a power device 100 in accordance with an exemplary embodiment of the present disclosure.
  • power device 100 includes a first device 1 and a second device 2.
  • the second device 2 can be a current sensing device, such as a mirrored current device.
  • the second device 2 is formed on the same substrate 3 as the first device 1, that is, the second device 2 and the first device 1 are coupled in the same chip, so that the second device 2 and the first device 1 can be as Under the same conditions (such as temperature).
  • the substrate 3 may be a P+N substrate, whereby the power device 100 may be an insulated gate bipolar transistor (IGBT), or the substrate may be an N+N substrate, whereby the power device Piece 100 can be a metal oxide semiconductor field effect transistor (MOSFET).
  • IGBT insulated gate bipolar transistor
  • MOSFET metal oxide semiconductor field effect transistor
  • the second device 2 is embedded in the first device 1 and the second device 2 is electrically isolated from the first device 1. Essentially, the second device 2 has a drain and a gate connected to the first device 1, except that the source regions are electrically isolated.
  • the second device 2 and the first device 1 are electrically isolated by a metal pitch region (not shown). That is, the source region of the second device 2 and the source region of the first device 1 can be electrically isolated by a certain distance from the source region metal.
  • the power device 100 further includes a gate electrode terminal 4, and each gate of the first device 1 and the second device 2 is connected to the gate electrode terminal 4. Specifically, polysilicon in each gate trench of the first device 1 and the second device 2 is connected to the gate electrode terminal 4.
  • the second device 2 is illustrated as being located approximately at the central portion of the first device 1 and only one second device 2 is illustrated, this is merely an example.
  • the second device 2 can be located at any other location of the first device 1, or more second devices 2 can be arranged, depending on the temperature distribution and specific requirements of the chip.
  • the total effective size area of the second device 2 (i.e., the metal source region area) is proportional to the total effective size area of the first device 1 (CSR) in order to obtain a current proportional to the current of the first device 1.
  • CSR total effective size area of the first device 1
  • power device 200 includes a first device 1 and a second device 2.
  • the second device 2 is embedded in the first device 1 and the second device 2 is electrically isolated from the first device 1 by a metal pitch region 5.
  • substantially the metal spacer region 5 electrically isolates the source region of the second device 2 from the source region of the first device 1.
  • a region other than the outer dashed line indicates the metal 11 of the first device 1
  • a region inside the inner dashed line indicates the metal 21 of the second device 2.
  • the uppermost layer of the chip is a metal layer
  • the area other than the outer dotted line is filled with the metal of the first device 1
  • the area inside the inner dotted line is filled with the metal of the second device 2.
  • the area between the two dashed lines is a metal pitch region 5 to separate the metal of the first device 1 from the metal of the second device 2, correspondingly separating the source region of the first device 1 from the source of the second device 2. open.
  • the metal pitch region 5 represents a certain distance between the metal 11 of the first device 1 and the metal 21 of the second device 2.
  • the first device 1 has a plurality of first source regions 12, each of the first source regions 12. There is a first metal contact 14 thereof. The first device 1 collects current through these first source regions 12 during operation.
  • the second device 2 has a plurality of second source regions 22, each having its second metal contact 24. The second device 2 collects current through these second source regions 22.
  • the current collected by the second device 2 through all of the second source regions 22 should be in a predetermined proportional relationship with the current collected by the first device 1 through all of the first source regions 12. By measuring the current collected by the second device 2, the amount of current conducted by the first device 1 can be determined, thereby monitoring the state of the first device 1. It should be understood that these source regions 12 and 22 are actually located below the metal layer, as illustrated below.
  • the first device 1 further includes a plurality of first trenches 13.
  • the first trench 13 can be a strip trench. These first trenches 13 electrically isolate the plurality of first source regions 12 of the first device 1 from each other.
  • the second device 2 further includes a plurality of second trenches 23.
  • the second trench 23 can be a strip trench. These second trenches 23 electrically isolate the plurality of second source regions 22 of the second device 2 from each other.
  • the second trench 23 of the second device 2 is in communication with a corresponding first trench 13 of the first device 1.
  • first trench 13 and the second trench 23 are actually located in the body regions of the first device 1 and the second device 2, respectively, and the first trench 13 and the second trench 23 correspond to the first device 1 respectively.
  • the gate and the gate of the second device 2, that is, the gate of the first device 1 are connected to the gate of the second device 2.
  • each second source region 22 of the second device 2 corresponds to a respective one of the first source regions 12 of the first device 1, and each second trench 23 of the second device 2 is A respective one of the first grooves 13 of the first device 1 is in communication.
  • Power device 200 also includes a plurality of third trenches 6.
  • Each of the third trenches 6 corresponds to a second source region 22 of the second device 2 and communicates with two second trenches 23 corresponding to the second source region 22.
  • each third trench 6 also corresponds to a first source region 12 of the first device 1 and connects the two first trenches 13 corresponding to the first source region 12, respectively. through.
  • the third trench 6 can be located within the metal pitch region 5.
  • the third trench 6 not only acts as a gate but also allows the source region 22 of the second device 2 to be sufficiently isolated from the corresponding source region 12 of the first device 1.
  • the third trench 6 can be a strip trench.
  • the third trench 6 is identical in structure to the first trench 13 and the second trench 23.
  • the second source region 22-1 of the second device 2 corresponds to a corresponding one of the first source regions 12-1 of the first device 1.
  • the second trenches 23-1 and 23-2 of the second device 2 are respectively associated with the first device 1
  • the respective first trenches 13-1 and 13-2 are in communication.
  • the third trench 6 corresponds to the second source region 22-1 of the second device 2, and connects the two second trenches 23-1 and 23-2 corresponding to the second source region 22-1.
  • the third trench 6 also corresponds to the first source region 12-1 of the first device 1, and the two first trenches corresponding to the first source region 12-1
  • the slots 13-1 and 13-2 are in communication.
  • the plurality of second source regions 22 of the second device 2 are separated by the second trenches 23, but the second source regions are collectively arranged, that is, adjacent two second sources. Zone 22 is not separated from any other source zone.
  • the six source regions of the second device 2 and the corresponding metal contacts are shown in FIG. 2, this is merely a schematic view, and the second device 2 may have more or fewer source regions and corresponding metal contacts, depending on A predetermined ratio CSR of the second device 2 to the first device 1.
  • FIG. 3 to 5 respectively show cross-sectional views along A-A, B-B, and C-C in Fig. 2.
  • Figure 3 is a cross-sectional view along line A-A of Figure 2.
  • the AA line spans the metal region of the first device 1 and the metal region of the second device 2, and both ends of the AA line are located just in the source region of the first device 1 and the source region of the second device 2.
  • the first device 1 and the second device 2 are formed on the same substrate 3.
  • the first device 1 may be formed on the P+N type substrate or the N+N type substrate with the second device 2.
  • an active region is formed on the substrate 3.
  • the active region is composed of an N-type layer and a P-type layer.
  • a trench 6 is formed in the active region.
  • An N+ layer is formed on the P-type layer, and a P+ region is formed in the P-type layer and the N+ layer.
  • An oxide layer 10 is deposited over the trenches 6 filled with polysilicon. The two sides of the oxide layer 10 are respectively the metal 11 of the first device 1 and the metal 21 of the second device 2, and the metal 11 of the first device 1 and the metal 21 of the second device 2 are separated by the metal pitch region 5, correspondingly
  • the source region 12 of the first device 1 and the source region 22 of the second device 2 are electrically isolated.
  • the trenches 6 filled with polysilicon not only serve to connect the gates of the first device 1 and the second device 2, but also help to sufficiently isolate the source region 12 of the first device 1 and the source region 22 of the second device 2. .
  • the first device 1 and the second device 2 collect respective currents via respective metal contacts 14 and 24 via respective metal contacts 14 and 24 along arrows I1 and I2 indicating current flow.
  • Figure 4 shows a cross-sectional view along line B-B of Figure 2.
  • the B-B line spans the metal 11 of the first device 1 and the metal 21 of the second device 2, and one end of the B-B line is located exactly
  • the source region of one device 1 is in metal contact 14 and the other end is not in contact with the source region of the second device 2.
  • the first device 1 and the second device 2 are formed on the same substrate 3, and the metal 11 of the first device 1 and the metal 21 of the second device 2 are separated by the metal pitch region 5. Since one end of the B-B line is located just above the source metal contact 14 of the first device 1, the first device 1 can collect current through the first metal contact 14 via the first source region.
  • the other end of the B-B line does not have a source metal contact corresponding to the second device 2, so the second device 2 does not collect current here.
  • the current in the region below the oxide layer 10 and the metal 21 of the second device 2 is collected by the first device 1 via the first source region through the first metal contact 14.
  • Figure 5 shows a cross-sectional view along line C-C of Figure 2.
  • the C-C line spans the metal 11 of the first device 1 and the metal 21 of the second device 2, and the C-C line is perpendicular and spans 5 trenches.
  • the first device 1 and the second device 2 are formed on the same substrate 3, and the metal 11 of the first device 1 and the metal 21 of the second device 2 are electrically isolated by the metal pitch region 5.
  • the intermediate trench below the oxide layer 10 i.e., in the metal pitch region also contributes to the isolation of the metal 11 of the first device 1 from the metal 21 of the second device 2.
  • one end of the C-C line enters the metal region of the first device 1, and the other end enters the metal region of the second device 2.
  • the first device 1 portion there are two further trenches 13, and there is a first metal contact 14 of the first source region between the two trenches, at a portion between the two trenches 13, a current is passed through the metal contact 14 was collected.
  • the second device 2 portion there are also two other trenches 23, and a second metal contact 24 of the second source region exists between the two trenches 23, a portion between the two trenches 23 Current is collected through the metal contact 24.
  • the first device 1 and the second device 2 respectively collect their own currents along the arrows I1 and I2 indicating the current flow direction as shown in the drawing.
  • portions of the second device 2 and the body region of the first device 1 other than the trench are active regions. That is, in addition to the second device 2 and the active region of the first device 1 itself, the embedded portion of the second device 2 and the first device 1 (including the source region and the first device such as the spacer second device 2) a portion of the metal pitch region of the source region of 1 , a source region portion of the first device 1 under the metal of the second device 2 (the metal of the second device 2 of the upper portion is the source lead-out line of the second device 2) There is no additional high concentration diffusion zone, ie there is no source zone.
  • the embedding of the second device 2 is smooth and does not cause a structural change to the first device 1, and thus does not cause any current or voltage performance of the first device 1. Negative Effects.
  • the second device 2 since the second device 2 is embedded in the portion of the first device 1 because there is no source region, this portion can still contribute to the current supply, so that there is no waste of any chip area.
  • FIG. 6 is a plan view showing a power second device 300 according to another exemplary embodiment of the present disclosure.
  • the power device 300 includes a first device 1 and a second device 2.
  • the second device 2 is embedded in the first device 1 and the second device 2 is isolated from the first device 1 by a metal pitch region 5.
  • the first device 1 has a plurality of source regions 12 and a plurality of trenches 13. These first trenches 13 electrically isolate the plurality of source regions 12 of the first device 1 from each other.
  • the second device 2 has a plurality of source regions 22 and a plurality of trenches 23. These second trenches 23 electrically isolate the plurality of source regions 22 of the second device 2 from each other.
  • the trench 23 of the second device 2 is in communication with the trench 13 of the first device 1, and the source region 22 of the second device 2 is arranged in a concentrated manner.
  • the power device 300 of FIG. 6 differs from the power device 200 of FIG. 2 in the arrangement of source regions and trenches. Therefore, aspects and details consistent with the power device 200 shown in FIG. 2 are not described herein again. The arrangement of the source regions and trenches of power device 300 is discussed in detail below.
  • each second source region 22 of the second device 2 corresponds to a respective two first source regions 12 of the first device 1
  • the power device 22 further includes a plurality of a fourth trench 7, each of the fourth trenches 7 having a three-terminal shape corresponding to a second source region 22 of the second device 2 and having two second trenches corresponding to the second source region 22 23 and the first trench 13 between the two first source regions 12 corresponding to the second source region 22 are in communication.
  • the source region 22-1 of the second device 2 has two corresponding second trenches 23-1 and 23-2, and with the two first source regions 12-1 and 12 of the first device 1 - 2 corresponds.
  • the fourth trench 7 has a three-terminal shape corresponding to the second source region 22-1, and connects the second trenches 23-1 and 23-2 with the first trench 13-1, wherein the three ends are The two ends are respectively connected to the second grooves 23-1 and 23-2, and the other ends are in contact with the first grooves 13-1.
  • the three end shapes are T-shaped.
  • the triad may have other shapes, such as a Y shape at any angle.
  • FIG. 7 to 8 are cross-sectional views along D-D and E-E, respectively, of Fig. 6.
  • Figure 7 shows a cross-sectional view along D-D in Figure 6.
  • the D-D line spans the metal region of the first device 1 and the metal region of the second device 2, and the position through which the D-D line passes does not pass through any source region metal contact.
  • the first device 1 and the second device 2 are formed on the same substrate 3, and the metal 11 of the first device 1 and the metal 21 of the second device 2 are separated by the metal pitch region 5.
  • a trench 7 is formed in the body region below the oxide layer 10 for communicating the trench of the first device 1 and the trench of the second device 2. Since the position through which the D-D line passes does not pass through any source metal contact, there is no current expression in Figure 7.
  • Figure 8 is a cross-sectional view along line E-E of Figure 6.
  • the E-E line spans the metal 11 of the first device 1 and the metal 21 of the second device 2, and the E-E line is perpendicular and spans 3 trenches.
  • the first device 1 and the second device 2 are formed on the same substrate 3, and the metal 11 of the first device 1 and the metal 21 of the second device 2 are electrically isolated by the metal pitch region 5.
  • the intermediate trench below the oxide layer 10 i.e., in the metal pitch region also contributes to the isolation of the metal 11 of the first device 1 from the metal 21 of the second device 2.
  • one end of the E-E line enters the metal region of the first device 1, and the other end enters the metal region of the second device 2.
  • the first device 1 portion there is another trench 13 and the left end of this trench has a metal contact 14 of the first source region through which current is collected.
  • the second device 2 portion there is also a trench 23, and at the right end of this trench 23 there is a metal contact 24 of the second source region through which current is collected.
  • the first device 1 and the second device 2 respectively collect their own currents along the arrows I1 and I2 indicating the current flow direction as shown in the drawing.
  • Figure 9 is a cross-sectional view showing different positions 601 to 602 in Figure 6.
  • location 601 is located in the region of first device 1 and spans the source region 14 of the trench 13 and its sides; position 602 is located in the region of the second device 2 and spans the T-shaped trench 7 The head portion and one end are located on the metal contact of the source region of the second device 2.
  • cross-sectional views of positions 601 and 602 are shown in Figures (a) and (b), respectively.
  • the uppermost layer is covered with the metal 11 of the first device 1. Since the location 601 is located on the trench 13, the trench 13 is illustrated in this view.
  • the trench 13 serves to isolate the source region 12 of the first device 1. Since both ends of the location 601 are located on the source metal contact 14 of the first device 1, two metal contacts 14 are illustrated in Figure 9(a), and the two metal contacts 14 respectively represent current flow Arrow I collects the respective currents.
  • the uppermost layer is covered with metal 21 of the first device 2. Due to location 602 cross The more the groove 7, the groove 7 is illustrated in this view.
  • the trench 13 serves to isolate the source region of the first device 1 from the source region of the second device 2. Since one end of the location 602 is located on the source metal contact 24 of the second device 2, a metal contact 24 is illustrated in Figure 9(b) and this metal contact 24 collects current along an arrow I indicative of current flow. .
  • position 603 is also shown in FIG.
  • the structure at location 603 is the same as the structure at location 601 except that the metal and source regions of the upper layer are in contact with the metal and source regions of the second device 2, which are labeled 21 and 24 in Figure 9(a),
  • the groove is correspondingly labeled as 23.
  • portions of the second device 2 and the body region of the first device 1 other than the trenches are active regions. That is, in addition to the second device 2 and the active region of the first device 1 itself, the embedded portion of the second device 2 and the first device 1 (including the source region and the first device such as the spacer second device 2) a portion of the metal pitch region of the source region of 1 , a source region portion of the first device 1 under the metal of the second device 2 (the metal of the second device 2 of the upper portion is the source lead-out line of the second device 2) There is no additional high concentration diffusion zone, ie there is no source zone.
  • FIG. 10 is a plan view showing a power device 400 according to another exemplary embodiment of the present disclosure. As shown in FIG. 10, like the power device 200 shown in FIG. 2, the power device 400 includes a first device 1 and a second device 2. The second device 2 is embedded in the first device 1 and the second device 2 is isolated from the first device 1 by a metal pitch region 5.
  • the first device 1 has a plurality of source regions 12 and a plurality of trenches 13. These first trenches 13 electrically isolate the plurality of metal contacts 12 of the first device 1 from each other.
  • the second device 2 has a plurality of second source regions 22 and a plurality of second trenches 23. These second trenches 23 electrically isolate the plurality of source regions 22 of the second device 2 from each other. Furthermore, the second trench 23 of the second device 2 is in communication with the first trench 13 of the first device 1, and the source regions 22 of the second device 2 are arranged centrally.
  • the power device 400 of FIG. 10 differs from the power device 200 of FIG. 2 in the arrangement of the source regions and trenches. Therefore, regarding aspects consistent with the power device 200 shown in FIG. 2 and Details will not be described here.
  • the arrangement of the source regions and trenches of power device 400 is discussed in detail below.
  • each of the second source regions 22 of the second device 2 corresponds to a corresponding one of the first source regions 12 of the first device 1, and each of the second devices 2
  • the two trenches 23 are in communication with a corresponding one of the first trenches 13 of the first device 1.
  • power device 400 does not have a third trench 6 as shown in FIG. Rather, the metal contact 24 of the second source region 22 of the second device 2 is at a distance L from the metal contact 14 of the respective first source region 12 of the first device 1 such that the current can no longer flow laterally along the plane, thereby Sufficient isolation of the source regions of the first device 1 and the second device 2 is achieved.
  • the distance L may be between 10 ⁇ m and 50 ⁇ m. It should be understood that the smaller the distance, the better, as long as the purpose of making the current no longer move laterally along the plane can be achieved.
  • FIG. 11 to 14 are cross-sectional views along F-F, G-G, and H-H, respectively, of Fig. 10.
  • Figure 11 is a cross-sectional view along line F-F of Figure 10.
  • the FF line spans the metal region of the first device 1 and the metal region of the second device 2, and both ends of the FF line are located just in the metal contact of the source region 12 of the first device 1 and the source of the second device 2.
  • the metal of zone 22 is in contact.
  • the metal 11 of the first device 1 and the metal 21 of the second device 2 are separated by a metal pitch region 5.
  • Below the metal layer is an oxide layer 10.
  • first device 1 and the second device 2 collect respective currents along the arrows I1 and I2 representing the direction of current flow through the metal contacts 14 and 24 via the source regions 12 and 22, respectively. As such, the current collection of the second device 2 does not affect the normal operation of the first device 1.
  • Figure 12 is a cross-sectional view along line G-G of Figure 10.
  • the G-G line traverses the metal region of the second device 2 and the two ends are respectively located on the metal contacts 14 of the first source region 12 on both sides of the first device 1.
  • the metal 11 of the first device 1 and the metal 21 of the second device 2 are separated by a metal pitch region 5.
  • an oxide layer 10 below the metal layer is an oxide layer 10.
  • the second device 2 collects current along an arrow I2 indicating current flow, but the first device 1 Current is collected through the metal contact 14 via the first source region 12 on either side of the GG line, as indicated by the arrow I1 indicating the direction of current flow.
  • Figure 13 is a cross-sectional view taken along line H-H of Figure 10.
  • H-H falls completely in the region of the first device 1 and spans three trenches 13, and the H-H line spans the two source metal contacts 14.
  • the uppermost layer is the metal 11 of the first device 1.
  • Below the metal layer is an oxide layer 10.
  • the H-H line spans the two source metal contacts 14
  • the two source metal contacts 14 are also mapped accordingly in this cross-sectional view. Through the two source metal contacts 14, the current between the respective trenches is collected along an arrow I1 representing the direction of current flow, respectively.
  • Figure 14 shows a cross-sectional view at position 1001 in Figure 10.
  • location 1001 falls within the area of second device 2, spans one trench 23, and one end is located on source metal contact 24.
  • the uppermost layer is the metal 21 of the second device 2.
  • the metal contact 24 is shown here in cross-sectional view. From the middle to the right, since one end of the position 1001 is located on the source metal contact 24, the metal contact 24 is shown in cross-section and the metal contact 24 collects current along an arrow I2 indicating the direction of current flow.
  • the portions other than the trenches in the body region of the second device 2 and the first device 1 are active regions. That is, in addition to the second device 2 and the active region of the first device 1 itself, the embedded portion of the second device 2 and the first device 1 (including the source region and the first device such as the spacer second device 2) a portion of the metal pitch region of the source region of 1 , a source region portion of the first device 1 under the metal of the second device 2 (the metal of the second device 2 of the upper portion is the source lead-out line of the second device 2) There is no additional high concentration diffusion zone, ie there is no source zone.
  • the embedding of the second device 2 is smooth and does not cause structural changes to the first device 1, and thus does not adversely affect the current-voltage performance of the first device 1.
  • the second device 2 since the second device 2 is embedded in the portion of the first device 1 because there is no source region, this portion can still contribute to the current supply, so that there is no waste of any chip area.
  • the structure of the power device according to the present disclosure has been described above by way of embodiments. It should be understood that the number of source regions and trenches may be the same or different than the described embodiments. It should also be noted that the structure of the second device and the first device in the left half and the right half of the figure are the same, the description about the left half also applies to the corresponding structure of the right half, and the description about the right half Also applies to the left half Part of the corresponding structure.
  • FIG. 15 illustrates a method 1500 of fabricating a power device in accordance with an example embodiment of the present invention.
  • method 1500 includes: S1501, providing a substrate.
  • step S1502 a body region of the first device and a body region of the at least one second device are formed on the substrate.
  • step S1503 a plurality of first trenches are formed in the body region of the first device, and a plurality of second trenches are formed in the body region of the second device, wherein the second trench of the second device is first
  • the respective first trenches of the device are in communication.
  • step S1504 a plurality of first source regions for the first device and a plurality of second source regions for the second device are formed, wherein the plurality of first source regions are each other through the plurality of first trenches Electrically isolating, the plurality of second source regions are electrically isolated from each other by the plurality of second trenches, wherein the second source region of the second device is electrically isolated from the first source region of the first device by a metal pitch region, wherein Portions of the device and the second device except the first trench and the second trench are active regions.
  • the plurality of second source regions of the second device are arranged centrally.
  • the substrate can be a P+N substrate and the power device is an insulated gate bipolar transistor. In one implementation, the substrate can be an N+N substrate and the power device is a metal oxide semiconductor field effect transistor.
  • each second source region of the second device corresponds to a respective one of the first source regions of the first device, and each of the second trenches of the second device and a corresponding one of the first devices A groove is connected.
  • the method 1500 further includes forming a plurality of third trenches in the metal pitch region, each third trench corresponding to a second source region of the second device, and two corresponding to the second source region The second trenches are in communication.
  • the first trench, the second trench, and the third trench are structurally identical.
  • the first source region of the first device has a first metal contact region
  • the second source region of the second device has a second metal contact region, the boundary of the first metal contact region being spaced from the boundary of the corresponding second metal contact region A certain distance so that the current can no longer flow laterally along the plane.
  • each second source region of the second device corresponds to a respective two first source regions of the first device
  • the method 1500 further includes forming a plurality of fourth trenches in the metal pitch region, each The fourth trench has a three-terminal shape corresponding to a second source region of the second device, and two second trenches corresponding to the second source region and two corresponding to the second source region
  • the first trench between the first source regions is in communication.
  • the first trench, the second trench, and the fourth trench are structurally identical.
  • the power device according to the present disclosure and a method of fabricating the same are discussed by way of specific embodiments.
  • the first device and the second device are simultaneously fabricated by the same process on the same substrate, wherein the first device and the second device are well electrically isolated.
  • the first device and the second device are coupled and isolated in a unique manner, and since the portion of the second device that is embedded with the first device has no additional high concentration diffusion regions (ie, no source region), the second device The embedding does not cause a structural change to the first device and therefore does not adversely affect the current-voltage performance of the first device.
  • the second device since the second device is embedded in the portion of the first device, since there is no source region, this portion can still contribute to the current supply, so that there is no waste of any chip area.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)

Abstract

A power device (200) and a preparation method therefor. The power device (200) comprises a first device (1) and at least one second device (2). The first device (1) is provided with multiple first source regions (12) and multiple first grooves (13). The multiple first grooves (13) electrically isolate the multiple first source regions (12). The at least one second device (2) is provided with multiple second source regions (22) and multiple second grooves (23). The multiple second grooves (23) electrically isolate the multiple second source regions (22). The second device (2) is embedded into the first device (1) and the second grooves (23) of the second device (2) communicate with the corresponding first grooves (13) of the first device (1). The second source regions (22) of the second device (2) and the first source regions (12) of the first device (1) are electrically isolated by means of metal spacing regions (5), and the parts, except the grooves, of body regions of the first device (1) and the second device (2) are active regions. According to the power device (200) and the preparation method therefor, the structure of the first device (1) is not changed when the second device (2) is embedded, so that current and voltage performance of the first device (1) is not affected.

Description

功率器件及其制备方法Power device and preparation method thereof 技术领域Technical field
本公开涉及半导体领域，尤其涉及功率器件及其制备方法。The present disclosure relates to the field of semiconductors, and more particularly to power devices and methods of making same.
背景技术Background technique
对于功率器件，为了监控该器件工作状态，要定量(通常是按主器件电流量缩小一个比例系数，这个系数一般用CSR表示)适时全量程测量该器件传导的电流量，以确保该器件的安全可靠，例如汽车电子领域。传统地，可以在整个器件(称为主器件)内选择一个适当位置耦合进诸如镜像电流器件的电流传感器件来提供这种测量。电流传感器件与主器件的耦合与隔离是非常重要的。For power devices, in order to monitor the operating state of the device, it is necessary to quantify (usually a scaling factor according to the amount of current in the main device, this coefficient is generally expressed in CSR). The current amount of current conducted by the device is measured at full scale to ensure the safety of the device. Reliable, for example in the field of automotive electronics. Conventionally, a current sensor device, such as a mirrored current device, can be selected throughout the device (referred to as the master device) to provide such measurements. The coupling and isolation of the current sensor device from the main device is very important.
发明内容Summary of the invention
根据本公开的一方面，提供一种功率器件，包括：第一器件，第一器件具有多个第一源区，并具有多个第一沟槽，其中，多个第一沟槽把多个第一源区彼此电学隔离；至少一个第二器件，第二器件具有多个第二源区并具有多个第二沟槽，多个第二沟槽把多个第二源区彼此电学隔离，其中第二器件内嵌在第一器件中，并且第二器件的第二沟槽与第一器件的相应的第一沟槽相连通，其中，第二器件的第二源区与第一器件的第一源区通过金属间距区被电学隔离，并且其中所述第一器件和所述第二器件的体区内除了沟槽的部分均为有源区。According to an aspect of the present disclosure, a power device is provided, including: a first device having a plurality of first source regions and having a plurality of first trenches, wherein the plurality of first trenches are plurality of The first source regions are electrically isolated from each other; at least one second device having a plurality of second source regions and having a plurality of second trenches, the plurality of second trenches electrically isolating the plurality of second source regions from each other, Wherein the second device is embedded in the first device, and the second trench of the second device is in communication with the corresponding first trench of the first device, wherein the second source region of the second device is The first source region is electrically isolated by a metal pitch region, and wherein portions of the first device and the second device except the trench are active regions.
根据本公开的一方面，提供一种功率器件的制备方法，包括：提供衬底；在衬底上形成第一器件的体区和至少一个第二器件的体区；在第一器件的体区内形成用于第一器件的多个第一沟槽，并在第二器件的体区内形成用于第二器件的多个第二沟槽，其中第二器件的第二沟槽与第一器件的相应的第一沟槽相连通；形成用于第一器件的多个第一源区和用于第二器 件的多个第二源区，其中，多个第一源区通过多个第一沟槽被彼此电学隔离，多个第二源区通过多个第二沟槽被彼此电学隔离；其中，第二器件的第二源区与第一器件的第一源区通过金属间距区被电学隔离，并且其中第一器件和所述第二器件的体区内除了沟槽的部分均为有源区。According to an aspect of the present disclosure, a method of fabricating a power device includes: providing a substrate; forming a body region of the first device and a body region of the at least one second device on the substrate; and a body region of the first device Forming a plurality of first trenches for the first device, and forming a plurality of second trenches for the second device in the body region of the second device, wherein the second trenches of the second device are first Corresponding first trenches of the device are in communication; forming a plurality of first source regions for the first device and for the second device a plurality of second source regions, wherein the plurality of first source regions are electrically isolated from each other by the plurality of first trenches, and the plurality of second source regions are electrically isolated from each other by the plurality of second trenches; wherein The second source region of the second device is electrically isolated from the first source region of the first device by a metal pitch region, and wherein the portions of the first device and the second device except the trench are active regions.
根据本公开的功率器件及其制备方法，第一器件与第二器件以特有的方式耦合与隔离，并且由于第二器件与第一器件相嵌的部分没有另外的高浓度扩散区(即没有去源区)，第二器件的嵌入是平顺的并不会给第一器件造成结构上的改变，因此不会对第一器件的电流电压性能造成任何不利影响。此外，第二器件与第一器件相嵌部分由于没有去源区，因此这部分仍可以对电流提供做出贡献，从而没有任何芯片面积浪费。According to the power device of the present disclosure and the method of fabricating the same, the first device and the second device are coupled and isolated in a unique manner, and since the portion of the second device embedded with the first device has no additional high concentration diffusion region (ie, no The source region), the embedding of the second device is smooth and does not cause structural changes to the first device, and thus does not adversely affect the current-voltage performance of the first device. In addition, since the second device is embedded in the portion of the first device, since there is no source region, this portion can still contribute to the current supply, so that there is no waste of any chip area.
附图说明DRAWINGS
通过参考附图会更加清楚地理解本发明的特征和优点，附图是示意性的而不应理解为对本公开进行任何限制，在附图中：The features and advantages of the present invention are more clearly understood from the following description of the accompanying drawings.
图1是示出根据本公开一个示例性实施例的功率器件的简化平面视图；1 is a simplified plan view showing a power device in accordance with an exemplary embodiment of the present disclosure;
图2是示出根据本公开一个示例性实施例的功率器件的细节的平面视图；2 is a plan view showing details of a power device in accordance with an exemplary embodiment of the present disclosure;
图3-图5分别示出图2中沿A-A、B-B、C-C的剖面视图；3 to 5 respectively show cross-sectional views along A-A, B-B, and C-C in FIG. 2;
图6是示出根据本公开一个示例性实施例的功率器件的细节的平面视图；FIG. 6 is a plan view showing details of a power device according to an exemplary embodiment of the present disclosure;
图7-图8分别示出图6中沿D-D、E-E的剖面视图；7 to 8 respectively show cross-sectional views along D-D, E-E in Fig. 6;
图9是示出图6中位置601～603处的剖面视图；Figure 9 is a cross-sectional view showing the position 601 to 603 in Figure 6;
图10是示出根据本公开一个示例性实施例的功率器件的细节的平面视图；FIG. 10 is a plan view showing details of a power device according to an exemplary embodiment of the present disclosure;
图11-图13分别示出图10中沿F-F、G-G、H-H的剖面视图；11-13 are cross-sectional views along F-F, G-G, and H-H, respectively, of FIG. 10;
图14是示出图10中位置1001处的剖面视图；以及Figure 14 is a cross-sectional view showing the position 1001 in Figure 10;
图15是示出根据本公开一个示例性实施例的功率器件的制备方法的流程图。 FIG. 15 is a flowchart illustrating a method of fabricating a power device, according to an exemplary embodiment of the present disclosure.
具体实施方式detailed description
下面对本公开的实施例的详细描述涵盖了许多具体细节，以便提供对本公开实施例的全面理解。但是，对于本领域技术人员来说显而易见的是，本发明可以在不需要这些具体细节中的一些细节的情况下实施。下面对实施例的描述仅仅是为了通过示出本发明的示例来提供对本发明更清楚的理解。本发明绝不限于下面所提出的任何具体配置，而是在不脱离本发明的精神的前提下覆盖了相关元素、部件的任何修改、替换和改进。The detailed description of the embodiments of the present disclosure is intended to However, it will be apparent to those skilled in the art that the present invention may be practiced without some of these details. The following description of the embodiments is merely intended to provide a further understanding of the invention. The present invention is in no way limited to any specific configuration as set forth below, but without departing from the spirit and scope of the invention.
下面的详细说明实际上仅仅是示例性的，并且无意于限制本发明或本发明的应用和使用。而且，无意于使本发明受限于前述的技术领域、背景技术或下面详细的说明书中提出的所表达或暗示的任何理论。The detailed description below is merely exemplary in nature and is not intended to limit the invention or the application and use of the invention. Furthermore, the invention is not intended to be limited to the scope of the inventions disclosed herein.
在本公开中使用了缩写“MOSFET”和“IGBT”，它们分别指金属氧化物半导体场效应晶体管和绝缘栅双极型晶体管。MOSFET和IGBT具有导体栅电极，然而应理解导体材料并非一定是金属材料，而可以是例如金属合金、半金属、金属半导体合金或化合物、掺杂半导体、它们的组合。在本公开中，提及的“金属接触”及类似物应该广义地解释为包括上面讨论的各种导体形式而不意欲仅仅限制为金属化导体。适合用在MOSFET和IGBT的绝缘材料的非限制示例有氧化物、氮化物、氧氮混合物、有机绝缘材料及其它电介质。The abbreviations "MOSFET" and "IGBT" are used in the present disclosure, which refer to metal oxide semiconductor field effect transistors and insulated gate bipolar transistors, respectively. The MOSFET and the IGBT have a conductor gate electrode, however it should be understood that the conductor material is not necessarily a metal material, but may be, for example, a metal alloy, a semimetal, a metal semiconductor alloy or compound, a doped semiconductor, or a combination thereof. In the present disclosure, reference to "metal contacts" and the like should be interpreted broadly to include the various conductor forms discussed above and is not intended to be merely limited to metallized conductors. Non-limiting examples of insulating materials suitable for use in MOSFETs and IGBTs are oxides, nitrides, oxygen-nitrogen mixtures, organic insulating materials, and other dielectrics.
为了简单清楚地说明，附图说明了通常的结构方式，且可能省略对众所周知的特征和技术的描述和细节，以避免不必要地模糊本发明。另外，附图中的元件不一定是按比例绘制的。例如，可能相对于其它元件或区域而放大了附图中的一些元件或区域的尺寸，以帮助提高对本发明的实施例的理解。The drawings illustrate the general constructions, and the description and details of the well-known features and techniques may be omitted to avoid unnecessarily obscuring the present invention. In addition, elements in the drawings are not necessarily to scale. For example, the dimensions of some of the elements or regions in the figures may be exaggerated with respect to other elements or regions to help improve the understanding of the embodiments of the invention.
在说明书和权利要求书中的诸如“第一”、“第二”、“第三”、“第四”等序数词可用于类似的元件或步骤之间的区分而不必然用于描述一个特定序列或先后顺序。需要理解，如此使用的术语在适当的情况下是可以互换的，以使本文所描述的发明中的实施例，例如，能够按照除了本文说明的或其它方式描述的那些顺次而工作或排列。此外，术语“包 含”、“包括”、“具有”以及它们的各种变化，意指覆盖了非排除的包括，以使包括一系列元件或步骤的工艺、方法、产品或设备不必限制为那些元件或步骤，而是可以包括没有明确列出或固有属于这些工艺、方法、产品或设备的其它元件或步骤。这里所使用的术语“连通”定义为直接或间接以电性或非电性方式的连接。如文中所使用的，术语“实质上的”和“实质上地”意味着在实践方式中足以完成所声称的目的，而且那些次要的缺陷，如果有的话，对所声称的目的没有明显的影响。Ordinal numbers such as "first", "second", "third", "fourth", and the like, may be used in the <RTI ID=0.0> Sequence or order. It is to be understood that the terms so used are interchangeable, where appropriate, such that the embodiments of the invention described herein, for example, can be . In addition, the term "package The inclusion of "including", "comprising", and variations thereof, is intended to be inclusive, and is not intended to Rather, other elements or steps may be included that are not explicitly listed or inherently belonging to such processes, methods, products, or devices. The term "connected" as used herein is defined as a direct or indirect connection in an electrical or non-electrical manner. As used herein, the terms "substantially" and "substantially" mean in a practical manner sufficient to accomplish the stated purpose, and those minor defects, if any, are not apparent to the claimed purpose. influences.
在说明书和权利要求书中的“另外的”是指超正常之外的。例如“另外的高浓度扩散”是指在正常的有源区扩散之外的扩散，并且浓度高于本体浓度。"Additional" in the specification and claims means beyond the normal. For example, "an additional high concentration diffusion" refers to diffusion outside the normal active region diffusion, and the concentration is higher than the bulk concentration.
如文中所使用的，术语“衬底”可指半导体衬底，所用半导体不论单晶、多晶还是非晶，并且包括IV族半导体、非IV族半导体、化合物半导体以及有机和无机半导体，并且可以例如是薄膜结构或层叠结构。As used herein, the term "substrate" may refer to a semiconductor substrate, whether used in single crystal, polycrystalline or amorphous, and includes Group IV semiconductors, non-IV semiconductors, compound semiconductors, and organic and inorganic semiconductors, and may For example, a film structure or a laminated structure.
为了说明的方便和不受局限，本文用硅半导体来描述功率器件及其制备方法，但是本领域技术人员将会理解也可以使用其它半导体材料。此外，各种器件类型和/或掺杂半导体区域可标记为N型或P型，但这只是为了说明的方便而不意欲限制，并且这样的标记可用“第一导电类型”或“第二、相反导电类型”的更通用的描述来代替，其中第一导电类型既可是N型也可是P型，而且第二导电类型也可是P型或N型。For convenience and non-limiting purposes of illustration, silicon semiconductors are used herein to describe power devices and methods for their preparation, but those skilled in the art will appreciate that other semiconductor materials can also be used. Furthermore, various device types and/or doped semiconductor regions may be labeled as N-type or P-type, but this is for convenience of illustration and is not intended to be limiting, and such markings may be "first conductivity type" or "second," Instead of the more general description of the opposite conductivity type, the first conductivity type can be either N-type or P-type, and the second conductivity type can also be P-type or N-type.
根据本公开的一方面，提供一种功率器件，包括：第一器件，第一器件具有多个第一源区并具有多个第一沟槽，其中，多个第一沟槽把多个第一源区彼此电学隔离；至少一个第二器件，第二器件具有多个第二源区并具有多个第二沟槽，多个第二沟槽把多个第二源区彼此电学隔离，其中第二器件内嵌在第一器件中，并且第二器件的第二沟槽与第一器件的相应的第一沟槽相连通，其中，第二器件的第二源区与第一器件的第一源区通过金属间距区被电学隔离，并且其中第一器件和第二器件的体区内除了沟槽的部分均为有源区。According to an aspect of the present disclosure, a power device is provided, including: a first device having a plurality of first source regions and having a plurality of first trenches, wherein the plurality of first trenches are plurality of first One source region is electrically isolated from each other; at least one second device having a plurality of second source regions and having a plurality of second trenches, the plurality of second trenches electrically isolating the plurality of second source regions from each other, wherein a second device is embedded in the first device, and a second trench of the second device is in communication with a corresponding first trench of the first device, wherein the second source region of the second device and the first device A source region is electrically isolated by a metal pitch region, and wherein portions of the first device and the second device except the trench are active regions.
在一个实施例中，第二器件的多个第二源区集中排布。In one embodiment, the plurality of second source regions of the second device are collectively arranged.
在一个实施例中，第一器件和第二器件被形成在P+N衬底上，并且功 率器件为绝缘栅双极型晶体管。在一个实施例中，第一器件和第二器件被形成在N+N衬底上，并且功率器件为金属氧化物半导体场效应晶体管。In one embodiment, the first device and the second device are formed on a P+N substrate and The rate device is an insulated gate bipolar transistor. In one embodiment, the first device and the second device are formed on an N+N substrate and the power device is a metal oxide semiconductor field effect transistor.
在一个实施例中，第二器件的每个第二源区与第一器件的相应一个第一源区相对应，并且第二器件的每个第二沟槽与第一器件的相应一个第一沟槽直接相连通。在一个实现方式中，功率器件还包括多个第三沟槽，每个第三沟槽与第二器件的一个第二源区相对应，并把与该第二源区相应的两个第二沟槽相连通。第一沟槽、第二沟槽、第三沟槽在结构上相同。在另一实现方式中，第一器件的第一源区具有第一金属接触区，第二器件的第二源区具有第二金属接触区，第一金属接触区的边界与相应第二金属接触区的边界相距一定距离，以使得电流不再能沿平面横向流动。In one embodiment, each second source region of the second device corresponds to a respective one of the first source regions of the first device, and each of the second trenches of the second device and the first one of the first device are first The trenches are in direct communication. In one implementation, the power device further includes a plurality of third trenches, each of the third trenches corresponding to a second source region of the second device, and two second regions corresponding to the second source region The grooves are connected. The first trench, the second trench, and the third trench are structurally identical. In another implementation, the first source region of the first device has a first metal contact region, and the second source region of the second device has a second metal contact region, the boundary of the first metal contact region being in contact with the corresponding second metal The boundaries of the zones are at a distance so that the current can no longer flow laterally along the plane.
在一个实施例中，第二器件的每个第二源区与第一器件的相应两个第一源区相对应，并且功率器件还包括多个第四沟槽，每个第四沟槽呈三端形，与第二器件的一个第二源区相对应，并把与该第二源区相应的两个第二沟槽和与该第二源区相应的两个第一源区之间的第一沟槽相连通。第一沟槽、第二沟槽、第四槽在结构上相同。In one embodiment, each second source region of the second device corresponds to a respective two first source regions of the first device, and the power device further includes a plurality of fourth trenches, each of the fourth trenches a trilateral shape corresponding to a second source region of the second device and between the two second trenches corresponding to the second source region and the two first source regions corresponding to the second source region The first grooves are connected. The first trench, the second trench, and the fourth trench are structurally identical.
根据本公开的功率器件及其制备方法，第一器件与第二器件以特有的方式耦合与隔离，并且由于第二器件与第一器件相嵌的部分没有另外的高浓度扩散区(即，没有去源区)，第二器件的嵌入是平顺的并不会给第一器件造成结构上的改变，因此不会对第一器件的电流电压性能造成任何不利影响。此外，第二器件与第一器件相嵌部分由于没有去源区，因此这部分仍可以对电流提供做出贡献，从而没有任何芯片面积浪费。According to the power device of the present disclosure and the method of fabricating the same, the first device and the second device are coupled and isolated in a unique manner, and there is no additional high concentration diffusion region due to the portion of the second device embedded with the first device (ie, no The source device), the embedding of the second device is smooth and does not cause structural changes to the first device, and thus does not adversely affect the current-voltage performance of the first device. In addition, since the second device is embedded in the portion of the first device, since there is no source region, this portion can still contribute to the current supply, so that there is no waste of any chip area.
下面将参照附图来更详细的描述根据本发明的实施例。Embodiments in accordance with the present invention will now be described in more detail with reference to the accompanying drawings.
图1是示出根据本公开一个示例性实施例的功率器件100的简化平面视图。如图1所示，功率器件100包括第一器件1和第二器件2。在一个示例中，第二器件2可以为电流传感器件，例如镜像电流器件。第二器件2形成在与第一器件1相同的衬底3上，即，第二器件2和第一器件1被耦合在同一个芯片内，从而第二器件2与第一器件1能够尽可能处于同样的条件(例如温度)下。衬底3可以为P+N衬底，由此功率器件100可为绝缘栅双极型晶体管(IGBT)，或者衬底可以为N+N衬底，由此功率器 件100可为金属氧化物半导体场效应晶体管(MOSFET)。FIG. 1 is a simplified plan view showing a power device 100 in accordance with an exemplary embodiment of the present disclosure. As shown in FIG. 1, power device 100 includes a first device 1 and a second device 2. In one example, the second device 2 can be a current sensing device, such as a mirrored current device. The second device 2 is formed on the same substrate 3 as the first device 1, that is, the second device 2 and the first device 1 are coupled in the same chip, so that the second device 2 and the first device 1 can be as Under the same conditions (such as temperature). The substrate 3 may be a P+N substrate, whereby the power device 100 may be an insulated gate bipolar transistor (IGBT), or the substrate may be an N+N substrate, whereby the power device Piece 100 can be a metal oxide semiconductor field effect transistor (MOSFET).
第二器件2内嵌于第一器件1中，并且第二器件2与第一器件1被电学隔离。实质上，第二器件2与第一器件1具有相连的漏极和栅极，只不过源区被电学隔离。第二器件2与第一器件1藉由一金属间距区(未图示)而被电学隔离。也就是说，第二器件2的源区与第一器件1的源区可以通过源区金属相距一定间距而被电学隔离。The second device 2 is embedded in the first device 1 and the second device 2 is electrically isolated from the first device 1. Essentially, the second device 2 has a drain and a gate connected to the first device 1, except that the source regions are electrically isolated. The second device 2 and the first device 1 are electrically isolated by a metal pitch region (not shown). That is, the source region of the second device 2 and the source region of the first device 1 can be electrically isolated by a certain distance from the source region metal.
如图1所示，功率器件100还包括栅电极引出端4，第一器件1和第二器件2的每一个栅极都与该栅电极引出端4连接。具体地，第一器件1和第二器件2的各个栅极沟槽中的多晶硅与该栅电极引出端4连接。As shown in FIG. 1, the power device 100 further includes a gate electrode terminal 4, and each gate of the first device 1 and the second device 2 is connected to the gate electrode terminal 4. Specifically, polysilicon in each gate trench of the first device 1 and the second device 2 is connected to the gate electrode terminal 4.
应理解，虽然第二器件2被图示为大约位于第一器件1的中心部分并且仅一个第二器件2被图示，但是这仅仅是示例。第二器件2可以位于第一器件1的任何其他位置，也可以布置更多个第二器件2，这依赖于芯片的温度分布和具体需求。It should be understood that although the second device 2 is illustrated as being located approximately at the central portion of the first device 1 and only one second device 2 is illustrated, this is merely an example. The second device 2 can be located at any other location of the first device 1, or more second devices 2 can be arranged, depending on the temperature distribution and specific requirements of the chip.
第二器件2的总有效尺寸面积(即，金属源区面积)与第一器件1的总有效尺寸面积成一定缩小比例(CSR)，以便获取与第一器件1的电流成比例的电流。如此，通过第二器件2收集的电流便可确定出第一器件1传导的电流量，从而实现对第一器件1的状态的监控。The total effective size area of the second device 2 (i.e., the metal source region area) is proportional to the total effective size area of the first device 1 (CSR) in order to obtain a current proportional to the current of the first device 1. Thus, the current collected by the second device 2 can determine the amount of current conducted by the first device 1, thereby enabling monitoring of the state of the first device 1.
图2是示出根据本公开一个实施例的功率器件200的细节的平面视图。如图2所示，功率器件200包括第一器件1和第二器件2。第二器件2内嵌于第一器件1中，并且第二器件2与第一器件1通过金属间距区5被电学隔离。如上所述，实质上该金属间距区5把第二器件2的源区与第一器件1的源区电学隔开。在图2中，外侧虚线以外的区域表示第一器件1的金属11，内侧虚线以内的区域表示第二器件2的金属21。更确切地，芯片的最上层为金属层，在外侧虚线以外的区域布满了第一器件1的金属，内侧虚线以内的区域布满第二器件2的金属。两个虚线之间的区域为金属间距区5，以把第一器件1的金属和第二器件2的金属隔开，相应地把第一器件1的源区和第二器件2的源区隔开。在本公开中，金属间距区5表示第一器件1的金属11和第二器件2的金属21间相距一定间距。2 is a plan view showing details of a power device 200 in accordance with one embodiment of the present disclosure. As shown in FIG. 2, power device 200 includes a first device 1 and a second device 2. The second device 2 is embedded in the first device 1 and the second device 2 is electrically isolated from the first device 1 by a metal pitch region 5. As described above, substantially the metal spacer region 5 electrically isolates the source region of the second device 2 from the source region of the first device 1. In FIG. 2, a region other than the outer dashed line indicates the metal 11 of the first device 1, and a region inside the inner dashed line indicates the metal 21 of the second device 2. More specifically, the uppermost layer of the chip is a metal layer, the area other than the outer dotted line is filled with the metal of the first device 1, and the area inside the inner dotted line is filled with the metal of the second device 2. The area between the two dashed lines is a metal pitch region 5 to separate the metal of the first device 1 from the metal of the second device 2, correspondingly separating the source region of the first device 1 from the source of the second device 2. open. In the present disclosure, the metal pitch region 5 represents a certain distance between the metal 11 of the first device 1 and the metal 21 of the second device 2.
接着参考图2，第一器件1具有多个第一源区12，每个第一源区12 具有其第一金属接触14。第一器件1工作时通过这些第一源区12来收集电流。类似地，第二器件2具有多个第二源区22，每个第一源区22具有其第二金属接触24。第二器件2通过这些第二源区22来收集电流。第二器件2通过所有第二源区22收集的电流与第一器件1通过所有第一源区12收集的电流应成预定比例关系。通过测量第二器件2收集的电流便能确定出第一器件1传导的电流量，进而实现对第一器件1状态的监控。应理解，这些源区12和22实际上位于金属层的下方，这在后文中图示说明。Referring next to FIG. 2, the first device 1 has a plurality of first source regions 12, each of the first source regions 12. There is a first metal contact 14 thereof. The first device 1 collects current through these first source regions 12 during operation. Similarly, the second device 2 has a plurality of second source regions 22, each having its second metal contact 24. The second device 2 collects current through these second source regions 22. The current collected by the second device 2 through all of the second source regions 22 should be in a predetermined proportional relationship with the current collected by the first device 1 through all of the first source regions 12. By measuring the current collected by the second device 2, the amount of current conducted by the first device 1 can be determined, thereby monitoring the state of the first device 1. It should be understood that these source regions 12 and 22 are actually located below the metal layer, as illustrated below.
此外，如图2所示，第一器件1还包括多个第一沟槽13。在一个示例中，第一沟槽13可为条形沟槽。这些第一沟槽13把第一器件1的多个第一源区12彼此电学隔离。类似地，第二器件2还包括多个第二沟槽23。在一个示例中，第二沟槽23可为条形沟槽。这些第二沟槽23把第二器件2的多个第二源区22彼此电学隔离。如图2所示，第二器件2的第二沟槽23与第一器件1的相应的第一沟槽13相连通。实质上，第一沟槽13和第二沟槽23实际分别位于第一器件1和第二器件2的体区内，并且第一沟槽13和第二沟槽23分别对应于第一器件1的栅极和第二器件2的栅极，也就是说，第一器件1的栅极与第二器件2的栅极相连。Further, as shown in FIG. 2, the first device 1 further includes a plurality of first trenches 13. In one example, the first trench 13 can be a strip trench. These first trenches 13 electrically isolate the plurality of first source regions 12 of the first device 1 from each other. Similarly, the second device 2 further includes a plurality of second trenches 23. In one example, the second trench 23 can be a strip trench. These second trenches 23 electrically isolate the plurality of second source regions 22 of the second device 2 from each other. As shown in FIG. 2, the second trench 23 of the second device 2 is in communication with a corresponding first trench 13 of the first device 1. In essence, the first trench 13 and the second trench 23 are actually located in the body regions of the first device 1 and the second device 2, respectively, and the first trench 13 and the second trench 23 correspond to the first device 1 respectively. The gate and the gate of the second device 2, that is, the gate of the first device 1 are connected to the gate of the second device 2.
此外，如图2所示，第二器件2的每个第二源区22与第一器件1的相应一个第一源区12相对应，并且第二器件2的每个第二沟槽23与第一器件1的相应一个第一沟槽13相连通。功率器件200还包括多个第三沟槽6。每个第三沟槽6与第二器件2的一个第二源区22相对应，并把与该第二源区22相应的两条第二沟槽23相连通。如图所示，相应地，每个第三沟槽6也与第一器件1的一个第一源区12相对应，并把与该第一源区12相应的两条第一沟槽13相连通。在一个示例中，第三沟槽6可位于金属间距区5内。第三沟槽6不仅起到栅极的作用，还可以使得第二器件2的源区22与第一器件1的相应的源区12充分隔离。在一个示例中，第三沟槽6可以为条形沟槽。第三沟槽6在结构上与第一沟槽13以及第二沟槽23相同。Furthermore, as shown in FIG. 2, each second source region 22 of the second device 2 corresponds to a respective one of the first source regions 12 of the first device 1, and each second trench 23 of the second device 2 is A respective one of the first grooves 13 of the first device 1 is in communication. Power device 200 also includes a plurality of third trenches 6. Each of the third trenches 6 corresponds to a second source region 22 of the second device 2 and communicates with two second trenches 23 corresponding to the second source region 22. As shown, each third trench 6 also corresponds to a first source region 12 of the first device 1 and connects the two first trenches 13 corresponding to the first source region 12, respectively. through. In one example, the third trench 6 can be located within the metal pitch region 5. The third trench 6 not only acts as a gate but also allows the source region 22 of the second device 2 to be sufficiently isolated from the corresponding source region 12 of the first device 1. In one example, the third trench 6 can be a strip trench. The third trench 6 is identical in structure to the first trench 13 and the second trench 23.
更具体地，第二器件2的第二源区22-1与第一器件1的相应一个第一源区12-1相对应。第二器件2的第二沟槽23-1和23-2分别与第一器件1 的相应第一沟槽13-1和13-2相连通。第三沟槽6与第二器件2的第二源区22-1相对应，并把与该第二源区22-1相应的两条第二沟槽23-1和23-2相连通。此外，如图所示，相应地，第三沟槽6也与第一器件1的第一源区12-1相对应，并把与该第一源区12-1相应的两条第一沟槽13-1和13-2相连通。More specifically, the second source region 22-1 of the second device 2 corresponds to a corresponding one of the first source regions 12-1 of the first device 1. The second trenches 23-1 and 23-2 of the second device 2 are respectively associated with the first device 1 The respective first trenches 13-1 and 13-2 are in communication. The third trench 6 corresponds to the second source region 22-1 of the second device 2, and connects the two second trenches 23-1 and 23-2 corresponding to the second source region 22-1. Further, as shown, correspondingly, the third trench 6 also corresponds to the first source region 12-1 of the first device 1, and the two first trenches corresponding to the first source region 12-1 The slots 13-1 and 13-2 are in communication.
此外，如图2所示，第二器件2的多个第二源区22虽然以第二沟槽23被隔开，但是这些第二源区被集中排布，即相邻两个第二源区22间没有相隔任何其他源区。虽然在图2中示出了第二器件2的六个源区以及相应金属接触，但是这仅仅是示意图，第二器件2可以具有更多或更少的源区以及相应金属接触，这依赖于第二器件2与第一器件1的预定比例CSR。In addition, as shown in FIG. 2, the plurality of second source regions 22 of the second device 2 are separated by the second trenches 23, but the second source regions are collectively arranged, that is, adjacent two second sources. Zone 22 is not separated from any other source zone. Although the six source regions of the second device 2 and the corresponding metal contacts are shown in FIG. 2, this is merely a schematic view, and the second device 2 may have more or fewer source regions and corresponding metal contacts, depending on A predetermined ratio CSR of the second device 2 to the first device 1.
图3-图5分别示出图2中沿A-A、B-B、C-C的剖面视图。图3示出图2中沿A-A的剖面视图。返回参考图2，A-A线跨越第一器件1的金属区和第二器件2的金属区，并且A-A线的两端正好位于第一器件1的源区金属接触14和第二器件2的源区金属接触24上。如图3所示，第一器件1与第二器件2形成于同一衬底3上。在一个实施例中，第一器件1可以与第二器件2形成在P+N型衬底或N+N型衬底上。3 to 5 respectively show cross-sectional views along A-A, B-B, and C-C in Fig. 2. Figure 3 is a cross-sectional view along line A-A of Figure 2. Referring back to FIG. 2, the AA line spans the metal region of the first device 1 and the metal region of the second device 2, and both ends of the AA line are located just in the source region of the first device 1 and the source region of the second device 2. Metal contacts 24 on. As shown in FIG. 3, the first device 1 and the second device 2 are formed on the same substrate 3. In one embodiment, the first device 1 may be formed on the P+N type substrate or the N+N type substrate with the second device 2.
此外，如图3所示，在衬底3上，形成有源区。有源区由N型层和P型层构成。沟槽6形成于有源区中。在P型层上形成有N+层，并且在P型层和N+层中形成P+区。填充有多晶硅的沟槽6上方沉积有氧化层10。氧化层10的两侧分别为第一器件1的金属11和第二器件2的金属21，第一器件1的金属11和第二器件2的金属21通过金属间距区5被隔离开，相应地，第一器件1的源区12和第二器件2的源区22被电学隔离。填充有多晶硅的沟槽6不仅起到连通第一器件1和第二器件2的栅极的作用，也助于把第一器件1的源区12和第二器件2的源区22充分隔离开。第一器件1和第二器件2分别经由各自的源区通过相应的金属接触14和24沿着表示电流流向的箭头I1和I2收集各自的电流。Further, as shown in FIG. 3, on the substrate 3, an active region is formed. The active region is composed of an N-type layer and a P-type layer. A trench 6 is formed in the active region. An N+ layer is formed on the P-type layer, and a P+ region is formed in the P-type layer and the N+ layer. An oxide layer 10 is deposited over the trenches 6 filled with polysilicon. The two sides of the oxide layer 10 are respectively the metal 11 of the first device 1 and the metal 21 of the second device 2, and the metal 11 of the first device 1 and the metal 21 of the second device 2 are separated by the metal pitch region 5, correspondingly The source region 12 of the first device 1 and the source region 22 of the second device 2 are electrically isolated. The trenches 6 filled with polysilicon not only serve to connect the gates of the first device 1 and the second device 2, but also help to sufficiently isolate the source region 12 of the first device 1 and the source region 22 of the second device 2. . The first device 1 and the second device 2 collect respective currents via respective metal contacts 14 and 24 via respective metal contacts 14 and 24 along arrows I1 and I2 indicating current flow.
图4示出图2中沿B-B的剖面视图。返回参考图2，B-B线跨越第一器件1的金属11和第二器件2的金属21，并且B-B线的一端正好位于第 一器件1的源区金属接触14上，而另一端没有对应第二器件2的源区金属接触。参考图4，第一器件1与第二器件2形成于同一衬底3上，并且第一器件1的金属11与第二器件2的金属21被金属间距区5隔开。由于B-B线的一端正好位于第一器件1的源区金属接触14上，因此，第一器件1可以经由第一源区通过第一金属接触14收集电流。然而，B-B线的另一端由于没有对应第二器件2的源区金属接触，所以第二器件2不在此处收集电流。如图所示，氧化层10以及第二器件2的金属21的下方的区域中的电流都由第一器件1经由第一源区通过第一金属接触14来收集。Figure 4 shows a cross-sectional view along line B-B of Figure 2. Referring back to FIG. 2, the B-B line spans the metal 11 of the first device 1 and the metal 21 of the second device 2, and one end of the B-B line is located exactly The source region of one device 1 is in metal contact 14 and the other end is not in contact with the source region of the second device 2. Referring to FIG. 4, the first device 1 and the second device 2 are formed on the same substrate 3, and the metal 11 of the first device 1 and the metal 21 of the second device 2 are separated by the metal pitch region 5. Since one end of the B-B line is located just above the source metal contact 14 of the first device 1, the first device 1 can collect current through the first metal contact 14 via the first source region. However, the other end of the B-B line does not have a source metal contact corresponding to the second device 2, so the second device 2 does not collect current here. As shown, the current in the region below the oxide layer 10 and the metal 21 of the second device 2 is collected by the first device 1 via the first source region through the first metal contact 14.
图5示出图2中沿C-C的剖面视图。返回参考图2，C-C线跨越第一器件1的金属11和第二器件2的金属21，并且C-C线垂直并跨越5个沟槽。参考图5，第一器件1与第二器件2形成于同一衬底3上，并且第一器件1的金属11与第二器件2的金属21通过金属间距区5被电学隔离。氧化层10的下方(即位于金属间距区)的中间沟槽也有助于第一器件1的金属11与第二器件2的金属21的隔离。此外，随着远离中间沟槽，C-C线一端进入第一器件1的金属区，另一端进入第二器件2的金属区。在第一器件1部分，有另外两个沟槽13，并且这两个沟槽间存在第一源区的第一金属接触14，在两个沟槽13之间的部分，电流通过该金属接触14被收集。另一方面，在第二器件2部分，也另有两个沟槽23，并且这两个沟槽23间存在第二源区的第二金属接触24，在两个沟槽23之间的部分，电流通过该金属接触24被收集。如此，第一器件1和第二器件2分别沿着图中所示表示电流流向的箭头I1和I2而各自收集自己的电流。Figure 5 shows a cross-sectional view along line C-C of Figure 2. Referring back to FIG. 2, the C-C line spans the metal 11 of the first device 1 and the metal 21 of the second device 2, and the C-C line is perpendicular and spans 5 trenches. Referring to FIG. 5, the first device 1 and the second device 2 are formed on the same substrate 3, and the metal 11 of the first device 1 and the metal 21 of the second device 2 are electrically isolated by the metal pitch region 5. The intermediate trench below the oxide layer 10 (i.e., in the metal pitch region) also contributes to the isolation of the metal 11 of the first device 1 from the metal 21 of the second device 2. Further, as it is away from the intermediate trench, one end of the C-C line enters the metal region of the first device 1, and the other end enters the metal region of the second device 2. In the first device 1 portion, there are two further trenches 13, and there is a first metal contact 14 of the first source region between the two trenches, at a portion between the two trenches 13, a current is passed through the metal contact 14 was collected. On the other hand, in the second device 2 portion, there are also two other trenches 23, and a second metal contact 24 of the second source region exists between the two trenches 23, a portion between the two trenches 23 Current is collected through the metal contact 24. Thus, the first device 1 and the second device 2 respectively collect their own currents along the arrows I1 and I2 indicating the current flow direction as shown in the drawing.
应注意，在根据本公开实施例的功率器件中，第二器件2与第一器件1的体区内除了沟槽之外的部分均为有源区。也就是说，除了第二器件2和第一器件1本身的有源区外，在第二器件2与第一器件1的相嵌部分(包括如间隔第二器件2的源区与第一器件1的源区的金属间距区的部分，第二器件2的金属下方的第一器件1的源区部分(这部分上层的第二器件2的金属即为第二器件2的源极引出线))没有另外的高浓度扩散区，即并没有去源区。如此，第二器件2的嵌入是平顺的并不会给第一器件1造成结构上的改变，因此不会对第一器件1的电流电压性能造成任何 不利影响。此外，第二器件2与第一器件1相嵌部分由于没有去源区，因此这部分仍可以对电流提供做出贡献，从而没有任何芯片面积浪费。It should be noted that in the power device according to an embodiment of the present disclosure, portions of the second device 2 and the body region of the first device 1 other than the trench are active regions. That is, in addition to the second device 2 and the active region of the first device 1 itself, the embedded portion of the second device 2 and the first device 1 (including the source region and the first device such as the spacer second device 2) a portion of the metal pitch region of the source region of 1 , a source region portion of the first device 1 under the metal of the second device 2 (the metal of the second device 2 of the upper portion is the source lead-out line of the second device 2) There is no additional high concentration diffusion zone, ie there is no source zone. As such, the embedding of the second device 2 is smooth and does not cause a structural change to the first device 1, and thus does not cause any current or voltage performance of the first device 1. Negative Effects. In addition, since the second device 2 is embedded in the portion of the first device 1 because there is no source region, this portion can still contribute to the current supply, so that there is no waste of any chip area.
图6是示出根据本公开另一个示例性实施例的功率第二器件300的平面视图。如图6所示，与图2中所示的功率器件200相同，功率器件300包括第一器件1和第二器件2。第二器件2内嵌于第一器件1中，并且第二器件2与第一器件1通过金属间距区5被隔离。此外，第一器件1具有多个源区12和多个沟槽13。这些第一沟槽13把第一器件1的多个源区12彼此电学隔离。第二器件2具有多个源区22和多个沟槽23。这些第二沟槽23把第二器件2的多个源区22彼此电学隔离。此外，同样地，第二器件2的沟槽23与第一器件1的沟槽13相连通，并且第二器件2的源区22集中排布。FIG. 6 is a plan view showing a power second device 300 according to another exemplary embodiment of the present disclosure. As shown in FIG. 6, like the power device 200 shown in FIG. 2, the power device 300 includes a first device 1 and a second device 2. The second device 2 is embedded in the first device 1 and the second device 2 is isolated from the first device 1 by a metal pitch region 5. Furthermore, the first device 1 has a plurality of source regions 12 and a plurality of trenches 13. These first trenches 13 electrically isolate the plurality of source regions 12 of the first device 1 from each other. The second device 2 has a plurality of source regions 22 and a plurality of trenches 23. These second trenches 23 electrically isolate the plurality of source regions 22 of the second device 2 from each other. Further, likewise, the trench 23 of the second device 2 is in communication with the trench 13 of the first device 1, and the source region 22 of the second device 2 is arranged in a concentrated manner.
图6中的功率器件300与图2所示的功率器件200不同之处在于源区和沟槽的布置方式。因此，关于与图2所示的功率器件200一致的方面及细节，在此不再赘述。下面详细讨论功率器件300的源区和沟槽的布置方式。The power device 300 of FIG. 6 differs from the power device 200 of FIG. 2 in the arrangement of source regions and trenches. Therefore, aspects and details consistent with the power device 200 shown in FIG. 2 are not described herein again. The arrangement of the source regions and trenches of power device 300 is discussed in detail below.
如图6所示，在本示例实施例中，第二器件2的每个第二源区22与第一器件1的相应两个第一源区12相对应，并且功率器件22还包括多个第四沟槽7，每个第四沟槽7呈三端形，与第二器件2的一个第二源区22相对应，并把与该第二源区22相应的两个第二沟槽23和与该第二源区22相应的两个第一源区12之间的第一沟槽13相连通。更具体地，第二器件2的源区22-1有两个相应的第二沟槽23-1和23-2，并且与第一器件1的两个第一源区12-1和12-2相对应。这两个第一源区12-1和12-2之间具有第一沟槽13-1。第四沟槽7呈三端形，与第二源区22-1相对应，并把第二沟槽23-1和23-2和第一沟槽13-1相连通，其中三端形的两端分别与第二沟槽23-1和23-2相接，另一端与第一沟槽13-1相接。在图8中，具体地，三端形为T形。然而，三端形可以为其他形状，如任意角度的Y形。As shown in FIG. 6, in the present exemplary embodiment, each second source region 22 of the second device 2 corresponds to a respective two first source regions 12 of the first device 1, and the power device 22 further includes a plurality of a fourth trench 7, each of the fourth trenches 7 having a three-terminal shape corresponding to a second source region 22 of the second device 2 and having two second trenches corresponding to the second source region 22 23 and the first trench 13 between the two first source regions 12 corresponding to the second source region 22 are in communication. More specifically, the source region 22-1 of the second device 2 has two corresponding second trenches 23-1 and 23-2, and with the two first source regions 12-1 and 12 of the first device 1 - 2 corresponds. There is a first trench 13-1 between the two first source regions 12-1 and 12-2. The fourth trench 7 has a three-terminal shape corresponding to the second source region 22-1, and connects the second trenches 23-1 and 23-2 with the first trench 13-1, wherein the three ends are The two ends are respectively connected to the second grooves 23-1 and 23-2, and the other ends are in contact with the first grooves 13-1. In Fig. 8, specifically, the three end shapes are T-shaped. However, the triad may have other shapes, such as a Y shape at any angle.
图7-图8分别示出图6中沿D-D、E-E的剖面视图。图7示出图6中沿D-D的剖面视图。返回参考图6，D-D线跨越第一器件1的金属区和第二器件2的金属区，并且D-D线经过的位置不经过任何源区金属接触。参 考图7，第一器件1与第二器件2形成于同一衬底3上，并且第一器件1的金属11与第二器件2的金属21被金属间距区5隔开。氧化层10下方的体区内形成有沟槽7，此沟槽7用于连通第一器件1的沟槽和第二器件2的沟槽。由于D-D线经过的位置不经过任何源区金属接触，因此在图7没有电流表述。7 to 8 are cross-sectional views along D-D and E-E, respectively, of Fig. 6. Figure 7 shows a cross-sectional view along D-D in Figure 6. Referring back to FIG. 6, the D-D line spans the metal region of the first device 1 and the metal region of the second device 2, and the position through which the D-D line passes does not pass through any source region metal contact. Reference Referring to FIG. 7, the first device 1 and the second device 2 are formed on the same substrate 3, and the metal 11 of the first device 1 and the metal 21 of the second device 2 are separated by the metal pitch region 5. A trench 7 is formed in the body region below the oxide layer 10 for communicating the trench of the first device 1 and the trench of the second device 2. Since the position through which the D-D line passes does not pass through any source metal contact, there is no current expression in Figure 7.
图8示出图6中沿E-E的剖面视图。返回参考图6，E-E线跨越第一器件1的金属11和第二器件2的金属21，并且E-E线垂直并跨越3个沟槽。参考图8，第一器件1与第二器件2形成于同一衬底3上，并且第一器件1的金属11与第二器件2的金属21通过金属间距区5被电学隔离。氧化层10的下方(即位于金属间距区)的中间沟槽也有助于第一器件1的金属11与第二器件2的金属21的隔离。此外，随着远离中间沟槽，E-E线一端进入第一器件1的金属区，另一端进入第二器件2的金属区。在第一器件1部分，有另外一个沟槽13，并且这个沟槽的左端存在第一源区的金属接触14，电流通过该金属接触14被收集。另一方面，在第二器件2部分，也另有一个沟槽23，并且这个沟槽23的右端存在第二源区的金属接触24，电流通过该金属接触24被收集。如此，第一器件1和第二器件2分别沿着图中所示表示电流流向的箭头I1和I2而各自收集自己的电流。Figure 8 is a cross-sectional view along line E-E of Figure 6. Referring back to FIG. 6, the E-E line spans the metal 11 of the first device 1 and the metal 21 of the second device 2, and the E-E line is perpendicular and spans 3 trenches. Referring to FIG. 8, the first device 1 and the second device 2 are formed on the same substrate 3, and the metal 11 of the first device 1 and the metal 21 of the second device 2 are electrically isolated by the metal pitch region 5. The intermediate trench below the oxide layer 10 (i.e., in the metal pitch region) also contributes to the isolation of the metal 11 of the first device 1 from the metal 21 of the second device 2. Further, as it is away from the intermediate trench, one end of the E-E line enters the metal region of the first device 1, and the other end enters the metal region of the second device 2. In the first device 1 portion, there is another trench 13 and the left end of this trench has a metal contact 14 of the first source region through which current is collected. On the other hand, in the second device 2 portion, there is also a trench 23, and at the right end of this trench 23 there is a metal contact 24 of the second source region through which current is collected. Thus, the first device 1 and the second device 2 respectively collect their own currents along the arrows I1 and I2 indicating the current flow direction as shown in the drawing.
图9是示出了图6中的不同位置601～602处的剖面视图。返回参考图6，位置601位于第一器件1的区域，并跨越了沟槽13及其两边的源区金属接触14；位置602位于第二器件2的区域，并跨越了T形沟槽7的头部部分，并且一端位于第二器件2的源区金属接触上。参考图9，分别用(a)和(b)图来示出了位置601和602的剖面视图。对于位置601，最上层均布满第一器件1的金属11。由于位置601位于沟槽13上，因此该视图中图示出了沟槽13。沟槽13用于把第一器件1的源区12隔离开。由于位置601的两端位于第一器件1的源区金属接触14上，因此在图9(a)中图示出了两个金属接触14，并且这两个金属接触14分别沿着表示电流流动的箭头I收集各自的电流。Figure 9 is a cross-sectional view showing different positions 601 to 602 in Figure 6. Referring back to FIG. 6, location 601 is located in the region of first device 1 and spans the source region 14 of the trench 13 and its sides; position 602 is located in the region of the second device 2 and spans the T-shaped trench 7 The head portion and one end are located on the metal contact of the source region of the second device 2. Referring to Figure 9, cross-sectional views of positions 601 and 602 are shown in Figures (a) and (b), respectively. For position 601, the uppermost layer is covered with the metal 11 of the first device 1. Since the location 601 is located on the trench 13, the trench 13 is illustrated in this view. The trench 13 serves to isolate the source region 12 of the first device 1. Since both ends of the location 601 are located on the source metal contact 14 of the first device 1, two metal contacts 14 are illustrated in Figure 9(a), and the two metal contacts 14 respectively represent current flow Arrow I collects the respective currents.
对于位置602，最上层均布满第一器件2的金属21。由于位置602跨 越沟槽7，因此该视图中图示出了沟槽7。沟槽13用于把第一器件1的源区和第二器件2的源区隔离开。由于位置602的一端位于第二器件2的源区金属接触24上，因此在图9(b)中图示出了一个金属接触24，并且这个金属接触24沿着表示电流流动的箭头I收集电流。For position 602, the uppermost layer is covered with metal 21 of the first device 2. Due to location 602 cross The more the groove 7, the groove 7 is illustrated in this view. The trench 13 serves to isolate the source region of the first device 1 from the source region of the second device 2. Since one end of the location 602 is located on the source metal contact 24 of the second device 2, a metal contact 24 is illustrated in Figure 9(b) and this metal contact 24 collects current along an arrow I indicative of current flow. .
应注意，在图6中还示出了位置603。位置603处的结构与位置601处的结构相同，只不过上层的金属和源区接触为第二器件2的金属和源区接触，这在图9(a)中被标注为21和24，另外，沟槽相应得被标注为23。It should be noted that position 603 is also shown in FIG. The structure at location 603 is the same as the structure at location 601 except that the metal and source regions of the upper layer are in contact with the metal and source regions of the second device 2, which are labeled 21 and 24 in Figure 9(a), The groove is correspondingly labeled as 23.
还应注意，在根据本公开实施例的功率器件中，第二器件2与第一器件1的体区内除了沟槽之外的部分均为有源区。也就是说，除了第二器件2和第一器件1本身的有源区外，在第二器件2与第一器件1的相嵌部分(包括如间隔第二器件2的源区与第一器件1的源区的金属间距区的部分，第二器件2的金属下方的第一器件1的源区部分(这部分上层的第二器件2的金属即为第二器件2的源极引出线))没有另外的高浓度扩散区，即并没有去源区。如此，第二器件2的嵌入是平顺的并不会给第一器件1造成结构上的改变，因此不会对第一器件1的电流电压性能造成任何不利影响。此外，第二器件2与第一器件1相嵌部分由于没有去源区，因此这部分仍可以对电流提供做出贡献，从而没有任何芯片面积浪费。图10是示出根据本公开另一个示例性实施例的功率器件400的平面视图。如图10所示，与图2中所示的功率器件200相同，功率器件400包括第一器件1和第二器件2。第二器件2内嵌于第一器件1中，并且第二器件2与第一器件1通过金属间距区5被隔离。此外，第一器件1具有多个源区12和多个沟槽13。这些第一沟槽13把第一器件1的多个金属接触12彼此电学隔离。第二器件2具有多个第二源区22和多个第二沟槽23。这些第二沟槽23把第二器件2的多个源区22彼此电学隔离。此外，第二器件2的第二沟槽23与第一器件1的第一沟槽13相连通，并且第二器件2的源区22集中排布。It should also be noted that in the power device according to an embodiment of the present disclosure, portions of the second device 2 and the body region of the first device 1 other than the trenches are active regions. That is, in addition to the second device 2 and the active region of the first device 1 itself, the embedded portion of the second device 2 and the first device 1 (including the source region and the first device such as the spacer second device 2) a portion of the metal pitch region of the source region of 1 , a source region portion of the first device 1 under the metal of the second device 2 (the metal of the second device 2 of the upper portion is the source lead-out line of the second device 2) There is no additional high concentration diffusion zone, ie there is no source zone. As such, the embedding of the second device 2 is smooth and does not cause structural changes to the first device 1, and thus does not adversely affect the current-voltage performance of the first device 1. In addition, since the second device 2 is embedded in the portion of the first device 1 because there is no source region, this portion can still contribute to the current supply, so that there is no waste of any chip area. FIG. 10 is a plan view showing a power device 400 according to another exemplary embodiment of the present disclosure. As shown in FIG. 10, like the power device 200 shown in FIG. 2, the power device 400 includes a first device 1 and a second device 2. The second device 2 is embedded in the first device 1 and the second device 2 is isolated from the first device 1 by a metal pitch region 5. Furthermore, the first device 1 has a plurality of source regions 12 and a plurality of trenches 13. These first trenches 13 electrically isolate the plurality of metal contacts 12 of the first device 1 from each other. The second device 2 has a plurality of second source regions 22 and a plurality of second trenches 23. These second trenches 23 electrically isolate the plurality of source regions 22 of the second device 2 from each other. Furthermore, the second trench 23 of the second device 2 is in communication with the first trench 13 of the first device 1, and the source regions 22 of the second device 2 are arranged centrally.
图10中的功率器件400与图2所示的功率器件200不同之处在于源区和沟槽的布置方式。因此，关于与图2所示的功率器件200一致的方面及 细节，在此不再赘述。下面详细讨论功率器件400的源区和沟槽的布置方式。The power device 400 of FIG. 10 differs from the power device 200 of FIG. 2 in the arrangement of the source regions and trenches. Therefore, regarding aspects consistent with the power device 200 shown in FIG. 2 and Details will not be described here. The arrangement of the source regions and trenches of power device 400 is discussed in detail below.
如图10所示，在本示例实施例中，第二器件2的每个第二源区22与第一器件1的相应一个第一源区12相对应，并且第二器件2的每个第二沟槽23与第一器件1的相应一个第一沟槽13相连通。与功率器件200不同，功率器件400不具有如图2所示的第三沟槽6。而是，第二器件2的第二源区22的金属接触24与第一器件1的相应第一源区12的金属接触14之间相距一定距离L，使得电流再不能沿平面横向流动，从而实现第一器件1和第二器件2的源区的充分隔离。在一个示例中，距离L可以在10μm～50μm之间。应理解，此距离越小越好，只要能够达到使得电流不再能沿平面横向移动的目的即可。As shown in FIG. 10, in the present exemplary embodiment, each of the second source regions 22 of the second device 2 corresponds to a corresponding one of the first source regions 12 of the first device 1, and each of the second devices 2 The two trenches 23 are in communication with a corresponding one of the first trenches 13 of the first device 1. Unlike power device 200, power device 400 does not have a third trench 6 as shown in FIG. Rather, the metal contact 24 of the second source region 22 of the second device 2 is at a distance L from the metal contact 14 of the respective first source region 12 of the first device 1 such that the current can no longer flow laterally along the plane, thereby Sufficient isolation of the source regions of the first device 1 and the second device 2 is achieved. In one example, the distance L may be between 10 μm and 50 μm. It should be understood that the smaller the distance, the better, as long as the purpose of making the current no longer move laterally along the plane can be achieved.
图11-图14分别示出图10中沿F-F、G-G、H-H的剖面视图。图11示出图10中沿F-F的剖面视图。返回参考图10，F-F线跨越第一器件1的金属区和第二器件2的金属区，并且F-F线的两端正好位于第一器件1的源区12的金属接触和第二器件2的源区22的金属接触上。如图11所示，第一器件1的金属11和第二器件2的金属21通过金属间距区5被相隔开。金属层下方为氧化层10。第一器件1的第一源区12和第二器件2的第二源区22之间没有沟槽，而是通过相距一定距离来使得电流不再能横向流动。如图所示，第一器件1和第二器件2分别经由源区12和22通过金属接触14和24沿着表示电流流向的箭头I1和I2收集各自的电流。如此，第二器件2的电流收集不会影响第一器件1的正常工作。11 to 14 are cross-sectional views along F-F, G-G, and H-H, respectively, of Fig. 10. Figure 11 is a cross-sectional view along line F-F of Figure 10. Referring back to FIG. 10, the FF line spans the metal region of the first device 1 and the metal region of the second device 2, and both ends of the FF line are located just in the metal contact of the source region 12 of the first device 1 and the source of the second device 2. The metal of zone 22 is in contact. As shown in FIG. 11, the metal 11 of the first device 1 and the metal 21 of the second device 2 are separated by a metal pitch region 5. Below the metal layer is an oxide layer 10. There is no trench between the first source region 12 of the first device 1 and the second source region 22 of the second device 2, but rather the distance between the first source region 12 of the second device 2 is such that the current is no longer laterally flowable. As shown, the first device 1 and the second device 2 collect respective currents along the arrows I1 and I2 representing the direction of current flow through the metal contacts 14 and 24 via the source regions 12 and 22, respectively. As such, the current collection of the second device 2 does not affect the normal operation of the first device 1.
图12示出图10中沿G-G的剖面视图。返回参考图10，G-G线横越第二器件2的金属区并且两端分别位于第一器件1的两侧的第一源区12的金属接触14上。参考图12，第一器件1的金属11和第二器件2的金属21通过金属间距区5被相隔开。金属层下方为氧化层10。由于在第二器件2的金属区中G-G经过的位置处布置有第二器件2的源区金属接触24，所以第二器件2沿着表示电流流动的箭头I2收集电流，而是第一器件1经由G-G线两侧的第一源区12通过金属接触14收集电流，如图中所示的表示电流流向的箭头I1。 Figure 12 is a cross-sectional view along line G-G of Figure 10. Referring back to FIG. 10, the G-G line traverses the metal region of the second device 2 and the two ends are respectively located on the metal contacts 14 of the first source region 12 on both sides of the first device 1. Referring to FIG. 12, the metal 11 of the first device 1 and the metal 21 of the second device 2 are separated by a metal pitch region 5. Below the metal layer is an oxide layer 10. Since the source metal contact 24 of the second device 2 is disposed at a position where the GG passes in the metal region of the second device 2, the second device 2 collects current along an arrow I2 indicating current flow, but the first device 1 Current is collected through the metal contact 14 via the first source region 12 on either side of the GG line, as indicated by the arrow I1 indicating the direction of current flow.
图13示出图10中沿H-H的剖面图。返回参考图10，H-H完全落在第一器件1的区域，并跨越3个沟槽13，并且H-H线跨越2个源区金属接触14。参考图13，最上层均为第一器件1的金属11。金属层下方为氧化层10。氧化层10下方的体区内具有3个沟槽13。最左边的沟槽13与中间的沟槽之间没有源区金属接触。此外，由于H-H线跨越了2个源区金属接触14，因此在该剖视图中也相应地图示出2个源区金属接触14。通过这两个源区金属接触14，相应沟槽间的电流分别沿着表示电流流向的箭头I1被收集。Figure 13 is a cross-sectional view taken along line H-H of Figure 10. Referring back to FIG. 10, H-H falls completely in the region of the first device 1 and spans three trenches 13, and the H-H line spans the two source metal contacts 14. Referring to Figure 13, the uppermost layer is the metal 11 of the first device 1. Below the metal layer is an oxide layer 10. There are three grooves 13 in the body region below the oxide layer 10. There is no source region metal contact between the leftmost trench 13 and the intermediate trench. Furthermore, since the H-H line spans the two source metal contacts 14, the two source metal contacts 14 are also mapped accordingly in this cross-sectional view. Through the two source metal contacts 14, the current between the respective trenches is collected along an arrow I1 representing the direction of current flow, respectively.
图14示出图10中位置1001处的剖面视图。返回参考图10，位置1001落在第二器件2的区域，跨越1个沟槽23，并且一端位于源区金属接触24上。参考图14，最上层均为第二器件2的金属21。在中间部分，由于第二器件2的源区22跨越1个沟槽23，所以在剖面视图中此处示出了沟槽23。从中间部分往右，由于位置1001的一端正位于源区金属接触24上，所以在剖面视图中示出了金属接触24，并且该金属接触24沿着表示电流流向的箭头I2收集电流。Figure 14 shows a cross-sectional view at position 1001 in Figure 10. Referring back to FIG. 10, location 1001 falls within the area of second device 2, spans one trench 23, and one end is located on source metal contact 24. Referring to Figure 14, the uppermost layer is the metal 21 of the second device 2. In the middle portion, since the source region 22 of the second device 2 spans one trench 23, the trench 23 is shown here in cross-sectional view. From the middle to the right, since one end of the position 1001 is located on the source metal contact 24, the metal contact 24 is shown in cross-section and the metal contact 24 collects current along an arrow I2 indicating the direction of current flow.
同样地，应注意，在根据本公开实施例的功率器件中，第二器件2与第一器件1的体区内除了沟槽之外的部分均为有源区。也就是说，除了第二器件2和第一器件1本身的有源区外，在第二器件2与第一器件1的相嵌部分(包括如间隔第二器件2的源区与第一器件1的源区的金属间距区的部分，第二器件2的金属下方的第一器件1的源区部分(这部分上层的第二器件2的金属即为第二器件2的源极引出线))没有另外的高浓度扩散区，即并没有去源区。如此，第二器件2的嵌入是平顺的并不会给第一器件1造成结构上的改变，因此不会对第一器件1的电流电压性能造成任何不利影响。此外，第二器件2与第一器件1相嵌部分由于没有去源区，因此这部分仍可以对电流提供做出贡献，从而没有任何芯片面积浪费。Also, it should be noted that in the power device according to the embodiment of the present disclosure, the portions other than the trenches in the body region of the second device 2 and the first device 1 are active regions. That is, in addition to the second device 2 and the active region of the first device 1 itself, the embedded portion of the second device 2 and the first device 1 (including the source region and the first device such as the spacer second device 2) a portion of the metal pitch region of the source region of 1 , a source region portion of the first device 1 under the metal of the second device 2 (the metal of the second device 2 of the upper portion is the source lead-out line of the second device 2) There is no additional high concentration diffusion zone, ie there is no source zone. As such, the embedding of the second device 2 is smooth and does not cause structural changes to the first device 1, and thus does not adversely affect the current-voltage performance of the first device 1. In addition, since the second device 2 is embedded in the portion of the first device 1 because there is no source region, this portion can still contribute to the current supply, so that there is no waste of any chip area.
上面通过实施例描述了根据本公开的功率器件的结构。应理解，源区和沟槽的数量可以与所描述的实施例相同或不同。还应注意，第二器件与第一器件在图中左半部分和右半部分的结构是相同的，关于左半部分的描述也适用于右半部分的相应结构，并且关于右半部分的描述也适用于左半 部分的相应结构。The structure of the power device according to the present disclosure has been described above by way of embodiments. It should be understood that the number of source regions and trenches may be the same or different than the described embodiments. It should also be noted that the structure of the second device and the first device in the left half and the right half of the figure are the same, the description about the left half also applies to the corresponding structure of the right half, and the description about the right half Also applies to the left half Part of the corresponding structure.
本公开还提供一种功率器件的制备方法。图15示出了根据本发明一个示例实施例的功率器件的制备方法1500。如图15所示，方法1500包括：S1501，提供衬底。接下来，在步骤S1502，在衬底上形成第一器件的体区和至少一个第二器件的体区。在步骤S1503，在第一器件的体区内形成多个第一沟槽，并在第二器件的体区内形成多个第二沟槽，其中，第二器件的第二沟槽与第一器件的相应的第一沟槽相连通。最后在步骤S1504中，形成用于第一器件的多个第一源区和用于第二器件的多个第二源区，其中，多个第一源区通过多个第一沟槽被彼此电学隔离，多个第二源区通过多个第二沟槽被彼此电学隔离，其中，第二器件的第二源区与第一器件的第一源区通过金属间距区被电学隔离，其中第一器件和第二器件的体区内除了第一沟槽和第二沟槽的部分均为有源区。The present disclosure also provides a method of fabricating a power device. FIG. 15 illustrates a method 1500 of fabricating a power device in accordance with an example embodiment of the present invention. As shown in FIG. 15, method 1500 includes: S1501, providing a substrate. Next, in step S1502, a body region of the first device and a body region of the at least one second device are formed on the substrate. In step S1503, a plurality of first trenches are formed in the body region of the first device, and a plurality of second trenches are formed in the body region of the second device, wherein the second trench of the second device is first The respective first trenches of the device are in communication. Finally, in step S1504, a plurality of first source regions for the first device and a plurality of second source regions for the second device are formed, wherein the plurality of first source regions are each other through the plurality of first trenches Electrically isolating, the plurality of second source regions are electrically isolated from each other by the plurality of second trenches, wherein the second source region of the second device is electrically isolated from the first source region of the first device by a metal pitch region, wherein Portions of the device and the second device except the first trench and the second trench are active regions.
在一个实现方式中，第二器件的多个第二源区集中排布。In one implementation, the plurality of second source regions of the second device are arranged centrally.
在一个实现方式中，衬底可以为P+N衬底，并且功率器件为绝缘栅双极型晶体管。在一个实现方式中，衬底可以为N+N衬底，并且功率器件为金属氧化物半导体场效应晶体管。In one implementation, the substrate can be a P+N substrate and the power device is an insulated gate bipolar transistor. In one implementation, the substrate can be an N+N substrate and the power device is a metal oxide semiconductor field effect transistor.
在一个实现方式中，第二器件的每个第二源区与第一器件的相应一个第一源区相对应，所述第二器件的每个第二沟槽与第一器件的相应一个第一沟槽相连通。所述方法1500还包括在金属间距区内形成多个第三沟槽，每个第三沟槽与第二器件的一个第二源区相对应，并把与该第二源区相应的两个第二沟槽相连通。第一沟槽、第二沟槽、第三沟槽在结构上相同。替代地，第一器件的第一源区具有第一金属接触区，第二器件的第二源区具有第二金属接触区，第一金属接触区的边界与相应第二金属接触区的边界相距一定距离，以使得电流不再能沿平面横向流动。In one implementation, each second source region of the second device corresponds to a respective one of the first source regions of the first device, and each of the second trenches of the second device and a corresponding one of the first devices A groove is connected. The method 1500 further includes forming a plurality of third trenches in the metal pitch region, each third trench corresponding to a second source region of the second device, and two corresponding to the second source region The second trenches are in communication. The first trench, the second trench, and the third trench are structurally identical. Alternatively, the first source region of the first device has a first metal contact region, and the second source region of the second device has a second metal contact region, the boundary of the first metal contact region being spaced from the boundary of the corresponding second metal contact region A certain distance so that the current can no longer flow laterally along the plane.
在一个实现方式中，第二器件的每个第二源区与第一器件的相应两个第一源区相对应，并且方法1500还包括在金属间距区内形成多个第四沟槽，每个第四沟槽呈三端形，与第二器件的一个第二源区相对应，并把与该第二源区相应的两个第二沟槽和与该第二源区相应的两个第一源区之间的第一沟槽相连通。第一沟槽、第二沟槽、第四槽在结构上相同。 In one implementation, each second source region of the second device corresponds to a respective two first source regions of the first device, and the method 1500 further includes forming a plurality of fourth trenches in the metal pitch region, each The fourth trench has a three-terminal shape corresponding to a second source region of the second device, and two second trenches corresponding to the second source region and two corresponding to the second source region The first trench between the first source regions is in communication. The first trench, the second trench, and the fourth trench are structurally identical.
如上，借助于具体实施例论述了根据本公开的功率器件及其制备方法。根据本公开的技术，在同一衬底上通过相同的工艺同时制备出第一器件和第二器件，其中第一器件和第二器件被很好地电学隔离。此外，第一器件与第二器件以特有的方式耦合与隔离，并且由于第二器件与第一器件相嵌的部分没有另外的高浓度扩散区(即，没有去源区)，第二器件的嵌入并不会给第一器件造成结构上的改变，因此不会对第一器件的电流电压性能造成任何不利影响。此外，第二器件与第一器件相嵌部分由于没有去源区，因此这部分仍可以对电流提供做出贡献，从而没有任何芯片面积浪费。As above, the power device according to the present disclosure and a method of fabricating the same are discussed by way of specific embodiments. According to the techniques of the present disclosure, the first device and the second device are simultaneously fabricated by the same process on the same substrate, wherein the first device and the second device are well electrically isolated. Furthermore, the first device and the second device are coupled and isolated in a unique manner, and since the portion of the second device that is embedded with the first device has no additional high concentration diffusion regions (ie, no source region), the second device The embedding does not cause a structural change to the first device and therefore does not adversely affect the current-voltage performance of the first device. In addition, since the second device is embedded in the portion of the first device, since there is no source region, this portion can still contribute to the current supply, so that there is no waste of any chip area.
虽然在前述本发明的详细描述中已经出现了至少一个示例性实施例和制备方法，应该意识到仍然存在大量的变换。也应该意识到一个示例性实施例或多个示例性实施例仅仅是作为举例，且目的不在于以任何方式来限制本发明的范围、应用或结构。相反地，前述的详细描述将为本领域技术人员提供一套方便地实施本发明示例性实施例的路线图，应该理解可在示例性实施例中描述的元件的功能和布置上做各种变化，而不脱离本发明如所附权利要求及其法律等同物所阐明的范围。 While at least one exemplary embodiment and method of fabrication have been presented in the foregoing detailed description of the invention, it should be appreciated that a It is also to be understood that the exemplification of the invention, Rather, the foregoing detailed description will provide those skilled in the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The scope of the invention as set forth in the appended claims and their legal equivalents.

Claims (20)

  1. 一种功率器件，包括：A power device comprising:
    第一器件，所述第一器件具有多个第一源区，并具有多个第一沟槽，其中，所述多个第一沟槽把所述多个第一源区彼此电学隔离；a first device, the first device having a plurality of first source regions and having a plurality of first trenches, wherein the plurality of first trenches electrically isolate the plurality of first source regions from each other;
    至少一个第二器件，所述第二器件具有多个第二源区，并具有多个第二沟槽，所述多个第二沟槽把所述多个第二源区彼此电学隔离，其中所述第二器件内嵌在所述第一器件中，并且所述第二器件的所述第二沟槽与所述第一器件的相应的第一沟槽相连通，其中，所述第二器件的第二源区与所述第一器件的第一源区通过金属间距区被电学隔离，并且At least one second device having a plurality of second source regions and having a plurality of second trenches electrically isolating the plurality of second source regions from each other, wherein The second device is embedded in the first device, and the second trench of the second device is in communication with a corresponding first trench of the first device, wherein the second A second source region of the device is electrically isolated from the first source region of the first device by a metal pitch region, and
    其中所述第一器件和所述第二器件的体区内除了沟槽的部分均为有源区。Wherein the portions of the first device and the second device except the trench are active regions.
  2. 根据权利要求1所述的功率器件，其中，所述第二器件的所述多个第二源区集中排布。The power device of claim 1 wherein said plurality of second source regions of said second device are arranged centrally.
  3. 根据权利要求1所述的功率器件，其中，所述第一器件和所述第二器件被形成在P+N衬底上，并且所述功率器件为绝缘栅双极型晶体管。The power device of claim 1, wherein the first device and the second device are formed on a P+N substrate, and the power device is an insulated gate bipolar transistor.
  4. 根据权利要求1所述的功率器件，其中，所述第一器件和所述第二器件被形成在N+N衬底上，并且所述功率器件为金属氧化物半导体场效应晶体管。The power device of claim 1, wherein the first device and the second device are formed on an N+N substrate, and the power device is a metal oxide semiconductor field effect transistor.
  5. 根据权利要求2所述的功率器件，其中，所述第二器件的每个第二源区与所述第一器件的相应一个第一源区相对应，并且所述第二器件的每个第二沟槽与所述第一器件的相应一个第一沟槽直接相连通。The power device of claim 2, wherein each second source region of the second device corresponds to a respective one of the first source regions of the first device, and each of the second devices The two trenches are in direct communication with a respective one of the first trenches of the first device.
  6. 根据权利要求5所述的功率器件，其中，所述功率器件还包括多个第三沟槽，所述第三沟槽位于所述金属间距区内，并且每个所述第三沟槽与所述第二器件的一个第二源区相对应，并把与该第二源区相应的两个第二沟槽相连通。The power device of claim 5, wherein the power device further comprises a plurality of third trenches, the third trench is located in the metal pitch region, and each of the third trenches A second source region of the second device corresponds to the second trench corresponding to the second source region.
  7. 根据权利要求6所述的功率器件，其中，所述第一沟槽、第二沟槽、第三沟槽在结构上相同。The power device of claim 6, wherein the first trench, the second trench, and the third trench are structurally identical.
  8. 根据权利要求5所述的功率器件，其中，所述第一器件的第一源区具有第一金属接触区，所述第二器件的第二源区具有第二金属接触区，所 述第一金属接触区的边界与相应的所述第二金属接触区的边界相距一定距离，以使得电流不再能沿平面横向流动。The power device of claim 5 wherein said first source region of said first device has a first metal contact region and said second source region of said second device has a second metal contact region The boundary of the first metal contact region is at a distance from the boundary of the corresponding second metal contact region such that current can no longer flow laterally along the plane.
  9. 根据权利要求2所述的功率器件，其中，所述第二器件的每个第二源区与所述第一器件的相应两个第一源区相对应，并且所述功率器件还包括多个第四沟槽，每个所述第四沟槽呈三端形，与所述第二器件的一个第二源区相对应，并把与该第二源区相应的两个第二沟槽和与该第二源区相应的两个第一源区之间的第一沟槽相连通。The power device of claim 2 wherein each second source region of said second device corresponds to a respective two first source regions of said first device, and said power device further comprises a plurality a fourth trench, each of the fourth trenches having a three-terminal shape corresponding to a second source region of the second device, and two second trenches corresponding to the second source region A first trench between the two first source regions corresponding to the second source region is in communication.
  10. 根据权利要求9所述的功率器件，其中，所述第一沟槽、第二沟槽、第四槽在结构上相同。The power device of claim 9 wherein said first trench, second trench, and fourth trench are structurally identical.
  11. 一种功率器件的制备方法，包括：A method of preparing a power device, comprising:
    提供衬底；Providing a substrate;
    在衬底上形成第一器件的体区和至少一个第二器件的体区；Forming a body region of the first device and a body region of the at least one second device on the substrate;
    在所述第一器件的体区内形成用于所述第一器件的多个第一沟槽，并在所述第二器件的体区内形成用于所述第二器件的多个第二沟槽，其中，所述第二器件的所述第二沟槽与所述第一器件的相应的第一沟槽相连通；Forming a plurality of first trenches for the first device in a body region of the first device and forming a plurality of second portions for the second device in a body region of the second device a trench, wherein the second trench of the second device is in communication with a corresponding first trench of the first device;
    形成用于所述第一器件的多个第一源区和用于所述第二器件的多个第二源区，其中，所述多个第一源区通过所述多个第一沟槽被彼此电学隔离，所述多个第二源区通过所述多个第二沟槽被彼此电学隔离，其中，所述第二器件的第二源区与所述第一器件的第一源区通过金属间距区被电学隔离，并且Forming a plurality of first source regions for the first device and a plurality of second source regions for the second device, wherein the plurality of first source regions pass through the plurality of first trenches Electrically isolated from each other, the plurality of second source regions being electrically isolated from each other by the plurality of second trenches, wherein the second source region of the second device and the first source region of the first device Electrically isolated by metal pitch zones, and
    其中所述第一器件和所述第二器件的体区内除了沟槽的部分均为有源区。Wherein the portions of the first device and the second device except the trench are active regions.
  12. 根据权利要求11所述的功率器件的制备方法，其所述第二器件的所述多个第二源区集中排布。The method of fabricating a power device according to claim 11, wherein said plurality of second source regions of said second device are arranged in a concentrated manner.
  13. 根据权利要求11所述的功率器件的制备方法，其中，所述第一器件和所述第二器件被形成在P+N衬底上，并且所述功率器件为绝缘栅双极型晶体管。The method of manufacturing a power device according to claim 11, wherein the first device and the second device are formed on a P+N substrate, and the power device is an insulated gate bipolar transistor.
  14. 根据权利要求11所述的功率器件的制备方法，其中，所述第一器件和所述第二器件被形成在N+N衬底上，并且所述功率器件为金属氧化 物半导体场效应晶体管。The method of fabricating a power device according to claim 11, wherein said first device and said second device are formed on an N+N substrate, and said power device is metal oxide Semiconductor field effect transistor.
  15. 根据权利要求12所述的功率器件的制备方法，其中，所述第二器件的每个第二源区与所述第一器件的相应一个第一源区相对应，并且所述第二器件的每个第二沟槽与所述第一器件的相应一个第一沟槽直接相连通。The method of fabricating a power device according to claim 12, wherein each second source region of said second device corresponds to a corresponding one of said first source regions of said first device, and said second device Each of the second trenches is in direct communication with a respective one of the first trenches of the first device.
  16. 根据权利要求15所述的功率器件的制备方法，其中，所述方法还包括在所述金属间距区内形成多个第三沟槽，每个所述第三沟槽与所述第二器件的一个第二源区相对应，并把与该第二源区相应的两个第二沟槽相连通。The method of fabricating a power device according to claim 15, wherein the method further comprises forming a plurality of third trenches in the metal pitch region, each of the third trenches and the second device A second source region corresponds to and connects the two second trenches corresponding to the second source region.
  17. 根据权利要求16所述的功率器件的制备方法，其中，所述第一沟槽、第二沟槽、第三沟槽在结构上相同。The method of fabricating a power device according to claim 16, wherein the first trench, the second trench, and the third trench are structurally identical.
  18. 根据权利要求15所述的功率器件的制备方法，其中，所述第一器件的第一源区具有第一金属接触区，所述第二器件的第二源区具有第二金属接触区，所述第一金属接触区的边界与相应的所述第二金属接触区的边界相距一定距离，以使得电流不再能沿平面横向流动。The method of fabricating a power device according to claim 15, wherein the first source region of the first device has a first metal contact region, and the second source region of the second device has a second metal contact region, The boundary of the first metal contact region is at a distance from the boundary of the corresponding second metal contact region such that current can no longer flow laterally along the plane.
  19. 根据权利要求12所述的功率器件的制备方法，其中，所述第二器件的每个第二源区与所述第一器件的相应两个第一源区相对应，并且所述方法还包括在所述金属间距区内形成多个第四沟槽，每个所述第四沟槽呈三端形，与所述第二器件的一个第二源区相对应，并把与该第二源区相应的两个第二沟槽和与该第二源区相应的两个第一源区之间的第一沟槽相连通。The method of fabricating a power device according to claim 12, wherein each of the second source regions of the second device corresponds to a respective two first source regions of the first device, and the method further comprises Forming a plurality of fourth trenches in the metal pitch region, each of the fourth trenches having a three-terminal shape corresponding to a second source region of the second device, and the second source The corresponding two second trenches of the region and the first trench between the two first source regions corresponding to the second source region are in communication.
  20. 根据权利要求19所述的功率器件的制备方法，其中，所述第一沟槽、第二沟槽、第四槽在结构上相同。 The method of fabricating a power device according to claim 19, wherein the first trench, the second trench, and the fourth trench are structurally identical.
PCT/CN2017/091823 2016-07-14 2017-07-05 Power device and preparation method therefor WO2018010581A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB1901361.4A GB2566895B (en) 2016-07-14 2017-07-05 Power device and method for manufacturing the power device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610556683.8 2016-07-14
CN201610556683.8A CN106229313B (en) 2016-07-14 2016-07-14 Power device and preparation method thereof

Publications (1)

Publication Number Publication Date
WO2018010581A1 true WO2018010581A1 (en) 2018-01-18

Family

ID=57520074

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/091823 WO2018010581A1 (en) 2016-07-14 2017-07-05 Power device and preparation method therefor

Country Status (3)

Country Link
CN (1) CN106229313B (en)
GB (1) GB2566895B (en)
WO (1) WO2018010581A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106229313B (en) * 2016-07-14 2019-12-06 王培林 Power device and preparation method thereof
JP6696450B2 (en) * 2017-01-27 2020-05-20 株式会社デンソー Silicon carbide semiconductor device
CN111564497B (en) * 2020-04-30 2023-04-18 西安理工大学 SiC MOSFET device with non-uniform body diode
CN112968052A (en) * 2020-12-23 2021-06-15 王培林 Planar grid type power device with current sensor and preparation method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103489862A (en) * 2012-06-12 2014-01-01 飞思卡尔半导体公司 Power MOSFET current sensing structure and method
US20160079377A1 (en) * 2014-09-15 2016-03-17 Infineon Technologies Austria Ag Semiconductor Device with Current Sensor
CN106229313A (en) * 2016-07-14 2016-12-14 王培林 Power device and preparation method thereof
CN106783985A (en) * 2016-11-21 2017-05-31 王培林 Power device and preparation method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6822288B2 (en) * 2001-11-20 2004-11-23 General Semiconductor, Inc. Trench MOSFET device with polycrystalline silicon source contact structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103489862A (en) * 2012-06-12 2014-01-01 飞思卡尔半导体公司 Power MOSFET current sensing structure and method
US20160079377A1 (en) * 2014-09-15 2016-03-17 Infineon Technologies Austria Ag Semiconductor Device with Current Sensor
CN106229313A (en) * 2016-07-14 2016-12-14 王培林 Power device and preparation method thereof
CN106783985A (en) * 2016-11-21 2017-05-31 王培林 Power device and preparation method thereof

Also Published As

Publication number Publication date
GB201901361D0 (en) 2019-03-20
CN106229313A (en) 2016-12-14
CN106229313B (en) 2019-12-06
GB2566895B (en) 2021-02-17
GB2566895A (en) 2019-03-27

Similar Documents

Publication Publication Date Title
WO2018010581A1 (en) Power device and preparation method therefor
US8928066B2 (en) Integrated circuit with power and sense transistors
TWI407548B (en) Integration of a sense fet into a discrete power mosfet
CN106463540B (en) Semiconductor device with a plurality of semiconductor chips
US20200273858A1 (en) Semiconductor device and semiconductor package
TWI595651B (en) Semiconductor device with enhanced mobility and method
US10234486B2 (en) Vertical sense devices in vertical trench MOSFET
JP5638645B2 (en) Sensing transistor integrated with high voltage vertical transistor
JP6008377B2 (en) P-channel power MOSFET
CN104969348B (en) Manufacturing silicon carbide semiconductor device
JP2012054378A (en) Semiconductor device
US9293535B2 (en) Power MOSFET current sense structure and method
US20140084361A1 (en) Power semiconductor device
CN107078061B (en) Method for manufacturing semiconductor device
JP2012069838A (en) Power semiconductor device
TWI415256B (en) Power semiconductor device
CN105938847A (en) Semiconductor device with first and second field electrode structures
JP2021015884A (en) Semiconductor device and method of manufacturing the same
JP2010287786A (en) Semiconductor device
JP2006019608A (en) Misfet device
JP6589845B2 (en) Semiconductor device
KR101369973B1 (en) Method of manufacturing power sense mosfet
JP2019176077A (en) Semiconductor device
CN209434191U (en) Slot type power device
JP6183075B2 (en) Semiconductor device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17826918

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 201901361

Country of ref document: GB

Kind code of ref document: A

Free format text: PCT FILING DATE = 20170705

122 Ep: pct application non-entry in european phase

Ref document number: 17826918

Country of ref document: EP

Kind code of ref document: A1