KR101369973B1 - Method of manufacturing power sense mosfet - Google Patents
Method of manufacturing power sense mosfet Download PDFInfo
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- KR101369973B1 KR101369973B1 KR1020130033804A KR20130033804A KR101369973B1 KR 101369973 B1 KR101369973 B1 KR 101369973B1 KR 1020130033804 A KR1020130033804 A KR 1020130033804A KR 20130033804 A KR20130033804 A KR 20130033804A KR 101369973 B1 KR101369973 B1 KR 101369973B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000012535 impurity Substances 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 34
- 230000008569 process Effects 0.000 claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 238000009792 diffusion process Methods 0.000 claims abstract description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 4
- 210000000746 body region Anatomy 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 230000000873 masking effect Effects 0.000 claims description 5
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims description 2
- 229910004298 SiO 2 Inorganic materials 0.000 claims 1
- 210000004027 cell Anatomy 0.000 description 164
- 108091006146 Channels Proteins 0.000 description 30
- 238000009413 insulation Methods 0.000 description 7
- 230000035945 sensitivity Effects 0.000 description 6
- 101000887873 Arabidopsis thaliana Glycolate oxidase 2 Proteins 0.000 description 5
- 230000005669 field effect Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000037361 pathway Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002353 field-effect transistor method Methods 0.000 description 1
- 210000004692 intercellular junction Anatomy 0.000 description 1
- 238000009421 internal insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7826—Lateral DMOS transistors, i.e. LDMOS transistors with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
Abstract
Disclosed is a method for manufacturing a sense MOSFET for power.
According to an embodiment of the present invention, a method for manufacturing a power MOSFET is,
(1) forming a junction bottleneck (JFET) region layer by implanting a first type impurity into the front surface of the N-drift region doped with the first type impurity;
(2) forming a first gate oxide film by depositing an oxide film on the entire surface of the junction bottleneck (JFET) region by a diffusion process or a CVD method;
(3) applying a photoresist layer over the first gate oxide layer and forming a photoresist pattern exposing a sense cell gate region;
(4) using the photoresist pattern as a mask to remove the first gate oxide layer in the senseFET gate region by an etch process;
(5) forming a second gate oxide film in the removed sense cell gate region,
The thickness of the second gate oxide layer may be formed to have a thickness of 80 to 85% of the thickness of the first gate oxide layer.
Description
The present invention relates to a method of manufacturing a sense MOSFET for power with improved reliability for current sensing.
The sense field effect transistor realizes the main cell and the sense cell on one chip, and the ratio of the current to be conducted can be determined by the number of the cells, so that knowing the current flowing to the sense cell can know the current flowing to the whole device.
If an external resistor is connected to the end of the sense cell, a voltage drop occurs across the resistor and the total current can be determined from this voltage. At this time, if the voltage drop across the resistor exceeds the set value, the circuit can be designed so that the gate voltage is grounded to prevent the overcurrent.
Since the proportional constant of the applied voltage and the sensed voltage is proportional to the parallelism of the insulation resistance and the external resistance of the two cells, the two resistance values must be large. The insulation resistance is a constant determined by the structure. It is necessary to design the device with a large insulation resistance so that the proportional constant between the drain voltage and the sensing voltage becomes large.
Ideally, if the main cell and the sense cell are completely separated and the insulation resistance is large, the greater the external resistance connected to the sense cell terminal, the larger the sensed voltage. In practice, however, the main cell and the sense cell must be fabricated on an epitaxial layer formed on one chip, so the two cells are not completely separated physically. For this reason, when an external resistor is connected to the sense cell, current flow may be induced not only in the sense cell but also in the main cell.
Therefore, it is ideal that the insulation resistance existing between the two cells should be large.
20 is a cross-sectional view showing the structure of a conventional sense field effect transistor.
As shown in FIG. 20, in the conventional sense field effect transistor, an n-type
On top of the
Here, one side is the main cell A and the other side is the sense cell part B around the center of the
The
The externally sensed voltage terminal Vc is connected to the
The vertical resistance of the main cell portion A is denoted by the resistance Rm and the vertical resistance of the sensing cell portion B is denoted by the resistance Rs at the positive terminal of the drain voltage Vd to explain the equivalent circuit inside. The horizontal resistance between the main cell A and the sensing cell B at the center is denoted by the resistance Ri.
In this conventional sense field effect transistor, the internal insulation resistance of the epi layer can be reduced by the accumulation layer formed on the contact surface of the silicon. If the insulation resistance of the epi layer becomes small, Layer to the main cell.
In order to overcome this problem, a technology has been developed in which a thick oxide film is adopted in the sense cell and the main cell, and the main cell and the sense cell are formed into chips by calculating the required number of cells according to the current ratio, and separating only the source.
However, if the oxide film is formed thick, the size of the chip is increased and the current sensitivity of the sense cell is decreased.
In addition, when a surge voltage is input or a sudden overload occurs, the main cell through which more current flows than the sense cell is damaged first, and thus the entire chip needs to be replaced, and the reliability as a power switching device occurs.
In order to solve this problem, trench type sense MOSFETs have been developed to form deep trenches between the main cell and the sense cells and to form an insulating material in the grooves.
However, the trench-type sense MOSFET type undergoes additional processes such as trench etch mask generation, trench etch, sacrificial oxide deposition, and stripping, and an additional mask called a hard mask is not sufficient to dig deep trenches. Film quality (usually oxide film or nitride film) deposition is required.
In addition, the trench wall must be smooth because it is a wall to be used as a channel of the MOSFET. However, since the wall is rough at the time of the trench etch, the sacrificial oxide layer needs to be grown and peeled off to smooth the process.
For this reason, the trench sense MOSFET type requires more time and cost than the planner sense MOSFET type.
Also, in the trench type, when the surge voltage is momentarily inputted, the main cell may be damaged before the sense cell is operated.
Therefore, an economical sense MOSFET is required with high current sensing reliability of the sense portion.
The present invention is to provide an economic power sense MOSFET that can reduce the chip size while high current sensing reliability of the sense cell.
Another object of the present invention is to provide a sense MOSFET for a power cell in which a sense cell is operated earlier than a main cell when an abnormal voltage is applied.
It is still another object of the present invention to provide a sense MOSFET for power with high current sensing reliability of a sense cell as a planar type.
According to an aspect of the present invention,
(1) forming a junction bottleneck (JFET) region layer by implanting a first type impurity into the front surface of the N-drift region doped with the first type impurity;
(2) forming a first gate oxide film by depositing an oxide film on the entire surface of the junction bottleneck (JFET) region by a diffusion process or a CVD method;
(3) applying a photoresist layer over the first gate oxide layer and forming a photoresist pattern exposing a sense cell gate region;
(4) using the photoresist pattern as a mask to remove the first gate oxide layer in the senseFET gate region by an etch process;
(5) forming a second gate oxide film in the removed sense cell gate region,
The thickness of the second gate oxide film is provided to have a power sense MOSFET manufacturing method, characterized in that formed to have a thickness of 80 to 85% of the thickness of the first gate oxide film.
Also,
(6) covering the remaining front with polysilicon removed in step (4);
(7) forming a sense cell gate and a main cell MOSFET gate in a region in which the polysilicon is formed using a photo and etching process;
(8) By using the sense cell gate and the main cell MOSFET gate as a mask, a second type of impurity is injected at a low concentration, so that the sense cell gate and the main cell MOSFET gate are used. A body region is formed under the gap, and a sense cell channel region is formed under the outside of the sense cell gate, and a main cell MOSFET channel region under the outside of the main cell MOSFET gate. Forming a;
In step (8), a SenseFET junction bottleneck (JFET) region is formed between the body region and the SenseFET channel region, and the body region and the main cell MOSFET channel region. The main cell MOSFET junction bottleneck (JFET) region is formed therebetween.
According to an embodiment of the present invention, it is possible to improve the current sensing sensitivity, there is an effect that can provide a method of manufacturing a power sense MOSFET to reduce the overall size of the chip of the power sense MOSFET compared to the prior art.
FIG. 1 is a cross-sectional view illustrating a sense amp for power with improved current sensitivity according to an exemplary embodiment of the present invention. Referring to FIG.
2 and 3 show an equivalent circuit of a power sense MOSFET according to an embodiment of the present invention.
4 to 19 illustrate a method of manufacturing a power sensing MOSFET according to an embodiment of the present invention.
20 is a cross-sectional view showing the structure of a conventional sense field effect transistor.
While the present invention has been described in connection with certain exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and similarities.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the power sense MOSFET according to the present invention will be described in detail with reference to the accompanying drawings. In the following description with reference to the accompanying drawings, the same or corresponding components are denoted by the same reference numerals, Is omitted.
It is also to be understood that the terms first, second, etc. used hereinafter are merely reference numerals for distinguishing between identical or corresponding components, and the same or corresponding components are defined by terms such as first, second, no.
In the specification of the present invention, when the first type impurity is an N type impurity, the second type impurity means a P type impurity. Or vice versa.
In addition, the N-type impurities may be replaced by P-type impurities as a whole, and the P-type impurities may also be replaced by N-type impurities as a whole.
FIG. 1 is a cross-sectional view illustrating a sense amp for power with improved current sensitivity according to an exemplary embodiment of the present invention. Referring to FIG.
According to one embodiment of the present invention, the left side is a sense cell region and the right side is a main cell region (Main), which is a center of the P type body region 10 (P - body) formed in the upper portion of the
Referring to FIG. 1, an N +
The N +
An
A P-type body region 10 (P - body) is formed on the center side of the
The P-
The
Junction regions (JFET)
A channel is formed in the channel region while the gate voltage exceeds Vth, and the current is made conductive by the voltage applied between the drain and the source. At this time, the electrons passing through the channel region pass through the junction bottleneck (JFET)
The first region has the effect of lowering the resistance when the current passes to the region where the electrons are driven due to the positive voltage of the gate at the time of turn-on of the gate, thereby preventing the current flow. However, in the case of the second region, a depletion layer is generated due to a reverse voltage applied between the P-body and N-drift on both sides at the time of turn-on, thereby pressing the passage through the current. Due to the pressure of this pathway, the current at turn-on is disturbed, and if both depletion layers blocking this pathway meet each other, the current path is completely blocked and the current can not flow.
Therefore, the width of the junction bottleneck (JFET) must be secured in consideration of the width of the depletion layer.
In the embodiment of the present invention, in the case of the 600V / 1A POWER SENSE MOSFET, when the N-drift concentration is applied to 3.5e14 [cm-3] and the concentration of the P-body 3.0e18 [cm-3] is applied, the junction Appropriate widths of the bottleneck (JFET)
In a preferred embodiment of the present invention, a 600 V / 1A POWER SENSE MOSFET chip was fabricated by applying 4.4 [[μm] to the appropriate width of the junction bottleneck (JFET)
When the width of the junction junction (JFET) region is 4 [μm] or less, the depletion layer does not operate the cell. Also, if the width of the junction bottleneck (JFET) region exceeds 4.5 [mu m], only the chip size becomes large, which is uneconomical.
A SenseFET ohmic contact region 12 'and a main cell MOSFET Ohmic Contact region 12' are formed at the upper outer side of the left and
The
A SenseFET source region 13 'and a main cell
That is, the
A portion of the SenseFET
A portion of the main cell MOSFET
A sense electrode is formed on the upper side so as to cover a portion of the upper portion of the sense electrode (SenseFET) source region 13 'to a portion of the upper portion of the
1, the SenseFET
A main cell MOSFET
According to an embodiment of the present invention, the thickness of the SenseFET
A SenseFET gate 1 'is connected to the upper part of the SenseFET
Also, the gate 1 'of the sense-SenseFET and the
The main cell
2 and 3 show an equivalent circuit of a power sense MOSFET according to an embodiment of the present invention.
Referring to FIGS. 2 and 3, the pad of the
That is, the sense cell source electrode and the main cell MOSFET source electrode are separated. The source of the main cell MOSFETs are all connected at once, the electrodes of the SenseFET source are connected separately from the main cell MOSFET source electrodes, and the gate electrodes are all external to the chip. They are connected together to form a circuit. Meanwhile, the drain electrode is connected to both a sense cell and a main cell MOSFET.
In another embodiment of the present invention, the thickness of the SenseFET
According to an embodiment of the present invention, an example implemented by applying to a power sense MOSFET having a 600 [V] withstand voltage is as follows.
In the experimental value, the breakdown voltage according to the thickness of the oxide film in the case of POWER SENSE MOSFET is tested to 1 [Å] per 1 [V]. However, considering the thickness margin in the oxide deposition process by the diffusion process or the CVD method, the process thickness 750 [Å] shall be adopted.
In addition, in the case of POWER SENSE MOSFET, a voltage exceeding the peak voltage is generated instantaneously, and in the case of the main cell MOSFET gate oxide, 900 [막] is adopted as an ideal oxide thickness in consideration of the voltage variation rate.
In the case of the SenseFET gate oxide film, it must be manufactured to withstand the 600 [V] breakdown voltage, so that 83% of the thickness of the main cell MOSFET
According to the experimental results, even when the thickness of the actual SenseFET gate oxide film is set to 83% of the thickness of the main cell MOSFET gate oxide film, the current of the normal rated state It will not be destroyed or malfunctioned in the state.
For this reason, the main current flows through the main cell MOSFET gate terminal, and only 1/100 of the current flows through the sense cell region. Therefore, the sensing current is normally sensed even though there is some voltage variation in the rated state. .
If the main cell MOSFET gate oxide film and the sense cell gate oxide film have the same thickness and an overvoltage or surge voltage is applied, the main cell MOSFET and the sense cell are simultaneously destroyed. Will occur. This prevents the SenseFET, which is installed to protect the main cell, from functioning.
In the case of the main cell (MOSFET), it should be protected against voltage fluctuation and overcurrent. However, when overvoltage or surge voltage is generated in the sense cell area, it is necessary to protect the circuit by grounding by sensing the current, The SenseFET region must be destroyed before the repair cost can be minimized.
Considering these experimental results, in the case of the SenseFET gate oxide film, it is considered that the thickness considering the voltage variation ratio is not considered in the normal sense operation.
In an exemplary embodiment of the present invention, the gate oxide film in the sense cell region may be formed thinner than the main cell MOSFET gate oxide by not considering a thickness due to a voltage variation rate. By doing this, it is possible to react more sensitively to the change of the gate voltage than the main cell, so that the current sensing sensitivity can be improved.
In addition, if the thickness of the sense cell gate oxide film is reduced, the Vth of the sense cell region becomes smaller than the Vth of the main cell MOSFET, so that the current ratio can be increased, so that the entire sense cell. The number of cells in charge of an area can be reduced.
Therefore, the power MOSFET chip manufactured according to the embodiment of the present invention can reduce the required sense cell area as a whole.
The current equation of the MOSFET is determined by the following equation: I = 1/2 x u x Cox x W / L x Vgs-Vth / 2 As the expression (Vgs-Vth) . When the actual thickness is reduced to 83%, in the conventional case, Vth is reduced from 3 [V] to about 2.5 [V], and the current ratio also increases by about 15%.
Therefore, as the current ratio is increased, the number of cells in charge of the entire sense cell area can be reduced. Thus, a power MOSFET chip manufactured according to an embodiment of the present invention requires a sense cell more than a conventional power MOSFET chip. The area can be reduced.
According to an embodiment of the present invention, the power MOSFET chip manufactured at 600V / 1A sensing ratio and 1/100 size may be manufactured as 8670 main cell MOSFET cells and 72 sense cell cells.
That is, when the sense cell gate oxide film is the same as the main cell (main cell MOSFET) gate oxide film as in the related art, the power cell according to an embodiment of the present invention requires 87, which is 1/100 ratio of the main cell. The chip can reduce the number of SenseFET cells with the same sensing ratio, and can reduce the size of the chip by this reduced number.
Therefore, the power sense MOSFET according to an embodiment of the present invention can improve the current sensing sensitivity, and can reduce the overall size of the chip of the power sense MOSFET compared to the prior art.
4 to 19 illustrate a method of manufacturing a power sensing MOSFET according to an embodiment of the present invention.
According to various embodiments to be described, various steps related to the manufacture of the sense sub-MOSPET are well known, and for the sake of simplicity, conventional known steps are referred to here simply or well known process details. Without providing, only the characteristic steps according to one embodiment of the present invention are introduced.
In addition, the manufacturing method of the power sense MOSFET according to an embodiment of the present invention provides a suitable embodiment of the SENSE POWER MOSFET having a voltage of 600 [V].
Figure 4 shows the step of forming a junction bottleneck (JFET) region.
Referring to FIG. 4, the junction bottleneck (JFET) region layer is doped by injecting N-type impurities to the entire surface of the N-drift region which is lightly doped with the prepared N-type impurities.
The proper doping concentration of the N-drift region according to an embodiment of the present invention is 3.5 e 14 [cm -3].
In addition, the doping concentration of the junction bottleneck (JFET) layer for optimizing the sense portion POWER SENSE MOSFET chip according to an embodiment of the present invention was applied to 0.1e18 [cm-3].
FIG. 5 shows the step of forming the primary gate oxide film GOX1 in the main cell MOSFET region.
According to an embodiment of the present invention, a primary gate oxide film GOX1 is formed on the entire upper surface of the junction junction region (JFET) region layer.
According to an embodiment of the present invention, an oxide film is made using a Diffusion process, or an oxide film is deposited by CVD.
In one embodiment of the present invention, an oxide film is formed using SiO2. However, various types of insulating materials such as SiON and HfO can also be applied to the oxide film material.
In order to optimize the power MOSFET according to the exemplary embodiment of the present invention, the thickness of the main cell (main cell MOSFET) gate oxide layer is 900 [Å].
FIGS. 6 and 7 illustrate a step of forming a SenseFET gate oxide film according to an embodiment of the present invention.
Referring to FIG. 6, after the photoresist layer is coated on the entire surface of the primary gate oxide layer GOX1 formed by FIG. 5, a photoresist pattern exposing a senseFET gate region is formed and used as a mask. The first gate oxide layer GOX1 formed in the exposed sense cell gate region is removed by dry etching.
Another masking method may be peeled off by wet etching after etching SiN, etc. and masking with a photo, and then etching only a sense cell region.
FIG. 7 shows a step of forming a gate oxide film GOX2 in a sense field region where the primary gate oxide film GOX1 is removed.
According to an exemplary embodiment of the present invention, as shown in FIG. 6, the entire gate oxide layer (GOX2, 31) is formed by growing the entire oxide layer by a Diffusion method including the region where the primary gate oxide layer (GOX1) is removed. At this time, the oxide film grows only in the region where the surface is exposed, and the oxide film does not grow in the region where the surface is not exposed.
This is used to grow the entire wafer to form gate oxide films GOX1 and 30 and gate oxide films GOX2 and 32 having different thicknesses for respective regions.
According to an embodiment of the present invention, the senseFET gate oxide layers GOX2 and 32 are formed to have a thickness of 80 to 85% of the main cell MOSFET gate oxide layers GOX1 and 31.
A thickness of a senseFET gate oxide film for optimizing a 600V / 1A POWER SENSE MOSFET chip according to an embodiment of the present invention is 750 [Å].
The first and second oxide layers GOX1 and 2 may be formed by forming the first oxide layer GOX1 and then removing the sense cell gate region by a corresponding thickness difference, but may be thinly removed. Due to the nature of the uniform thickness can not be guaranteed.
There is also a method of forming a 750 Å thick second oxide film first and then using a mask pattern to process a relatively slow oxidization process only in the main cell region to further form a thin 150 Å gate oxide film , It is difficult to ensure a uniform thickness because the thickness is thin.
Therefore, in an embodiment of the present invention, a method of removing a primary oxide film generated in a sense cell region as described above and growing a uniform oxide film over two times is adopted.
Figures 8 and 9 illustrate the step of forming a gate.
8 and 9, the entire surface of the oxide layers GOX1 and GOX2 is covered with polysilicon to form a gate, and then only the gate remains in a region set by using a Photo and Etch process.
10 shows the steps of forming a P-type body region and a P-type channel region.
According to an embodiment of the present invention, after the above-described step of forming the gate, a step of implanting P-type impurities at a low concentration using the formed
By implanting the impurity, a P-
In addition, a sense cell junction bottleneck (JFET)
The P-
An appropriate concentration of the P-
11 and 12 are steps of forming an ohmic contact region according to an embodiment of the present invention.
After the above-described senseFET channel region 9 'and main cell
Referring to FIG. 11, in order to form an ohmic contact region, a P-type impurity is implanted at a high concentration after masking with a photo to expose only an ohmic contact region.
FIG. 12 illustrates a step in which P + type
In the P-type impurity implantation step, a SenseFET Ohmic Contact region 12 'is formed on one end of the SenseFET channel region 9', and a Main Cell MOSFET channel region is formed. A main cell MOSFET
13 and 14 illustrate forming a source region according to an embodiment of the present invention.
After the
Referring to FIG. 14, when N-type impurities are implanted at a high concentration after masking with a photo, a sense
15 illustrates forming an insulating layer.
After the
According to an embodiment of the present invention, the insulating
16-18 illustrate steps of forming an electrode.
Referring to FIG. 16, after forming the insulating
According to an embodiment of the present invention, the process proceeds to a dry etching process, wherein the N +
Referring to FIG. 17, an electrode metal (Metal 90) is covered on the etched portion.
According to one embodiment of the present invention, a conductive material such as Al is filled by using sputtering or other commercial metal deposition methods.
18 shows the step of separating the electrodes.
Referring to FIG. 18, each electrode is separated by removing between a sense cell gate and a main cell MOSFET gate region.
At this time, the
19 shows the step of forming an N + drain.
After the upper process is completed, a step of forming an N + drain of the bottom surface is performed.
In the step of forming the N + drain, after the upper process is completed, the N-side is inverted to inject a high concentration of N-type impurities into the bottom surface of the wafer.
In another embodiment of the present invention, P-type impurities may be implanted instead of N-type impurities.
That is, in the IGBT, P + impurities may be implanted to form a P + collector.
1, 42 to 45: Gate
2, 3, 31, 32: gate oxide film
6: drift region
7: drain region
8: drain electrode
9, 9 ': channel region
10: Body area
11, 11 ': junction bottleneck (JFET) region
12, 12 ': Ohmic contact area
13, 13 ': source region 13'
70: Insulation layer
91. 92: source electrode
Claims (9)
(2) forming a first gate oxide film by depositing an oxide film on the entire surface of the junction bottleneck (JFET) region by a diffusion process or a CVD method;
(3) applying a photoresist layer over the first gate oxide layer and forming a photoresist pattern exposing a sense cell gate region;
(4) using the photoresist pattern as a mask to remove the first gate oxide layer in the senseFET gate region by an etch process;
(5) forming a second gate oxide film in the removed sense cell gate region,
The thickness of the second gate oxide film is a power sensing MOSFET manufacturing method, characterized in that formed to have a thickness of 80 ~ 85% of the thickness of the first gate oxide film.
After step (5) above,
(6) covering the remaining front with polysilicon removed in step (4);
(7) forming a sense cell gate and a main cell MOSFET gate in a region in which the polysilicon is formed using a photo and etching process;
Power sensing MOSFET manufacturing method comprising a
After step (7) above
(8) By using the sense cell gate and the main cell MOSFET gate as a mask, a second type of impurity is injected at a low concentration, so that the sense cell gate and the main cell MOSFET gate are used. A body region is formed under the gap, and a sense cell channel region is formed under the outside of the sense cell gate, and a main cell MOSFET channel region under the outside of the main cell MOSFET gate. Forming a;
In step (8), a SenseFET junction bottleneck (JFET) region is formed between the body region and the SenseFET channel region, and the body region and the main cell MOSFET channel region. Method for manufacturing power sense MOSFET, characterized in that the main cell (JFET) junction bottleneck (JFET) region is formed between
After step (8) above
(9) After exposing the regions where ohmic contacts are to be formed by photo masking, and injecting a high concentration of the second type impurities, the upper side of one side of the senseFET channel region is formed. Forming a sense cell ohmic contact region and forming a main cell MOSFET ohmic contact region at an upper end of one side of the main cell MOSFET channel region; And
(10) After step (9), through the process of photomasking so that only the source regions are exposed, and then implanting the first type impurities in a high concentration, the SenseFET Ohmic Contact (SenseFET) Forming a sense cell source region on one side of the region and forming a source region of a main cell MOSFET on one side of the main cell ohmic contact region;
Power sensing MOSFET manufacturing method comprising a
After step (10) above
(11) Any one of PSG, BPSG, or FSG is formed on the first gate oxide layer and the second gate oxide layer on the sense cell gate, the main cell MOSFET gate, and the main cell MOSFET region. Depositing an SiO 2 insulator comprising one by CVD to form an insulating layer;
Power sensing MOSFET manufacturing method comprising a
After step (11) above
(12) etching a portion of the insulating layer to form electrodes;
(13) covering an electrode metal on the etched portion;
(14) after the step (13), and removing the metal between the sense cell gate and the main cell MOSFET gate region to separate each electrode;
The etching may be performed at one time so that the sense cell ohmic contact region and the sense cell source region may be connected to one electrode, and the main cell MOSFET ohmic contact A method for manufacturing a power sense MOSFET, wherein etching is performed at a time so that the ohmic contact region and the main cell MOSFET source region can be connected to one electrode.
The junction bottleneck (JFET) layer is a power sensing MOSFET manufacturing method characterized in that the doped to 0.1e18 [cm-3] concentration.
The concentration of the N-drift region is a power sensing MOSFET manufacturing method, characterized in that 3.5e14 [cm-3].
The method of manufacturing a sense MOSFET for power, characterized in that the concentration of the body region 3.0e18 [cm-3].
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| KR1020130033804A KR101369973B1 (en) | 2013-03-28 | 2013-03-28 | Method of manufacturing power sense mosfet |
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| KR1020130033804A KR101369973B1 (en) | 2013-03-28 | 2013-03-28 | Method of manufacturing power sense mosfet |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101737601B1 (en) * | 2015-06-08 | 2017-05-22 | 메이플세미컨덕터(주) | Method for manufacture sense mosfet having controlling function of sensor rate |
| CN109768089A (en) * | 2019-01-23 | 2019-05-17 | 电子科技大学 | A kind of voltage-controlled Sampling device based on SenseFET |
| CN111370492A (en) * | 2020-04-27 | 2020-07-03 | 上海华虹宏力半导体制造有限公司 | Ultrahigh-voltage LDMOS composite tube integrating functions and process method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08236770A (en) * | 1996-03-06 | 1996-09-13 | Nippondenso Co Ltd | Semiconductor element for power |
| KR20080084967A (en) * | 2005-12-14 | 2008-09-22 | 프리스케일 세미컨덕터, 인크. | Superjunction power mosfet |
-
2013
- 2013-03-28 KR KR1020130033804A patent/KR101369973B1/en not_active IP Right Cessation
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08236770A (en) * | 1996-03-06 | 1996-09-13 | Nippondenso Co Ltd | Semiconductor element for power |
| KR20080084967A (en) * | 2005-12-14 | 2008-09-22 | 프리스케일 세미컨덕터, 인크. | Superjunction power mosfet |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101737601B1 (en) * | 2015-06-08 | 2017-05-22 | 메이플세미컨덕터(주) | Method for manufacture sense mosfet having controlling function of sensor rate |
| CN109768089A (en) * | 2019-01-23 | 2019-05-17 | 电子科技大学 | A kind of voltage-controlled Sampling device based on SenseFET |
| CN111370492A (en) * | 2020-04-27 | 2020-07-03 | 上海华虹宏力半导体制造有限公司 | Ultrahigh-voltage LDMOS composite tube integrating functions and process method |
| CN111370492B (en) * | 2020-04-27 | 2023-04-28 | 上海华虹宏力半导体制造有限公司 | Ultra-high voltage LDMOS composite tube integrating sampling function and process method |
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