WO2018007320A1

WO2018007320A1 - Luminescence diode and method for producing same

Info

Publication number: WO2018007320A1
Application number: PCT/EP2017/066505
Authority: WO
Inventors: Christoph Rupprich; Andreas Rudolph; Hubert Halbritter
Original assignee: Osram Opto Semiconductors Gmbh
Priority date: 2016-07-07
Filing date: 2017-07-03
Publication date: 2018-01-11
Also published as: DE102016112502A1; US11081520B2; US20200119084A1

Abstract

A luminescence diode (100) for the infrared spectral range is described, comprising – a carrier substrate (13), – a first semiconductor layer sequence (1), which has a first active layer (4a) suitable for emitting radiation having a first dominant wavelength λ_dom ₁, – a second semiconductor layer sequence (2), which has a second active layer (4b) suitable for emitting radiation having a second dominant wavelength λ_dom2, wherein – the first semiconductor layer sequence (1) and the second semiconductor layer sequence (2) are arranged alongside one another on the carrier substrate (13), and – the dominant wavelength λ_dom1 of the first active layer (4a) and the dominant wavelength λ_dom2 of the second active layer (4b) are different from one another. Furthermore, a method for producing the luminescence diode (100) is described.

Description

description

Luminescence diode and method for its production The application relates to a light-emitting diode, the

is intended in particular for emission in the infrared spectral range, and a method for producing the

Luminescence diode. This patent application claims the priority of German Patent Application 10 2016 112 502.4, the disclosure of which is hereby incorporated by reference.

An object to be solved is to specify a light-emitting diode which emits radiation in a broad wavelength range. Furthermore, a for the production of the

Luminescent diode suitable method can be specified.

These objects are achieved by a light emitting diode and a method according to the independent claims. Advantageous embodiments and further developments of

Invention are the subject of the dependent claims.

The light-emitting diode described here is in particular for the emission of radiation in the infrared spectral range

intended. In particular, the light-emitting diode for

Emission of radiation in the wavelength range between about 780 nm and about 1100 nm be provided. At this

Embodiment emits the light emitting diode in the near-infrared spectral range (NIR).

The luminescence diode advantageously comprises a carrier substrate on which a first semiconductor layer sequence and a second semiconductor layer sequence Semiconductor layer sequence are arranged side by side. The first semiconductor layer sequence and the second

In other words, semiconductor layer sequences are offset in a lateral direction relative to one another on the carrier substrate

arranged. Preferably, the first overlap

Semiconductor layer sequence and the second

Semiconductor layer sequence in the lateral direction not.

The first semiconductor layer sequence has a first active layer which is suitable for emitting radiation having a first dominant wavelength X _dom i. The second

Semiconductor layer sequence has a second active layer, which is used to emit radiation with a second active layer

dominant wavelength X _dom 2 is suitable. Here, the dominant wavelength X _dom i of the first active layer and the dominant wavelength X _dom 2 of the second active layer are advantageously different from one another.

Due to the fact that in the case of the light-emitting diode

Semiconductor layer sequences with the first active layer and the second active layer, which are different

Emitting wavelengths, are arranged side by side on the carrier substrate, a broad-band emission spectrum is advantageously obtained in the far field of the light emitting diode, which contains the radiation of both active layers. As a result of the arrangement on the common carrier substrate, the active layers are arranged spatially close to one another, so that the radiation in the far field of the light-emitting diode

is advantageously homogeneous. Compared to the realization of a broadband radiation by separately from each other

arranged single light-emitting diodes is the here

described light-emitting diode particularly space-saving and inexpensive. The first active layer and the second active layer preferably each have an arsenide

Compound semiconductor material or an arsenide-phosphide compound semiconductor material. _Y As with x ^ O ^ l, O ^ y ^ l and x + y <1, or Al _x In _y Ga _x -yAs _n Pi-n with O ^ - In particular, the active layers of Al _x In _y Ga _x can x ^ l, O ^ y ^ l and x + y <1 and 0 -S n <1, wherein the first active layer and the second active layer in the

Material composition differ from each other. By choosing the material composition for the first active layer and the second active layer, in particular the

Dominant wavelengths X _dom i, X _{dom2 be} targeted. Preferably, 780 nm <X _d omi, Xdom2 - 1100 nm with Xdomi Xdom2.

According to one embodiment of the light-emitting diode, the first semiconductor layer sequence and the second

Semiconductor layer sequence in the vertical direction offset from one another. The first semiconductor layer sequence and the second semiconductor layer sequence are thus offset from each other both in the lateral direction and in the vertical direction. In particular, the first

Semiconductor layer sequence and the second

Semiconductor layer sequence on different vertical distances from the carrier substrate. The different vertical

Distance of the semiconductor layer sequences to the carrier substrate can be described in more detail below

Production method of the light emitting diode result, in which the semiconductor layer sequences are advantageously deposited one above the other. The first and the second semiconductor layer sequence are preferably connected to the carrier substrate by means of a connection layer, in particular a solder layer. The carrier substrate is in particular not equal to

Growth substrate of the semiconductor layer sequences, but is advantageous only after the preparation of the

Semiconductor layer sequences associated with these. The

The carrier substrate therefore advantageously does not have to be suitable for the epitaxial growth of the semiconductor layer sequences, but instead can be classified according to its mechanical and / or thermal properties, in particular the

Thermal conductivity or the thermal

Expansion coefficients are selected. For example, the carrier substrate may be a semiconductor material such as

For example, silicon or germanium, or a metal or a metal alloy.

By means of a solder layer, which connects the semiconductor layer sequence to the carrier substrate, the different distances of the semiconductor layer sequences from the carrier substrate are advantageously compensated. For example, the solder layer is in a region between the carrier substrate and the

Semiconductor layer sequence with the greater distance to the

Carrier substrate thicker than in an area between the

Carrier substrate and the semiconductor layer sequence with the smaller distance to the carrier substrate.

The first semiconductor layer sequence and the second

Semiconductor layer sequence can in particular by the

Lotschicht be electrically connected to each other. The

Lotschicht can, for example, each electrical

Establish connection to a contact of the semiconductor layer sequences, which faces the carrier substrate. According to an advantageous embodiment, the semiconductor layer sequences are electrically contacted at a side remote from the carrier substrate by a common bonding pad. In this case, the common bonding pad may, in particular, have a gap between them

Span semiconductor layer sequences. The gap can be advantageous in this case with an electric

be filled with insulating material.

The first semiconductor layer sequence and the second

Semiconductor layer sequence are preferably connected in parallel in the light-emitting diode. Thus emit at

Operation of the light emitting diode in each case both active layers light simultaneously, without having to be connected separately electrically. The parallel connection can be effected in particular by virtue of the fact that the semiconductor layer sequences each have a common contact layer or at least one another electrically, both on the side facing the carrier substrate and on the side remote from the carrier substrate

having connected contact layers.

According to a further advantageous embodiment, both the first semiconductor layer sequence and the second semiconductor layer sequence each have an arrangement of

Microprisms, wherein the microprisms extend starting from a carrier substrate facing away from the first main surface of the semiconductor layer sequences in the semiconductor layer sequences inside. Preferably, a shrinking

Cross section of the microprisms starting from the first

Main surface in the vertical direction. It is still a process for producing a

Luminescence diode, in particular a light emitting diode for the infrared spectral range specified. According to at least one embodiment, in the method a first

A semiconductor layer sequence having a first active layer suitable for emitting radiation having a first dominant wavelength X _dom i onto a growth substrate

grew up. In particular, growth is achieved by an epitaxial process, such as metal-organic vapor deposition (MOVPE).

In a further method step, a second semiconductor layer sequence, which has a second active layer suitable for the emission of radiation having a second dominant wavelength X _dom 2, is advantageously provided over the first

Grown up semiconductor layer sequence. The growth takes place, as in the case of the first semiconductor ^{layer sequence,} in particular by an epitaxial process such as, for example, metal-organic vapor deposition (MOVPE).

Subsequently, the second semiconductor layer sequence is removed again in a first region from the first semiconductor layer sequence. This can in particular photolithographically by applying a mask layer and a subsequent

Etching process done. The first area is preferably about half as large as the total area of the second

Semiconductor layer sequence. For example, the first

Area have an area fraction between 30% and 70% or preferably between 40% and 60% of the total area of the second semiconductor layer sequence. The of the

Brightness produced by the LED can be dependent on the emitted wavelength. By hiring the In each case, the brightness of _doml and _dom2 can be matched to each other for a more homogeneous _{lighting image} .

In a subsequent process step, the

Semiconductor layer sequences are advantageously connected to a carrier substrate at a side remote from the growth substrate. This can be done in particular by means of a solder layer, which preferably has a vertical spacing between the surfaces of the first semiconductor layer sequence facing away from the growth substrate and the second one

Semiconductor layer sequence compensated. The solder layer can, in particular, in the first region in which the second

Semiconductor layer sequence was removed, a greater thickness than in a second region in which the second

Semiconductor layer sequence not from the

Semiconductor layer sequence has been removed. In other words, the solder layer connects the carrier substrate, which in particular has a flat surface, with a stepped surface passing through the side by side

arranged semiconductor layer sequences is formed.

In a further method step, the growth substrate is removed from the semiconductor layer sequences. This can

for example, by an etching process, by a

mechanical process such as grinding, or by a combination of such processes. By the

Removing the growth substrate is advantageously the first semiconductor layer sequence at the originally the

Growth substrate facing surface exposed. The exposure of the first semiconductor layer sequence by removing the

Growth substrate allows in particular, the first

Semiconductor layer sequence in a subsequent

Partially remove process steps. In particular, the first semiconductor layer sequence in a second region, which is offset laterally from the first region, is removed after the removal of the growth substrate. The second region may in particular be complementary to the first region, ie the first semiconductor layer sequence is preferably removed outside the first region in which the second semiconductor layer sequence was previously removed. The carrier substrate advantageously has the partial

Removing the first semiconductor layer sequence on a first region in which only the first semiconductor layer sequence is present, and a laterally offset therefrom second region in which only the second semiconductor layer sequence is present. The partial removal of the first

Semiconductor layer sequence may be like the previous one

Removing the second semiconductor layer sequence, for example, by the photolithographic deposition of a mask layer and a subsequent etching process done. In an advantageous embodiment of the method, an etching stop layer is applied to the first semiconductor layer sequence before the growth of the second semiconductor layer sequence. The etch stop layer is arranged in this case at the interface between the first semiconductor layer sequence and the second semiconductor layer sequence. The

Etch stop layer has the advantage that when partially

Removing the second semiconductor layer sequence, the first semiconductor layer sequence is not attacked substantially, and in the subsequent partial removal of the first semiconductor layer sequence, the second semiconductor layer sequence is not attacked substantially. In one embodiment of the method, the first semiconductor layer sequence and the second one are based

Semiconductor layer sequence advantageously each on one

Arsenide compound semiconductor. In this case it is

advantageous when the etch stop layer is a phosphide

Contains compound semiconductor material. The etch stop layer may in particular comprise InGaP.

In a further advantageous embodiment, before connecting the semiconductor layer sequences with the

Carrier substrate both in the first semiconductor layer sequence and in the second semiconductor layer sequence each made microprisms, wherein the microprisms

starting from a first main surface of the semiconductor layer sequences facing away from the growth substrate in the

Extend semiconductor layer sequences into it, and wherein a cross section of the microprisms decreases from the first main surface. Due to the arrangement of the microprisms in the semiconductor layer sequences can advantageously the

Current spreading limited on the p-side of the semiconductor layer sequence, improves the radiation extraction and the

Be homogenized radiation. In particular, the microprisms may have the function of positive charge carriers

(Holes) of areas of the semiconductor layer sequence

be kept away in which contact layers such as bond pads or contact webs are applied for electrical contact. In a recombination of the holes below the contact layers would otherwise be the emitted light at the exit from the semiconductor layer sequence in the

Contact layers are absorbed.

In a further advantageous embodiment of the method, the growth substrate before joining with the Carrier substrate thinned. The thinning of the growth substrate can be carried out in particular by mechanical removal, such as grinding. It has been found to be particularly advantageous, the growth substrate before the

Connect to the carrier substrate to thin, because the

Using mechanical processes such as grinding after bonding with the carrier substrate could lead to damage to the device, for example to a

Damage to the solder joint between the carrier substrate and the semiconductor layer sequences and / or to the formation of cracks or microcracks in the semiconductor layer sequences. Cracks are microscopically and macroscopically visible damage to the semiconductor layer sequences and can lead to defective chips, microcracks are microscopically and macroscopically not visible damage within the semiconductor layers, which lead to increased aging of the later chips.

If, in contrast, the growth substrate is already thinned with the semiconductor layer sequences before the carrier substrate has been joined, after the connection to the carrier substrate it is advantageously only necessary to remove the remaining part of the growth substrate. The removal of the remaining part of the growth substrate is preferably carried out by means of an etching process, which causes no significant mechanical stress. When thinning the growth substrate by mechanical

Ablation before joining to the carrier substrate, the semiconductor layer sequences on a side opposite the growth substrate with an auxiliary carrier such as

For example, be connected to a film, wherein the

Subcarrier is removed after thinning again.

The remaining thickness of the growth substrate after thinning is preferably not more than 260 μm. This has the Advantage that only a comparatively small thickness must be removed by, for example, an etching process after bonding to the carrier substrate. The for the

Etching process required process time is advantageously reduced by the previous mechanical thinning.

Further advantageous embodiments of the method will become apparent from the description of the light emitting diode and vice versa. The invention will be described below with reference to

Embodiments explained in more detail in connection with Figures 1 to 17.

Show it:

Figures 1 to 16 is a schematic representation of a

Embodiment of the method for producing the light-emitting diode by means of intermediate steps, and

FIG. 17 shows a schematic representation of a cross section through a light-emitting diode in accordance with FIG

Embodiment. Identical or equivalent elements are shown in the figures with the same reference numerals. The components shown and the size ratios of the components with each other are not to be considered as true to scale. FIG. 1 schematically shows an intermediate step in an initial example of the method for producing a

Luminescence diode shown in which a first

Semiconductor layer sequence 1 and a second Semiconductor layer sequence 2 have been grown on a growth substrate 10. The first semiconductor layer sequence 1 and the second semiconductor layer sequence 2 can each be based on an arsenide compound semiconductor. "Based on an arsenide compound semiconductor" means in

present context, that the active epitaxial layer sequence or at least one layer thereof

Arsenide compound semiconductor material, preferably

Al _n Ga _m I Ni _n - _m As, wherein 0 <n <1, 0 <m <1 and n + m <1. This material does not necessarily have a

have mathematically exact composition according to the above formula. Rather, it can have one or more dopants and additional constituents. For the sake of simplicity, however, the above formula contains only the essential constituents of the crystal lattice (Al, Ga, In, As), even if these may be partially replaced by small amounts of other substances.

The semiconductor layer sequences 1, 2 are in particular epitaxially grown on the growth substrate 10, wherein the growth substrate 10 preferably comprises GaAs.

The first semiconductor layer sequence 1 and the second

Semiconductor layer sequence 2 each have several

Sublayers on. Furthermore, between the first

Semiconductor layer sequence 1 and the second

Semiconductor layer sequence 2 preferably arranged an etch stop layer. The partial layers of the semiconductor layer sequences 1, 2 and the etch stop layer are not shown in detail in FIG. 1 and the following FIGS. 3 to 17 for the sake of simplicity. Various embodiments of the layer stack of the first semiconductor layer sequence 1 and the second

Semiconductor layer sequence 2 are shown in FIGS. 2A to 2D. In the one shown in Figure 2A

Embodiment, the first semiconductor layer sequence 1, starting from the growth substrate, an n-type

Semiconductor region 3a, a first active layer 4a and a p-type semiconductor region 5a. The second semiconductor layer sequence 2 arranged above has an n-type

Semiconductor region 3b, a second active layer 4b and a p-type semiconductor region 5b on. The n-type semiconductor regions 3a, 3b and the p-type semiconductor regions 5a, 5b may each be composed of a plurality of sub-layers and may not necessarily consist exclusively of n-doped layers or p-doped layers, but may be

for example, also have one or more undoped layers.

The preferably each on one

Arsenide compound semiconductor material based active

Layers 4a, 4b are preferably suitable for the emission of radiation in the infrared spectral range. For example, the first active layer 4a may have a dominant wavelength X _dom i and the second active layer 4b may have a dominant wavelength X _dom 2, the dominant wavelengths X _dom i and X _dom 2 being included in the wavelength range between 780 nm and 1100 nm, and X _dom i and X _dom 2 are different from each other.

On the first semiconductor layer sequence 1 is a

Etch stop layer 6 is arranged, which preferably comprises a phosphide compound semiconductor material. The etch stop layer 6 may in particular In _x Al _y Ga _x - include _y P, where 0 <x <1, 0 < y <1 and x + y <1. Preferably, the etching stop layer 6 comprises In _x Gai_ _x P with 0 <x <1.

In the exemplary embodiment illustrated in FIG. 2A, the n-type is in each case in both semiconductor layer sequences 1, 2

Semiconductor region 3a, 3b facing the growth substrate.

Alternatively, each of the p-type semiconductor region 5a, 5b may face the growth substrate, as shown in Figure 2B.

It is alternatively also possible that the

Semiconductor layer sequences 1, 2 with opposite

Polarity are arranged one above the other. For example, in the embodiment illustrated in FIG. 2C, the n-type semiconductor region 3a of the first semiconductor layer sequence 1 and the p-type semiconductor region 5b of the second are

Semiconductor layer sequence 2 facing the growth substrate, and in the embodiment shown in Figure 2D, the p-type semiconductor region 5a of the first

Semiconductor layer sequence 1 and the n-type semiconductor region 3b of the second semiconductor layer sequence 2 facing the growth substrate.

In Figure 3 is a next intermediate step in the

Embodiment of the method shown, wherein here and in the following figures, the sub-layers of

Semiconductor layer sequence 1, 2 and the etching stop layer are not shown again for simplicity. In the intermediate step shown here is the second

Semiconductor layer sequence 2 has been removed in a first region 11, for example by photolithographic deposition of a mask and a subsequent etching process. In the etching process, the preferably between the Semiconductor layer sequences 1, 2 arranged etch stop layer as a stop layer and prevents that in the etching process, the first semiconductor layer sequence 1 is attacked. The after partial removal of the second

Semiconductor layer sequence 2 in the first region 11

exposed etch stop layer is then preferably in a separate etching step selectively to the

Semiconductor layer sequences removed. The first region 11 may, for example, have an area which is between 30% and 70%, preferably between 40% and 60%, of the total area of the first semiconductor layer sequence 1. By adjusting the area proportions, the proportion of emitted

Wavelengths on the total emitted radiation

be advantageously targeted.

In a subsequent intermediate step shown schematically in FIG. 4, in each case an arrangement of microprisms 7 has been advantageously formed in the first semiconductor layer sequence 1 and the second semiconductor layer sequence 2. The microprisms 7 each extend from a surface 8a, 8b facing away from the growth substrate 10

Semiconductor layer sequences 1, 2 in the

Semiconductor layer sequences 1, 2 into it. Here it is

advantageous if the microprisms 7 have a cross-section which decreases starting from the surfaces 8a, 8b facing away from the growth substrate 10. The microprisms 7 serve in the finished light emitting diode

in particular for improving the radiation decoupling and the homogeneity of the emitted radiation.

In another in Figure 5 shown schematically

Intermediate step are on the semiconductor layer sequences 1, 2 each area contact metallizations 14a, 14b has been applied. The contact metallizations 14a, 14b are used to make electrical contact with the adjacent semiconductor regions of

Semiconductor layer sequences 1, 2.

In a preferred variant of the method is in an intermediate step, which is shown in Figure 6, the

Growth substrate 10 thinned before it in a later

Step is removed from the first semiconductor layer sequence 1. The thinning of the growth substrate 10 is preferably carried out by a mechanical processing,

for example by grinding. In this intermediate step, the thickness of the growth substrate 10 is preferably reduced to a thickness d ^ 260 ym.

In another shown schematically in Figure 7

Intermediate step, the semiconductor layer sequences 1, 2 have been connected to a support substrate 13 on a side facing away from the growth substrate 10 by means of a connection layer 9 such as a solder layer. The height difference between the area where the second

Semiconductor layer sequence was removed, and the area that still has both semiconductor layer sequences can be compensated by the solder layer 9 advantageous. The solder layer 9 preferably contains AuSn, NiSn, Alul, InSn, AuInSn.

The carrier substrate 13 may, for example, a

Semiconductor material such as germanium or silicon or alternatively a metal or a metal alloy

exhibit. Preferably, the carrier substrate 13 is electrically conductive. The growth substrate 10 is subsequently removed completely, as shown in FIG. The

Semiconductor layer sequences 1, 2 are now shown rotated by 180 °, since now the carrier substrate 13 as a carrier

acts. The removal of the growth substrate 10 may

in particular by means of an etching process. This has the advantage that in comparison to mechanical methods such as grinding no large mechanical forces act on the solder joint. In order to reduce the process time in the etching process, it is advantageous if the growth substrate, as in the intermediate step shown in FIG. 6, was already mechanically thinned before the solder layer 9 was produced. In a further intermediate step illustrated in FIG. 9, the first semiconductor layer sequence 1 has been removed from the second semiconductor layer sequence 2 in a second region 12. This is done, for example, like that

previous partial removal of the second

Semiconductor layer sequence 2 by a photolithographic

Process, wherein the etching process advantageously by a between the first semiconductor layer sequence 1 and the second

Semiconductor layer 2 contained Ätzstoppschicht is stopped. The after partial removal of the first semiconductor layer sequence 1 in the second region 12

Semiconductor layer sequences removed. In a further in Figure 10 shown schematically

Intermediate step, the first semiconductor layer sequence 2 and the second semiconductor layer sequence 2 at least

partially provided with a roughening 15, whereby the radiation decoupling is improved in the light emitting diode.

In a schematically illustrated in Figure 11

Intermediate step is, for example, by one

Etching process a mesa structure in the first

Semiconductor layer sequence 1 and the second

Semiconductor layer sequence 2 has been generated, whereby the

Semiconductor layer sequences 1, 2 have been separated from each other in particular in the lateral direction. In particular, a mesa trench 16 has been formed between the semiconductor layer sequences 1, 2. Furthermore, mesa flanks 17 have been formed on the outer sides of the semiconductor layer sequences 1, 2. As an alternative to the illustrated mesa trench 16, which may extend as far as the carrier substrate, it is also possible to separate only the two semiconductor layer sequences 1, 2 from one another. For this purpose, a gap of a few ym width, for example, less than 10 ym width, between the Halbeleiterschichtenfolgen 1, 2 be sufficient.

In the intermediate step shown schematically in FIG. 12, the mesa trench 16 and the mesa flanks 17 have each been provided with a passivation layer 18. The

Passivation layer 18 is preferably one

Silicon oxide layer or a silicon nitride layer.

In the further schematically shown in Figure 13

Intermediate step of the procedure are on the first

Semiconductor layer sequence 1 and the second

Semiconductor layer sequence 2 each have a bonding pad 19a, 19b applied for electrical contacting. Here are different ways to arrange the

Bonding pads 19a, 19b on the semiconductor layer sequences 1, 2, of some of which are illustrated by way of example in the following figures 14A to 14H.

FIGS. 14A to 14H show the semiconductor layer sequences 1, 2 and the bonding pads 19a, 19b each in a plan view. Different examples for the spatial arrangement of one bonding pad 19a on the first semiconductor layer sequence 1 and one further bonding pad 19b on the second semiconductor layer sequence 2 are shown in FIGS. 14A to 14F. In the example shown in FIG. 14G, contact webs 20, in each case in addition to the bond pads 19a, 19b, are applied to the semiconductor layer sequences 1, 2, which are each connected to the bond pad 19a, 19b. The contact webs 20 may, for example, a frame around the

Radiation exit surfaces of the semiconductor layer sequences 1, 2 be guided around. In this way, in particular, the flow expansion can be improved.

In the example of Figure 14H, both are advantageous

Semiconductor layer sequences 1, 2 contacted by a common bonding pad 19c. This is particularly advantageous if the semiconductor layer sequences 1, 2 are also on the

opposite side are contacted together

for example, by the solder layer 9 and the preferably electrically conductive carrier substrate 13. Die

Semiconductor layer sequences 1, 2 can in this way

in particular be connected in parallel. The common

Bond pad 19c can in particular span a gap between the semiconductor layer sequences 1, 2. This is

schematically shown in the following figures 15 and 16.

In the example shown in FIG. 15, this fills

electrically conductive material of the common bond pad 19c the Mesagraben 16 between the semiconductor layer sequences 1, 2 and contacts the semiconductor layer sequences 1, 2 each at their upper sides. To avoid a short circuit, the carrier substrate 13, the solder layer 9 and the side edges of the semiconductor layer sequences 1, 2 by the previously

applied passivation layer 18 of the material of the bonding pad 19c electrically isolated.

In a further advantageous embodiment with a common bonding pad 19c, which is shown in FIG. 16, the mesa trench 16 is filled with a preferably electrically insulating filling layer 21 before the bonding pad 19c is applied. This can advantageously further reduce the risk of a short circuit.

To complete the illustrated in Figure 17

Embodiment of the light emitting diode 100 is

Subsequently, at least one further contact layer 22 for the back-side contacting of the semiconductor layer sequences 1, 2 is produced. For example, a backside contact 20 may be applied to the back side of the carrier substrate 13.

In this case, it is possible for the further contact layer 22

over the entire surface or structured on the back of the

Apply carrier substrate 13.

The light-emitting diode 100 finished in this manner has two adjacent to one another on the carrier substrate 13

arranged semiconductor layer sequences 1, 2, the

Emission of radiation, in particular in the infrared spectral range between 780 and 1100 nm, are suitable, with the dominant wavelengths in the

Semiconductor layer sequences 1, 2 contained active layers differ from each other. By way of example, the first semiconductor layer sequence 1 may have a dominant wavelength X _dom i = 850 nm and the second semiconductor layer sequence 2 a

dominant wavelength X _dom 2 = 940 nm. The fact that the semiconductor layer sequences 1, 2 are arranged side by side on the common carrier substrate 13, is the

Distance of the emission points in comparison to juxtaposed separately manufactured light-emitting diodes

comparatively low. In the far field, therefore, results in a broadband emission spectrum that contains the radiation components of both active layers in the semiconductor layer sequences 1, 2.

The invention is not limited by the description with reference to the embodiments. Rather, the includes

Invention every new feature as well as every combination of

Features, which includes in particular any combination of features in the claims, even if this feature or this combination itself is not explicitly in the

Claims or embodiments is given.

Reference sign list

1 first semiconductor layer sequence

2 second semiconductor layer sequence

3a n-type semiconductor region

3b n-type semiconductor region

4a active layer

4b active layer

5a p-type semiconductor region

5b p-type semiconductor region

6 etch stop layer

7 microprisms

8a surface

8b surface

9 solder layer

10 growth substrate

11 first area

12 second area

13 carrier substrate

14a contact metallization

14b contact metallization

15 roughening

16 mesograbes

17 Mesakante

18 passivation

19a first bondpad

19b second bondpad

19c common bondpad

20 contact bridges

21 filling layer

22 back contact

100 luminescent diode

Claims

Light-emitting diode (100) for the infrared

Spectral range, comprising

a carrier substrate (13),

a first semiconductor layer sequence (1), one for emission of radiation having a first dominant

Wavelength X _dom i has a suitable first active layer (4a),

a second semiconductor layer sequence (2) having a second active layer (4b) suitable for emission of radiation having a second dominant wavelength X _dom 2, wherein

- The first semiconductor layer sequence (1) and the second semiconductor layer sequence (2) side by side on the

Carrier substrate (13) are arranged, and

- The dominant wavelength X _dom i of the first active layer (4a) and the dominant wavelength X _dom 2 of the second active layer (4b) are different from each other.

Light-emitting diode according to Claim 1,

wherein the first active layer (4a) and the second active layer (4b) are each a

Arsenidverbindungshalbleitermaterial have.

Luminescence diode according to one of the preceding

Claims,

wherein the first semiconductor layer sequence (1) and the second semiconductor layer sequence (2) in vertical

Direction are offset from each other so that they have different vertical distances from the carrier substrate (13) have,

and wherein the first semiconductor layer sequence (1) and the second semiconductor layer sequence (2) by means of a

Lotschicht (9) are connected to the carrier substrate (13) which compensates for the different vertical distances.

Luminescence diode according to one of the preceding

Claims,

wherein the first semiconductor layer sequence (1) and the second semiconductor layer sequence (2) are electrically connected to one another by the solder layer (9).

Luminescence diode according to one of the preceding

Claims,

wherein the first semiconductor layer sequence (1) and the second semiconductor layer sequence (2) by a

common bond pad (19c) are electrically contacted, wherein the common bond pad spans a gap between the semiconductor layer sequences (1, 2).

Luminescence diode according to one of the preceding

Claims,

wherein the first semiconductor layer sequence (1) and the second semiconductor layer sequence (2) are connected in parallel.

Luminescence diode according to one of the preceding

Claims,

wherein both the first semiconductor layer sequence (1) and the second semiconductor layer sequence (2) each have an array of microprisms (7), wherein the microprisms (7) starting from one of the Carrier substrate (13) facing surface (8a, 8b) of the semiconductor layer sequences (1, 2) in the

Semiconductor layer sequences (1, 2) extend into it, and wherein a cross section of the microprisms (7)

starting from the surface (8a, 8b) reduced.

A method of manufacturing a light emitting diode (100) for the infrared spectral region, comprising

steps

Growing a first semiconductor layer sequence (1) which has a first active one suitable for emitting radiation having a first dominant wavelength X _dom i

Layer (4a), on a growth substrate (10),

Growing a second semiconductor layer sequence (2) having a second active layer (4b) suitable for emitting radiation having a second dominant wavelength X _dom 2 over the first one

Semiconductor layer sequence (1),

Removing the second semiconductor layer sequence (2) in a first region (11),

Connecting the semiconductor layer sequences (1, 2) on a side facing away from the growth substrate (10) to a carrier substrate (13),

Removing the growth substrate (10), and

- Removing the first semiconductor layer sequence (1) in a second region (12) laterally offset from the first region (11).

Method according to claim 8,

wherein before growing up the second

Semiconductor layer sequence (2) an etch stop layer (6) on the first semiconductor layer end sequence (1) applied becomes .

10. The method according to claim 9,

wherein the first semiconductor layer sequence (1) and the second semiconductor layer sequence (2) each on a

Arsenidverbindungshalbleitermaterial based, and wherein the etching stop layer (6) a

Phosphide compound semiconductor material has. 11. The method according to any one of claims 8 to 10,

wherein prior to bonding the semiconductor layer sequences (Im 2) to the carrier substrate both in the first

Semiconductor layer sequence (1) and in the second semiconductor layer sequence (2) in each case an array of microprisms (7) is produced, wherein the

Microprisms (7) in each case starting from one of

Wax substrate remote surface (8a, 8b) of the semiconductor layer sequences (1, 2) in the

starting from the surface (8a, 8b) reduced.

12. The method according to any one of claims 8 to 11,

wherein the growth substrate (10) is thinned prior to bonding to the carrier substrate (13).

13. The method according to claim 12,

wherein the thinning of the growth substrate (10) is performed by mechanical abrasion, and wherein the

Growth substrate (10) after connecting the

Semiconductor layer sequences (1, 2) with the carrier substrate (13) is removed by an etching process.

14. The method according to claim 12 or 13,

wherein a thickness of the growth substrate (10) after thinning is not more than 260 μm.