WO2018006483A1 - 2.7-3.5 GHz 2W GaN单片功率放大器及设计方法 - Google Patents

2.7-3.5 GHz 2W GaN单片功率放大器及设计方法 Download PDF

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WO2018006483A1
WO2018006483A1 PCT/CN2016/096418 CN2016096418W WO2018006483A1 WO 2018006483 A1 WO2018006483 A1 WO 2018006483A1 CN 2016096418 W CN2016096418 W CN 2016096418W WO 2018006483 A1 WO2018006483 A1 WO 2018006483A1
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capacitor
matching network
inductor
port
output
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PCT/CN2016/096418
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French (fr)
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许欢
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成都泰格微波技术股份有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only

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  • the invention relates to microelectronic technology, microwave technology, semiconductor monolithic integration technology, advanced material technology and microwave power amplification technology, in particular, miniaturization, high efficiency, high power density monolithic microwave integrated power amplification technology, in particular, a kind of 2.7 -3.5GHz 2W GaN monolithic power amplifier and design method.
  • MMIC Microwave Integrated Circuit
  • GaN materials Due to the unique advantages of GaN materials, such as excellent noise figure, high maximum current, high breakdown voltage, high oscillation frequency, wide frequency band, large dynamic range, high power, high additional efficiency, strong anti-electromagnetic radiation capability, etc.
  • a wide range of applications in the military, aerospace and defense, automotive and high power sectors of industry, solar, power generation and wind provide a unique choice.
  • the expansion of application areas and the increase in military demand are the main forces driving the growth of the GaN semiconductor device market.
  • the increase in demand is mainly due to the significant improvements in device weight and size that GaN devices can bring.
  • the increase in breakdown voltage of GaN devices is expected to drive the use of GaN in electric vehicles.
  • HEMT High Electron Mobility Transistor
  • This is a heterojunction field effect transistor, also known as a modulation doped field effect transistor (MODFET), a two-dimensional electron gas field effect transistor (2-DEGFET), a selective doped heterojunction transistor (SDHT), and the like.
  • the HEMT is a voltage control device.
  • the gate voltage Vg controls the depth of the heterojunction well, and the surface density of the 2-DEG in the well is controlled to control the operating current of the device.
  • High mobility two-dimensional electron gas (2-DEG) exists in the modulation doped heterojunction. This 2-DEG not only has high mobility, but also does not “freeze” at very low temperatures.
  • HEMT has Very good low temperature performance, can be used in low temperature research work (such as fractional quantum Hall effect). In fact, for very short channel HEMTs, often a much higher transient drift speed plays a decisive role. This results in higher saturation current and saturated transconductance.
  • pHEMT is an improved structure for HEMTs, also known as ytterbium-doped heterojunction field effect transistors (pMODFETs).
  • the amplifier of WIN Foundry's NP25-00GaN process takes into account that the gain compression of GaN devices is slow, and the maximum power or efficiency point is generally reached at the 8-10dB gain compression point. Therefore, the linearity of the GaN power amplifier is poor, so the harmonic suppression is also Poor.
  • the small signal gain is about 29-31dB, which requires two-stage amplification. Considering that the higher small-signal gain will lead to a decrease in stability, the amplifier is prone to self-oscillation, so it is necessary to design the matching and power bias networks very carefully. , control amplifier gain and stability factor.
  • the object of the present invention is to overcome the deficiencies of the prior art, and to disclose a 2.7-3.5 GHz 2W GaN single-chip power amplifier and a design method thereof.
  • 2.7-3.5GHz 2W GaN monolithic power amplifier includes input matching network, interstage matching network network, output matching network, gate bias power supply, drain bias power supply, pHEMT transistors S1, S2;
  • the port 1 of the input matching network is connected to the signal source, and the port 3 of the input matching network is respectively connected with the port 4 of the inter-stage matching network and one end of the inductor L1, and the other end of the inductor L1 and the gate bias power supply
  • the positive pole is connected, the negative pole of the gate bias current is grounded,
  • the port 2 of the input matching network is connected to the gate of the pHEMT transistor S1, the source of the pHEMT transistor S1 is grounded, and the drain of the pHEMT transistor S1 is connected to the port 1 of the interstage matching network.
  • Port 3 of the interstage matching network is connected to the anode of the drain bias power supply, the negative pole of the drain bias power supply is grounded, the port 2 of the interstage matching network is connected to the gate of the pHEMT transistor S2, and the source of the pHEMT transistor S2 is grounded.
  • the drain of the pHEMT transistor S2 is connected to the port 1 of the output matching network, the port 2 of the output matching network is connected to the load, the port 3 of the output matching network is connected to the anode of the drain bias power supply, and the negative terminal of the drain bias power supply is grounded.
  • each matching level network is as follows:
  • the input matching network includes a capacitor C1 connected to the port 3 of the inter-stage matching network, a capacitor C2, and a resistor R1.
  • the other end of the capacitor C1 is connected to one end of the back hole BVIA1, and the back hole BVIA1 is another.
  • the other end of the circular capacitor C2 is connected to one end of the back hole BVIA2, and the other end of the back hole BVIA2 Grounding, the other end of the resistor R1 is connected to one end of the inductor L2, the other end of the inductor L2 is connected to one end of the microstrip line TL1, the other end of the microstrip line TL1 is respectively connected to one end of the resistor R2, and one end of the microstrip line TL2, the capacitor One end of C5 is connected to one end of the resistor R3, the other end of the microstrip line TL2 is connected to one end of the capacitor C3, the other end of the capacitor C3 is connected to the port 1 of the input matching network, and the other end of the resistor R2 is connected to one end of the capacitor C4.
  • the other end of the capacitor C4 is connected to one end of the back hole BVIA3, the other end of the back hole BVIA3 is grounded, and the port 2 input to the matching network is respectively connected to the other end of the capacitor C5 and the other end of the resistor R3;
  • the inter-stage matching network includes a capacitor C6 connected to the port 3 of the inter-stage matching network, a capacitor C7 connected to the inductor L3, and the other end of the capacitor C6 is connected to one end of the back hole BVIA4, and the back hole BVIA4
  • the other end is grounded, the other end of the capacitor C7 is connected to one end of the back hole BVIA5, the other end of the back hole BVIA5 is grounded, the other end of the inductor L3 is connected to one end of the microstrip line TL3, and the other end of the microstrip line TL3 is respectively
  • One end of the line TL4 is connected to one end of the inductor L4, the other end of the microstrip line TL4 is connected to the port 1 of the interstage matching network, the other end of the inductor L4 is connected to one end of the capacitor C10, and the other end of the capacitor C10 is respectively connected with the microstrip One end of the line TL5, one end of the capacitor C11 and one end of
  • the other end of the capacitor C9 is connected to one end of the back hole BVIA7, and the other end of the back hole BVIA7 is grounded.
  • Another for C8 One end is connected to one end of the back hole BVIA7, and the other end of the back hole BVIA6 is grounded;
  • the output matching network includes a capacitor C12, a capacitor C13, and an inductor L6 connected to the port 3 of the output matching network.
  • the other end of the capacitor C12 is connected to one end of the back hole BVIA8, and the other end of the back hole BVIA8.
  • Grounding, the other end of the capacitor C13 is connected to one end of the back hole BVIA9, the other end of the back hole BVIA9 is grounded, the other end of the inductor L6 is connected to one end of the microstrip line TL6, and the other end of the microstrip line TL6 is respectively matched with the output network port.
  • Capacitor C12, capacitor C13, capacitor C15, and capacitor C16 are all MIM capacitors; resistors R1, R2, resistor R3, and resistor R4 are thin film resistors.
  • the inductor L7 is a square coil planar inductor.
  • the power density of the pHEMT transistor die the power of the die itself, the gate width, the circuit loss, and the efficiency requirements of the entire operating frequency band, the die size is determined, and the output stage die and the input stage die are further selected, and the output is output.
  • the matching network design is performed according to the optimal load impedance of the die and the optimal source impedance.
  • the input matching network is responsible for converting the 50 Ohm input impedance to Z S1 and simultaneously providing the gate bias power of the input stage die.
  • the interstage matching network is responsible for transforming Z L1 to Z S2 and providing both the drain bias supply of the input stage die and the gate bias supply of the output stage.
  • the output matching network is responsible for converting Z L2 to 50 Ohm while providing the output stage. The drain of the die is biased to the power supply.
  • the S-parameter simulation is used to calculate the index of the amplifier including small signal gain, input-output VSWR, and stability factor
  • harmonic balance simulation is used to calculate the power gain and output power of the amplifier when inputting the input power of the input die.
  • Indicators for power supply additional efficiency and harmonic suppression optimize the matching network of each stage of the amplifier, that is, adjust the resistance, capacitance, inductance, and microstrip line size of each part of the network, so that multiple parameters meet the requirements;
  • the layout layout design is carried out, and the chip size is limited to the design range; the circuit and the electromagnetic field joint simulation are performed on the layout, wherein in the simulation process, the die is set to circuit simulation, and the rest includes transmission lines, capacitors, The passive part including the resistor and the inductor is set to simulate electromagnetic field.
  • the beneficial effects of the invention optimize the stability coefficient, input and output standing wave system, gain, power, efficiency, harmonic suppression and other indicators, so that the small signal gain is controlled at about 31 dB, and the stability coefficient is greater than 1.05 in the range of 0.1 to 10 GHz, and the output is The power is greater than 2.3W, the power supply additional efficiency is greater than 45%, and the harmonic rejection is greater than 20dBc.
  • 1 is a block diagram showing the principle of an amplifier of the present invention
  • Figure 2 is a layout of an amplifier of the present invention
  • Figure 3 shows the input matching network design diagram
  • Figure 5 shows the output matching network design diagram
  • Figure 6 is a graph of input and output impedance Smith
  • Figure 7 is a schematic diagram of input and output reflection
  • Figure 8 is a schematic diagram of the stability factor
  • Figure 9 is a graph of output power (W) and power supply additional efficiency
  • Figure 10 is a list of output power (W) and power supply additional efficiency list
  • Figure 11 is a comparison of power gain and output power (W).
  • Figure 12 is a harmonic suppression map.
  • 2.7-3.5 GHz 2W GaN single-chip power amplifier comprising: an input matching network, an inter-stage matching network network, an output matching network, a gate bias power supply, a drain bias power supply, pHEMT transistors S1, S2;
  • the port 1 of the input matching network is connected to the signal source, and the port 3 of the input matching network is respectively connected with the port 4 of the inter-stage matching network and one end of the inductor L1, and the other end of the inductor L1 and the gate bias power supply
  • the positive pole is connected, the negative pole of the gate bias current is grounded, and the port 2 of the matching network is connected with the pHEMT crystal.
  • the gate of the body tube S1 is connected, the source of the pHEMT transistor S1 is grounded, the drain of the pHEMT transistor S1 is connected to the port 1 of the interstage matching network, and the port 3 of the interstage matching network is connected to the anode of the drain bias power supply, and the drain
  • the negative pole of the pole bias power supply is grounded
  • the port 2 of the interstage matching network is connected to the gate of the pHEMT transistor S2, the source of the pHEMT transistor S2 is grounded, the drain of the pHEMT transistor S2 is connected to the port 1 of the output matching network, and the output matching network is connected.
  • Port 2 is connected to the load, port 3 of the output matching network is connected to the positive pole of the drain bias power supply, and the negative pole of the drain bias power supply is grounded;
  • each matching level network is as follows:
  • the input matching network includes a capacitor C1 connected to the port 3 of the inter-stage matching network, a capacitor C2, and a resistor R1.
  • the other end of the capacitor C1 is connected to one end of the back hole BVIA1, and the back hole BVIA1 is another.
  • One end is grounded, the other end of the circular capacitor C2 is connected to one end of the back hole BVIA2, the other end of the back hole BVIA2 is grounded, the other end of the resistor R1 is connected to one end of the inductor L2, and the other end of the inductor L2 is connected to one end of the microstrip line TL1.
  • the other end of the microstrip line TL1 is respectively connected to one end of the resistor R2, one end of the microstrip line TL2, one end of the capacitor C5 and one end of the resistor R3, and the other end of the microstrip line TL2 is connected to one end of the capacitor C3, and the capacitor C3
  • the other end is connected to port 1 of the input matching network
  • the other end of the resistor R2 is connected to one end of the capacitor C4
  • the other end of the capacitor C4 is connected to one end of the back hole BVIA3, and the other end of the back hole BVIA3 is grounded, and the port 2 of the matching network is input.
  • the other end of the capacitor C5 is connected to the other end of the resistor R3;
  • the inter-stage matching network includes a capacitor C6 connected to port 3 of the inter-stage matching network, a capacitor C7, and an inductor L3.
  • the other end of the capacitor C6 is connected to one end of the back hole BVIA4, the other end of the back hole BVIA4 is grounded, the other end of the capacitor C7 is connected to one end of the back hole BVIA5, the other end of the back hole BVIA5 is grounded, and the other end of the inductor L3 is micro One end of the line TL3 is connected, and the other end of the microstrip line TL3 is connected to one end of the microstrip line TL4 and one end of the inductor L4, and the other end of the microstrip line TL4 is connected to the port 1 of the interstage matching network, and the other end of the inductor L4 One end is connected to one end of the capacitor C10, and the other end of the capacitor C10 is respectively connected to one end of the microstrip line TL5, one end of the capacitor C11
  • Port 4 is connected, the other end of the microstrip line TL5 is connected to one end of the inductor L5, and the other end of the inductor L5 is respectively connected to one end of the capacitor C9, one end of the capacitor C8 and the port 2 of the inter-stage matching network, and the other end of the capacitor C9 Connected to one end of the back hole BVIA7, the other end of the back hole BVIA7 is grounded, the other end of the capacitor C8 is connected to one end of the back hole BVIA7, and the other end of the back hole BVIA6 is grounded;
  • the output matching network includes a capacitor C12, a capacitor C13, and an inductor L6 connected to the port 3 of the output matching network.
  • the other end of the capacitor C12 is connected to one end of the back hole BVIA8, and the other end of the back hole BVIA8.
  • Grounding, the other end of the capacitor C13 is connected to one end of the back hole BVIA9, the other end of the back hole BVIA9 is grounded, the other end of the inductor L6 is connected to one end of the microstrip line TL6, and the other end of the microstrip line TL6 is respectively matched with the output network port.
  • the capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C7, capacitor C9, capacitor C11, capacitor C12, capacitor C13, capacitor C15, capacitor C16 are all MIM capacitors; resistors R1, R2, resistor R3, The resistor R4 is a thin film resistor, and the inductor L2, the inductor L3, the inductor L4, the inductor L5, the inductor L6, and the inductor L7 are square coil planar inductors.
  • the design method of the 2.7-3.5GHz 2W GaN monolithic power amplifier is as follows:
  • the power density of the NP25-00 process die is about 4.9W/mm.
  • the gate width of the output stage die is only 0.41mm minimum, but considering the circuit loss and For the efficiency of the entire working frequency band, the output stage selects a 6*125um die with a power gain of approximately 10dB; the input stage selects a 4*75um die.
  • the power density of the pHEMT transistor die the power of the die itself, the gate width, the circuit loss, and the efficiency requirements of the entire operating frequency band, the die size is determined, and the output stage die and the input stage die are further selected, and the output is output.
  • interstage matching network is responsible for converting the Z L1 to Z S2 provides an input stage while die Paranoid power output stage and the drain gate bias power supply, the output matching network is responsible for the conversion to Z L2 50Ohm drain bias while providing a power output stage die.
  • the S-parameter simulation is used to calculate the index of the amplifier including small signal gain, input-output VSWR, and stability factor, and harmonic balance simulation is used to calculate the power gain and output power of the amplifier when inputting the input power of the input die.
  • Indicators such as power supply additional efficiency and harmonic suppression; simulation effects such as simulation results are shown in Figure 6 to Figure 12.
  • Optimize the matching network of each stage of the amplifier that is, adjust the resistance, capacitance, inductance, and microstrip line size of each part of the network, so that multiple parameters meet the requirements;
  • the layout layout design is carried out, and the chip size is limited to the design range; the circuit and the electromagnetic field joint simulation are performed on the layout, wherein in the simulation process, the die is set to circuit simulation, and the rest includes transmission lines, capacitors, The passive part including the resistor and the inductor is set to simulate electromagnetic field.
  • the beneficial effects of the invention optimize the stability coefficient, input and output standing wave system, gain, power, efficiency, harmonic suppression and other indicators, so that the small signal gain is controlled at about 31 dB, and the stability coefficient is greater than 1.05 in the range of 0.1 to 10 GHz, and the output is The power is greater than 2.3W, the power supply additional efficiency is greater than 45%, and the harmonic rejection is greater than 20dBc.

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  • Microwave Amplifiers (AREA)
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Abstract

一种2.7-3.5GHz 2W GaN单片功率放大器及设计方法，该放大器包括输入匹配网络、级间匹配网络、输出匹配网络及PHEMT晶体管，输入匹配网络通过PHEMT晶体管与级间匹配网络相连，级间匹配网络通过PHEMT晶体管与输出匹配网络相连，栅极偏置电源分别与输入匹配网络和级间匹配网络相连，漏极偏置电源分别与级间匹配网络和输出匹配网络相连。该设计方法简化了模块电路的设计难度，相比传统混合集成电路尺寸明显减小，确定了管芯的最佳负载阻抗和最佳源阻抗，并且设计了输入、输出和级间匹配网络的电路原理图，优化了稳定系数、输入输出驻波系统、增益、功率、效率、谐波抑制等指标，设计了单片微波功率放大器的版图。

Description

2.7-3.5GHz 2W GaN单片功率放大器及设计方法 技术领域
本发明专利涉及微电子技术、微波技术、半导体单片集成技术、先进材料技术和微波功率放大技术，特别是小型化、高效率、高功率密度单片微波集成功率放大技术，尤其涉及一种2.7-3.5GHz 2W GaN单片功率放大器及设计方法。
背景技术
单片微波集成电路(Monolithic Microwave Integrated Circuit，MMIC)已成为当前发展各种高科技武器的重要支柱，已广泛用于各种先进的战术导弹、电子战、通信系统、陆海空基的各种先进的相控阵雷达(特别是机载和星载雷达)，在民用商业的移动电话、无线通信、个人卫星通信网、全球定位系统、直播卫星接收和毫米波自动防撞系统等方面已形成正在飞速发展的巨大市场。
由于GaN材料所具有的独特优势，如噪声系数优良、最大电流高、击穿电压高、振荡频率高、频带宽、动态范围大、功率大、附加效率高、抗电磁辐射能力强等特点，为军事、宇航和国防、汽车领域以及工业、太阳能、发电和风力等高功率领域的多种应用提供了独特的选择。应用领域的扩展和军事需求的增加是驱动GaN半导体器件市场增长的主要力量。需求量的增加主要是由于GaN器件所能带来的在器件重量和尺寸方面的显著改进。另外，GaN器件击穿电压的提升有望推动GaN在电动车辆中的使用量。
HEMT(High Electron Mobility Transistor)，高电子迁移率晶体管。这是一种异质结场效应晶体管，又称为调制掺杂场效应晶体管(MODFET)、二维电子气场效应晶体管(2-DEGFET)、选择掺杂异质结晶体管(SDHT)等。HEMT是电压控制器件，栅极电压Vg可控制异质结势阱的深度，则可控制势阱中2-DEG的面密度，从而控制着器件的工作电流。高迁移率的二维电子气(2-DEG)存在于调制掺杂的异质结中，这种2-DEG不仅迁移率很高，而且在极低温度下也不“冻结”，则HEMT有很好的低温性能，可用于低温研究工作(如分数量子Hall效应)中。实际上，对很短沟道的HEMT，往往是高得多的瞬态漂移速度起着决定作用， 从而有更高的饱和电流和饱和跨导。pHEMT是对HEMT的一种改进结构，也称为赝调制掺杂异质结场效应晶体管(pMODFET)。
采用WIN Foundry的NP25-00GaN工艺的放大器考虑到GaN器件增益压缩较缓慢，一般在8-10dB增益压缩点达到最大功率或效率点，因此GaN功率放大器的线性度较差，故谐波抑制度也较差。小信号增益约为29-31dB，需要两级放大；又考虑到较高的小信号增益将导致稳定性能下降，放大器容易发生自激震荡，因此需要非常小心的设计各级匹配和电源偏置网络，控制放大器增益的和稳定系数。
技术问题
本发明的目的在于克服现有技术的不足，公开了一种2.7-3.5GHz 2W GaN单片功率放大器及设计方法。
问题的解决方案
技术解决方案
2.7-3.5GHz 2W GaN单片功率放大器包括输入匹配网络、级间匹配网络网络、输出匹配网络、栅极偏置电源、漏极偏置电源、pHEMT晶体管S1、S2；
本发明原理框图，输入匹配网络的端口1与信号源连接，输入匹配网络的端口3分别与级间匹配网络的端口4和电感L1的一端相连，电感L1的另一端与栅极偏置电源的正极相连，栅极偏置电流的负极接地，输入匹配网络的端口2与pHEMT晶体管S1的栅极相连，pHEMT晶体管S1的源极接地，pHEMT晶体管S1的漏极与级间匹配网络的端口1相连，级间匹配网络的端口3与漏极偏置电源的正极相连，漏极偏置电源的负极接地，级间匹配网络的端口2与pHEMT晶体管S2的栅极相连，pHEMT晶体管S2的源极接地，pHEMT晶体管S2的漏极与输出匹配网络的端口1相连，输出匹配网络的端口2与负载相连，输出匹配网络的端口3与漏极偏置电源的正极相连，漏极偏置电源的负极接地；
各匹配级网络具体设计如下：
如图3所示，所述的输入匹配网络包括与级间匹配网络的端口3连接的电容C1、电容C2和电阻R1相连电容C1的另一端与背孔BVIA1的一端连接，背孔BVIA1的另一端接地，圆电容C2的另一端与背孔BVIA2的一端相连，背孔BVIA2的另一端 接地，电阻R1的另一端与电感L2的一端相连，电感L2的另一端与微带线TL1的一端相连，微带线TL1的另一端分别与电阻R2的一端，微带线TL2的一端，电容C5的一端以及电阻R3的一端相连，微带线TL2的另一端与电容C3的一端相连，电容C3的另一端与输入匹配网络的端口1相连，电阻R2的另一端与电容C4的一端相连，电容C4的另一端与背孔BVIA3的一端相连，背孔BVIA3的另一端接地，输入匹配网络的端口2分别与电容C5的另一端与电阻R3的另一端相连；
如图4所示，所述的级间匹配网络包括与级间匹配网络的端口3相连的电容C6、电容C7和电感L3相连，电容C6的另一端与背孔BVIA4的一端相连，背孔BVIA4的另一端接地，电容C7的另一端与背孔BVIA5的一端相连，背孔BVIA5的另一端接地，电感L3的另一端与微带线TL3的一端相连，微带线TL3的另一端分别与微带线TL4的一端和电感L4的一端相连，微带线TL4的另一端与级间匹配网络的端口1相连，电感L4的另一端与电容C10的一端相连，电容C10的另一端分别与微带线TL5的一端，电容C11的一端以及电阻R4的一端相连，电容C11的另一端分别与电阻R4的另一端和级间匹配网络的端口4相连，微带线TL5的另一端与电感L5的一端相连，电感L5的另一端分别与电容C9的一端，电容C8的一端以及级间匹配网络的端口2相连，电容C9的另一端与背孔BVIA7的一端连接，背孔BVIA7的另一端接地，电容C8的另一端与背孔BVIA7的一端连接，背孔BVIA6的另一端接地；
如图5所示，所述的输出匹配网络包括与输出匹配网络的端口3相连的电容C12、电容C13和电感L6，电容C12的另一端与背孔BVIA8的一端相连，背孔BVIA8的另一端接地，电容C13的另一端与背孔BVIA9的一端相连，背孔BVIA9的另一端接地，电感L6的另一端与微带线TL6的一端相连，微带线TL6的另一端分别与输出匹配网络端口1和电容C14的一端相连，电容C14的另一端分别与电容C15的一端和微带线TL7的一端相连，电容C15的另一端和背孔BVIA10的一端相连，背孔BVIA10的另一端接地，微带线TL7的另一端与电感L7的一端相连，电感L7的另一端分别与电容C16的一端和输出匹配网络的端口2相连，电容C16的另一端和背孔BVIA11的一端相连，背孔BVIA11的另一端接地。
其中所述的电容C2、电容C3、电容C4、电容C5、电容C7、、电容C9、电容C1 1、电容C12、电容C13、电容C15、电容C16均为MIM电容；电阻R1、R2、电阻R3、电阻R4均为薄膜电阻，所述的电感L2、电感L3、电感L4、电感L5、电感L6、电感L7均为方形线圈平面电感。
根据pHEMT晶体管管芯采用的功率密度、管芯本身的功率大小、栅宽、电路损耗和整个工作频段的效率要求，确定管芯的尺寸，并进一步选取输出级管芯和输入级管芯，输出级选取6*125um管芯，输入级选取4*75um管芯。
使用负载牵引找出输出级管芯和输出级管芯的最佳负载阻抗即ZL1、ZL2和最佳源阻抗即ZS1、ZS2，所述的最佳负载阻抗和最佳源阻抗指管芯功率最大和效率最大进行折中的一个阻抗点；具体包括：分别使用LoadPull即负载牵引和SourcePul1即源牵引找出两种管芯的最佳负载阻抗即ZL1、ZL2和最佳源阻抗即ZS1、ZS2；通过给管芯设置不同的输入源阻抗和输出负载阻抗，使用谐波平衡法计算各种输入输出阻抗条件下输出级管芯的功率和效率值，经过反复的LoadPull、Source Pull迭代最终找到一个使管芯功率或者效率最大的输入源阻抗和输出负载阻抗；
根据管芯的最佳负载阻抗和最佳源阻抗进行各级匹配网络设计，具体地说，输入匹配网络负责将50Ohm输入阻抗变换至ZS1并同时提供输入级管芯的栅极偏置电源，级间匹配网络负责将ZL1变换至ZS2并同时提供输入级管芯的漏极偏执电源和输出级的栅极偏置电源，输出匹配网络则负责将ZL2变换至50Ohm并同时提供输出级管芯的漏极偏置电源。
使用S参数仿真计算放大器的包括小信号增益、输入输出驻波系数、稳定系数在内的指标，使用谐波平衡仿真计算放大器在输入管芯的输入功率大小的输入时的包括功率增益、输出功率、电源附加效率、谐波抑制在内的指标；优化放大器的各级匹配网络，即调整网络各部分的电阻、电容、电感、微带线尺寸，使得多个参数符合要求；
按照优化后的电路原理图进行版图Layout设计，并将芯片尺寸限制在设计范围内；对版图进行电路、电磁场联合仿真，其中在仿真过程中，管芯设置为电路仿真，其余包括传输线、电容、电阻、电感在内的无源部分设置为电磁场仿真。
发明的有益效果
有益效果
本发明的有益效果优化了稳定系数、输入输出驻波系统、增益、功率、效率、谐波抑制等指标，使小信号增益控制在31dB左右，稳定系数在0.1～10GHz范围内均大于1.05，输出功率大于2.3W，电源附加效率大于45％，谐波抑制大于20dBc。
对附图的简要说明
附图说明
图1为本发明放大器原理框图；
图2为本发明放大器版图；
图3输入匹配网络设计图；
图4级间匹配网络设计图；
图5输出匹配网络设计图；
图6为输入输出阻抗Smith圆图；
图7为输入输出反射示意图；
图8为稳定系数示意图；
图9为输出功率(W)与电源附加效率曲线图；
图10为输出功率(W)与电源附加效率列表图；
图11为功率增益与输出功率(W)对比图；
图12为谐波抑制图。
发明实施例
本发明的实施方式
下面结合附图进一步详细描述本发明的技术方案：
2.7-3.5GHz 2W GaN单片功率放大器，其特征在于，包括输入匹配网络、级间匹配网络网络、输出匹配网络、栅极偏置电源、漏极偏置电源、pHEMT晶体管S1、S2；
本发明原理框图，输入匹配网络的端口1与信号源连接，输入匹配网络的端口3分别与级间匹配网络的端口4和电感L1的一端相连，电感L1的另一端与栅极偏置电源的正极相连，栅极偏置电流的负极接地，输入匹配网络的端口2与pHEMT晶 体管S1的栅极相连，pHEMT晶体管S1的源极接地，pHEMT晶体管S1的漏极与级间匹配网络的端口1相连，级间匹配网络的端口3与漏极偏置电源的正极相连，漏极偏置电源的负极接地，级间匹配网络的端口2与pHEMT晶体管S2的栅极相连，pHEMT晶体管S2的源极接地，pHEMT晶体管S2的漏极与输出匹配网络的端口1相连，输出匹配网络的端口2与负载相连，输出匹配网络的端口3与漏极偏置电源的正极相连，漏极偏置电源的负极接地；
各匹配级网络具体设计如下：
如图3所示，所述的输入匹配网络包括与级间匹配网络的端口3连接的电容C1、电容C2和电阻R1相连电容C1的另一端与背孔BVIA1的一端连接，背孔BVIA1的另一端接地，圆电容C2的另一端与背孔BVIA2的一端相连，背孔BVIA2的另一端接地，电阻R1的另一端与电感L2的一端相连，电感L2的另一端与微带线TL1的一端相连，微带线TL1的另一端分别与电阻R2的一端，微带线TL2的一端，电容C5的一端以及电阻R3的一端相连，微带线TL2的另一端与电容C3的一端相连，电容C3的另一端与输入匹配网络的端口1相连，电阻R2的另一端与电容C4的一端相连，电容C4的另一端与背孔BVIA3的一端相连，背孔BVIA3的另一端接地，输入匹配网络的端口2分别与电容C5的另一端与电阻R3的另一端相连；
如图4所示，所述的级间匹配网络包括与级间匹配网络的端口3相连的电容C6、电容C7和电感L3相连。，电容C6的另一端与背孔BVIA4的一端相连，背孔BVIA4的另一端接地，电容C7的另一端与背孔BVIA5的一端相连，背孔BVIA5的另一端接地，电感L3的另一端与微带线TL3的一端相连，微带线TL3的另一端分别与微带线TL4的一端和电感L4的一端相连，微带线TL4的另一端与级间匹配网络的端口1相连，电感L4的另一端与电容C10的一端相连，电容C10的另一端分别与微带线TL5的一端，电容C11的一端以及电阻R4的一端相连，电容C11的另一端分别与电阻R4的另一端和级间匹配网络的端口4相连，微带线TL5的另一端与电感L5的一端相连，电感L5的另一端分别与电容C9的一端，电容C8的一端以及级间匹配网络的端口2相连，电容C9的另一端与背孔BVIA7的一端连接，背孔BVIA7的另一端接地，电容C8的另一端与背孔BVIA7的一端连接，背孔BVIA6的另一端接地；
如图5所示，所述的输出匹配网络包括与输出匹配网络的端口3相连的电容C12、电容C13和电感L6，电容C12的另一端与背孔BVIA8的一端相连，背孔BVIA8的另一端接地，电容C13的另一端与背孔BVIA9的一端相连，背孔BVIA9的另一端接地，电感L6的另一端与微带线TL6的一端相连，微带线TL6的另一端分别与输出匹配网络端口1和电容C14的一端相连，电容C14的另一端分别与电容C15的一端和微带线TL7的一端相连，电容C15的另一端和背孔BVIA10的一端相连，背孔BVIA10的另一端接地，微带线TL7的另一端与电感L7的一端相连，电感L7的另一端分别与电容C16的一端和输出匹配网络的端口2相连，电容C16的另一端和背孔BVIA11的一端相连，背孔BVIA11的另一端接地。
其中所述的电容C2、电容C3、电容C4、电容C5、电容C7、、电容C9、电容C11、电容C12、电容C13、电容C15、电容C16均为MIM电容；电阻R1、R2、电阻R3、电阻R4均为薄膜电阻，所述的电感L2、电感L3、电感L4、电感L5、电感L6、电感L7均为方形线圈平面电感。
2.7-3.5GHz 2W GaN单片功率放大器的设计方法如下：
首先确定管芯的有源尺寸，NP25-00工艺管芯的功率密度约为4.9W/mm，则对2W放大器而言输出级管芯的栅宽最小仅需0.41mm，但是考虑到电路损耗以及整个工作频段的效率要求，输出级选取6*125um管芯，功率增益约为10dB；输入级选取4*75um管芯。
根据pHEMT晶体管管芯采用的功率密度、管芯本身的功率大小、栅宽、电路损耗和整个工作频段的效率要求，确定管芯的尺寸，并进一步选取输出级管芯和输入级管芯，输出级选取6*125um管芯，输入级选取4*75um管芯。
使用负载牵引找出输出级管芯和输出级管芯的最佳负载阻抗即ZL1、ZL2和最佳源阻抗即ZS1、ZS2，所述的最佳负载阻抗和最佳源阻抗指管芯功率最大和效率最大进行折中的一个阻抗点；具体包括：分别使用LoadPull即负载牵引和SourcePul1即源牵引找出两种管芯的最佳负载阻抗即ZL1、ZL2和最佳源阻抗即ZS1、ZS2；通过给管芯设置不同的输入源阻抗和输出负载阻抗，使用谐波平衡法计算各种输入输出阻抗条件下输出级管芯的功率和效率值，经过反复的LoadPull、Source Pull迭代最终找到一个使管芯功率或者效率最大的输入源阻抗和输出负载阻抗； 根据管芯的最佳负载阻抗和最佳源阻抗进行各级匹配网络设计，具体地说，输入匹配网络负责将50Ohm输入阻抗变换至ZS1并同时提供输入级管芯的栅极偏置电源，级间匹配网络负责将ZL1变换至ZS2并同时提供输入级管芯的漏极偏执电源和输出级的栅极偏置电源，输出匹配网络则负责将ZL2变换至50Ohm并同时提供输出级管芯的漏极偏置电源。
使用S参数仿真计算放大器的包括小信号增益、输入输出驻波系数、稳定系数在内的指标，使用谐波平衡仿真计算放大器在输入管芯的输入功率大小的输入时的包括功率增益、输出功率、电源附加效率、谐波抑制在内的指标；仿真效果如仿真效果如图6～图12所示。优化放大器的各级匹配网络，即调整网络各部分的电阻、电容、电感、微带线尺寸，使得多个参数符合要求；
按照优化后的电路原理图进行版图Layout设计，并将芯片尺寸限制在设计范围内；对版图进行电路、电磁场联合仿真，其中在仿真过程中，管芯设置为电路仿真，其余包括传输线、电容、电阻、电感在内的无源部分设置为电磁场仿真。
本发明的有益效果优化了稳定系数、输入输出驻波系统、增益、功率、效率、谐波抑制等指标，使小信号增益控制在31dB左右，稳定系数在0.1～10GHz范围内均大于1.05，输出功率大于2.3W，电源附加效率大于45％，谐波抑制大于20dBc。

Claims (5)

  1. 一种2.7-3.5GHz 2W GaN单片功率放大器，其特征在于，包括输入匹配网络、级间匹配网络网络、输出匹配网络、栅极偏置电源、漏极偏置电源、pHEMT晶体管S1、S2；
    所述的输入匹配网络的端口1与信号源连接，输入匹配网络的端口3分别与级间匹配网络的端口3和电感L1的一端相连，电感L1的另一端与栅极偏置电源的正极相连，栅极偏置电流的负极接地，输入匹配网络的端口2与pHEMT晶体管S1的栅极相连，pHEMT晶体管S1的源极接地，pHEMT晶体管S1的漏极与级间匹配网络的端口1相连，级间匹配网络的端口4与漏极偏置电源的正极相连，漏极偏置电源的负极接地，级间匹配网络的端口2与pHEMT晶体管S2的栅极相连，pHEMT晶体管S2的源极接地，pHEMT晶体管S2的漏极与输出匹配网络的端口1相连，输出匹配网络的端口2与负载相连，输出匹配网络的端口3与漏极偏置电源的正极相连，漏极偏置电源的负极接地；
    所述的输入匹配网络包括与级间匹配网络的端口3连接的电容C1、电容C2和电阻R1相连电容C1的另一端与背孔BVIA1的一端连接，背孔BVIA1的另一端接地，圆电容C2的另一端与背孔BVIA2的一端相连，背孔BVIA2的另一端接地，电阻R1的另一端与电感L2的一端相连，电感L2的另一端与微带线TL1的一端相连，微带线TL1的另一端分别与电阻R2的一端，微带线TL2的一端，电容C5的一端以及电阻R3的一端相连，微带线TL2的另一端与电容C3的一端相连，电容C3的另一端与输入匹配网络的端口1相连，电阻R2的另一端与电容C4的一端相连，电容C4的另一端与背孔BVIA3的一端相连，背孔BVIA3的另一端接地，输入匹配网络的端口2分别与电容C5的另一端与电阻R3的另一端相连；
    所述的级间匹配网络包括与级间匹配网络的端口3相连的电容C6、电容C7和电感L3相连；
    电容C6的另一端与背孔BVIA4的一端相连，背孔BVIA4的另一端接地，电容C7的另一端与背孔BVIA5的一端相连，背孔BVIA5的另一端接地，电感L3的另一端与微带线TL3的一端相连，微带线TL3的另一端分别与微带线TL4的一端和电感L4的一端相连，微带线TL4的另一端与级间匹配网络的端口1相连，电感L4的另一端与电容C10的一端相连，电容C10的另一端分别与微带线TL5的一端，电容C11的一端以及电阻R4的一端相连，电容C11的另一端分别与电阻R4的另一端和级间匹配网络的端口4相连，微带线TL5的另一端与电感L5的一端相连，电感L5的另一端分别与电容C9的一端，电容C8的一端以及级间匹配网络的端口2相连，电容C9的另一端与背孔BVIA7的一端连接，背孔BVIA7的另一端接地，电容C8的另一端与背孔BVIA7的一端连接，背孔BVIA6的另一端接地；
    所述的输出匹配网络包括与输出匹配网络的端口3相连的电容C12、电容C13和电感L6，电容C12的另一端与背孔BVIA8的一端相连，背孔BVIA8的另一端接地，电容C13的另一端与背孔BVIA9的一端相连，背孔BVIA9的另一端接地，电感L6的另一端与微带线TL6的一端相连，微带线TL6的另一端分别与输出匹配网络端口1和电容C14的一端相连，电容C14的另一端分别与电容C15的一端和微带线TL7的一端相连，电容C15的另一端和背孔BVIA10的一端相连，背孔BVIA10的另一端接地，微带线TL7的另一端与电感L7的一端相连，电感L7的另一端分别与电容C16的一端和输出匹配网络的端口2相连，电容C16的另一端和背孔BVIA11的一端相连，背孔BVIA11的另一端接地。
  2. 根据权利要求1所述的一种2.7-3.5GHz 2W GaN单片功率放大器，其特征在于，所述的pHEMT晶体管S1、S2，其中pHEMT晶体管S1为输出级管芯，pHEMT晶体管S2为输出级管芯；
    其中所述的电容C2、电容C3、电容C4、电容C5、电容C7、、电容C9、电容C11、电容C12、电容C13、电容C15、电容C16均为MI M电容；电阻R1、R2、电阻R3、电阻R4均为薄膜电阻，所述的电感L2、电感L3、电感L4、电感L5、电感L6、电感L7均为方形线圈平面电感。
  3. 如权利要求1或2所述的一种2.7-3.5GHz 2W GaN单片功率放大器的设计方法，其特征在于，包括以下步骤：
    根据pHEMT晶体管管芯采用的功率密度、管芯本身的功率大小、栅宽、电路损耗和整个工作频段的效率要求，确定管芯的尺寸；并进一步选取输出级管芯和输入级管芯；
    使用负载牵引找出输出级管芯和输出级管芯的最佳负载阻抗即ZL1、ZL2和最佳源阻抗即ZS1、ZS2，所述的最佳负载阻抗和最佳源阻抗指管芯功率最大和效率最大进行折中的一个阻抗点；具体包括：分别使用LoadPull即负载牵引和SourcePull即源牵引找出两种管芯的最佳负载阻抗即ZL1、ZL2和最佳源阻抗即ZS1、ZS2；通过给管芯设置不同的输入源阻抗和输出负载阻抗，使用谐波平衡法计算各种输入输出阻抗条件下输出级管芯的功率和效率值，经过反复的LoadPull、SourcePull迭代最终找到一个使管芯功率或者效率最大的输入源阻抗和输出负载阻抗；
    使用S参数仿真计算放大器的包括小信号增益、输入输出驻波系数、稳定系数在内的指标，使用谐波平衡仿真计算放大器在输入管芯的输入功率大小的输入时的包括功率增益、输出功率、电源附加效率、谐波抑制在内的指标；优化放大器的各级匹配网络，即调整网络各部分的电阻、电容、电感、微带线尺寸，使得多个参数符合要求；
    按照优化后的电路原理图进行版图Layout设计，并将芯片尺寸限制在设计范围内；对版图进行电路、电磁场联合仿真，其中在仿真过程中，管芯设置为电路仿真，其余包括传输线、电容、电阻、电感在内的无源部分设置为电磁场仿真。
  4. 根据权利要求3所述的设计方法，其特征在于，所述的输出级管芯 和输入管级芯采用WIN Foundry的NP25-00GaN工艺，管芯功率密度为4.9W/mm。
  5. 根据权利要求3所述的设计方法，其特征在于，所述的使得多个参数符合要求包括使小信号增益控制在31dB左右，稳定系数在0.1-10GHz范围内均＞1.05，输出功率＞2.3W，电源附加效率＞45％，谐波抑制＞20dBc。
PCT/CN2016/096418 2016-07-05 2016-08-23 2.7-3.5 GHz 2W GaN单片功率放大器及设计方法 WO2018006483A1 (zh)

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