WO2018004697A1 - Dispositifs rram à oxyde métallique double couche et procédés de fabrication - Google Patents

Dispositifs rram à oxyde métallique double couche et procédés de fabrication Download PDF

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Publication number
WO2018004697A1
WO2018004697A1 PCT/US2016/040873 US2016040873W WO2018004697A1 WO 2018004697 A1 WO2018004697 A1 WO 2018004697A1 US 2016040873 W US2016040873 W US 2016040873W WO 2018004697 A1 WO2018004697 A1 WO 2018004697A1
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Prior art keywords
metal oxide
oxide layer
layer
sub
bottom electrode
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PCT/US2016/040873
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English (en)
Inventor
Niloy Mukherjee
Uday Shah
Ravi Pillarisetty
Prashant Majhi
Elijah V. KARPOV
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Intel Corporation
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Priority to PCT/US2016/040873 priority Critical patent/WO2018004697A1/fr
Publication of WO2018004697A1 publication Critical patent/WO2018004697A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H10N70/8265—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx

Definitions

  • Embodiments of the invention are in the field of integrated circuit fabrication and, in particular, dual layer metal oxide resistive random access memory (RRAM) devices and their methods of fabrication.
  • RRAM resistive random access memory
  • Non-volatile embedded memory with RRAM devices e.g., on-chip embedded memory with non-volatility can enable energy and computational efficiency.
  • the technical chal lenges of creating an appropriate stack for fabrication of RRAM devices that exhibit high device endurance, high retention and operability at low voltages and currents presents daunting roadblocks to commercialization of this technology today.
  • the objective of memory technology to control tail bit data in a large array of memory bits necessitates tighter control of the variations in metal oxide break down and switching events in individual bits.
  • filamentary RRAM systems the latter is dictated by fine tuning oxygen vacancy concentration which is widely understood to drive filament formation and dissolution in metal oxide films.
  • significant improvements are still needed in the area of metal oxide stack engineering which rely on material advancements, deposition techniques or a combination of both. This area of process development is an integral part of the non-volatile memory roadmap.
  • FIG. 1 A illustrates a cross-sectional view of a resistive random access memory (RRAM) cell formed on top of a conductive electrode and a first dielectric layer, and surrounded by a dielectric spacer and a second dielectri c l ayer, in accordance with an embodiment of the present invention.
  • RRAM resistive random access memory
  • Figure IB illustrates a cross-sectional view of an RRAM cell where a highly stoichiometric metal oxide layer, a sub-stoichiometric metal oxide layer and a top electrode are disposed in an opening in a dielectric layer, in accordance with an embodiment of the present invention.
  • Figure 1C illustrates a cross-sectional view of an RRAM cell where a bottom electrode, a highly stoichiometric metal oxide layer, a sub-stoichiometric metal oxide layer and a top electrode are disposed in an opening in a dielectric layer, in accordance with an embodiment of the present invention.
  • Figures 2A-2J illustrate cross-sectional views representing various operations in a method of fabricating an RRAM device integrated on a conductive interconnect, which may be used to fabricate a memory device such as described in association with Figure 1 A, in accordance with an embodiment of the present invention.
  • Figure 2A illustrates a conductive interconnect surrounded by a first dielectric layer
  • Figure 2B illustrates a material layer stack for a resistive random access memory application formed on a conductive interconnect.
  • Figure 2C illustrates a resist pattern formed on a dielectric hardmask layer formed on the material layer stack.
  • Figure 2D illustrates the structure of Figure 2C following an etch process used to transfer the resist pattern into the dielectric hardmask layer to form a dielectric hardmask pattern.
  • Figure 2E illustrates the structure of Figure 2D following the removal of the resist pattern.
  • Figure 2F illustrates the structure of Figure 2E following an etch process used to transfer the dielectric hardmask pattern into the material layer stack to form a resistive random access memory device.
  • Figure 2G illustrates the structure of Figure 2F following the formation of a dielectric spacer layer covering the sidewails of the resistive random access memory device, the top dielectric hardmask pattern and the top of the first dielectric layer surrounding the conductive interconnect.
  • Figure 2H illustrates the structure of Figure 2G following an anisotropic plasma etch of the dielectric spacer layer to form a dielectric spacer.
  • Figure 21 illustrates the structure of Figure 2H following formation of a second dielectric layer covering the resistive random access memory device, the dielectric hardmask pattern, the dielectric spacer and the first dielectric layer surrounding the conductive interconnect.
  • Figure 2J illustrates the structure of Figure 21 following planarization of the second dielectric layer, the dielectric spacer, and the top portion of the top electrode.
  • Figure 3 illustrates a cross-sectional view representing an RRAM device where the width of a bottom electrode is smaller than the width of a conducive interconnect, in accordance with an embodiment of the present invention.
  • Figure 4 illustrates a cross-sectional view representing an RRAM device where the width of a bottom electrode is smaller than the width of a conducive interconnect, and the interconnect includes a capping layer, in accordance with an embodiment of the present invention.
  • Figures 5A-5L illustrate cross-sectional views representing various operations in a method of fabricating a resistive random access memory device integrated on a conductive interconnect, which may be used to fabricate a memory device such as described in association with Figure IB, in accordance with an embodiment of the present invention.
  • Figure 5A illustrates a conductive interconnect formed in a first dielectric layer above a substrate.
  • Figure 5B illustrates the structure of Figure 5 A following recessing of the conductive interconnect to a level below an uppermost surface of the first dielectric layer.
  • Figure 5C illustrates the structure of Figure 5B following formation of a bottom electrode material on the recessed conductive interconnect and on the uppermost surface of the first dielectric layer.
  • Figure 5D illustrates the structure of Figure 5C following planarization of the bottom electrode material to form a bottom electrode.
  • Figure 5E illustrates the structure of Figure 5D following formation of a second dielectric layer on an uppermost surface of the bottom electrode and on the uppermost surface of the first dielectric layer.
  • Figure 5F illustrates the structure of Figure 5E following patterning of a photoresist material to form a mask to define a via location.
  • Figure 5G illustrates the structure of Figure 5F following an etch process to create a via in the second dielectric layer.
  • Figure 5H illustrates the structure of Figure 5G following removal of the mask.
  • Figure 51 illustrates the structure of Figure 5H following formation of a highly
  • Figure 5J illustrates the structure of Figure 51 following formation of a sub-stoichiometric metal oxide material in the via and on the highly stoichiometric metal oxide material.
  • Figure 5 illustrates the structure of Figure 5 J following formation of a top electrode metal material in the via and on the sub-stoichiometric metal oxide material.
  • Figure 5L illustrates the structure of Figure 5K following a planarization process to form a top electrode, a sub-stoichiometric metal oxide layer, and a stoichiometric metal oxide layer.
  • Figures 6A-6J illustrate cross-sectional views representing various operations in a method of fabricating a resistive random access memory device integrated on a conductive interconnect, which may be used to fabricate a memory device such as described in association with Figure 1C, in accordance with an embodiment of the present invention
  • Figure 6A illustrates a conductive interconnect formed in a first dielectric layer above a substrate.
  • Figure 6B illustrates the structure of Figure 6A following formation of a second dielectric layer on an uppermost surface of the conductive interconnect and on an uppermost surface of the first dielectric layer.
  • Figure 6C illustrates the structure of Figure 6B following patterning of a photoresist material to form a mask to define a via location.
  • Figure 6D illustrates the structure of Figure 6C following an etch process to create a via in the second dielectric layer.
  • Figure 6E illustrates the structure of Figure 6D following removal of the mask.
  • Figure 6F illustrates the structure of Figure 6E following formation of a bottom electrode metal material in the via and on the conductive interconnect.
  • Figure 6G illustrates the structure of Figure 6F following formation of a highly
  • Figure 6H illustrates the structure of Figure 6G following formation of a sub- stoichiometric metal oxide material in the via and on the highly stoichiometric metal oxide material.
  • Figure 61 illustrates the structure of Figure 6H following formation of a top electrode metal material in the via and on the sub-stoichiometric metal oxide material.
  • Figure 6J illustrates the structure of Figure 61 following a planarization process to form a top electrode, a sub-stoichiometric metal oxide layer, a stoichiometric metal oxide layer, and a bottom electrode.
  • Figure 7 A illustrates a plan view of an array of RRAM cells of the type illustrated in Figure 1 A, in accordance with an embodiment of the present invention.
  • Figure 7B illustrates a plan view of an array of RRAM cells of the type illustrated in Figure IB, in accordance with an embodiment of the present invention.
  • Figure 7C illustrates a plan view of an array of RRAM cells of the type illustrated in Figure 1 C, in accordance with an embodiment of the present invention.
  • Figure 8 illustrates a cross-sectional view of a conventional RRAM device.
  • Figures 9 illustrates an I-V plot, demonstrating concepts involved with filament formation and voltage cycling (reading and writing) in an RRAM device, in accordance with embodiments of the present invention.
  • Figure 0 illustrates a cross-sectional view of an RRAM element coupled to a drain side of a select transi stor, in accordance with an embodiment of the present invention.
  • Figures 1 1 A-l I E illustrate schematic views of several options for positioning an RRAM element in an integrated circuit, in accordance with embodiments of the present invention.
  • Figure 12 illustrates a schematic of a memory bit cell which includes a metal -conductive oxide-metal RRAM device, in accordance with embodiments of the present invention.
  • FIG. 13 illustrates a block diagram of an electronic system, in accordance with embodiments of the present invention.
  • Figure 14 illustrates a computing device in accordance with embodiments of the present invention.
  • Figure 15 illustrates an interposer in accordance with embodiments of the present invention.
  • Dual layer metal oxide resistive random access memory (RRAM) devices and their methods of fabrication are described.
  • numerous specific details are set forth, such as novel structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features, such as switching operations associated with embedded memory, are described in lesser detail in order to not unnecessarily obscure embodiments of the present invention.
  • the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.
  • integrating a memory array with low voltage logic circuitry such as logic circuitry operational at a voltage less than or equal to 1 Volt, may be advantageous since it enables higher operation speeds compared to having physically separate logic and memory chips.
  • approaches to integrating an RRAM device onto a transistor to create embedded memory presents material challenges that have become far more daunting with scaling. As transistor operating voltages are scaled down in an effort to become energy efficient, RRAM memory devices that are connected in series with such transistors are also required to function at lower voltages and currents.
  • FIG 8 illustrates a cross-sectional view of a conventional RRAM device 800.
  • the RRAM device 800 includes a top electrode 812, an oxygen exchange layer 810, a stoichiometric metal oxide switching layer 808, and a bottom electrode 806.
  • the RRAM device 800 is above an interconnect 804 formed in a dielectric layer 802 above a substrate 801.
  • the oxygen exchange layer 810 of RRAM device 800 is a metal that acts as a source or sink of oxygen vacancies.
  • the oxygen exchange layer 810 may require protection from extraneous sources of oxidation during the fabrication process for reliable device
  • an oxygen exchange layer is replaced with a uniform sub-stoichiometric metal oxide layer.
  • FIG. 1 A illustrates a cross-sectional view of a resistive random access memory (RRAM) ceil formed on top of a conductive electrode and a first dielectric layer, and surrounded by a dielectric spacer and a second dielectric layer, in accordance with an
  • FIG. 1 A illustrates a cross-sectional view of an RRAM cell, in accordance with an embodiment of the present invention.
  • the RRAM cell includes an RRAM memory device 100 disposed on a conductive interconnect 104, such as a conductive line or via.
  • a conductive interconnect 104 such as a conductive line or via.
  • the conductive interconnect 104 includes a barrier layer, such as tantalum nitride, and a fill material, such as copper, as is known in the art.
  • the conductive interconnect 104 is disposed within a dielectric layer 102 disposed above a substrate 101.
  • the RRAM device 100 includes a bottom electrode 106 disposed above the conductive interconnect 104.
  • a highly stoichiometric metal oxide layer 108 is disposed on the bottom electrode 106.
  • a sub-stoichiometric metal oxide layer 110 is disposed on the highly stoichiometric metal oxide layer 108 .
  • a top electrode 1 12 is disposed on the sub-stoichiometric oxide layer 1 10.
  • the bottom electrode 106 extends laterally onto a portion of the dielectric layer 102, as is depicted.
  • a dielectric spacer 1 16 is disposed adjacent and on sidewalls of the RRAM device 100 and on the first dielectric layer 102.
  • the dielectric spacer 1 16 extends from the uppermost surface of the first dielectric layer 102 to an upper most surface of the top electrode 1 12 and may be any suitable dielectric material such as but not limited to carbon doped silicon nitride or silicon nitride.
  • the dielectric material of the dielectric spacer 1 16 is a non-oxygen- containing material.
  • a second dielectric layer 1 18 is disposed on the first dielectric layer 102 and laterally adjacent to the dielectric spacer 1 16. An uppermost surface of the second dielectric layer 118 is coplanar or substantially coplanar with an uppermost surface of the dielectric spacer 1 16 and the uppermost surface of the top electrode 1 12,
  • the bottom electrode 106 includes a material such as but not limited to titanium nitride, tantalum, tantalum nitride, tungsten or ruthenium. In an embodiment, the bottom electrode 106 has a thickness in the range of 40 to 100 nanometers (nm). In an embodiment, the composition and thickness of the bottom electrode 106 are tuned to m eet specific device attributes such as series resistance, programming voltage and current. In an embodiment, a portion of the bottom electrode 106 at an interface between the bottom electrode 106 and the highly stoichiometric metal oxide layer 108 is oxidized. In one such embodiment, the bottom electrode 106 includes tungsten or ruthenium and the oxidized portion of the bottom electrode 106 remains conductive.
  • the highly stoichiometric metal oxide layer 108 is composed of a metal (M), such as but not limited to, hafnium, tantalum or titanium.
  • M metal
  • the highly stoichiometric metal oxide layer 108 has a chemical composition, MOx, where O is oxygen and X is or is substantially close to 2.
  • the highly stoichiometric metal oxide layer 108 has a chemical composition, M 2 Ox, where O is oxygen and X is or is substantially close to 5.
  • the highly stoichiometric metal oxide layer 108 has a thickness approximately in the range of 1-5 nm.
  • the sub-stoichiometric metal oxide layer 110 acts as a source of oxygen vacancy or as a sink for O 2" .
  • the sub-stoichiometric metal oxide layer 1 10 is less stoichiometric than the highly stoichiometric metal oxide layer 108.
  • the sub-stoichiometric metal oxide layer 110 is composed of a metal (M), such as but not limited to, hafnium, tantalum or titanium.
  • the sub-stoichiometric metal oxide layer 1 10 has a chemical composition, ⁇ 0 2 . ⁇ , where O is oxygen and Y is approximately in the range of 0.01 to 0.05.
  • the sub-stoichiometric metal oxide layer 110 has a chemical composition, M2O5-Y, where O is oxygen and Y is approximately in the range of 0.01 to 0.05.
  • the sub-stoichiometric metal oxide layer 110 has a thickness approximately in the range of 3-20 nm.
  • the metal (M) of the highly stoichiometric metal oxide layer 108 is the same as the metal (M) of the sub-stoichiometric metal oxide layer 110. In another embodiment, the metal (M) of the highly stoichiometric metal oxide layer 108 is different than the metal (M) of the sub-stoichiometric metal oxide layer 1 10. In an embodiment, the highly stoichiometric metal oxide layer 108 is more stoichiometric than the sub-stoichiometric metal oxide layer 110 by at least 0.1% in oxygen content.
  • the highly stoichiometric metal oxide layer 108 is more stoichiometric than the sub-stoichiometric metal oxide layer 1 10 by at least 0.2% in oxygen content.
  • the thickness of the sub-stoichiometric metal oxide layer 10 is at least twice the thickness of the highly stoichiometric metal oxide layer 108. In another embodiment, the thickness of the sub-stoichiometric metal oxide layer 1 10 is at least three times the thickness of the highly stoichiometric metal oxide layer 108.
  • the top electrode 112 is composed of a material such as, but not limited to, titanium nitride, tantalum nitride, tungsten and ruthenium.
  • the bottom electrode 106 and the top electrode 12 are composed of the same material.
  • the top electrode has a thickness approximately in the range of 30 to 100 nm.
  • the composition and thickness of the top electrode 1 12 are tuned to meet specific device attributes such as series resistance, programming voltage and current.
  • FIG. IB illustrates a cross-sectional view of an R AM cell where a highly stoichiometric metal oxide layer, a sub-stoichiometric metal oxide layer and a top electrode disposed in an opening in a dielectric layer, in accordance with an embodiment of the present invention.
  • the RRAM ceil includes an RRAM device 120 disposed on a conductive interconnect 104, such as a conductive line or via, disposed in a first dielectric iayer 102.
  • the conductive interconnect 104 is recessed to provide a recess 107, and the bottom electrode 106 of the RRAM device 120 is included in the recess 107.
  • the highly stoichiometric metal oxide layer 108, the sub- stoichiometric metal oxide layer 1 10, and the top electrode 12 of the RRAM device 120 are disposed in an opening of a second dielectric layer 114 disposed above the first dielectric layer 102.
  • the highly stoichiometric metal oxide layer 108 is disposed on the bottom electrode 106 included in the recess 07.
  • the bottom electrode 106 has a width, Wbe, approximately equal to a width, Wei, of the conductive interconnect 104.
  • Wbe width
  • Wei width
  • an uppermost surface of the bottom electrode 106 is coplanar or substantially coplanar with the uppermost surface of the dielectric layer 102.
  • the uppermost portion of the second dielectric layer 14, the highly stoichiometric metal oxide iayer 108, the sub-stoichiometric oxide layer 110 and the top electrode 112 are coplanar or substantially coplanar with one another.
  • width, W t0 of the top of the opening in the second dielectric layer
  • the 114 is greater than the width, Wbo, of the base of the opening.
  • the sidewalls of the opening are slanted by an angle of approximately 45 degrees with respect to a vertical axis of the opening.
  • the width, Wbo, of the base of the opening may be larger or sm aller than the width of the bottom electrode 106, W e. It is to be appreciated that, in an embodiment, the portion of the highly stoichiometric metal oxide layer 108 that is in contact with the bottom electrode 106 determines an effective device size.
  • Figure 1C illustrates a cross-sectional view of an RRAM cell where a bottom electrode, a highly stoichiometric metal oxide layer, a sub-stoichiometric metal oxide layer and a top electrode are disposed in an opening in a dielectric layer, in accordance with an embodiment of the present invention.
  • the RRAM cell includes an RRAM device 140 disposed on a conductive interconnect 104, such as a conductive line or via, disposed in a first dielectric layer 102.
  • the conductive interconnect 04 of Figure 1C is not recessed.
  • the bottom electrode 106, the highly stoichiometric metal oxide layer 108, the sub- stoichiometric metal oxide layer 110, and the top electrode 1 12 of the RRAM device 140 are disposed in an opening of a second dielectric layer 1 14 disposed above the first dielectric layer 102,
  • the bottom electrode 106 is disposed on the conductive interconnect 104.
  • the uppermost portion of the second dielectric layer 11 , the bottom electrode 106, the highly stoichiometric metal oxide layer 08, the sub-stoichiometric oxide layer 110 and the top electrode 12 are coplanar or substantially coplanar with one another.
  • the portion of the bottom electrode 106 that is in contact with the uppermost surface of the conductive interconnect 104 has a thickness that is greater than a thickness of portions of the bottom electrode 106 disposed along the sidewalls of the second dielectric layer 4, In another embodiment, the portion of the bottom electrode 106 that is in contact with the uppermost surface of the conductive interconnect 104 has a thickness approximately the same as a thickness of portions of the bottom electrode 106 disposed along the sidewalls of the second dielectric layer 114.
  • Figures 2A-2J illustrate cross-sectional views representing various operations in a method of fabricating a resistive random access memory device integrated on a conductive interconnect, which may be used to fabricate a memory device such as described in association with Figure 1 A, in accordance with an embodiment of the present invention.
  • FIG. 2A illustrates a conductive interconnect 204 surrounded by a first dielectric layer 202 formed above a substrate 200.
  • Dielectric layer 202 may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (Si0 2 ), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or
  • the dielectric layer 202 may include pores or air gaps to further reduce their dielectric constant. In an embodiment, the total thickness of dielectric layer 202 may be in the range of 2000 A - 3000 A.
  • the conductive interconnect 204 may be fabricated using dual damascene processing or subtractive etching.
  • the dielectric layer 202 has an uppermost surface substantially co-planar with an uppermost surface of the conductive interconnect 204.
  • Figure 2B illustrates a material layer stack 220 for a resistive random access memory application formed on the conductive interconnect.
  • the material layer stack includes a bottom electrode material 206, a highly stoichiometric metal oxide material 208, a sub-stoichiometric oxide material 210 and a top electrode material 212 formed on the uppermost surface of the conductive interconnect 204 and the uppermost surface of the first dielectric layer 202.
  • the bottom electrode material 206 is a material having a composition and a thickness such as described above in association with the bottom electrode 106.
  • the bottom electrode material 206 is formed using a PVD or an ALD process process.
  • the bottom electrode material 204 includes a material deposited by a physical vapor deposition (PVD) process.
  • the bottom electrode material 204 is deposited by PVD and is composed of a material such as, but not limited to, TiN, TaN, W or Ru.
  • the bottom electrode material 206 is deposited by PVD to a thickness approximately in the range of 30 nm to lOOnm.
  • the process of depositing the bottom electrode metal material 206 using PVD may include an in-situ sputter cleans to first remove any oxide residue from the uppermost surface of the conductive interconnect 204.
  • a gas containing Ar may be used to energetically bombard the surface of the bottom electrode material 206 to remove any native oxide.
  • the bottom electrode material 206 is formed by a PVD process and is subsequently polished to achieve a surface roughness of 1 nm or less. Reducing surface roughness using a polishing process may offer advantages during cycling of an RRAM device as it may serve to reduce abmpt filament nucleation and hence lessen variation in cycling voltage in a large device array.
  • the bottom electrode material 206 is deposited using an atomic layer deposition (ALD) process.
  • ALD atomic layer deposition
  • the ALD process may offers advantages such as greater film thickness uniformity ( ⁇ 1 %) compared to a PVD process (-5%), but may have a slower deposition rate, e.g., a deposition rate of 0.5 nm - 2nm/min.
  • a planarization process is not needed subsequent to depositing using an ALD process. Reducing surface roughness using an ALD process may offer advantages during cycling of an RRAM device as it serves to reduce abrupt filament nucleation and hence lessen variation in cycling voltage in a large device array.
  • the bottom electrode material 206 is deposited by ALD and is composed of a material such as, but not limited to, TiN, TaN, W and Ru.
  • the highly stoichiometric metal oxide material 208 is formed on the bottom electrode material 206.
  • the highly stoichiometric metal oxide material 208 is a material having a composition and a thickness such as described above in association with the highly stoichiometric metal oxide layer 108.
  • the highly stoichiometric metal oxide material 208 is formed using an ALD process.
  • the ALD process may be characterized by a slow and a highly controlled metal oxide deposition rate.
  • the ALD process may also be highly uniform (e.g., approximately O. lnm level variation).
  • a pre-clean of the surface of the bottom electrode material 206 is performed immediately pri or to deposition of the highly stoichiometric metal oxide material 208.
  • the bottom electrode material 206 and the highly stoichiometric metal oxide material 208 are deposited sequentially in a same chamber or in a same tool without breaking vacuum. In such a case, it may not be necessary to perform an in-situ pre-clean immediately prior to deposition of the highly stoichiometric metal oxide material 208.
  • the sub-stoichiometric metal oxide material 210 is formed on the highly stoichiometric metal oxide material 208.
  • the sub-stoichiometric metal oxide material 208 is a material having a composition and a thickness such as described above in association with the sub-stoichiometric metal oxide layer 10.
  • the sub-stoichiometric metal oxide material 210 is formed using a PVD process.
  • the PVD process may offer an advantage of a controllable oxygen flow rate resulting in a sub-stoichiometric metal oxide layer that is oxygen deficient.
  • the oxygen flow rate is varied during the deposition process leading, to an oxygen concentration gradient within the resulting sub- stoichiometric metal oxide material.
  • the concentration gradient has a higher concentration of oxygen proximate to the highly stoichiometric metal oxide material 210 and a lower concentration of oxygen distal from the highly stoichiometric metal oxide material 210.
  • Such an arrangement may preferably provide greater oxygen vacancies in a location that aids with filament formation and dissolution.
  • the top electrode material 212 is formed on the sub- stoichiometric metal oxide material 210.
  • the top electrode material 212 is a material having a composition and a thickness such as described above in association with the top electrode 1 2.
  • the top electrode material 212 is formed using a PVD process.
  • the top electrode material 212 and the sub-stoichiometric metal oxide material 210 are deposited sequentially in a same chamber or in a same tool without breaking vacuum. By doing so, the sub-stoichiometric metal oxide may retain its oxygen vacancies.
  • the top electrode material 212 has a same composition as the bottom electrode layer 206.
  • Figure 2C illustrates a resist pattern 215 formed on a dielectric hardmask layer 214 formed on the material layer stack 220.
  • the dielectric hardmask material 214 is devoid of oxygen.
  • the dielectric hardmask material 214 is a material such as, but not limited to, silicon nitride, silicon carbide or carbon-doped silicon nitride.
  • the dielectric hardmask material 214 has a thickness approximately in the range of 50-100nm. The thickness of the dielectric hardmask materi al 214 may be determined by patterning fidelity and subsequent processing tolerances, as will be discussed further below.
  • the resist pattern 215 has a shape that ultimately defines a shape of an RRAM device fabricated from the material stack 220.
  • the resist pattern 215 has rectangular shape or a circular shape.
  • the resist pattern 215 has a shortest width in the range of 20-100nm.
  • Resist pattern 215 may include one or more materials such as an anti-reflective coating (ARC), gap-fill and pianarizing material in addition to or in place of a photoresist material.
  • the resist pattern 215 is formed to a thickness sufficient to retain its profile during subsequent patterning of the dielectric hardmask material 214 but not so thick as to prevent lithographic patterning into the smallest dimensions (e.g., critical dimensions) possible with photolithography processing.
  • Figure 2D illustrates the structure of Figure 2C following an etch process used to transfer the pattern of resist pattern 215 into the dielectric hardmask layer 214.
  • an anisotropic plasma etch process is used to pattern dielectric hardmask layer 214 with selectivity to the resist pattern 215.
  • a selectivity of greater than 3 to 1 between photoresist material and dielectric hardmask layer 214 is achieved, it is to be appreciated that chemical etchants utilized in the plasma etch process may depend on the dielectric material being etched, and may include one or more of CH x F y , 0 2 , Ar, N 2 and CF 4 .
  • Sidewali angles of the patterned dielectric hardmask layer 214 may be tailored to vary from 85-90 degrees depending on the type of etch conditions employed.
  • Figure 2E illustrates the structure of Figure 2D following removal of the resist pattern 215 selectively to the dielectric hardmask layer 214.
  • the resist pattern 215 is removed using an ash process.
  • the ash process may include use of a gas containing O2, H2 N2, etc.
  • polymeric films which may result from the interaction between a photoresist material and etch byproducts during memory device etch, may adhere to the sidewali portions of an etched RRAM material stack. If portions of such polymeric layers have metallic components, device performance may be significantly degraded.
  • the resist pattern 215 is removed prior to etching the material stack 220.
  • Figure 2F illustrates the structure of Figure 2E following an etch process used to transfer the dielectric hardmask pattern into the material layer stack 220 to form a resistive random access memory device 230.
  • etching of the material layer stack 220 is performed during a single introduction into an etch tool to etch all layers of the material layer stack 220 in a single pass.
  • the sub-stoichiometric material 210 is notched during the etch process to form a notch 211 in the resulting patterned sub-stoichiometric layer (indicated by the dotted line shown in Figure 2F).
  • the width of the bottom electrode 206 is larger than the width of the conductive interconnect 204.
  • the bottom electrode material 206 is completely etched the underlying first dielectric layer 202 is exposed.
  • there may be a small but noticeable amount of recess 203 in the dielectric layer 202 (indicated by the dotted line in Figure 2F).
  • Figure 2G illustrates the structure of Figure 2F following the formation of a dielectric spacer layer 216 covering the sidewalls of the resistive random access memory device 230, the top dielectric hardmask pattern 214 and the top of the first dielectric layer 202 surrounding the conductive interconnect 204.
  • deposition of the dielectric spacer material 216 is performed immediately post RRAM device etch, prior to breaking vacuum in the same tool or chamber used for the etch process. Such a procedure, known in the art as in-situ deposition, may hermetically seal the device and potentially decrease oxidation of sensitive sub-stoichiometric metal oxide layers.
  • the dielectric spacer material 216 is a material such as, but not limited to, silicon nitride, silicon carbide, carbon-doped silicon nitride, or any suitable non-oxygen containing material.
  • the dielectric spacer material 216 has a thickness approximately in the range of 20-50nm.
  • the RRAM device and the dielectric hardmask layer 214 have angled sidewalls between 80-90 degrees, and the dielectric spacer material 216 is deposited to a thickness greater than 50nm.
  • Figure 2H illustrates the structure of Figure 2G following an anisotropic plasma etch of the dielectric spacer layer 216 to form a dielectric spacer 217.
  • a silicon nitride dielectric spacer material 216 is etched using reactive ion etching utilizing a chemistry including Ar, 0 2 , and a fluorocarbon such as but not limited to CHF 3 , CH2F2, or C 4 F 8 .
  • Figure 21 illustrates the structure of Figure 2H following formation of a second dielectric layer 218 covering the resistive random access memory device 230, the dielectric hardmask pattern 214, the dielectric spacer 217 and the first dielectric layer 202 surrounding the conductive interconnect 204.
  • Suitable materials for the second dielectric layer 218 may be the same as those described in association with the first dielectric layer 202.
  • a total thickness of the second dielectric layer 218 is approximately 2 to 2.5 times the combined height of the RRAM device 230 and the dielectric hardmask layer 214.
  • Figure 2J illustrates the structure of Figure 21 following planarization of the second dielectric layer 218, the dielectric spacer 217, the dielectric hardmask layer 214, and an upper portion of the top electrode 212.
  • a chemical mechanical polishing (CMP) process is used for the planarizing.
  • CMP chemical mechanical polishing
  • the CMP process may include multiple processes.
  • a first processing operation includes use of a first slurry to planarize the second dielectric material 2 8, the dielectric hardmask layer 214 and a portion of the dielectric spacer layer 216.
  • a second, different, slurn,' is used to polish a portion of the top electrode 212.
  • the resulting structure may include uppermost portions of the second dielectric layer 218, the dielectric spacer 217 and the top electrode 212 that are co-planar with one another.
  • Figure 3 illustrates a cross-sectional view representing an RRAM device where the width of a bottom electrode is smaller than the width of a conducive interconnect, in accordance with an embodiment of the present invention.
  • the widt of the bottom electrode 206 is smaller than the width of the conductive interconnect 204.
  • etching of the bottom electrode material 206 exposes the uppermost surface of the conductive interconnect 204.
  • the etch may undesirably create recesses 302 and sputter copper particles 304 across the surface of the substrate.
  • Figure 4 illustrates a cross-sectional view representing an RRAM device where the width of a bottom electrode is smaller than the width of a conductive interconnect 400, and the conductive interconnect 400 includes a capping layer, in accordance with an embodiment of the present invention.
  • the conductive interconnect 400 includes capping layer 402 over a conductive fill material 404 and between a barrier layer 406.
  • the capping layer 402 is composed of a material different than the material of the fill material 404.
  • the conductive interconnect 400 is fabricated by recessing a fill material of the conductive interconnect 204 described in association with Figure 2A.
  • the capping layer 402 is composed of a different material than the bottom electrode 206 such that the bottom electrode 206 may be selectively etched top the capping layer 406 such that the capping layer 402 is not recessed during the formation of the bottom electrode 206.
  • the capping layer 402 is composed of the same material as the bottom electrode 206 and is recessed to form recesses 408 during the formation of the bottom electrode 206.
  • the capping layer 402 is sufficiently thick such that the recesses 408 do not expose a copper surface.
  • Figures 5A-5L illustrate cross-sectional views representing various operations in a method of fabricating a resistive random access memory device integrated on a conductive interconnect, which may be used to fabricate a memory device such as described in association with Figure IB, in accordance with an embodiment of the present invention.
  • Figure 5A illustrates a conductive interconnect 504 formed in a first dielectric layer 502 above a substrate 500.
  • Conductive interconnect 504 may be fabricated in a manner similar to the interconnect 204 described in association with Figure 2A.
  • Figure 5B illustrates the structure of Figure 5 A following recessing of the conductive interconnect 504 to a level below an uppermost surface of the first dielectric layer 502 to form a recess 503.
  • the recessing is performed by a combination of a dry and a wet etch process.
  • the recess 503 has a depth approximately in the range of 30nm- 60nm.
  • the recessing process may or may not recess all components of the conductive interconnect 504.
  • a conductive fill material is recessed and a diffusion barrier layer is not recessed and extends above the recessed conductive fill material.
  • both a conductive fill material and a diffusion barrier layer are recessed.
  • Figure 5C illustrates the structure of Figure 5B following formation of a bottom electrode material 505 on the recessed conductive interconnect 504 and on the uppermost surface of the first dielectric layer 502. Exemplary materials and deposition processes for the bottom electrode material 505 are as described above in association with bottom electrode 206.
  • Figure 5D illustrates the structure of Figure 5C following planarization of the bottom electrode material 505 to form a bottom electrode 506.
  • the bottom electrode material 505 is planarized using a CMP process.
  • the CMP process provides the bottom electrode 506 with an uppermost surface co-planar with the uppermost surface of the ILD layer 502.
  • Figure 5E illustrates the structure of Figure 51) following formation of a second dielectric layer 514 on an uppermost surface of the bottom electrode 506 and on the uppermost surface of the first dielectric layer 502.
  • the second dielectric material 514 is a material such as, but not limited to, silicon nitride, carbon doped nitride and silicon carbide. In another embodiment, the second dielectric material 514 is composed of an amorphous silicon oxynitride material. In an embodiment, the thickness of the second dielectric layer 514 is selected based on the width and height of the RRAM device to be fabricated. The thickness may be selected to account for an amount to be sacrificed during a CMP operation used at the end of an RRAM device structure fabrication process.
  • Figure 5F illustrates the structure of Figure 5E following patterning of a photoresist material to form a mask 516 to define a via location.
  • the via location is selected to ultimately expose at least a portion of the bottom electrode 506.
  • Figure 5G illustrates the structure of Figure 5F following an etch process used to create a via 517 in the second dielectric layer 514.
  • the via 517 exposes at least a portion of the bottom electrode 506.
  • the width of the top of the via 517 is wider than the bottom of the via.
  • the via 517 has sloped sidewails.
  • the sloped sidewails have an angle between 45-60 degrees with respect to a vertical axis of the via 517.
  • the width of the bottom of the via 517 is approximately the same size as the width of the bottom electrode 506.
  • a central vertical axis of the via 517 is centered with a center of the bottom electrode 506. In another embodiment, the central vertical axis of the via 517 is off-set with the center of the bottom electrode 506.
  • Figure 5H illustrates the structure of Figure 5G following removal of the mask 516.
  • the mask 516 is removed using a resist strip and cleans process.
  • the bottom electrode 506 is exposed to a plasma during the mask 516 removal .
  • the bottom electrode 506 is subjected to a sputter clean treatment prior to deposition of a next RRAM material layer stack.
  • Figure 51 illustrates the structure of Figure 5H following formation of a highly
  • the RRAM: device size may be determined by the smallest effective contact area between the highly stoichiometric metal oxide layer 507 and the bottom electrode 506.
  • the highly stoichiometric metal oxide layer 507 is formed at the bottom of the via 517 on the electrode 506, along the sidewails of the via 517, and on the uppermost surface of the second dielectric layer 514.
  • Exemplary material compositions and deposition techniques for forming the highly stoichiometric metal oxide layer 507 may be as described above for the highly stoichiometric metal oxide layer 208.
  • Figure 5J illustrates the structure of Figure 51 following formation of a sub-stoichiometric metal oxide material 509 in the via 5 1 7 and on the highly stoichiometric metal oxide material 507.
  • the sub-stoichiometric metal oxide layer 509 is formed at the bottom of the via 517 on the highly stoichiometric metal oxide material 507, along the sidewails of the via 517, and above the uppermost surface of the second dielectric layer 514.
  • Exemplary material compositions and deposition techniques for forming the sub-stoichiometric metal oxide layer 509 may be as described above for the sub-stoichiometric metal oxide layer 210.
  • Figure 5K illustrates the structure of Figure 5 J following formation of a top electrode material 511 in the via 517 and on the sub-stoichiometric metal oxide material 509.
  • the top electrode material 51 1 completely fills the via 517 and extends over the uppermost surface of the second dielectric layer 514.
  • Exemplary material compositions and deposition techniques for forming the top electrode material 51 1 may be as described above for the top electrode material 212.
  • Figure 5L illustrates the structure of Figure 5K following a planarization process to form a top electrode 512, a sub-stoichiometric metal oxide layer 510, and a highly stoichiometric metal oxide layer 508.
  • the planarization process is a CMP process.
  • the CMP process provides the top electrode 512, the sub-stoichiometric metal oxide layer 510, and the highly stoichiometric metal oxide layer 508 with uppermost surfaces co- planar with the uppermost surface of the second dielectric layer 514.
  • Figures 6A-6J illustrate cross-sectional views representing various operations in a method of fabricating a resistive random access memon,' device integrated on a conductive interconnect, which may be used to fabricate a memory device such as described in association with Figure 1C, in accordance with an embodiment of the present invention.
  • Figure 6A illustrates a conductive interconnect 604 formed in a first dielectric layer 602 above a substrate 600.
  • Conductive interconnect 604 may be fabricated in a manner similar to the interconnect 204 described in association with Figure 2 A,
  • Figure 6B illustrates the staicture of Figure 6 A following formation of a second dielectric layer 614 on an uppermost surface of the conductive interconnect 604 and on an uppermost surface of the first dielectric layer 602.
  • the second dielectric layer 614 may be composed of a material described in association with second dielectric layer 214.
  • the thickness of the second dielectric layer 614 is selected based on the width and height of the RRAM device to be fabricated. The thickness may be selected to account for an amount to be sacrificed during a CMP operation used at the end of an RRAM device structure fabrication process.
  • Figure 6C illustrates the structure of Figure 6B following patterning of a photoresist material to form a mask 616 to define a via location.
  • the via location is selected to ultimately expose at least a portion of the conductive interconnect 604.
  • Figure 6D illustrates the structure of Figure 6C following an etch process to create a via 617 in the second dielectric layer 614,
  • the width of the top of the via 617 is wider than the bottom of the via.
  • the via 617 has sloped sidewalls.
  • the sloped sidewalls have an angle between 45-60 degrees with respect to a vertical axis of the via 617.
  • the width of the bottom of the via 617 is approximately the same size as the width of the conductive interconnect 604. In one
  • a central vertical axis of the via 617 is centered with a center of the conductive interconnect 604. In another embodiment, the central vertical axis of the via 617 is off-set with the center of the conductive interconnect 604.
  • Figure 6E illustrates the structure of Figure 6D following removal of the mask 616.
  • the mask 616 is removed using a resist strip and cleans process.
  • the conductive interconnect 604 is exposed to a plasma during the mask 616 removal. In one such embodiment, the conductive interconnect 604 is subjected to a sputter clean treatment prior to deposition of a next RRAM material layer stack.
  • Figure 6F illustrates the structure of Figure 6E following formation of a bottom electrode metal material 605 in the via 617 and on the conductive interconnect 604.
  • the bottom electrode metal material 605 is formed at the bottom of the via 617 on the conductive interconnect 604, along the sidewalls of the via 617, and on the uppermost surface of the second dielectric layer 614.
  • Exemplar ⁇ ' material compositions and deposition techniques for forming the bottom electrode metal material 605 may be as described above for the bottom electrode metal material 206.
  • Figure 6G illustrates the structure of Figure 6F following formation of a highly
  • the highly stoichiometric metal oxide layer 607 is formed at the bottom of the via 617 on the bottom electrode material 605, along the sidewalls of the via 617, and above the uppermost surface of the second dielectric layer 614.
  • Exemplary material compositions and deposition techniques for forming the highly stoichiometric metal oxide layer 607 may be as described above for the highly stoichiometric metal oxide layer 608.
  • Figure 6H illustrates the structure of Figure 6G following formation of a sub- stoichiometric metal oxide material 609 in the via 617 and on the highly stoichiometric metal oxide material 607.
  • the sub-stoichiometric metal oxide layer 609 is formed at the bottom of the via 617 on the highly stoichiometric metal oxide material 607, along the sidewalis of the via 617, and above the uppermost surface of the second dielectric layer 614.
  • Exemplary material compositions and deposition techniques for forming the sub-stoichiometric metal oxide layer 609 may be as described above for the sub-stoichiometric metal oxide layer 210
  • Figure 61 illustrates the structure of Figure 6H following formation of a top electrode material 611 in the via 617 and on the sub-stoichiometric metal oxide material 609.
  • the top electrode material 61 1 completely fills the via 61 7 and extends over the uppermost surface of the second dielectric layer 614.
  • Exemplary material compositions and deposition techniques for forming the top electrode material 611 may be as described above for the top electrode material 212.
  • Figure 6J illustrates the structure of Figure 61 following a planarization process to form a top electrode 612, a sub-stoichiometric metal oxide layer 610, a highly stoichiometric metal oxide layer 608, and a bottom electrode 606.
  • the planarization process is a CMP process.
  • the CMP process provides the top electrode 612, the sub-stoichiometric metal oxide layer 610, the highly stoichiometric metal oxide layer 608, and the bottom electrode 606 with uppermost surfaces co-planar with the uppermost surface of the second dielectric layer 514.
  • Figure 7A illustrates a plan view of an array of RRAM cells of the type illustrated in
  • each RRAM device 100 has a circular shape from a plan view perspective, as is shown.
  • the shape of each RRAM device 100 from the plan view perspective is a shape such as, but not limited to, a square, a rectangle, or an oval.
  • Figure 7B illustrates a plan view of an array of RRAM cells of the type illustrated in
  • each RRAM: device 120 has a circular shape from a plan view perspective, as is shown.
  • the shape of each RRAM device 120 from the plan view perspective is a shape such as, but not limited to, a square, a rectangle, or an oval ,
  • Figure 7C illustrates a plan view of an array of RRAM cells of the type illustrated in
  • each RRAM device 140 has a circular shape from a plan view perspective, as is shown.
  • the shape of each RRAM device 140 from the plan view perspective is a shape such as, but not limited to, a square, a rectangle, or an oval ,
  • RRAM devices presented in connection with Figure 1A-1C, are connected to form a two terminal device discussed in more detail in connection with Figure 12,
  • the various embodiments of the RRAM devices typically undergo a high temperature anneal process at the end of the fabrication process.
  • anneal temperatures reach 400°C and last for a time period of 60 minutes.
  • Annealing is a thermal phenomenon that serves to drive the O 2' from the fully stoichiometric metal oxide thus creating Oxygen vacancies, V 0 in this layer.
  • the O 2" from the fully stoichiometric metal oxide layer diffuses to the sub-stoichiometric layer above. The effect serves to increase the V 0 density in a once highly stoichiometric metal oxide layer priming it for a conductive filament creation.
  • FIG. 9 illustrates an I-V plot, demonstrating concepts involved with filament formation and voltage cycling (reading and writing) in an RRAM device, in accordance with embodiments of the present invention.
  • the various operations are highlighted as follows.
  • the initial operation of an RRAM undergoes an operation where a voltage, that is gradually increasing in magnitude, is applied between the top and the bottom electrodes of an RRAM device.
  • oxygen vacancies are pumped in from the sub- stoichiometric metal oxide layer leading to a formation of a conductive V 0 filament in the stoichiometric film (point B), With a conductive filament bridging the two electrodes, the RRAM: device is said to be almost immediately conductive and thus, in a low resistance state (point C), By sweeping the voltage between the electrodes in the reversed direction (point C to D and then to F), thereby reversing the electric field direction, the oxygen vacancies (technically positively charged ions) are now directed towards the sub-stoichiometric metal oxide layer leading to a dissolution of the conductive filament at some critical voltage (point F).
  • This critical voltage is termed VR eS et and the device returns to a high resistance state (point G). It is to be appreciated that the high resistance level, of point G, is different and lower in magnitude compared to the resistance level of the device before the onset of the forming process.
  • V se t the filament completely bridges the two electrodes and the device is once again said to be in a conductive mode or a low resistance state, point J.
  • V se t and VReset generally refer to a portion of a voltage that is applied to a transistor in series with the RRAM element.
  • the RRAM coupled with a transistor in this manner is given the term embedded memory.
  • FIG 10 illustrates a RRAM device 1004, formed on a conductive interconnect 1002 disposed in a via and integrated with a logic transistor 1030 disposed above a substrate 1005.
  • RRAM device 1004 includes a bottom electrode 1006, a fully stoichiometric metal oxide layer 1008, a sub -stoichiometric metal oxide layer 1010 and a top electrode 1012.
  • the RRAM device 1004 is a device such as described in association with Figure 1 A.
  • the RRAM device is disposed directly on a conductive interconnect coupled to a contact structure 1012 connected to the drain end 1020 of the transistor.
  • the RRAM device 1004 is a device such as described in association with Figure IB or 1C.
  • the underlying semiconductor substrate 1005 represents a general workpiece object used to manufacture integrated circuits.
  • the semiconductor substrate often includes a wafer or other piece of silicon or another semiconductor material.
  • Suitable semiconductor substrates include, but are not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other
  • the substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates.
  • transistors associated with substrate 1005 are metal-oxide- semiconductor field-effect transistors (MOSFET or simply MOS transistors), fabricated on the substrate 1005.
  • MOSFET metal-oxide- semiconductor field-effect transistors
  • the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both.
  • onpianar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.
  • each MOS transistor 1030 of substrate 1005 includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer.
  • the gate dielectric layer may include one layer or a stack of layers.
  • the one or more layers may include silicon oxide, silicon dioxide (Si0 2 ) a d/or a high-k dielectric material .
  • the high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.
  • the gate electrode layer of each MOS transistor of substrate 1005 is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type
  • the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer.
  • metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide,
  • a P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5,2 eV.
  • metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, allovs of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide.
  • An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3,9 eV and about 4,2 eV.
  • the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.
  • at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate.
  • the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures.
  • the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers,
  • a pair of sidewall spacers 1040 may be formed on opposing sides of the gate stack that bracket the gate stack.
  • the sidewall spacers may be fomied from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
  • source 1030 and drain 1020 regions are formed within the substrate adjacent to the gate stack of each MOS transistor.
  • the source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process.
  • dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions.
  • An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process.
  • the substrate may first be etched to form recesses at the locations of the source and drain regions.
  • the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide.
  • the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous.
  • the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.
  • integrating memory directly onto a microprocessor chip would be advantageous since it enables higher operation speeds compared to having physically separate logic and memory chips.
  • traditional charge-based memory technologies such as DRAM and NAND Flash are now facing severe scalability issues related to increasingly precise charge placement and sensing requirements.
  • embedding charge-based memory directly onto a high performance logic chip is not very attractive for future technology nodes.
  • a memory technology that does have the potential to scale to much smaller geometries compared to traditional charge-based memories is resistive random access memory (RRAM), since it relies on resistivity rather than charge as the information storage.
  • RRAM resistive random access memory
  • an appropriate integrated logic plus RRAM structure and fabrication method is needed.
  • Embodiments of the present invention include such structures and fabrication processes.
  • Embodiments described herein include a fabrication method for embedding RRAM bit cell arrays into a logic process technology. Embodiments described may be advantageous for processing schemes involving the fabrication of logic processors with embedded memory arrays.
  • an RRAM element may be included in an integrated circuit in regions typically referred to as back end or back end of line (BEOL) layers of the integrated circuit.
  • BEOL back end or back end of line
  • Figures 1 1 A - 1 IE illustrate schematic views of several options for positioning an RRAM element in an integrated circuit, in accordance with embodiments of the present invention. Referring to all Figures 1 1 A-l IE, in each case, a memory region 1100 and a logic region 1 102 of an integrated circuit are depicted schematically. Each memory region 1 100 includes a select transistor 1104 and overlying alternating metal lines and vias. Each logic region includes a plurality of transistors 1106 and overlying alternating metal lines and vias which can be used to connect the plurality of transistors 1106 into functional circuits, as is well known in the art.
  • an RRAM device 1120 is disposed between a lower conductive via 1 122 and an upper conductive line 124.
  • the lower conductive via 122 is in electrical contact with a bottom electrode of the RRAM device 1120
  • the upper conductive line 1 24 is in electrical contact with an upper electrode of the RRAM device 1 120.
  • the lower conductive via 1122 is in direct contact with a bottom electrode of the RRAM: device 1 120
  • the upper conductive line 1 124 is in direct contact with an upper electrode of the RRAM device 1120.
  • an RRAM device 1130 is disposed between a lower conductive line 1132 and an upper conductive via 1134.
  • the lower conductive line 1 132 is in electrical contact with a bottom electrode of the RRAM device 1 130
  • the upper conductive via 1 134 is in electrical contact with an upper electrode of the RRAM device 1130.
  • the lower conductive line 1 132 is in direct contact with a bottom electrode of the RRAM device 1130
  • the upper conductive via 1 134 is in direct contact with an upper electrode of the RRAM device 1 130.
  • an RRAM: device 1 40 is disposed between a lower conductive line 1 42 and an upper conductive line 1144 without an intervening conductive via.
  • the lower conductive line 1142 is in electrical contact with a bottom electrode of the RRAM device 1140
  • the upper conductive line 1144 is in electrical contact with an upper electrode of the RRAM device 1 140.
  • the lower conductive line 1 142 is in direct contact with a bottom electrode of the RRAM device 140
  • the upper conductive line 1 144 is in direct contact with an upper electrode of the RRAM device 1140.
  • an RRAM device 1 150 is disposed between a lower conductive via 1152 and an upper conductive via 1154 without an intervening conductive line.
  • the lower conductive via 152 is in electrical contact with a bottom electrode of the RRAM device 1150
  • the upper conductive via 1 1 54 is in electrical contact with an upper electrode of the RRAM device 1150.
  • the lower conductive via 1152 is in direct contact with a bottom electrode of the RRAM device 1150
  • the upper conductive via 1 154 is in direct contact with an upper electrode of the RRAM device 1 150.
  • an RRAM device 1 160 is disposed between a lower conductive line 1 162 and an upper conductive via 1164 in place of an intervening conductive line and conductive via pairing.
  • the lower conductive line 1162 is in electrical contact with a bottom electrode of the RRAM device 1 160
  • the upper conductive via 164 is in electrical contact with an upper electrode of the RRAM device 1160.
  • the lower conductive line 1162 is in direct contact with a bottom electrode of the RRAM device 1160, and the upper conductive via 1164 is in direct contact with an upper electrode of the RR AM device 1 160.
  • Figure 12 illustrates a schematic of a memory bit cell which includes a metal -conductive oxide-metal RRAM device, in accordance with embodiments of the present invention.
  • the RRAM memory element 1210 may include a bottom electrode metal layer 1212 with a stoichiometric metal oxide layer 1213 adjacent the bottom electrode metal layer 1212.
  • a sub-stoichiometric metal oxide layer 1214 is formed on the stoichiometric metal oxide layer 1213.
  • a top electrode 1216 is adjacent the sub-stoichiometric metal oxide layer.
  • the top electrode 1216 may be electrically connected to a bit line 1232.
  • the bottom electrode 1212 may be coupled with a transistor 1234.
  • the transistor 1234 may be coupled with a wordline 1236 and a source line 1238 in a manner that will be understood to those skilled in the art.
  • the RRAM cell 1200 may further include additional read and write circuitry (not shown), a sense amplifier (not shown), a bit line reference (not shown), and the like, as will be understood by those skilled in the art, for the operation of the RRAM cell 1200. It is to be appreciated that a plurality of the RRAM cells 1200 may be operabiy connected to one another to form a memory array, wherein the memory array can be incorporated into a non-volatile memory region of a substrate in common with a logic region. It is to be appreciated that the nomenclature top and bottom refer to relative positioning of the metal electrodes with respect to the metal oxide layers (stoichiometric and sub-stoichiometric). The transistor 1234 may be connected to layer 1216 although only connection to layer 1212 is shown.
  • FIG. 13 illustrates a block diagram of an electronic system 1300, in accordance with an embodiment of the present invention.
  • the electronic system 1300 can correspond to, for example, a portable system, a computer system, a process control system, or any other system that utilizes a processor and an associated memory.
  • the electronic system 1300 may include a microprocessor 1302 (having a processor 1304 and control unit 1306), a memory device 1308, and an input/output device 13 10 (it is to be appreciated that the electronic system 1300 may have a plurality of processors, control units, memory device units and/or input/output devices in various embodiments).
  • the electronic system 1300 has a set of instructions that define operations which are to be performed on data by the processor 1304, as well as, other transactions between the processor 1304, the memory device 1308, and the input/output device 1310.
  • the control unit 1306 coordinates the operations of the processor 1304, the memory device 1308 and the input/output device 1310 by cycling through a set of operations that cause instructions to be retrieved from the memory device 1308 and executed.
  • the memory device 1308 can include a memory element having a conductive oxide and electrode stack as described in the present description.
  • the memory device 1308 is embedded in the microprocessor 1302, as depicted in Figure 13.
  • the processor 1304, or another component of electronic system 1300 includes an array of RRAM devices.
  • FIG 14 illustrates a computing device 1400 in accordance with one embodiment of the invention.
  • the computing device 1400 houses a board 1402.
  • the board 1402 may include a number of components, including but not limited to a processor 1404 and at least one communication chip 1406.
  • the processor 1404 is physically and electrically coupled to the board 1402,
  • the at least one communication chip 1406 is also physically and electrically coupled to the board 1402.
  • the communication chip 1406 is part of the processsor 1404.
  • computing device 1400 may include other components that may or may not be physically and electrically coupled to the board 1402. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • flash memory e.g., a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna,
  • the communication chip 1406 enables wireless communications for the transfer of data to and from the computing device 1400.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 1406 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.1 1 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, ⁇ DM A, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 1400 may include a plurality of communication chips 1406.
  • a first communication chip 1406 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1206 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 1404 of the computing device 1400 includes an integrated circuit die packaged within the processor 1404.
  • the integrated circuit die of the processor includes one or more arrays, such as RRAM memory arrays integrated into a logic processor, built in accordance with embodiments of the present invention.
  • the term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communication chip 1406 also includes an integrated circuit die packaged within the communication chip 1406.
  • the integrated circuit die of the communication chip includes RRAM memory arrays integrated into a logic processor, built in accordance with embodiments of the present invention.
  • another component housed within the computing device 1400 may contain a stand-alone integrated circuit memory die that includes one or more arrays, such as RRAM memory arrays integrated into a logic processor, built in accordance with
  • the computing device 1400 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 1400 may be any other electronic device that processes data.
  • one or more embodiments of the present invention relate generally to the fabrication of embedded microelectronic memory.
  • the microelectronic memory may be non- volatile, wherein the memory can retain stored information even when not powered.
  • FIG. 15 illustrates an interposer 1500 that includes one or more embodiments of the invention.
  • the interposer 1500 is an intervening substrate used to bridge a first substrate 1502 to a second substrate 1504.
  • the first substrate 1502 may be, for instance, an integrated circuit die.
  • the second substrate 1504 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die.
  • the purpose of an interposer 1500 is to spread a connection to a wider pitch or to reroute a connection to a different connection.
  • an interposer 1500 may couple an integrated circuit die to a ball grid array (BGA) 506 that can subsequently be coupled to the second substrate 1504.
  • BGA ball grid array
  • the first and second substrates 502/1504 are attached to opposing sides of the interposer 1500.
  • the first and second substrates 1502/1504 are attached to the same side of the interposer 1500.
  • three or more substrates are interconnected by way of the interposer 1500.
  • the interposer 1500 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide.
  • the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.
  • the interposer may include metal interconnects 1508 and vias 1510, including but not limited to through-silicon vias (TS Vs) 1512.
  • the interposer 1500 may further include embedded devices 1514, including both passive and active devices.
  • Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices.
  • More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1500.
  • RF radio- frequency
  • embodiments of the present invention include approaches for fabricating RRAM stacks with dual metal oxide layers, and the resulting staictures and devices.
  • a resistive random access memory (RRAM) cell includes a conductive interconnect disposed in a dielectric layer above the above the substrate.
  • a resistive random access memory device is coupled to the conductive interconnect, the resistive random access memory includes a bottom electrode disposed above the conductive interconnect and on a portion of the dielectric layer, a highly stoichiometric metal oxide layer disposed on the bottom electrode, a sub-stoichiornetric metal oxide layer disposed on the highly stoichiometric metal oxide layer and a top electrode disposed on the sub-stoichiornetric oxide layer.
  • the bottom electrode, the highly stoichiometric oxide layer, the sub- stoichiometric oxide layer and the top electrode form a stack having sidewalls
  • the resistive random access memory device further comprises a dielectric spacer surrounding the sidewalls of the stack and extending from a lowermost portion of the bottom electrode to the uppermost portion of the top electrode.
  • highly stoichiometric metal oxide layer and the sub-stoichiometric metal oxide layer includes oxides of a same metal, the metal selected from the group consisting of hafnium, tantalum and titanium.
  • the highly stoichiometric metal oxide layer has a chemical composition, MOx, where M is a metal and O is an oxygen with a numerical value of X close to 2, and the sub-stoichiometric metal oxide layer has a chemical composition of MCKy, where O is oxygen and Y is approximately in the range of 0.01 to 0.05.
  • the highly stoichiometric metal oxide layer has a thickness approximately in the range of 1-5 nanometers and the sub-stoichiometric metal oxide layer has a thickness approximately in the range of 3-20 nanometers.
  • the bottom electrode includes a material selected from the group consisting of titanium nitride, tantalum nitride, tungsten and ruthenium and wherein at least a portion of an interface between the bottom electrode and the highly stoichiometric metal oxide layer is oxidized.
  • the top electrode includes a material selected from the group consisting of titanium nitride, tantalum nitride, tungsten and ruthenium where at least a portion of an interface between the top electrode and the sub-stoichiometric metal oxide layer is oxidized.
  • the bottom electrode and the top electrode are a same material, the material selected from the group consisting of titanium nitride, tantalum nitride, tungsten and ruthenium.
  • a portion of the bottom electrode is above the conductive interconnect and a portion is above the dielectric layer surrounding the conductive interconnect.
  • a resistive random access memory cell includes a conductive interconnect disposed in a dielectric layer above the substrate.
  • a resistive random access memory device is coupled to the conductive interconnect and includes a bottom electrode metal layer disposed above the conductive interconnect, an insulating layer disposed above the dielectric layer, the insulating layer having an opening with a bottom and sidewalls, a highly stoichiometric metal oxide layer disposed in the opening, on the bottom electrode , conformal with the bottom and the sidewalls of the opening, a sub-stoichiometric metal oxide layer disposed in the opening, on the highly stoichiometric metal oxide layer, conformal with the bottom and the sidewalls of the opening and a top electrode disposed in the opening, on the sub- stoichiometric oxide layer.
  • the bottom electrode is disposed on the conductive interconnect.
  • the bottom electrode has sidewalls adjacent to the dielectric layer and an uppermost surface coplanar with the uppermost surface of the dielectric layer.
  • the bottom electrode is disposed in the opening, on the conductive interconnect and conformai with the sidewails and the bottom of the opening.
  • the highly stoichiometric metal oxide layer and the sub-stoichiometric metal oxide layer comprise oxides of a same metal selected from the group consisting of hafnium, tantalum and titanium.
  • the highly stoichiometric metal oxide layer has a chemical
  • the highly stoichiometric metal oxide layer has a thickness
  • the sub-stoichiometric metal oxide layer has a thickness approximately in the range of 3-20 nanometers.
  • a method of fabricating resistive random access memory includes forming a conductive interconnect in a dielectric material above a substrate, forming a bottom electrode metal material on the conductive interconnect, forming a highly stoichiometric metal oxide material on the bottom electrode metal material, forming a sub- stoichiometric metal oxide material on the stoichiometric oxide material and forming a top electrode material on the stoichiometric oxide material.
  • forming the RRAM device further includes forming a dielectric hardmask material on the top electrode metal material, patterning the dielectric hardmask material and using the patterned dielectric hardmask layer as a mask to etch the top electrode material, the sub-stoichiometric metal oxide material, the highly stoichiometric metal oxide material and the bottom electrode metal material to form a patterned material layer stack having sidewails.
  • forming the RRAM device further includes forming a dielectric spacer surrounding the patterned material layer stack, wherein the dielectric spacer extends from the bottom electrode to the top of the dielectric hardmask layer.
  • forming the highly stoichiometric metal oxide layer includes depositing a metal oxide layer using an atomic layer deposition process and forming the sub- stoichiometric metal oxide layer includes depositing a metal oxide layer using a physical vapor deposition process.
  • forming the sub-stoichiometric metal oxide layer comprises depositing a metal film using a physical vapor deposition process in an ambient containing oxygen flowing at a constant or a variable rate.
  • the top electrode material is formed on the sub-stoichiometric metal oxide layer, without an air break, post deposition of the sub-stoichiometric metal oxide layer.
  • forming the RRAM device further includes forming a bottom electrode on the conductive interconnect.
  • the bottom electrode has sidewalls adjacent to a first dielectric layer and an uppermost surface coplanar with the uppermost surface of the first dielectric layer.
  • forming the REAM device further includes forming a bottom electrode in the opening, on the conductive interconnect and conformal with the bottom and the sidewalls of the opening.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention porte sur des approches pour intégrer un empilement double couche pour une cellule de mémoire vive résistive, et sur les structures résultantes. Dans un exemple, une cellule de mémoire vive résistive (RRAM) comprend une interconnexion conductrice disposée dans une couche diélectrique au-dessus d'un substrat. Un dispositif de mémoire vive résistive est couplé à l'interconnexion conductrice, la mémoire vive résistive comprenant une électrode inférieure disposée au-dessus de l'interconnexion conductrice et sur une partie de la couche diélectrique, une couche d'oxyde métallique hautement stœchiométrique disposée sur l'électrode inférieure, une couche d'oxyde métallique sous-stœchiométrique disposée sur la couche d'oxyde métallique hautement stœchiométrique, et une électrode supérieure disposée sur la couche d'oxyde sous-stœchiométrique. Un film d'espacement diélectrique est disposé sur les parois latérales du dispositif de mémoire s'étendant d'une partie inférieure de l'électrode inférieure à la partie supérieure de l'électrode supérieure.
PCT/US2016/040873 2016-07-01 2016-07-01 Dispositifs rram à oxyde métallique double couche et procédés de fabrication WO2018004697A1 (fr)

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