WO2018004693A1 - Substrats pour circuits intégrés - Google Patents

Substrats pour circuits intégrés Download PDF

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Publication number
WO2018004693A1
WO2018004693A1 PCT/US2016/040865 US2016040865W WO2018004693A1 WO 2018004693 A1 WO2018004693 A1 WO 2018004693A1 US 2016040865 W US2016040865 W US 2016040865W WO 2018004693 A1 WO2018004693 A1 WO 2018004693A1
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WIPO (PCT)
Prior art keywords
layer
area
orientation
logic
over
Prior art date
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PCT/US2016/040865
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English (en)
Inventor
Sansaptak DASGUPTA
Peter G. Tolchinsky
Han Wui Then
Marko Radosavljevic
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Intel Corporation
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Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2016/040865 priority Critical patent/WO2018004693A1/fr
Priority to TW106117440A priority patent/TW201810613A/zh
Publication of WO2018004693A1 publication Critical patent/WO2018004693A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only

Definitions

  • Embodiments of the present disclosure generally relate to the field of integrated circuits, and more particularly, to substrates with dissimilar materials to integrate heterogeneous devices on a same integrated circuit.
  • SoC system on a chip or system on chip
  • IC integrated circuit
  • FIGS 1A-1 C schematically illustrate cross-section side views of substrates for system on chip (SoC) devices as described herein, in accordance with some embodiments.
  • SoC system on chip
  • Figures 2A-2C schematically illustrate cross-section side views of SoC devices built on the substrates as described herein, while Figure 2D schematically illustrates cross-section side views of a logic device and an RF device and a three dimensional view of a logic device, in accordance with some embodiments.
  • Figures 3A and 3C schematically illustrate flow diagrams of processes for fabricating SoC devices as described herein, while Figure 3B illustrates a SoC device fabricated following the process shown in Figure 3A, in accordance with some embodiments.
  • FIG. 4 schematically illustrates an example system that may include a SoC device as described herein, in accordance with some embodiments.
  • SoC system on a chip or system on chip
  • IC integrated circuit
  • a SoC device may contain digital or logic devices, analog devices, high voltage devices, and/or radio-frequency (RF) devices - ail on a single chip substrate.
  • RF radio-frequency
  • SoC devices have become widely accepted, and used in embedded systems, mobile devices, such as smartphones and tablets, and so forth.
  • the terms a SoC, a SoC chip, and a SoC device may be used interchangeably herein.
  • Silicon on insulator (SOI) technology refers to the use of a layered silicon-- insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance, thereby improving performance.
  • SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator.
  • the insulating layer and the silicon layers used in SOI may vary widely with applications.
  • iil-V semiconductors may be obtained by combining group ill elements (e.g., Aluminium (Ai), Gallium (Ga), and indium (in)) with group V elements (e.g., Nitrogen (N), Phosphorus (P), Arsenic (As), and Antimony (Sb)). All of these ill-V combinations crystallize either in the diamond lattice like Silicon (Si) or Germanium (Ge) structure, or in a hexagonal lattice.
  • group ill elements e.g., Aluminium (Ai), Gallium (Ga), and indium (in)
  • group V elements e.g., Nitrogen (N), Phosphorus (P), Arsenic (As), and Antimony (Sb)
  • Embodiments of the present disclosure describe techniques for materials and substrates that integrate dissimilar materials to enable the coexistence of logic devices, analog devices, high voltage devices, and/or RF devices on the same chip or die.
  • a layered SOI substrate may comprise a first layer of Si of a first orientation, a second layer of Si of a second orientation different from the first orientation, and a separation layer between the first layer of Si and the second layer of Si.
  • the substrate may include two layers of Si with different crystal planes bonded together by a separation layer.
  • the first layer of Si may facilitate better implementation for RF devices based on 111— INI materials as the first layer of Si presents a much reduced lattice mismatch than the second layer of Si.
  • the first layer of Si may have a high resistance, e.g. , a resistance greater than 500 ohm-cm, to improve noise isolation between RF devices over the first layer of Si and logic devices over the second layer of Si.
  • an RF device may be located within a first area, wherein the RF device may be over and in contact with the first layer; and a logic device may be located within a second area, wherein the logic device may be over and in contact with the second layer.
  • a high voltage device may also be located within the first area separated from the logic device within the second area.
  • an exclusion area may lie between the first area and the second area, wherein the RF device within the first area may be separated from the logic device within the second area by the exclusion area, in some embodiments, the exclusion area may be a shallow trench isolation (STI) including a dielectric material, in some embodiments, the first area may comprise 111— INI material, wherein the second area may be formed within a logic layer comprising Si, Ge, SiGe, or l l l-V material.
  • STI shallow trench isolation
  • the separation layer between the first layer and the second layer may comprise a buried oxide layer, a sapphire layer, an AI N layer, or a diamond layer. In some embodiments, the separation layer may comprise a buried oxide layer and a sapphire layer.
  • a system may comprise a memory device, a display coupled to the memory device, and a system-on-chip (SoC) device coupled to the display and the memory.
  • the SoC device may include a substrate having a first layer of Si of a first orientation, e.g. , 100, a second layer of Si of a second orientation different from the first orientation, e.g. , 1 1 1 , and a separation layer, e.g. , AI N, between the first layer and the second layer.
  • an RF device may be over and in contact with the separation layer, e.g., AIN, and a logic device is over and in contact with the second layer of Si (1 1 1 ).
  • Embodiments of the present disclosure describe processes for materials and substrates that integrate ill-V materials to enable the coexistence of logic devices, analog devices, high voltage devices, and RF devices on the same chip or die.
  • a process for forming a SoC device comprising: providing a first layer of Si of a first orientation; forming a logic layer over the first layer of Si, wherein the logic layer may comprise Si, Ge, SiGe, or ill-V material; forming a separation layer over the logic layer; forming a second layer of Si of a second orientation different from the first orientation over the separation layer; forming a layer of l ll-N material over the second layer of Si; forming an RF device within the layer of lll-N material; forming a logic device within the logic layer; and forming an exclusion area through the separation layer, the second layer of Si, and the layer of ll l-N material, wherein the RF device within the layer of lll-N material may be separated from the logic
  • phrase “A and/or B” means (A), (B), or (A and B)
  • phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
  • the description may use perspective-based descriptions such as top/bottom, side, over/under, and the like. Such descriptions are merely used to facilitate the discussion and are not intended to restrict the application of embodiments described herein to any particular orientation.
  • the description may use the phrases “in an embodiment,” or “in embodiments,” which may each refer to one or more of the same or different embodiments.
  • the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.
  • Coupled with along with its derivatives, may be used herein.
  • Coupled may mean one or more of the following. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term “directly coupled” may mean that two or more elements are in direct contact.
  • the phrase "a first feature formed, deposited, or otherwise disposed on a second feature” may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a part of the first feature may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a part of the second feature.
  • circuitry may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality.
  • ASIC Application Specific Integrated Circuit
  • FIGS 1A-1 C schematically illustrate cross-section side views of substrates for system on chip (SoC) devices as described herein, in accordance with some embodiments.
  • SoC system on chip
  • a wafer also called a slice or a substrate, e.g., such as a silicon— insulator-silicon substrate for SOI, may be a thin slice of semiconductor material, such as a crystalline silicon (Si), used in electronics for the fabrication of integrated circuits.
  • Si crystalline silicon
  • Silicon or SOI wafers may be available in a variety of diameters, e.g. , from 25.4 mm (1 inch) to 300 mm (1 1 .8 inches).
  • Semiconductor fabrication plants may be referred to by the diameter of wafers that they are tooled to produce. The diameter has gradually increased to improve throughput and reduce cost with the current state-of-the-art fabrication using 300 mm, in addition to a possibility to adopt 450 mm. Technologies used for the fabrication of different wafer sizes may be different. Embodiments described herein may be applied to the fabrication using 300 mm. Additionally, or alternatively, embodiments described herein may be applied to other wafer sizes, including future wafer sizes.
  • Wafers may be grown from crystal having a regular crystal structure, with silicon having a diamond cubic structure of a lattice.
  • the surface When cut info wafers, the surface may be aligned in one of several relative directions known as crystal orientations. Silicon orientation may be defined by the Miller index, such as a silicon substrate with an orientation of (100), (1 1 1 ), or (1 10).
  • Figure 1A schematically illustrates a cross-section side view of a substrate 120 including different layers of silicon, e.g., a first layer of Si 103 and a second layer of Si 107, in accordance with some embodiments.
  • the first layer of Si 103 may have a first orientation; while the second layer of Si 107 may have a second orientation different from the first orientation, in embodiments, the first orientation may be 1 1 1 and the second orientation may be 100.
  • the second orientation may be 1 10.
  • the first orientation may be 100 and the second orientation may be 1 1 1 .
  • the first layer of Si 103 and the second layer of Si 107 may be separated by a separation layer 105 between the first layer of Si 103 and the second layer of Si 107.
  • the separation layer 105 may include a buried oxide layer, a sapphire layer, or a diamond layer.
  • the separation layer 105 may include AIN, which is a very efficient thermal conductor and a very good choice for efficient heat extraction from RF circuits and high voltage circuits made on lll-N materials.
  • the first layer of Si 103 may be below the separation layer 105, which may further be below the second layer of Si 107.
  • Figure 1 B illustrates a cross-section side view of an alternative substrate 130 including different layers of silicon, e.g., a first layer of Si 103 and a second layer of Si 107, in accordance with some embodiments.
  • the second layer of Si 107 may be below the separation layer 105, which may further be below the first layer of Si 103.
  • the details of the first layer of Si 103, the second layer of Si 107, and the separation layer 105 may be similar to the details of the corresponding layers in the substrate 120 described above with respect to Figure 1A,
  • Figure 1 C illustrates a cross-section side view of an alternative substrate 140 including different layers of silicon, e.g., a first layer of Si 103 and a second layer of Si 107, in accordance with some embodiments.
  • the separation layer 105 may include a plurality of layers, such as a buried oxide layer 1051 and a sapphire layer 1053.
  • the first layer of Si 103 may be below the separation layer 105 comprising a plurality of layers, which may be further below the second layer of Si 107.
  • the first layer of Si 103 maybe above the separation layer 105 comprising a plurality of layers, which may further be above the second layer of Si 107.
  • the details of the first layer of Si 103, the second layer of Si 107, and the separation layer 105 may be similar to the details of the corresponding layers in substrate 120 described above with respect to Figure 1A.
  • Figures 2A-2C schematically illustrate cross-section side views of SoC devices built on the substrates as described herein, while Figure 2D schematically illustrates cross-section side views of a logic device and an RF device and a three dimensional view of a logic device, in accordance with some embodiments.
  • Figure 2A illustrates a cross-section side view of a SoC device 210 built on a substrate including a first layer of Si 203 and a second layer of Si 207, separated by a separation layer 205, which may be the same as the substrate 120 shown in Figure 1A.
  • the first layer of Si 203 may have a first orientation; while the second layer of Si 207 may have a second orientation different from the first orientation.
  • the first orientation may be 1 1 1 and the second orientation may be 100.
  • embodiments may include the substrate 130 and/or 140 shown in Figures 1 B-1 C.
  • the SoC device 210 may include a first area 202 and a second area 206, where the first area 202 and the second area 206 cross ail layers of the SoC device 210, and are separated from each other.
  • Devices like an RF device 204 and a logic device 208 may be formed within the first area 202 and the second area 206, respectively.
  • the RF device 204 may be located within the first area 202, wherein the RF device 204 may be over and in contact with the first layer of Si 203.
  • a high voltage device may be located within the first area 202 as well.
  • the logic device 208 may be located within the second area 208, wherein the logic device 208 may be over and in contact with the second layer of Si 207.
  • the RF device 204 may include 111— INI material, while the logic device 208 may be formed within a layer including Si, Ge, SiGe, or IH-V material, in embodiments, the RF device 204 may be an RF power amplifier, or an RF filter.
  • the logic device 208 may be a logic circuit, a processor, a memory circuit, or a circuit performing digital functions and referred to as a digital circuit, which are often fabricated by CMOS technology.
  • the first area 202 may include a device layer stack that includes an AI N layer (2021 ), a transition layer (2023), a GaN layer (2025), and an Al l nN layer or an AIGaN layer (2027).
  • the transition layer 2023 may include one or more of AIGaN, AIN, and/or GaN.
  • an exclusion area 209 may be between the first area 202 and the second area 206, wherein the RF device 204 within the first area 202 may be separated from the logic device 208 within the second area 208 by the exclusion area 209. Furthermore, a resistance of the first layer of Si 203 may be higher than 500 ohm-cm, to improve RF noise isolation, in embodiments, the exclusion area 209 may be a shallow trench isolation (ST!) including a dielectric material.
  • ST shallow trench isolation
  • the separation layer 205 may be above the first layer of Si 203, and the second layer of Si 207 may be above the separation layer 205.
  • the RF device 204 may be over the first layer of Si 203 through the second layer of Si 207 and the separation layer 205, and the logic device 208 may be over the second layer of Si 207 separated from the first layer of Si 203 by the separation layer 205.
  • Figure 2B schematically illustrates a cross-section side view of a SoC device 220 including the first layer of Si 203 and the second layer of Si 207, similar to the corresponding layers in Figure 2A.
  • the first layer of Si 203 may have a first orientation; while the second layer of Si 207 may have a second orientation different from the first orientation, in embodiments, the first orientation may be 1 1 1 and the second orientation may be 100.
  • the SoC device 220 may include a first area 202 and a second area 206, where the first area 202 and the second area 206 cross all layers of the SoC device 220, and are separated from each other.
  • Devices like an RF device 204 and a logic device 208 may be formed within the first area 202 and the second area 206, respectively.
  • the RF device 204 may be located within a first area 202, and may be over and in contact with the first layer of Si 203, where the RF device 204 may include the same or similar materials as the RF device 204 in Figure 2A.
  • the logic device 208 may be located within a second area 206, and may be over and in contact with the second layer of Si 207.
  • an exclusion area 209 may be between the first area 202 and the second area 206, wherein the RF device 204 within the first area 202 may be separated from the logic device 208 within the second area 206 by the exclusion area 209.
  • the separation layer 205 may be above the second layer of Si 207, and the first layer of Si 203 may be above the separation layer 205.
  • the RF device 204 may be over the first layer of Si 203 separated from the second layer of Si 207 by the separation layer 205, and the logic device 208 may be over the second layer of Si 207 separated from the first layer of Si 203 by the separation layer 205.
  • the separation layer 205 may be a sapphire layer and may be disposed above the second layer of Si 207, the first layer of Si 203 may be above the sapphire layer 205, the RF device 204 may be disposed over the first layer of Si 203 separated from the second layer of Si 207 by the sapphire layer 205, and the logic device 208 may be disposed over the second layer of Si 207 separated from the first layer of Si 203 by the sapphire layer 205, in embodiments, the separation layer 205 may include a plurality of layers as shown in Figure 1 C.
  • Figure 2C schematically illustrates a cross-section side view of a system on chip (SoC) device 230, in accordance with some embodiments.
  • the SoC device 230 may comprise a substrate having a first layer of Si 203, a separation layer 205, and a second layer of Si 207.
  • the first layer of Si 203 may have a first orientation, e.g., 100
  • the second layer of Si 207 may have a second orientation different from the first orientation, e.g., 1 1 1
  • the separation layer 205 may include AIN.
  • the first layer of Si 203 may be below the separation layer 205, which may be further below the second layer of Si 207.
  • the SoC device 230 may include a first area 202 and a second area 208, where the first area 202 and the second area 206 cross all layers of the SoC device 220, and are separated from each other.
  • Devices like an RF device 204 and a logic device 208 may be formed within the first area 202 and the second area 206, respectively.
  • the RF device 204 may be disposed within the first area 202 over and in contact with the separation layer 205, the logic device 208 may be disposed within the second area 206 and in contact with the second layer of Si 207; and an exclusion area 209 between the first area 202 and the second area 206, wherein the RF device 204 within the first area 202 may be separated from the logic device 208 within the second area 206 by the exclusion area 209.
  • the exclusion area 209 may be a shallow trench isolation (STI) including a dielectric material.
  • STI shallow trench isolation
  • the logic device 208 may be formed as nanowires using lll-V material or Ge.
  • the RF device 204 may comprise lll-N material, similar to ⁇ ⁇ - ⁇ material shown in Figure 2A.
  • the first area 202 may be designated for RF devices and the second area 206 may be designated for logic devices.
  • the first area 202 may also be designated for RF devices and high voltage devices, and the second area 206 may be designated for logic devices.
  • Figure 2D schematically illustrates a cross-section side view of an RF device, e.g. the RF device 204 of Figures 2A-2C, a cross-section side view of a logic device, e.g. , the logic device 208 of Figures 2A-2C, and a three dimensional view of a logic device, e.g., the logic device 208 of Figures 2A-2C, in accordance with some embodiments.
  • the RF device 204 may include a substrate 2041 comprising GaN, a channel 2042 comprising AIGaN, a gate 2043 comprising metal, and a source 2046 and a drain 2046, comprising InGaN.
  • the RF device 204 may include a source contact 2047 and a drain contact 2047, a gate contact 2044 which may include a thick metal to reduce gate resistance and increase RF operation frequency, a spacer 2045, a thin layer 2048 comprising A!N to enhance channel mobility.
  • the RF device 204 may include two dimensional electron gas 2050.
  • the embodiments shown in Figure 2D(i) may be one example of an RF device 204. There may be a plurality of other structures and configurations for the RF device 204, which are not shown.
  • the logic device 208 may include a substrate 2081 , an oxide layer 2082, Fin 2083, source/drain 2084, and a gate 2085, as shown in Figure 2D(iii) as a three dimensional transistor.
  • a metal layer 2088 may be deposited next to the gate 2085, and a hi-k dielectric layer 2087 may be between the gate 2085 and the Fin 2083.
  • the embodiments shown in Figure 2D(i) and 2D(iii) may be one example of a logic device 208. There may be a plurality of other structures and configurations for the logic device 208, which are not shown.
  • FIGS 3A and 3C schematically illustrate flow diagrams of processes for fabricating SoC devices as described herein, while Figure 3B illustrates a SoC device fabricated following the process shown in Figure 3A, in accordance with some embodiments.
  • the SoC devices fabricated following the processes in Figures 3A and 3C may be the SoC devices illustrated in Figures 2A-2C.
  • Figure 3A illustrates a process 300 to fabricate a SoC device, such as the SoC device illustrated in Figure 2A.
  • the process 300 may include providing a substrate, wherein the substrate comprises a first layer of Si of a first orientation, such as the first layer of Si 203 of orientation 1 1 1 in Figure 2A, a second layer of Si of a second orientation different from the first orientation, such as the second layer of Si 207 of orientation 100 in Figure 2A, and a separation layer between the first layer of Si and the second layer of Si, such as the separation layer 205 in Figure 2A.
  • the separation layer may comprise one or more of a buried oxide layer, a sapphire layer, or a diamond layer.
  • the separation layer may comprise a buried oxide layer and a sapphire layer.
  • the process 300 may include forming a logic layer over the substrate, wherein the logic layer may comprise Si, Ge, SiGe, or i ll-V material for making logic devices, in various embodiments, block 303 may also include forming logic devices (e.g., the logic device 208 in Figure 2A) within a first area, e.g., the first area 208, of the logic layer, which is formed over and in contact with the second layer of Si.
  • logic devices e.g., the logic device 208 in Figure 2A
  • a SoC device 320 may comprise a substrate including a first layer of Si 203 and a second layer of Si 207, separated by a separation layer 205, which may be the same as the substrate 120 shown in Figure 1A and Figure 2A.
  • the logic layer formed over the substrate may be a layer including Si, Ge, SiGe, or lll-V material, where a first area 206 may include the logic layer.
  • a logic device 208 may be formed within the first area 206, where the logic device may comprise a logic circuit, a processor, a memory circuit, or a circuit performing digital functions and referred to as a digital circuit.
  • the logic device 208 may be over and in contact with the second layer of Si 207.
  • the process 300 may include opening a trench through the logic layer, the second layer of Si, the separation layer, to reach the first layer of Si.
  • the SoC device 320 may comprise a trench 321 , where the trench 321 goes through the logic layer, the second layer of Si 207, and the separation layer 205.
  • an RF device 204 may be formed within the trench 321 , through operations demonstrated in the following blocks 307-309.
  • the process 300 may include forming inside the trench, a layer of a first ⁇ - ⁇ material, in embodiments, the layer of the first i l!-N material may be deposited as a blanket layer inside the trench (3071 ), or grown out of patterned areas on the first layer of Si (3073).
  • a layer of a first lii-N material e.g., the layer 2021 may be formed within the trench, by growing out of the patterned area 331 of the first layer of Si 203.
  • the layer of the first lll-N material may be a part of a process of forming an RF device over and in contact with the first layer of Si 203.
  • the process 300 may include forming, inside the trench, a second layer of a second iil-N material over the first layer of the first lll-N material, such as the transition layer 2023 illustrated in Figure 2A.
  • the process 300 may include forming one or more RF devices, e.g. , the RF device 204 as illustrated in Figure 2A, inside the trench within the first layer of the first ! i l-N material, e.g. , 2021 , and the second layer of the second 111— INI material, e.g. , 2023.
  • the RF devices, e.g. , 204, and the logic devices, e.g., 208 may be separated by an exclusion area between the first area and the trench, in some embodiments, a high voltage device may be located within the first area 202 as well .
  • Figure 3C illustrates another process 310 that may be used to fabricate SoC devices, such as the SoC devices illustrated in Figures 2A-2B.
  • the process 310 may include providing a first layer of Si, e.g. , the first layer of Si 203, of a first orientation, e.g. , 1 1 1 .
  • the process 310 may include forming a logic layer over the first layer, wherein the logic layer may comprise Si, Ge, SiGe, or i i l-V material, e.g. , the area 208 of Figures 2A-2B.
  • the process 310 may include forming a separation layer, e.g. , the separation layer 205, over the logic layer, in embodiments, the separation layer may comprise a buried oxide layer, a sapphire layer, or a diamond layer, in some embodiments, the separation layer may comprise a buried oxide layer and a sapphire layer.
  • the separation layer may comprise a buried oxide layer, a sapphire layer, or a diamond layer, in some embodiments, the separation layer may comprise a buried oxide layer and a sapphire layer.
  • the process 31 0 may include forming a second layer of Si of a second orientation different from the first orientation, over the separation layer, e.g. , the second layer of Si 207, of a second orientation, e.g. , 1 00.
  • the process 310 may include forming a layer of l i i-N material over the second layer of Si, e.g. , the layers for the area 202.
  • the layer of 111— INI material may comprise an A!N layer, a transition layer, a GaN layer, and an All nN layer or an AIGaN layer, where the transition layer may comprise material selected from a group consisting of AIGaN, A!N, and GaN.
  • the process 310 may include forming an RF device within the layer of 111— INI material, e.g. , the RF device 204. i n embodiments, the RF device may comprise an RF power amplifier, or an RF filter.
  • the process 310 may include forming a logic device within the second layer, e.g. , the logic device 208.
  • the logic device may comprise a logic circuit, a processor, or a memory circuit.
  • the process 310 may include forming an exclusion area, e.g., the exclusion area 209, through the separation layer, the second layer of Si, and the layer of lll-N material, wherein the RF device within the layer of iil-N material may be separated from the logic device within the second layer by the exclusion area.
  • an exclusion area e.g., the exclusion area 209
  • FIG. 4 schematically illustrates an example system (e.g., computing device 400) that may include a SoC device (e.g., SoC 210, SoC 220, SoC 230, and/or a SoC fabricated using the processes 300 and 310) as described herein, in accordance with some embodiments.
  • Components of the computing device 400 may be housed in an enclosure (e.g., housing 408).
  • the motherboard 402 may include a number of components, including but not limited to a processor 404 and at least one communication chip 406.
  • the processor 404 may be physically and electrically coupled to the motherboard 402. in some implementations, the at least one communication chip 406 may also be physically and electrically coupled to the motherboard 402.
  • the communication chip 408 may be part of the processor 404.
  • computing device 400 may include other components that may or may not be physically and electrically coupled to the motherboard 402. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • flash memory e.g., a graphics processor, a digital signal processor, a crypto processor, a chipse
  • the communication chip 406 may enable wireless communications for the transfer of data to and from the computing device 400.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 406 may implement any of a number of wireless standards or protocols, including but not limited to institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (I EEE 802.1 1 family), IEEE 802.16 standards (e.g., IEEE 802.18- 2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as "3GPP2”), etc.).
  • IEEE 802.16 compatible broadband wireless access (BWA) networks are generally referred to as WilvlAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.18 standards.
  • the communication chip 406 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network.
  • GSM Global System for Mobile Communication
  • GPRS General Packet Radio Service
  • UMTS Universal Mobile Telecommunications System
  • High Speed Packet Access HSPA
  • E-HSPA Evolved HSPA
  • LTE LTE network.
  • the communication chip 408 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN).
  • EDGE Enhanced Data for GSM Evolution
  • GERAN GSM EDGE Radio Access Network
  • UTRAN Universal Terrestrial Radio Access Network
  • E-UTRAN Evolved UTRAN
  • the communication chip 408 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the communication chip 406 may operate in accordance with other wireless protocols in other embodiments.
  • the computing device 400 may include a plurality of communication chips 408.
  • a first communication chip 406 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 406 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others.
  • the processor 404 of the computing device 400 may include and/or be part of a SoC device as described herein (e.g., SoC 210, SoC 220, SoC 230, and/or a SoC fabricated using the processes 300 and 310).
  • a plurality of the blocks of the computing device 400 may be packaged together in a SoC, e.g., the processor 404, communication chip 406, graphics CPU, etc.
  • the SoC devices 210 and 220 of Figures 2A-2B may be mounted in a package assembly that is mounted on a circuit board such as the motherboard 402.
  • the term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communication chip 406 may also include and/or be part of a SoC as described herein (e.g., SoC 210, SoC 220, SoC 230, and/or a SoC fabricated using the processes 300 and 310).
  • another component e.g., memory device or other integrated circuit device housed within the computing device 400 may include and/or be part of a SoC device described herein (e.g., SoC 210, SoC 220, SoC 230, and/or a SoC fabricated using the processes 300 and 310).
  • the computing device 400 may be a mobile computing device, a laptop, a netbook, a notebook, an uitrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder, in further implementations, the computing device 400 may be any other electronic device that processes data.
  • PDA personal digital assistant
  • Example 1 may include a system on chip (SoC) apparatus comprising: a first layer of Si of a first orientation;
  • SoC system on chip
  • an RF device located within a first area, wherein the RF device is over and in contact with the first layer;
  • a logic device located within a second area, wherein the logic device is over and in contact with the second layer;
  • Example 2 may include the apparatus of example 1 and/or some other examples herein, wherein the exclusion area is a shallow trench isolation (STi) including a dielectric material.
  • Example 3 may include the apparatus of any one of examples 1 -2 and/or some other examples herein, wherein the first orientation is 1 1 1 and the second orientation is 100.
  • Example 4 may include the apparatus of example 1 and/or some other examples herein, wherein the separation layer comprises a buried oxide layer, a sapphire layer, or a diamond layer.
  • Example 5 may include the apparatus of example 1 and/or some other examples herein, wherein the separation layer comprises a buried oxide layer and a sapphire layer.
  • Example 6 may include the apparatus of example 1 and/or some other examples herein, further comprising:
  • a high voltage device located within the first area.
  • Example 7 may include the apparatus of any one of examples 1 -6 and/or some other examples herein, wherein the separation layer is above the first layer, the second layer is above the separation layer, the first area is over the first layer through the second layer and the separation layer, and the second area is over the second layer separated from the first layer by the separation layer.
  • Example 8 may include the apparatus of any one of examples 1 -6 and/or some other examples herein, wherein the separation layer is above the second layer, the first layer is above the separation layer, the first area is over the first layer separated from the second layer by the separation layer, and the second area is over the second layer separated from the first layer by the separation layer.
  • Example 9 may include the apparatus of example 1 and/or some other examples herein, wherein the separation layer is a sapphire layer and is disposed above the second layer, the first layer is above the sapphire layer, the RF device is disposed over the first layer separated from the second layer by the sapphire layer, and the logic device is disposed over the second layer separated from the first layer by the sapphire layer.
  • Example 10 may include the apparatus of example 1 and/or some other examples herein, wherein a resistance of the first layer is higher than 500 ohm-cm.
  • Example 1 1 may include the apparatus of example 1 and/or some other examples herein, wherein the first area comprises lii-N material.
  • Example 12 may include the apparatus of example 1 and/or some other examples herein, wherein the second area is formed within a layer comprising Si, Ge, SiGe, or ll l-V material.
  • Example 13 may include the apparatus of example 1 and/or some other examples herein, wherein the RF device comprises an RF power amplifier, or an RF filter.
  • Example 14 may include the apparatus of example 1 and/or some other examples herein, wherein the logic device comprises a logic circuit, a processor, or a memory circuit.
  • Example 15 may include the apparatus of example 1 and/or some other examples herein, wherein the RF device is formed within a device layer stack that includes an AIN layer, a transition layer, a GaN layer, and an AllnN layer or an AIGaN layer.
  • Example 16 may include the apparatus of example 15 and/or some other examples herein, wherein the transition layer comprises material selected from a group consisting of AIGaN, AIN, and GaN.
  • Example 17 may include an electrical system comprising:
  • a display coupled to the memory device, and a system-on-chip (SoC) coupled to the display and the memory, including: a first layer of Si of a first orientation;
  • SoC system-on-chip
  • Example 18 may include the system of example 17 and/or some other examples herein, wherein the first orientation is 100 and the second orientation is 1 1 1 .
  • Example 19 may include the system of any one of examples 17-18 and/or some other examples herein, wherein the logic device is formed as nanowires using !il-V material or Ge.
  • Example 20 may include the system of any one of examples 17-18 and/or some other examples herein, wherein the RF device comprises lii-N material.
  • Example 21 may include the system of example 17 and/or some other examples herein, wherein the first area is designated for RF devices and the second area is designated for logic devices.
  • Example 22 may include the system of example 17 and/or some other examples herein, wherein the first area is designated for RF devices and high voltage devices, and the second area is designated for logic devices.
  • Example 23 may include the system of example 17 and/or some other examples herein, wherein the exclusion area is a shallow trench isolation (STI) including a dielectric material.
  • Example 24 may include a method for forming a system on chip (SoC), the method comprising:
  • the logic layer comprises Si, Ge, SiGe, or lll-V material
  • Example 25 may include the method of example 24 and/or some other examples herein, wherein the first orientation is 100 and the second orientation is 1 1 1 .
  • Example 26 may include the method of example 24 and/or some other examples herein, wherein the separation layer comprises a buried oxide layer, a sapphire layer, or a diamond layer.
  • Example 27 may include the method of example 24 and/or some other examples herein, wherein the separation layer comprises a buried oxide layer and a sapphire layer.
  • Example 28 may include the method of any one of examples 24-27 and/or some other examples herein, further comprising:
  • Example 29 may include the method of any one of examples 24-27 and/or some other examples herein, wherein the logic device comprises a logic circuit, a processor, or a memory circuit.
  • Example 30 may include the method of any one of examples 24-27 and/or some other examples herein, wherein the RF device comprises an RF power amplifier, or an RF filter.
  • Example 31 may include the method of example 24 and/or some other examples herein, wherein the layer of ⁇ - ⁇ material further comprises an AIN layer, a transition layer, a GaN layer, and an AllnN layer or an AIGaN layer.
  • Example 32 may include the method of example 31 and/or some other examples herein, wherein the transition layer comprises material selected from a group consisting of AIGaN, AIN, and GaN.
  • Example 33 may include a method for forming a system on chip (SoC), the method comprising:
  • the substrate comprises a first layer of Si of a first orientation, a second layer of Si of a second orientation different from the first orientation, and a separation layer between the first layer of Si and the second layer of Si;
  • RF devices inside the trench within the first layer of the first ill-N material and the second layer of the second ill-N material, wherein the RF devices and the logic devices are separated by an exclusion area between the first area and the trench.
  • Example 34 may include the method of example 33 and/or some other examples herein, wherein the first layer of the first ill-N material comprises AIN, and the second layer of the second lll-N material comprises a transition layer.
  • Example 35 may include the method of any one of examples 33-34 and/or some other examples herein, further comprising:
  • Example 36 may include the method of example 34 and/or some other examples herein, wherein the transition layer comprises materia! selected from a group consisting of AIGaN, AIN, and GaN.
  • Example 37 may include the method of example 33 and/or some other examples herein, wherein the first layer of the first lll-N material is formed by blanket depositing the first layer of the first lll-N material, or by growing the first layer of the first lll-N material on the first layer of Si.
  • Example 38 may include the method of example 33 and/or some other examples herein, wherein the first orientation is 100 and the second orientation is 1 1 1 .
  • Example 39 may include the method of example 33 and/or some other examples herein, wherein the separation layer comprises a buried oxide layer, a sapphire layer, or a diamond layer.
  • Example 40 may include the method of example 33 and/or some other examples herein, wherein the separation layer comprises a buried oxide layer and a sapphire layer.
  • Example 41 may include the method of example 33 and/or some other examples herein, wherein the logic device comprises a logic circuit, a processor, or a memory circuit.
  • Example 42 may include the method of example 33 and/or some other examples herein, wherein the RF device comprises an RF power amplifier, or an RF filter.
  • Various embodiments may include any suitable combination of the above- described embodiments including alternative (or) embodiments of embodiments that are described in conjunctive form (and) above (e.g., the "and” may be “and/or”).
  • some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions, stored thereon, that when executed result in actions of any of the above- described embodiments.
  • some embodiments may include apparatuses or systems having any suitable means for carrying out the various operations of the above-described embodiments.

Abstract

Des modes de réalisation de l'invention décrivent des techniques pour fabriquer un système sur un dispositif en puce (Sc) à l'aide d'une technologie silicium sur isolant (SOI). Un substrat comprend une première couche de Si d'une première orientation, par exemple 111, et une seconde couche de Si d'une seconde orientation différente de la première, par exemple 100, séparées par une couche de séparation. Un dispositif RF peut être placé sur la première couche de Si et en contact avec celle-ci; tandis qu'un dispositif logique peut être au-dessus et en contact avec la seconde couche de Si, séparé par une zone d'exclusion entre le dispositif logique et le dispositif RF. Un autre substrat comprend une couche de Si (100), une couche de Si (111), séparées par une couche d'AIN, où un dispositif RF est sur la couche d'AIN et en contact avec celle-ci, et un dispositif logique est au-dessus et en contact avec la couche de Si (111).
PCT/US2016/040865 2016-07-01 2016-07-01 Substrats pour circuits intégrés WO2018004693A1 (fr)

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