WO2018003113A1 - Reception device - Google Patents

Reception device Download PDF

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Publication number
WO2018003113A1
WO2018003113A1 PCT/JP2016/069622 JP2016069622W WO2018003113A1 WO 2018003113 A1 WO2018003113 A1 WO 2018003113A1 JP 2016069622 W JP2016069622 W JP 2016069622W WO 2018003113 A1 WO2018003113 A1 WO 2018003113A1
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WO
WIPO (PCT)
Prior art keywords
signal
output
converter
output signal
signals
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PCT/JP2016/069622
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French (fr)
Japanese (ja)
Inventor
裕翔 榊
圭佑 中村
田島　賢一
檜枝　護重
Original Assignee
三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2016/069622 priority Critical patent/WO2018003113A1/en
Publication of WO2018003113A1 publication Critical patent/WO2018003113A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J1/00—Frequency-division multiplex systems
    • H04J1/02—Details

Definitions

  • the present invention relates to a receiving apparatus that performs signal processing by converting a plurality of received analog signals having different frequencies into digital signals.
  • the direct RF method is different from the well-known techniques of heterodyne method and direct conversion method, and does not frequency-convert the received analog signal, but directly inputs it to the AD converter to convert the analog signal into a digital signal. It is a method.
  • undersampling is a method of operating an AD converter below the Nyquist frequency to sample an analog signal and convert it into a digital signal.
  • Aliasing occurs from the Nyquist theorem, and a digital signal can be obtained by using the aliasing.
  • the direct RF undersampling system is a system combining these two, and the direct RF undersampling receiver indicates a receiver having the above system.
  • analog signals can be converted simultaneously into digital signals with a single AD converter using undersampling.
  • the frequency of the sampling signal is selected so that signals output from the AD converter do not overlap each other.
  • a wide vacant frequency region occurs between the signals output from the AD converter after undersampling. In such a case, the frequency of the sampling signal increases and the power consumption of the AD converter increases.
  • the AD converter can be operated at a frequency lower than that of the method of selecting the frequency of the sampling signal so that the bands of the signals after undersampling do not overlap each other.
  • the power consumption of the AD converter can be reduced.
  • the receiver described in Patent Document 1 has a problem that the signals cannot be separated when three or more analog signals are received.
  • the present invention has been made to solve such a problem, and an object of the present invention is to provide a receiving apparatus capable of separating signals even when three or more analog signals are received.
  • a receiving apparatus includes a first AD converter and a second AD converter that sample three analog signals having different frequencies, and a low-pass filter that passes the output of the first AD converter in a low-pass manner.
  • a high pass filter that passes the output of the first AD converter in a high pass
  • a first decimation processor that makes the output signal of the low pass filter and the high pass filter a half frequency
  • a second Three analog signals having different frequencies by performing an operation using the output signal of the first thinning processor, the output signal of the second thinning processor, and the output signal of the second AD converter.
  • the sampling frequency of the second AD converter is 1 ⁇ 2 of the sampling frequency of the first AD converter, and the first AD Supply to the converter
  • the pulling signal and the sampling signal of the second AD converter have a phase difference of 90 °, and the sampling frequencies of the first AD converter and the second AD converter are overlapped with the frequency bands of the three analog signals.
  • the frequency is set so that it does not become.
  • the sampling frequency of the second AD converter is set to 1 ⁇ 2 of the sampling frequency of the first AD converter, and the sampling signal supplied to the first AD converter and the second AD converter A signal obtained by processing the output of the first AD converter with the low-pass filter and the first decimation processor and the output of the first AD converter with a 90 ° phase difference from the sampling signal of the AD converter.
  • the three signals are separated and output using the signal processed by the high-pass filter and the second thinning processor and the signal output from the second AD converter. Thereby, even when three analog signals are received, the signals can be separated.
  • FIG. FIG. 1 is a configuration diagram of a receiver to which a receiving apparatus according to this embodiment is applied.
  • the receiver shown in FIG. 1 includes an antenna 1, an analog circuit unit 2, and a signal processing unit 3.
  • the analog circuit unit 2 includes an amplifier 21, a filter 22, and a sampling circuit 23.
  • the antenna 1 is an antenna that receives a plurality of analog signals having different frequencies.
  • the analog circuit unit 2 is a circuit that processes an analog signal received by the antenna 1.
  • the signal processing unit 3 is a processing unit that performs signal processing using the output signal of the analog circuit unit 2.
  • the amplifier 21 in the analog circuit unit 2 is an amplifier that amplifies an analog signal received by the antenna 1 with a predetermined amplification factor.
  • the filter 22 is a filter that suppresses unnecessary analog signals.
  • the sampling circuit 23 is a circuit that performs processing for converting an analog signal into a digital signal, and corresponds to the receiving apparatus of the present embodiment.
  • FIG. 2 is a configuration diagram showing details of the sampling circuit 23.
  • the sampling circuit 23 includes an oscillator 101, a first power divider 102, a two-frequency divider 103, a phase shifter 104, a second power divider 105, a first AD converter 106, a low frequency band, Pass filter (hereinafter referred to as LPF) 107, first decimation processor 108, first delay unit 109, high-pass filter (hereinafter referred to as HPF) 110, second decimation processor 111, second delay unit 112, a second AD converter 113, a third delay unit 114, and a signal separation unit 115.
  • LPF Pass filter
  • HPF high-pass filter
  • the oscillator 101 is an oscillator that excites a reference signal of a sampling signal input to the first AD converter 106 and the second AD converter 113.
  • a crystal oscillator is used.
  • Oscillator 101 is connected to a first power splitter 102, it oscillates at a frequency 2f 0, and outputs an oscillation signal to the power divider 102.
  • the first power distributor 102 is a circuit that receives the signal output from the oscillator 101 and distributes the power of the signal into two. For example, a discrete power distributor is used.
  • the first power divider 102 is connected to the oscillator 101, the two-frequency divider 103, and the phase shifter 104.
  • the first power divider 102 distributes the power of the signal output from the oscillator 101 to two, and the two-frequency divider 103 and the phase shifter 104. To each output.
  • the phase shifter 104 is a circuit that delays the phase of the signal output from the first power distributor 102 by 90 ° and outputs the delayed signal. For example, a discrete phase shifter is used.
  • the phase shifter 104 is connected to the first power divider 102 and the first AD converter 106, delays the phase of the signal output by the first power divider 102 by 90 °, and the first AD converter 106. Output to.
  • the frequency divider 103 is a circuit that halves the frequency of the signal output from the first power distributor 102.
  • the two-frequency divider 103 is connected to the first power divider 102 and the second AD converter 113, halves the frequency of the signal output from the first power divider 102, and the second AD converter 113.
  • the second power distributor 105 is a circuit that distributes the power of the signal output from the filter 22 into two.
  • a discrete power distributor is used.
  • the second power distributor 105 is connected to the filter 22, the first AD converter 106, and the second AD converter 113, and distributes the power of the signal output from the filter 22 into two, and the first AD converter 106 and the second AD converter 113, respectively.
  • the first AD converter 106 is a circuit that uses the signal output from the phase shifter 104 as a sampling signal, converts the signal output from the second power distributor 105 into a digital signal using the sampling signal, and outputs the digital signal. is there.
  • an IC AD converter is used.
  • the first AD converter 106 is connected to the phase shifter 104, the second power distributor 105, the LPF 107, and the HPF 110, converts the signal output from the second power distributor 105 into a digital signal, and the LPF 107 and the HPF 110. To each output.
  • the LPF 107 is a circuit that passes a frequency band below a specific frequency in the digital signal output from the first AD converter 106 and attenuates the frequency band above the specific frequency. For example, it is configured with an FPGA logic circuit.
  • the LPF 107 is connected to the first AD converter 106 and the first decimation processor 108, and passes a signal having a low frequency among the signals output from the first AD converter 106, and the first decimation processor To 108.
  • the first decimation processor 108 is a circuit that decimates the signal output from the LPF 107.
  • the first decimation processor 108 is connected to the LPF 107 and the first delay unit 109, decimates the signal output from the LPF 107, and outputs it to the first delay unit 109.
  • the first delay unit 109 is a circuit that delays the signal output from the first decimation processor 108 and outputs the delayed signal. For example, it is configured with an FPGA logic circuit.
  • the first delay unit 109 is connected to the first decimation processor 108 and the signal separation unit 115, delays the signal output from the first decimation processor 108 in time, and outputs the delayed signal to the signal separation unit 115. .
  • the HPF 110 is a circuit that passes a frequency band of a specific frequency or higher and attenuates a frequency band of a specific frequency or lower in the digital signal output from the first AD converter 106. For example, it is configured with an FPGA logic circuit.
  • the HPF 110 is connected to the first AD converter 106 and the second decimation processor 111, and passes a signal having a high frequency among the signals output from the first AD converter 106, and the second decimation processor To 111.
  • the second decimation processor 111 is a circuit that decimates the signal output from the HPF 110. For example, it is configured with an FPGA logic circuit.
  • the second decimation processor 111 is connected to the HPF 110 and the second delay unit 112, decimates the signal output from the HPF 110, and outputs the signal to the second delay unit 112.
  • the second delay unit 112 is a circuit that delays the signal output from the second decimation processor 111 and outputs the delayed signal. For example, it is configured with an FPGA logic circuit.
  • the second delay unit 112 is connected to the second decimation processor 111 and the signal separation unit 115, delays the signal output from the second decimation processor 111 in time, and outputs the delayed signal to the signal separation unit 115.
  • the second AD converter 113 uses the signal output from the frequency divider 103 as a sampling signal, converts the signal output from the second power distributor 105 into a digital signal using the sampling signal, and outputs the digital signal It is. For example, an IC AD converter is used.
  • the second AD converter 113 is connected to the frequency divider 103, the second power distributor 105, and the third delay device 114, and the signal output from the frequency divider 103 is used as a sampling signal. Is used to convert the signal output from the second power distributor 105 into a digital signal and output it to the third delay unit 114.
  • the third delay unit 114 is a circuit that delays the signal output from the second AD converter 113 and outputs the delayed signal. For example, it is configured with an FPGA logic circuit.
  • the third delay unit 114 is connected to the second AD converter 113 and the signal separation unit 115, delays the signal output from the second AD converter 113 in time, and outputs the delayed signal to the signal separation unit 115.
  • FIG. 3 is a configuration diagram of the signal separation unit 115.
  • the signal separation unit 115 includes a phase shifter 201, an adder 202, and a separator 203.
  • the phase shifter 201 is a circuit that delays the phase of the signal output from the first delay unit 109 by 90 ° and outputs the delayed signal. For example, it is configured with an FPGA logic circuit.
  • the phase shifter 201 is connected to the first delay unit 109, the adder 202, and the signal processing unit 3, delays the phase of the signal output from the first delay unit 109 by 90 °, and adds the adder 202 and the signal processing unit 3. Output to.
  • the adder 202 is a circuit that adds the signals output from the third delay device 114 and the phase shifter 201.
  • the adder 202 adds the signals output from the third delay unit 114 and the phase shifter 201 and outputs the result to the separator 203.
  • the separator 203 is a circuit that separates the signals output from the second delay unit 112 and the adder 202.
  • it is configured with an FPGA logic circuit.
  • the separator 203 separates the signal using the signals output from the second delay unit 112 and the adder 202 and outputs the separated signal to the signal processing unit 3.
  • FIG. 4 is a configuration diagram illustrating an example of the separator 203.
  • the separator 203 includes a phase shifter 301, a subtracter 302, and an adder 303.
  • the phase shifter 301 is a circuit that delays the phase of the signal output from the second delay unit 112 by 90 ° and outputs the delayed signal.
  • the subtractor 302 is a circuit that subtracts the output signal of the phase shifter 301 and the signal output from the adder 202 to obtain the output 1 of the separator 203.
  • the adder 303 is a circuit that adds the output signal of the phase shifter 301 and the signal output from the adder 202 to output 2 of the separator 203.
  • FIG. 5 shows the phase of the signal.
  • 5B shows a signal delayed by 90 ° with respect to the phase of the signal shown in FIG. 5A
  • FIG. 5C shows a signal delayed by 180 °
  • FIG. 5D shows a signal delayed by 270 °.
  • the second power distributor 105 distributes the power of the signal output from the filter 22 into two, and outputs the signal to the first AD converter 106 and the second AD converter 113.
  • An example of a signal input to the second power distributor 105 is shown in FIG.
  • the signals input to the second power distributor 105 are three signals having different frequencies from those of the signal 1, the signal 2, and the signal 3. Further, the signal 1, the signal 2, and the signal 3 exist between 0 to 1 / 2f 0 , 1 / 2f 0 to f 0 , and f 0 to 3 / 2f 0 , respectively. That is, the sampling frequency of the first AD converter 106 and the second AD converter 113 is set to a frequency that does not overlap with the bands of the signal 1, the signal 2, and the signal 3.
  • the Oscillator 101 outputs a signal of the frequency 2f 0.
  • the first power distributor 102 divides the power of the signal output from the oscillator 101 into two, and outputs the signal to the two-frequency divider 103 and the phase shifter 104.
  • the phase shifter 104 delays the phase of the signal output from the oscillator 101 by 90 °, and outputs the signal to the first AD converter 106.
  • the first AD converter 106 operates with the signal having the frequency 2f 0 output from the phase shifter 104, samples the signal 1 and the signal 2 among the output signals of the second power distributor 105, and outputs the signal 3. Undersampling is performed, and signals are output to the LPF 107 and the HPF 110.
  • An output signal of the first AD converter 106 is shown in FIG. Among the output signals of the first AD converter 106, the phases of the signals 1 and 2 are delayed by 90 ° compared to FIG. 6, and the phase of the signal 3 is delayed by 270 °.
  • the LPF 107 passes a signal in the range of 0 to 1 / 2f 0 among the signals output from the first AD converter 106 and outputs the signal to the first decimation processor 108.
  • the output signal of the LPF 107 is shown in FIG.
  • the first decimation processor 108 decimates the output signal of the LPF 107 with a decimation factor of 2, and outputs a signal to the first delay unit 109.
  • the output signal of the LPF 107 is a digital signal having a time period of 1 / (2f 0 ).
  • the first decimation processor 108 operating with the decimation factor 2 extracts and outputs one of the two digital signals from the digital signal output from the LPF 107.
  • the output signal of the first decimation processor 108 is a digital signal with a time period of 1 / f 0 .
  • the HPF 110 passes the signal in the range of 1 / 2f 0 to f 0 among the signals output from the first AD converter 106 and outputs the signal to the first thinning processor 108.
  • the output signal of the HPF 110 is shown in FIG.
  • the second decimation processor 111 decimates the output signal of the HPF 110 with a decimation factor of 2, and outputs a signal to the second delay unit 112.
  • the output signal of the HPF 110 is a digital signal having a time period of 1 / (2f 0 ).
  • the second decimation processor 111 operating with the decimation factor 2 extracts and outputs one of the two digital signals from the digital signal output from the HPF 110.
  • the output signal of the second decimation processor 111 is a digital signal with a time period of 1 / f 0 .
  • a signal existing between 1 / 2f 0 and f 0 is frequency-converted by the second decimation processor 111 from 0 to 1 / 2f 0 .
  • the output signal of the second thinning processor 111 is shown in FIG.
  • the frequency divider 103 divides the frequency 2f 0 signal output from the first power divider 102 by 2 and outputs the signal to the second AD converter 113.
  • the second AD converter 113 operates with the signal of the frequency f 0 output from the frequency divider 103, samples the signal 1 out of the output signal of the second power divider 105, and outputs the signal 2 and the signal 3. Is undersampled and a signal is output to the third delay unit 114.
  • An output signal of the second AD converter 113 is shown in FIG.
  • the phase of the output signal of the second AD converter 113 is the same for all signals compared to FIG.
  • the signals input from the first delay unit 109, the second delay unit 112, and the third delay unit 114 to the signal separation unit 115 do not coincide with each other in time. Don't be. Therefore, the delay amounts of the first delay unit 109, the second delay unit 112, and the third delay unit 114 are determined so that the signals input to the signal separation unit 115 coincide with each other in time. Therefore, the delay amounts of the first delay device 109, the second delay device 112, and the third delay device 114 are not the same.
  • the signals output from the first delay unit 109, the second delay unit 112, and the third delay unit 114 to the signal separation unit 115 are the same as those in FIGS. 8, 10, and 11, respectively.
  • the phase shifter 201 delays the phase of the output signal of the first delay unit 109 by 90 °, and outputs a signal to the adder 202 and the signal processing unit 3.
  • the output signal of the phase shifter 201 is shown in FIG.
  • the phase of the signal 1 is delayed by 180 ° compared to FIG.
  • the adder 202 adds the output signals of the third delay unit 114 and the phase shifter 201 and outputs a signal to the separator 203.
  • the signal 1 that is the output signal of the phase shifter 201 is 180 degrees out of phase with the signal 1 that is the output signal of the third delay device 114.
  • the separator 203 separates signals using the output signals of the second delay unit 112 and the adder 202 shown in FIGS. 10 and 13, respectively, and outputs a signal to the signal processing unit 3. Signal separation is performed using other well known techniques including Weber architecture or Hartley architecture.
  • a signal 2 is output from the output 1 of the separator 203 shown in FIG. 4 and a signal 3 is output from the output 2.
  • the output 1 and output 2 signals of the separator 203 are shown in FIGS. 14 and 15, respectively.
  • three signals having different frequencies can be separated and output to the signal processing unit 3.
  • the signal 2 and the signal 3 are 180 degrees out of phase with respect to the signal 1, but this is because the signal processing unit 3 rotates the phase of the signal 1 by 180 degrees. It can be demodulated. Further, the direction of the signal 2 in FIG. 14 is left and right inverted as compared with FIG. 6, but this can also be restored by the signal processing unit 3 and demodulated.
  • phase shifter 201 may be a 270 ° phase shifter. In that case, the same effect can be obtained by changing the adder 202 to a subtracter.
  • the signal 2 is output from the output 1 of the separator 203 and the signal 3 is output from the output 2, but the output 1 is separated so that the signal 3 is output and the signal 2 is output from the output 2.
  • the vessel 203 may be configured. That is, the signal output by replacing the subtracter 302 and the adder 303 shown in FIG. 4 is reversed.
  • the first AD converter and the second AD converter that sample three analog signals having different frequencies, and the output of the first AD converter.
  • the low-pass filter that passes the low-pass signal, the high-pass filter that passes the output of the first AD converter high-pass, and the output signals of the low-pass filter and the high-pass filter are 1 ⁇ 2 the frequency. Calculation is performed using the first thinning processor and the second thinning processor, the output signal of the first thinning processor, the output signal of the second thinning processor, and the output signal of the second AD converter.
  • a signal separation unit that separates and outputs three signals corresponding to three analog signals having different frequencies
  • the sampling frequency of the second AD converter is set to 1 / of the sampling frequency of the first AD converter. 2 and the second
  • the sampling signal supplied to the AD converter and the sampling signal of the second AD converter have a phase difference of 90 °, and the sampling frequencies of the first AD converter and the second AD converter are set to three Since the frequency is set so as not to overlap with the frequency band of the analog signal, the signal can be separated even when three analog signals are received.
  • the signal separation unit includes a phase shifter that shifts the output of the first decimation processor by 90 °, an output signal of the phase shifter, and the second AD converter. And an adder that adds the output signals of the second decimation processor and an output signal of the adder, and outputs two separated signals, the output of the phase shifter Since the signal and the two separated signals of the separator are output as three signals, the signals can be separated even when three analog signals are received.
  • the signal separation unit includes a phase shifter that shifts the output of the first decimation processor by 270 °, the output signal of the phase shifter, and the second AD conversion.
  • a subtractor for subtracting the output signal of the counter, and a separator for inputting the output signal of the second decimation processor and the output signal of the subtractor and outputting two separated signals Since the output signal and the two separated signals of the separator are output as three signals, the signals can be separated even when three analog signals are received.
  • the first delay device that delays the output of the first decimation processor, the second delay device that delays the output of the second decimation processor, A third delay unit that delays the output of the second AD converter, and outputs the delay amounts of the first delay unit, the second delay unit, and the third delay unit from the first decimation processor The signal output from the second delay unit and the signal output from the second AD converter are input to the signal separation unit at the same timing.
  • the signals to be processed are the same in time, and there is no need to match the timing in the signal separation unit.
  • Embodiment 2 FIG. In the first embodiment, the configuration in which three analog signals having different frequencies input to the second power distributor 105 are separated has been described. In the second embodiment, a configuration in which four analog signals having different frequencies input to the second power distributor 105 are separated will be described.
  • FIG. 16 is a configuration diagram of the sampling circuit 23a of the second embodiment.
  • FIG. 17 is a configuration diagram of the signal separation unit 115a shown in FIG.
  • the configuration of the receiver to which the receiving apparatus of the second embodiment is applied is the same as that of the first embodiment shown in FIG.
  • the first LPF 116 is provided between the second power distributor 105 and the second AD converter 113.
  • the first LPF 116 is a circuit that passes a frequency band equal to or lower than a specific frequency and reflects a frequency band equal to or higher than a specific frequency among signals output from the second power distributor 105.
  • it is mounted using a chip inductor, a chip capacitor, or the like.
  • the first LPF 116 is connected to the second power divider 105 and the second AD converter 113, and passes a frequency band equal to or lower than a specific frequency among the signals output from the second power divider 105, Output to the second AD converter 113. Since the configuration other than the signal separation unit 115a in the sampling circuit 23a is the same as that of the first embodiment shown in FIG. 2, the same reference numerals are given to the corresponding portions, and the description thereof is omitted. In the second embodiment, the LPF 107 is described as the second LPF 107 in order to distinguish it from the first LPF 116.
  • the adder 202 of the first embodiment is deleted, and a second adder 401, a first subtracter 402, a second subtractor 403, a first An adder 404 and a third subtracter 405 are provided.
  • the second adder 401 is a circuit that adds the signal output from the phase shifter 201 and the signal output from the third subtractor 405. For example, it is configured with an FPGA logic circuit.
  • the second adder 401 is connected to the phase shifter 201, the third subtracter 405, and the signal processing unit 3, and adds the signal output from the phase shifter 201 and the signal output from the third subtractor 405. Output to the signal processing unit 3.
  • the first subtractor 402 is a circuit that subtracts the signal output from the third delay unit 114 and the signal output from the separator 203.
  • the first subtractor 402 is connected to the third delay unit 114, the separator 203, the first adder 404 and the signal processing unit 3, and the signal output from the third delay unit 114 and the separator 203 output The obtained signals are subtracted and output to the first adder 404 and the signal processing unit 3.
  • the second subtractor 403 is a circuit that subtracts the signal output from the third delay unit 114 and the signal output from the separator 203.
  • the second subtractor 403 is connected to the third delay unit 114, the separator 203, the first adder 404, and the signal processing unit 3, and the signal output from the third delay unit 114 and the separator 203 output The obtained signals are subtracted and output to the first adder 404 and the signal processing unit 3.
  • the first adder 404 is a circuit that adds the signal output from the first subtractor 402 and the signal output from the second subtractor 403. For example, it is configured with an FPGA logic circuit.
  • the first adder 404 is connected to the first subtractor 402, the second subtractor 403, and the third subtracter 405, and the signal output from the first subtractor 402 and the second subtractor 403 are connected to each other.
  • the output signals are added and output to the third subtractor 405.
  • the third subtracter 405 is a circuit that subtracts the signal output from the third delay unit 114 and the signal output from the first adder 404.
  • the third subtractor 405 is connected to the third delay unit 114, the first adder 404, the second adder 401, and the signal processing unit 3, and the third delay unit 114 and the first adder 404 are connected. Is subtracted and output to the second adder 401 and the signal processing unit 3.
  • the second power distributor 105 distributes the power of the signal output from the filter 22 into two, and outputs the signal to the first AD converter 106 and the first LPF 116.
  • An example of a signal input to the second power distributor 105 is shown in FIG.
  • Signals input to the second power distributor 105 are four signals having frequencies different from those of the signal 1, the signal 2, the signal 3, and the signal 4.
  • signal 1, signal 2, signal 3, and signal 4 exist between 0 to 1 / 2f 0 , 1 / 2f 0 to f 0 , f 0 to 3 / 2f 0 , and 3 / 2f 0 to 2f 0 , respectively. To do.
  • the first AD converter 106 operates on the signal of the frequency 2f 0 output from the phase shifter 104, samples the signal 1 and the signal 2 among the output signals of the second power divider 105, The signal 4 is undersampled, and a signal is output to the second LPF 107 and the HPF 110.
  • An output signal of the first AD converter 106 is shown in FIG. Among the output signals of the first AD converter 106, the phases of the signals 1 and 2 are delayed by 90 ° compared to FIG. 18, and the phases of the signals 3 and 4 are delayed by 270 °.
  • the second LPF 107 passes a signal in the range of 0 to 1 / 2f 0 among the signals output from the first AD converter 106 and outputs the signal to the first decimation processor 108.
  • the output signal of the second LPF 107 is shown in FIG.
  • the first thinning processor 108 performs the same operation as in the first embodiment.
  • the HPF 110 performs the same operation as in the first embodiment.
  • the output signal of the HPF 110 is shown in FIG.
  • the second thinning processor 111 performs the same operation as in the first embodiment.
  • the output signal of the second thinning processor 111 is shown in FIG.
  • the first LPF 116 passes a signal in the range of 0 to 3 / 2f 0 among the signals output from the second power distributor 105 and outputs the signal to the second AD converter 113.
  • the output signal of the first LPF 116 is shown in FIG.
  • the second AD converter 113 operates with the signal of the frequency f 0 output from the frequency divider 103, samples signal 1 out of the output signal of the second power divider 105, and outputs signal 2 and signal 3. Is undersampled and a signal is output to the third delay unit 114.
  • the output signal of the second AD converter 113 is shown in FIG.
  • the phase of the output signal of the second AD converter 113 is the same for all signals compared to FIG.
  • the first delay device 109, the second delay device 112, and the third delay device 114 operate in the same manner as in the first embodiment.
  • the phase shifter 201 delays the phase of the output signal of the first delay unit 109 by 90 ° and outputs a signal to the second adder 401.
  • the output signal of the phase shifter 201 is shown in FIG.
  • the phase of signal 1 is 180 ° behind that of FIG. 18, and signal 4 is in phase.
  • the separator 203 performs signal separation using the output signals of the second delay unit 112 and the third delay unit 114 shown in FIGS. 22 and 24, respectively, and performs the first subtractor 402 and the second subtractor 402.
  • a signal is output to the subtracter 403.
  • Signal separation is performed using other well-known techniques, including Weber architecture or Hartley architecture.
  • the signal 1 and the signal 2 are output from the output 1 of the separator 203 shown in FIG. 17, and the signal 1 and the signal 3 are output from the output 2.
  • the output 1 and output 2 signals of the separator 203 are shown in FIGS. 26 and 27, respectively.
  • the first subtractor 402 subtracts the output signal of the third delay unit 114 shown in FIGS. 24 and 26 and the separated signal of the output 1 in the separator 203, and uses the output signal as a signal processing unit. 3 and the first adder 404.
  • the output signal of the first subtractor 402 is shown in FIG.
  • the second subtracter 403 performs subtraction between the output signal of the third delay unit 114 shown in FIGS. 24 and 27 and the output 2 separation signal in the separator 203, and outputs the output to the signal processing unit 3. And a signal is output to the first adder 404.
  • the output signal of the second subtractor 403 is shown in FIG.
  • the first adder 404 adds the output signal of the first subtractor 402 and the output signal of the second subtractor 403 shown in FIGS. 28 and 29, respectively, and sends the signal to the third subtracter 405. Output.
  • the output signal of the first adder 404 is shown in FIG.
  • the third subtracter 405 subtracts the output signal of the third delay unit 114 and the output signal of the first adder 404 shown in FIGS. 24 and 30, respectively, and outputs the output signal to the signal processing unit 3. Output to.
  • the output signal of the third subtractor 405 is shown in FIG.
  • the second adder 401 adds the output signal of the phase shifter 201 and the output signal of the third subtractor 405 shown in FIGS. 25 and 31 respectively, and outputs the output signal to the signal processing unit 3. .
  • the output signal of the second adder 401 is shown in FIG.
  • phase shifter 201 may be a 270 ° phase shifter. In that case, the same effect can be obtained by changing the second adder 401 to a subtracter.
  • the first LPF 116 may be changed to a notch filter for removing one specific signal.
  • the notch filter when used, the band of the signal 4 is blocked.
  • the first AD converter that samples four analog signals having different frequencies and the first low-pass signal that allows the four analog signals to pass through the low-frequency signal.
  • the sampling frequency of the second AD converter is set to 1 ⁇ 2 of the sampling frequency of the first AD converter.
  • the sampling signal of the converter is set to a phase difference of 90 °, and the sampling frequencies of the first AD converter and the second AD converter are set to frequencies that do not overlap with the frequency bands of the four analog signals. Therefore, even when four analog signals are received, the signals can be separated.
  • the signal separation unit includes a phase shifter that shifts the output of the first decimation processor by 90 °, the output signal of the second decimation processor, and the second signal.
  • a separator that inputs the output signal of the AD converter 113 and outputs the first and second separated signals, and a first that subtracts the first separated signal and the output signal of the second AD converter.
  • a subtracter, a second subtractor for subtracting the second separated signal and the output signal of the second AD converter, and the output signal of the first subtracter and the output signal of the second subtractor are added.
  • the first adder, the third subtracter for subtracting the output signal of the first adder and the output signal of the second AD converter, the output signal of the phase shifter and the third subtractor A second adder for adding the output signal, an output signal of the second adder, an output signal of the first subtractor, an output signal of the second subtractor, 3 of the output signal of the subtractor, since the output as four signal, it is possible to separate the signals even in the case of receiving the four analog signals.
  • Embodiment 3 FIG. In the third embodiment, a configuration in which an analog signal received by the antenna 1 is frequency-converted and then output to the sampling circuit 23 will be described.
  • FIG. 33 is a configuration diagram of a receiver to which the receiving apparatus of the third embodiment is applied.
  • the receiver includes an antenna 1, an analog circuit unit 2, and a signal processing unit 3, and the analog circuit unit 2 includes an amplifier 21, a filter 22, a sampling circuit 23, and a frequency converter 24.
  • the third embodiment is different from the first embodiment in that a frequency converter 24 is provided between the filter 22 and the sampling circuit 23.
  • the frequency converter 24 is a circuit that converts the frequency of the analog signal output from the filter 22 to a low frequency.
  • it is composed of a mixer, a filter, and an IC PLL.
  • the frequency converter 24 converts the analog signal output from the filter 22 into a low frequency and outputs the signal to the sampling circuit 23.
  • the configuration of the sampling circuit 23 is the same as that of the first embodiment shown in FIG. 2 except that the signal input to the second power distributor 105 is the output signal of the frequency converter 24. This is different from the first form.
  • the receiving frequency is generally 1 GHz to 2 GHz.
  • the frequency converter 24 lowers it in advance from several MHz to several tens of MHz, and then the signal is input to the sampling circuit 23. As a result, the cost of the AD converter can be reduced.
  • the frequency converter 24 is provided for the configuration of the first embodiment, but may be applied to the configuration of the second embodiment.
  • the three analog signals having different frequencies are used as input signals, and the frequency converter is provided that converts the frequency of the input signal to a low frequency to be an output signal, Since the first AD converter and the second AD converter sample the output signal of the frequency converter, the frequency of the target signal can be lowered, so that the cost of the receiving apparatus can be reduced. Can be achieved.
  • the receiving apparatus relates to a configuration for performing signal processing by converting a plurality of analog signals having different frequencies into digital signals, and is suitable for use in a multi-channel receiver.

Abstract

In the present invention the phase of a sampling signal of a first A/D converter (106) is offset 90°. A second A/D converter (113) operates at ½ the sampling frequency. The output from the first A/D converter (106) passes through a LPF (107) and a first thinning processor (108) and passes through a HPF (110) and a second thinning processor (111), and is input to a signal separation unit (115). The output from the second A/D converter (113) is input to the signal separation unit (115). On the basis of these input signals the signal separation unit (115) separates out signals corresponding to three analog signals having different frequencies.

Description

受信装置Receiver
　本発明は、受信した周波数の異なる複数のアナログ信号をデジタル信号に変換して信号処理を行う受信装置に関するものである。 The present invention relates to a receiving apparatus that performs signal processing by converting a plurality of received analog signals having different frequencies into digital signals.
　複数のアナログ信号を同時に受信する受信機を小型化する方法として、ダイレクトＲＦアンダーサンプリング方式を用いて一つのアナログデジタル変換器（以下、ＡＤ変換器という）で受信する方法がある。
　ここで、ダイレクトＲＦ方式とは、周知の技術であるヘテロダイン方式やダイレクトコンバージョン方式と異なり、受信したアナログ信号を周波数変換せず、直接、ＡＤ変換器に入力してアナログ信号をデジタル信号に変換する方式の事である。一方、アンダーサンプリングとは、ナイキスト周波数以下でＡＤ変換器を動作させ、アナログ信号をサンプリングしデジタル信号に変換する方式の事である。ナイキストの定理よりエイリアシングが発生し、それを利用することによりデジタル信号を得ることができる。
　ダイレクトＲＦアンダーサンプリング方式とは、これら二つを組み合わせた方式であり、ダイレクトＲＦアンダーサンプリング受信機とは、前記の方式を備えた受信機の事を示す。 As a method for reducing the size of a receiver that simultaneously receives a plurality of analog signals, there is a method of receiving a single analog-digital converter (hereinafter referred to as an AD converter) using a direct RF undersampling method.
Here, the direct RF method is different from the well-known techniques of heterodyne method and direct conversion method, and does not frequency-convert the received analog signal, but directly inputs it to the AD converter to convert the analog signal into a digital signal. It is a method. On the other hand, undersampling is a method of operating an AD converter below the Nyquist frequency to sample an analog signal and convert it into a digital signal. Aliasing occurs from the Nyquist theorem, and a digital signal can be obtained by using the aliasing.
The direct RF undersampling system is a system combining these two, and the direct RF undersampling receiver indicates a receiver having the above system.
　アンダーサンプリングを用いて一つのＡＤ変換器で複数のアナログ信号を同時にデジタル信号に変換することができる。通常、アンダーサンプリング後、ＡＤ変換器から出力する信号が互いに重複しないようにサンプリング信号の周波数を選定している。ＡＤ変換器に入力するアナログ信号の周波数によっては、アンダーサンプリング後、ＡＤ変換器から出力する信号間に広い空き周波数領域が生じる。このような場合、サンプリング信号の周波数が高くなり、ＡＤ変換器の消費電力が増加する。 ア ン ダ ー Multiple analog signals can be converted simultaneously into digital signals with a single AD converter using undersampling. Usually, after undersampling, the frequency of the sampling signal is selected so that signals output from the AD converter do not overlap each other. Depending on the frequency of the analog signal input to the AD converter, a wide vacant frequency region occurs between the signals output from the AD converter after undersampling. In such a case, the frequency of the sampling signal increases and the power consumption of the AD converter increases.
　例えば、特許文献１に記載された従来の受信機では、同じ周波数をもち、所定の位相によりオフセットされる二つのサンプリング信号で二つのＡＤ変換器をそれぞれ動作させ、アナログ信号をアンダーサンプリングしてデジタル信号に変換した後に、一般的にイメージリジェクションミクサとして利用されるウェーバーアーキテクチャーまたはハートレーアーキテクチャーを含む、その他の周知の技術を用いて受信した信号を分離する。 For example, in the conventional receiver described in Patent Document 1, two AD converters are operated with two sampling signals having the same frequency and offset by a predetermined phase, and analog signals are undersampled to perform digital sampling. After conversion to a signal, the received signal is separated using other well-known techniques, including Weber architecture or Hartley architecture, commonly used as an image rejection mixer.
特表２０１１－５２６１３２号公報Special table 2011-526132 gazette
　上記特許文献１に記載された従来の受信機では、アンダーサンプリング後の信号の帯域が互いに重複しないようにサンプリング信号の周波数を選定する方式と比較して低い周波数でＡＤ変換器を動作させることが可能となり、ＡＤ変換器の消費電力を小さくすることが可能となる。しかしながら、上記特許文献１に記載された受信機では、三つ以上のアナログ信号を受信した場合に信号を分離することができないという問題があった。 In the conventional receiver described in Patent Document 1, the AD converter can be operated at a frequency lower than that of the method of selecting the frequency of the sampling signal so that the bands of the signals after undersampling do not overlap each other. Thus, the power consumption of the AD converter can be reduced. However, the receiver described in Patent Document 1 has a problem that the signals cannot be separated when three or more analog signals are received.
　この発明は、かかる問題を解決するためになされたもので、三つ以上のアナログ信号を受信した場合でも信号を分離することのできる受信装置を提供することを目的とする。 The present invention has been made to solve such a problem, and an object of the present invention is to provide a receiving apparatus capable of separating signals even when three or more analog signals are received.
　この発明に係る受信装置は、周波数の異なる三つのアナログ信号をサンプリングする第１のＡＤ変換器及び第２のＡＤ変換器と、第１のＡＤ変換器の出力を低域通過させる低域通過フィルタと、第１のＡＤ変換器の出力を高域通過させる高域通過フィルタと、低域通過フィルタ及び高域通過フィルタの出力信号を１／２の周波数とする第１の間引き処理器及び第２の間引き処理器と、第１の間引き処理器の出力信号と第２の間引き処理器の出力信号と第２のＡＤ変換器の出力信号とを用いて演算を行い、周波数の異なる三つのアナログ信号に対応した三つの信号を分離して出力する信号分離部とを備え、第２のＡＤ変換器のサンプリング周波数を第１のＡＤ変換器のサンプリング周波数の１／２とし、かつ、第１のＡＤ変換器に供給するサンプリング信号と第２のＡＤ変換器のサンプリング信号とを９０゜の位相差とすると共に、第１のＡＤ変換器及び第２のＡＤ変換器のサンプリング周波数を、三つのアナログ信号の周波数帯域と重ならない周波数に設定するようにしたものである。 A receiving apparatus according to the present invention includes a first AD converter and a second AD converter that sample three analog signals having different frequencies, and a low-pass filter that passes the output of the first AD converter in a low-pass manner. A high pass filter that passes the output of the first AD converter in a high pass, a first decimation processor that makes the output signal of the low pass filter and the high pass filter a half frequency, and a second Three analog signals having different frequencies by performing an operation using the output signal of the first thinning processor, the output signal of the second thinning processor, and the output signal of the second AD converter. And a signal separation unit that separates and outputs three signals corresponding to the second AD converter, the sampling frequency of the second AD converter is ½ of the sampling frequency of the first AD converter, and the first AD Supply to the converter The pulling signal and the sampling signal of the second AD converter have a phase difference of 90 °, and the sampling frequencies of the first AD converter and the second AD converter are overlapped with the frequency bands of the three analog signals. The frequency is set so that it does not become.
　この発明に係る受信装置は、第２のＡＤ変換器のサンプリング周波数を第１のＡＤ変換器のサンプリング周波数の１／２とし、かつ、第１のＡＤ変換器に供給するサンプリング信号と第２のＡＤ変換器のサンプリング信号とを９０゜の位相差とし、第１のＡＤ変換器の出力を低域通過フィルタ及び第１の間引き処理器で処理した信号と、第１のＡＤ変換器の出力を高域通過フィルタ及び第２の間引き処理器で処理した信号と、第２のＡＤ変換器から出力した信号とを用いて三つの信号を分離して出力するようにしたものである。これにより、三つのアナログ信号を受信した場合でも信号を分離することができる。 In the receiving apparatus according to the present invention, the sampling frequency of the second AD converter is set to ½ of the sampling frequency of the first AD converter, and the sampling signal supplied to the first AD converter and the second AD converter A signal obtained by processing the output of the first AD converter with the low-pass filter and the first decimation processor and the output of the first AD converter with a 90 ° phase difference from the sampling signal of the AD converter The three signals are separated and output using the signal processed by the high-pass filter and the second thinning processor and the signal output from the second AD converter. Thereby, even when three analog signals are received, the signals can be separated.
この発明の実施の形態１の受信装置が適用される受信機の構成図である。BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram of the receiver with which the receiver of Embodiment 1 of this invention is applied. この発明の実施の形態１の受信装置の構成図である。It is a block diagram of the receiver of Embodiment 1 of this invention. この発明の実施の形態１の受信装置における信号分離部の一例を示す構成図である。It is a block diagram which shows an example of the signal separation part in the receiver of Embodiment 1 of this invention. この発明の実施の形態１の受信装置における分離器の一例を示す構成図である。It is a block diagram which shows an example of the separator in the receiver of Embodiment 1 of this invention. 図５Ａ～図５Ｄは、信号の位相を定義する説明図である。5A to 5D are explanatory diagrams for defining the phase of the signal. この発明の実施の形態１の受信装置における第２の電力分配器に入力する信号の一例を示す説明図である。It is explanatory drawing which shows an example of the signal input into the 2nd power divider | distributor in the receiver of Embodiment 1 of this invention. この発明の実施の形態１の受信装置における第１のＡＤ変換器の出力信号を示す説明図である。It is explanatory drawing which shows the output signal of the 1st AD converter in the receiver of Embodiment 1 of this invention. この発明の実施の形態１の受信装置におけるＬＰＦの出力信号を示す説明図である。It is explanatory drawing which shows the output signal of LPF in the receiver of Embodiment 1 of this invention. この発明の実施の形態１の受信装置におけるＨＰＦの出力信号を示す説明図である。It is explanatory drawing which shows the output signal of HPF in the receiver of Embodiment 1 of this invention. この発明の実施の形態１の受信装置における第２の間引き処理器の出力信号を示す図である。It is a figure which shows the output signal of the 2nd thinning-out processor in the receiver of Embodiment 1 of this invention. この発明の実施の形態１の受信装置における第２のＡＤ変換器の出力信号を示す説明図である。It is explanatory drawing which shows the output signal of the 2nd AD converter in the receiver of Embodiment 1 of this invention. この発明の実施の形態１の受信装置における移相器の出力信号を示す説明図である。It is explanatory drawing which shows the output signal of the phase shifter in the receiver of Embodiment 1 of this invention. この発明の実施の形態１の受信装置における加算器の出力信号を示す説明図である。It is explanatory drawing which shows the output signal of the adder in the receiver of Embodiment 1 of this invention. この発明の実施の形態１の受信装置における分離器の出力１の信号を示す説明図である。It is explanatory drawing which shows the signal of the output 1 of the separator in the receiver of Embodiment 1 of this invention. この発明の実施の形態１の受信装置における分離器２０３の出力２の信号を示す説明図である。It is explanatory drawing which shows the signal of the output 2 of the separator 203 in the receiver of Embodiment 1 of this invention. この発明の実施の形態２の受信装置の構成図である。It is a block diagram of the receiver of Embodiment 2 of this invention. この発明の実施の形態２の受信装置における信号分離部の一例を示す構成図である。It is a block diagram which shows an example of the signal separation part in the receiver of Embodiment 2 of this invention. この発明の実施の形態２の受信装置における第２の電力分配器に入力する信号の一例を示す説明図である。It is explanatory drawing which shows an example of the signal input into the 2nd power divider | distributor in the receiver of Embodiment 2 of this invention. この発明の実施の形態２の受信装置における第１のＡＤ変換器の出力信号を示す説明図である。It is explanatory drawing which shows the output signal of the 1st AD converter in the receiver of Embodiment 2 of this invention. この発明の実施の形態２の受信装置における第２のＬＰＦの出力信号を示す説明図である。It is explanatory drawing which shows the output signal of the 2nd LPF in the receiver of Embodiment 2 of this invention. この発明の実施の形態２の受信装置におけるＨＰＦの出力信号を示す説明図である。It is explanatory drawing which shows the output signal of HPF in the receiver of Embodiment 2 of this invention. この発明の実施の形態２の受信装置における第２の間引き処理器の出力信号を示す説明図である。It is explanatory drawing which shows the output signal of the 2nd thinning processor in the receiver of Embodiment 2 of this invention. この発明の実施の形態２の受信装置における第１のＬＰＦの出力信号を示す説明図である。It is explanatory drawing which shows the output signal of 1st LPF in the receiver of Embodiment 2 of this invention. この発明の実施の形態２の受信装置における第２のＡＤ変換器の出力信号を示す説明図である。It is explanatory drawing which shows the output signal of the 2nd AD converter in the receiver of Embodiment 2 of this invention. この発明の実施の形態２の受信装置における移相器の出力信号を示す説明図である。It is explanatory drawing which shows the output signal of the phase shifter in the receiver of Embodiment 2 of this invention. この発明の実施の形態２の受信装置における分離器の出力１の信号を示す説明図である。It is explanatory drawing which shows the signal of the output 1 of the separator in the receiver of Embodiment 2 of this invention. この発明の実施の形態２の受信装置における分離器の出力２の信号を示す説明図である。It is explanatory drawing which shows the signal of the output 2 of the separator in the receiver of Embodiment 2 of this invention. この発明の実施の形態２の受信装置における第１の減算器の出力信号を示す説明図である。It is explanatory drawing which shows the output signal of the 1st subtractor in the receiver of Embodiment 2 of this invention. この発明の実施の形態２の受信装置における第２の減算器の出力信号を示す説明図である。It is explanatory drawing which shows the output signal of the 2nd subtractor in the receiver of Embodiment 2 of this invention. この発明の実施の形態２の受信装置における第１の加算器の出力信号を示す説明図である。It is explanatory drawing which shows the output signal of the 1st adder in the receiver of Embodiment 2 of this invention. この発明の実施の形態２の受信装置における第３の減算器の出力信号を示す説明図である。It is explanatory drawing which shows the output signal of the 3rd subtractor in the receiver of Embodiment 2 of this invention. この発明の実施の形態２の受信装置における第２の加算器の出力信号を示す説明図である。It is explanatory drawing which shows the output signal of the 2nd adder in the receiver of Embodiment 2 of this invention. この発明の実施の形態３の受信装置が適用される受信機の一例を示す構成図である。It is a block diagram which shows an example of the receiver with which the receiver of Embodiment 3 of this invention is applied.
　以下、この発明をより詳細に説明するために、この発明を実施するための形態について、添付の図面に従って説明する。
実施の形態１．
　図１は、本実施の形態による受信装置を適用する受信機の構成図である。
　図１に示す受信機は、アンテナ１、アナログ回路部２、信号処理部３を備え、アナログ回路部２は、増幅器２１、フィルタ２２、サンプリング回路２３を備える。アンテナ１は、周波数の異なる複数のアナログ信号を受信するアンテナである。アナログ回路部２は、アンテナ１で受信したアナログ信号の処理を行う回路である。信号処理部３は、アナログ回路部２の出力信号を用いて信号処理を行う処理部である。アナログ回路部２における増幅器２１は、アンテナ１で受信したアナログ信号を所定の増幅率で増幅する増幅器である。フィルタ２２は、不要なアナログ信号を抑圧するフィルタである。サンプリング回路２３はアナログ信号をデジタル信号に変換する処理を行う回路であり、本実施の形態の受信装置に相当する。 Hereinafter, in order to explain the present invention in more detail, modes for carrying out the present invention will be described with reference to the accompanying drawings.
Embodiment 1 FIG.
FIG. 1 is a configuration diagram of a receiver to which a receiving apparatus according to this embodiment is applied.
The receiver shown in FIG. 1 includes an antenna 1, an analog circuit unit 2, and a signal processing unit 3. The analog circuit unit 2 includes an amplifier 21, a filter 22, and a sampling circuit 23. The antenna 1 is an antenna that receives a plurality of analog signals having different frequencies. The analog circuit unit 2 is a circuit that processes an analog signal received by the antenna 1. The signal processing unit 3 is a processing unit that performs signal processing using the output signal of the analog circuit unit 2. The amplifier 21 in the analog circuit unit 2 is an amplifier that amplifies an analog signal received by the antenna 1 with a predetermined amplification factor. The filter 22 is a filter that suppresses unnecessary analog signals. The sampling circuit 23 is a circuit that performs processing for converting an analog signal into a digital signal, and corresponds to the receiving apparatus of the present embodiment.
　図２は、サンプリング回路２３の詳細を示す構成図である。
　図示のように、サンプリング回路２３は、発振器１０１、第１の電力分配器１０２、２分周器１０３、移相器１０４、第２の電力分配器１０５、第１のＡＤ変換器１０６、低域通過フィルタ（以下、ＬＰＦという）１０７、第１の間引き処理器１０８、第１の遅延器１０９、高域通過フィルタ（以下、ＨＰＦという）１１０、第２の間引き処理器１１１、第２の遅延器１１２、第２のＡＤ変換器１１３、第３の遅延器１１４、信号分離部１１５を備える。 FIG. 2 is a configuration diagram showing details of the sampling circuit 23.
As illustrated, the sampling circuit 23 includes an oscillator 101, a first power divider 102, a two-frequency divider 103, a phase shifter 104, a second power divider 105, a first AD converter 106, a low frequency band, Pass filter (hereinafter referred to as LPF) 107, first decimation processor 108, first delay unit 109, high-pass filter (hereinafter referred to as HPF) 110, second decimation processor 111, second delay unit 112, a second AD converter 113, a third delay unit 114, and a signal separation unit 115.
　発振器１０１は、第１のＡＤ変換器１０６と第２のＡＤ変換器１１３に入力するサンプリング信号の基準信号を励振する発振器である。例えば、水晶発振器が用いられる。発振器１０１は、第１の電力分配器１０２に接続され、周波数２ｆ０にて発振し、発振した信号を電力分配器１０２へ出力する。第１の電力分配器１０２は、発振器１０１が出力した信号が入力され、その信号の電力を２分配する回路である。例えば、ディスクリートの電力分配器が用いられる。第１の電力分配器１０２は、発振器１０１と２分周器１０３と移相器１０４とに接続され、発振器１０１が出力した信号の電力を２分配し、２分周器１０３と移相器１０４へそれぞれ出力する。移相器１０４は、第１の電力分配器１０２が出力した信号の位相を９０°遅らせて出力する回路である。例えば、ディスクリートの移相器が用いられる。移相器１０４は、第１の電力分配器１０２と第１のＡＤ変換器１０６に接続され、第１の電力分配器１０２が出力した信号の位相を９０°遅らせ、第１のＡＤ変換器１０６へ出力する。 The oscillator 101 is an oscillator that excites a reference signal of a sampling signal input to the first AD converter 106 and the second AD converter 113. For example, a crystal oscillator is used. Oscillator 101 is connected to a first power splitter 102, it oscillates at a frequency 2f 0, and outputs an oscillation signal to the power divider 102. The first power distributor 102 is a circuit that receives the signal output from the oscillator 101 and distributes the power of the signal into two. For example, a discrete power distributor is used. The first power divider 102 is connected to the oscillator 101, the two-frequency divider 103, and the phase shifter 104. The first power divider 102 distributes the power of the signal output from the oscillator 101 to two, and the two-frequency divider 103 and the phase shifter 104. To each output. The phase shifter 104 is a circuit that delays the phase of the signal output from the first power distributor 102 by 90 ° and outputs the delayed signal. For example, a discrete phase shifter is used. The phase shifter 104 is connected to the first power divider 102 and the first AD converter 106, delays the phase of the signal output by the first power divider 102 by 90 °, and the first AD converter 106. Output to.
　２分周器１０３は、第１の電力分配器１０２が出力した信号の周波数を半分にする回路である。例えば、ＩＣの分周器が用いられる。２分周器１０３は、第１の電力分配器１０２と第２のＡＤ変換器１１３に接続され、第１の電力分配器１０２が出力した信号の周波数を半分にし、第２のＡＤ変換器１１３へ出力する。第２の電力分配器１０５は、フィルタ２２が出力した信号の電力を２分配する回路である。例えば、ディスクリートの電力分配器が用いられる。第２の電力分配器１０５は、フィルタ２２と第１のＡＤ変換器１０６と第２のＡＤ変換器１１３に接続され、フィルタ２２が出力した信号の電力を２分配し、第１のＡＤ変換器１０６と第２のＡＤ変換器１１３へそれぞれ出力する。 The frequency divider 103 is a circuit that halves the frequency of the signal output from the first power distributor 102. For example, an IC frequency divider is used. The two-frequency divider 103 is connected to the first power divider 102 and the second AD converter 113, halves the frequency of the signal output from the first power divider 102, and the second AD converter 113. Output to. The second power distributor 105 is a circuit that distributes the power of the signal output from the filter 22 into two. For example, a discrete power distributor is used. The second power distributor 105 is connected to the filter 22, the first AD converter 106, and the second AD converter 113, and distributes the power of the signal output from the filter 22 into two, and the first AD converter 106 and the second AD converter 113, respectively.
　第１のＡＤ変換器１０６は、移相器１０４が出力した信号をサンプリング信号とし、そのサンプリング信号を用いて第２の電力分配器１０５が出力した信号をデジタル信号に変換して出力する回路である。例えば、ＩＣのＡＤ変換器が用いられる。第１のＡＤ変換器１０６は、移相器１０４と第２の電力分配器１０５とＬＰＦ１０７とＨＰＦ１１０に接続され、第２の電力分配器１０５が出力した信号をデジタル信号に変換し、ＬＰＦ１０７とＨＰＦ１１０へそれぞれ出力する。 The first AD converter 106 is a circuit that uses the signal output from the phase shifter 104 as a sampling signal, converts the signal output from the second power distributor 105 into a digital signal using the sampling signal, and outputs the digital signal. is there. For example, an IC AD converter is used. The first AD converter 106 is connected to the phase shifter 104, the second power distributor 105, the LPF 107, and the HPF 110, converts the signal output from the second power distributor 105 into a digital signal, and the LPF 107 and the HPF 110. To each output.
　ＬＰＦ１０７は、第１のＡＤ変換器１０６が出力したデジタル信号の内、特定の周波数以下の周波数帯域を通過させ、特定の周波数以上の周波数帯域を減衰させる回路である。例えば、ＦＰＧＡの論理回路で構成される。ＬＰＦ１０７は、第１のＡＤ変換器１０６と第１の間引き処理器１０８に接続され、第１のＡＤ変換器１０６で出力した信号の内、周波数の低い信号を通過させ、第１の間引き処理器１０８へ出力する。第１の間引き処理器１０８は、ＬＰＦ１０７が出力した信号を間引く回路である。例えば、ＦＰＧＡの論理回路で構成される。第１の間引き処理器１０８は、ＬＰＦ１０７と第１の遅延器１０９に接続され、ＬＰＦ１０７が出力した信号を間引き、第１の遅延器１０９へ出力する。 The LPF 107 is a circuit that passes a frequency band below a specific frequency in the digital signal output from the first AD converter 106 and attenuates the frequency band above the specific frequency. For example, it is configured with an FPGA logic circuit. The LPF 107 is connected to the first AD converter 106 and the first decimation processor 108, and passes a signal having a low frequency among the signals output from the first AD converter 106, and the first decimation processor To 108. The first decimation processor 108 is a circuit that decimates the signal output from the LPF 107. For example, it is configured with an FPGA logic circuit. The first decimation processor 108 is connected to the LPF 107 and the first delay unit 109, decimates the signal output from the LPF 107, and outputs it to the first delay unit 109.
　第１の遅延器１０９は、第１の間引き処理器１０８が出力した信号を時間的に遅延させて出力する回路である。例えば、ＦＰＧＡの論理回路で構成される。第１の遅延器１０９は、第１の間引き処理器１０８と信号分離部１１５とに接続され、第１の間引き処理器１０８が出力した信号を時間的に遅延させ、信号分離部１１５へ出力する。 The first delay unit 109 is a circuit that delays the signal output from the first decimation processor 108 and outputs the delayed signal. For example, it is configured with an FPGA logic circuit. The first delay unit 109 is connected to the first decimation processor 108 and the signal separation unit 115, delays the signal output from the first decimation processor 108 in time, and outputs the delayed signal to the signal separation unit 115. .
　ＨＰＦ１１０は、第１のＡＤ変換器１０６が出力したデジタル信号の内、特定の周波数以上の周波数帯域を通過させ、特定の周波数以下の周波数帯域を減衰させる回路である。例えば、ＦＰＧＡの論理回路で構成される。ＨＰＦ１１０は、第１のＡＤ変換器１０６と第２の間引き処理器１１１に接続され、第１のＡＤ変換器１０６が出力した信号の内、周波数の高い信号を通過させ、第２の間引き処理器１１１へ出力する。第２の間引き処理器１１１は、ＨＰＦ１１０が出力した信号を間引く回路である。例えば、ＦＰＧＡの論理回路で構成される。第２の間引き処理器１１１は、ＨＰＦ１１０と第２の遅延器１１２に接続され、ＨＰＦ１１０が出力した信号を間引き、第２の遅延器１１２へ出力する。 The HPF 110 is a circuit that passes a frequency band of a specific frequency or higher and attenuates a frequency band of a specific frequency or lower in the digital signal output from the first AD converter 106. For example, it is configured with an FPGA logic circuit. The HPF 110 is connected to the first AD converter 106 and the second decimation processor 111, and passes a signal having a high frequency among the signals output from the first AD converter 106, and the second decimation processor To 111. The second decimation processor 111 is a circuit that decimates the signal output from the HPF 110. For example, it is configured with an FPGA logic circuit. The second decimation processor 111 is connected to the HPF 110 and the second delay unit 112, decimates the signal output from the HPF 110, and outputs the signal to the second delay unit 112.
　第２の遅延器１１２は、第２の間引き処理器１１１が出力した信号を時間的に遅延させて出力する回路である。例えば、ＦＰＧＡの論理回路で構成される。第２の遅延器１１２は、第２の間引き処理器１１１と信号分離部１１５に接続され、第２の間引き処理器１１１が出力した信号を時間的に遅延させ、信号分離部１１５へ出力する。第２のＡＤ変換器１１３は、２分周器１０３が出力した信号をサンプリング信号とし、そのサンプリング信号を用いて第２の電力分配器１０５が出力した信号をデジタル信号に変換して出力する回路である。例えば、ＩＣのＡＤ変換器が用いられる。第２のＡＤ変換器１１３は、２分周器１０３と第２の電力分配器１０５と第３の遅延器１１４に接続され、２分周器１０３が出力した信号をサンプリング信号とし、そのサンプリング信号を用いて第２の電力分配器１０５が出力した信号をデジタル信号に変換し、第３の遅延器１１４へ出力する。第３の遅延器１１４は、第２のＡＤ変換器１１３が出力した信号を時間的に遅延させて出力する回路である。例えば、ＦＰＧＡの論理回路で構成される。第３の遅延器１１４は、第２のＡＤ変換器１１３と信号分離部１１５に接続され、第２のＡＤ変換器１１３が出力した信号を時間的に遅延させ、信号分離部１１５へ出力する。 The second delay unit 112 is a circuit that delays the signal output from the second decimation processor 111 and outputs the delayed signal. For example, it is configured with an FPGA logic circuit. The second delay unit 112 is connected to the second decimation processor 111 and the signal separation unit 115, delays the signal output from the second decimation processor 111 in time, and outputs the delayed signal to the signal separation unit 115. The second AD converter 113 uses the signal output from the frequency divider 103 as a sampling signal, converts the signal output from the second power distributor 105 into a digital signal using the sampling signal, and outputs the digital signal It is. For example, an IC AD converter is used. The second AD converter 113 is connected to the frequency divider 103, the second power distributor 105, and the third delay device 114, and the signal output from the frequency divider 103 is used as a sampling signal. Is used to convert the signal output from the second power distributor 105 into a digital signal and output it to the third delay unit 114. The third delay unit 114 is a circuit that delays the signal output from the second AD converter 113 and outputs the delayed signal. For example, it is configured with an FPGA logic circuit. The third delay unit 114 is connected to the second AD converter 113 and the signal separation unit 115, delays the signal output from the second AD converter 113 in time, and outputs the delayed signal to the signal separation unit 115.
　図３は、信号分離部１１５の構成図である。信号分離部１１５は、移相器２０１、加算器２０２、分離器２０３を備える。移相器２０１は、第１の遅延器１０９が出力した信号の位相を９０°遅らせて出力する回路である。例えば、ＦＰＧＡの論理回路で構成される。移相器２０１は、第１の遅延器１０９と加算器２０２と信号処理部３に接続され、第１の遅延器１０９が出力した信号の位相を９０°遅らせ、加算器２０２及び信号処理部３へ出力する。加算器２０２は、第３の遅延器１１４と移相器２０１が出力した信号を加算する回路である。例えば、ＦＰＧＡの論理回路で構成される。加算器２０２は、第３の遅延器１１４と移相器２０１が出力した信号を加算し、分離器２０３へ出力する。分離器２０３は、第２の遅延器１１２及び加算器２０２が出力した信号を分離する回路である。例えば、ＦＰＧＡの論理回路で構成される。分離器２０３は、第２の遅延器１１２と加算器２０２が出力した信号を用いて信号を分離し、信号処理部３へ出力する。 FIG. 3 is a configuration diagram of the signal separation unit 115. The signal separation unit 115 includes a phase shifter 201, an adder 202, and a separator 203. The phase shifter 201 is a circuit that delays the phase of the signal output from the first delay unit 109 by 90 ° and outputs the delayed signal. For example, it is configured with an FPGA logic circuit. The phase shifter 201 is connected to the first delay unit 109, the adder 202, and the signal processing unit 3, delays the phase of the signal output from the first delay unit 109 by 90 °, and adds the adder 202 and the signal processing unit 3. Output to. The adder 202 is a circuit that adds the signals output from the third delay device 114 and the phase shifter 201. For example, it is configured with an FPGA logic circuit. The adder 202 adds the signals output from the third delay unit 114 and the phase shifter 201 and outputs the result to the separator 203. The separator 203 is a circuit that separates the signals output from the second delay unit 112 and the adder 202. For example, it is configured with an FPGA logic circuit. The separator 203 separates the signal using the signals output from the second delay unit 112 and the adder 202 and outputs the separated signal to the signal processing unit 3.
　図４は、分離器２０３の一例を示す構成図である。分離器２０３は、移相器３０１、減算器３０２、加算器３０３を備える。移相器３０１は第２の遅延器１１２が出力した信号の位相を９０゜遅らせて出力する回路である。減算器３０２は移相器３０１の出力信号と加算器２０２が出力した信号との減算を行い、分離器２０３の出力１とする回路である。加算器３０３は、移相器３０１の出力信号と加算器２０２が出力した信号とを加算し、分離器２０３の出力２とする回路である。 FIG. 4 is a configuration diagram illustrating an example of the separator 203. The separator 203 includes a phase shifter 301, a subtracter 302, and an adder 303. The phase shifter 301 is a circuit that delays the phase of the signal output from the second delay unit 112 by 90 ° and outputs the delayed signal. The subtractor 302 is a circuit that subtracts the output signal of the phase shifter 301 and the signal output from the adder 202 to obtain the output 1 of the separator 203. The adder 303 is a circuit that adds the output signal of the phase shifter 301 and the signal output from the adder 202 to output 2 of the separator 203.
　次に、実施の形態１の受信装置におけるサンプリング回路２３の動作を説明する。
　図５は、信号の位相を示している。図５Ａで示す信号の位相を基準として、位相が９０°遅れた信号を図５Ｂで、位相が１８０°遅れた信号を図５Ｃで、位相が２７０°遅れた信号を図５Ｄで示す。 Next, the operation of the sampling circuit 23 in the receiving apparatus according to the first embodiment will be described.
FIG. 5 shows the phase of the signal. 5B shows a signal delayed by 90 ° with respect to the phase of the signal shown in FIG. 5A, FIG. 5C shows a signal delayed by 180 °, and FIG. 5D shows a signal delayed by 270 °.
　第２の電力分配器１０５は、フィルタ２２が出力した信号の電力を２分配し、第１のＡＤ変換器１０６及び第２のＡＤ変換器１１３に信号を出力する。第２の電力分配器１０５に入力する信号の一例を図６に示す。第２の電力分配器１０５に入力する信号は、信号１、信号２、信号３と周波数の異なる三つの信号とする。また、信号１、信号２、信号３は、それぞれ０から１／２ｆ０、１／２ｆ０からｆ０、ｆ０から３／２ｆ０の間に存在する。すなわち、第１のＡＤ変換器１０６と第２のＡＤ変換器１１３のサンプリング周波数は、信号１、信号２、信号３の帯域とは重ならない周波数に設定されている。 The second power distributor 105 distributes the power of the signal output from the filter 22 into two, and outputs the signal to the first AD converter 106 and the second AD converter 113. An example of a signal input to the second power distributor 105 is shown in FIG. The signals input to the second power distributor 105 are three signals having different frequencies from those of the signal 1, the signal 2, and the signal 3. Further, the signal 1, the signal 2, and the signal 3 exist between 0 to 1 / 2f 0 , 1 / 2f 0 to f 0 , and f 0 to 3 / 2f 0 , respectively. That is, the sampling frequency of the first AD converter 106 and the second AD converter 113 is set to a frequency that does not overlap with the bands of the signal 1, the signal 2, and the signal 3.
　発振器１０１は、周波数２ｆ０の信号を出力する。第１の電力分配器１０２は、発振器１０１が出力した信号の電力を２分配し、２分周器１０３及び移相器１０４へ信号を出力する。移相器１０４は、発振器１０１が出力した信号の位相を９０°遅らせ、第１のＡＤ変換器１０６へ信号を出力する。第１のＡＤ変換器１０６は、移相器１０４が出力した周波数２ｆ０の信号で動作し、第２の電力分配器１０５の出力信号の内、信号１及び信号２をサンプリングし、信号３をアンダーサンプリングし、ＬＰＦ１０７及びＨＰＦ１１０へ信号を出力する。第１のＡＤ変換器１０６の出力信号を図７に示す。第１のＡＤ変換器１０６の出力信号の内、信号１及び信号２の位相は図６と比較して９０°遅れており、信号３の位相は２７０°遅れている。 Oscillator 101 outputs a signal of the frequency 2f 0. The first power distributor 102 divides the power of the signal output from the oscillator 101 into two, and outputs the signal to the two-frequency divider 103 and the phase shifter 104. The phase shifter 104 delays the phase of the signal output from the oscillator 101 by 90 °, and outputs the signal to the first AD converter 106. The first AD converter 106 operates with the signal having the frequency 2f 0 output from the phase shifter 104, samples the signal 1 and the signal 2 among the output signals of the second power distributor 105, and outputs the signal 3. Undersampling is performed, and signals are output to the LPF 107 and the HPF 110. An output signal of the first AD converter 106 is shown in FIG. Among the output signals of the first AD converter 106, the phases of the signals 1 and 2 are delayed by 90 ° compared to FIG. 6, and the phase of the signal 3 is delayed by 270 °.
　ＬＰＦ１０７は、第１のＡＤ変換器１０６が出力した信号の内、０から１／２ｆ０の範囲の信号を通過させ、第１の間引き処理器１０８へ出力する。ＬＰＦ１０７の出力信号を図８に示す。第１の間引き処理器１０８は、間引き係数２でＬＰＦ１０７の出力信号を間引き、第１の遅延器１０９へ信号を出力する。ＬＰＦ１０７の出力信号は１／（２ｆ０）の時間周期のデジタル信号である。間引き係数２で動作する第１の間引き処理器１０８は、ＬＰＦ１０７から出力されたデジタル信号において２点の内１点のデジタル信号を抽出して出力する。第１の間引き処理器１０８の出力信号は１／ｆ０の時間周期のデジタル信号となる。 The LPF 107 passes a signal in the range of 0 to 1 / 2f 0 among the signals output from the first AD converter 106 and outputs the signal to the first decimation processor 108. The output signal of the LPF 107 is shown in FIG. The first decimation processor 108 decimates the output signal of the LPF 107 with a decimation factor of 2, and outputs a signal to the first delay unit 109. The output signal of the LPF 107 is a digital signal having a time period of 1 / (2f 0 ). The first decimation processor 108 operating with the decimation factor 2 extracts and outputs one of the two digital signals from the digital signal output from the LPF 107. The output signal of the first decimation processor 108 is a digital signal with a time period of 1 / f 0 .
　ＨＰＦ１１０は、第１のＡＤ変換器１０６が出力した信号の内、１／２ｆ０からｆ０の範囲の信号を通過させ、第１の間引き処理器１０８へ出力する。ＨＰＦ１１０の出力信号を図９に示す。第２の間引き処理器１１１は、間引き係数２でＨＰＦ１１０の出力信号を間引き、第２の遅延器１１２へ信号を出力する。ＨＰＦ１１０の出力信号は１／（２ｆ０）の時間周期のデジタル信号である。間引き係数２で動作する第２の間引き処理器１１１は、ＨＰＦ１１０から出力されたデジタル信号において、２点の内１点のデジタル信号を抽出して出力する。第２の間引き処理器１１１の出力信号は１／ｆ０の時間周期のデジタル信号となる。１／２ｆ０からｆ０の間に存在している信号は、第２の間引き処理器１１１により０から１／２ｆ０内に周波数変換される。第２の間引き処理器１１１の出力信号を図１０に示す。 The HPF 110 passes the signal in the range of 1 / 2f 0 to f 0 among the signals output from the first AD converter 106 and outputs the signal to the first thinning processor 108. The output signal of the HPF 110 is shown in FIG. The second decimation processor 111 decimates the output signal of the HPF 110 with a decimation factor of 2, and outputs a signal to the second delay unit 112. The output signal of the HPF 110 is a digital signal having a time period of 1 / (2f 0 ). The second decimation processor 111 operating with the decimation factor 2 extracts and outputs one of the two digital signals from the digital signal output from the HPF 110. The output signal of the second decimation processor 111 is a digital signal with a time period of 1 / f 0 . A signal existing between 1 / 2f 0 and f 0 is frequency-converted by the second decimation processor 111 from 0 to 1 / 2f 0 . The output signal of the second thinning processor 111 is shown in FIG.
　２分周器１０３は、第１の電力分配器１０２が出力した周波数２ｆ０の信号を２分周し、第２のＡＤ変換器１１３へ信号を出力する。第２のＡＤ変換器１１３は、２分周器１０３が出力した周波数ｆ０の信号で動作し、第２の電力分配器１０５の出力信号の内、信号１をサンプリングし、信号２及び信号３をアンダーサンプリングし、第３の遅延器１１４へ信号を出力する。第２のＡＤ変換器１１３の出力信号を図１１に示す。第２のＡＤ変換器１１３の出力信号の位相は、図６と比較していずれの信号も位相は等しい。 The frequency divider 103 divides the frequency 2f 0 signal output from the first power divider 102 by 2 and outputs the signal to the second AD converter 113. The second AD converter 113 operates with the signal of the frequency f 0 output from the frequency divider 103, samples the signal 1 out of the output signal of the second power divider 105, and outputs the signal 2 and the signal 3. Is undersampled and a signal is output to the third delay unit 114. An output signal of the second AD converter 113 is shown in FIG. The phase of the output signal of the second AD converter 113 is the same for all signals compared to FIG.
　信号分離部１１５で信号を分離するためには，第１の遅延器１０９、第２の遅延器１１２、第３の遅延器１１４から信号分離部１１５へ入力する信号が時間的に一致しなければならない。そこで、信号分離部１１５へ入力する信号が時間的に一致するよう、第１の遅延器１０９、第２の遅延器１１２、第３の遅延器１１４の遅延量を決定する。そのため、第１の遅延器１０９、第２の遅延器１１２、第３の遅延器１１４の遅延量はそれぞれ同一ではない。第１の遅延器１０９、第２の遅延器１１２、第３の遅延器１１４から信号分離部１１５へ出力する信号は、それぞれ、図８、図１０、図１１と等しい。 In order to separate the signals by the signal separation unit 115, the signals input from the first delay unit 109, the second delay unit 112, and the third delay unit 114 to the signal separation unit 115 do not coincide with each other in time. Don't be. Therefore, the delay amounts of the first delay unit 109, the second delay unit 112, and the third delay unit 114 are determined so that the signals input to the signal separation unit 115 coincide with each other in time. Therefore, the delay amounts of the first delay device 109, the second delay device 112, and the third delay device 114 are not the same. The signals output from the first delay unit 109, the second delay unit 112, and the third delay unit 114 to the signal separation unit 115 are the same as those in FIGS. 8, 10, and 11, respectively.
　次に、実施の形態１の受信装置における信号分離部１１５の動作を説明する。
　移相器２０１は、第１の遅延器１０９の出力信号の位相を９０°遅らせ、加算器２０２及び信号処理部３へ信号を出力する。移相器２０１の出力信号を図１２に示す。信号１の位相は図６と比較して１８０°遅れている。加算器２０２は、第３の遅延器１１４及び移相器２０１の出力信号を加算し、分離器２０３へ信号を出力する。移相器２０１の出力信号である信号１は、第３の遅延器１１４の出力信号である信号１と比較して位相が１８０°遅れている。そのため、移相器２０１の出力信号と第３の遅延器１１４の出力信号を加算器２０２で加算すると信号１は打ち消され、信号２及び信号３が加算器２０２から出力する。加算器２０２の出力信号を図１３に示す。 Next, the operation of signal separation section 115 in the receiving apparatus of Embodiment 1 will be described.
The phase shifter 201 delays the phase of the output signal of the first delay unit 109 by 90 °, and outputs a signal to the adder 202 and the signal processing unit 3. The output signal of the phase shifter 201 is shown in FIG. The phase of the signal 1 is delayed by 180 ° compared to FIG. The adder 202 adds the output signals of the third delay unit 114 and the phase shifter 201 and outputs a signal to the separator 203. The signal 1 that is the output signal of the phase shifter 201 is 180 degrees out of phase with the signal 1 that is the output signal of the third delay device 114. Therefore, when the output signal of the phase shifter 201 and the output signal of the third delay unit 114 are added by the adder 202, the signal 1 is canceled and the signal 2 and the signal 3 are output from the adder 202. The output signal of the adder 202 is shown in FIG.
　分離器２０３は、図１０及び図１３でそれぞれ示した第２の遅延器１１２及び加算器２０２の出力信号を用いて、信号の分離を行い信号処理部３へ信号を出力する。信号の分離は、ウェーバーアーキテクチャーまたはハートレーアーキテクチャーを含むその他の周知の技術を用いて実行される。図４で示した分離器２０３の出力１から信号２、出力２から信号３が出力する。分離器２０３の出力１及び出力２の信号をそれぞれ図１４及び図１５で示す。 The separator 203 separates signals using the output signals of the second delay unit 112 and the adder 202 shown in FIGS. 10 and 13, respectively, and outputs a signal to the signal processing unit 3. Signal separation is performed using other well known techniques including Weber architecture or Hartley architecture. A signal 2 is output from the output 1 of the separator 203 shown in FIG. 4 and a signal 3 is output from the output 2. The output 1 and output 2 signals of the separator 203 are shown in FIGS. 14 and 15, respectively.
　図１２、図１４、図１５の結果より、実施の形態１によれば、周波数の異なる三つの信号を分離し、信号処理部３へ出力することができる。なお、これらの図に示すように、信号１と比較して信号２及び信号３は位相が１８０°異なっているが、これは、信号処理部３において信号１の位相を１８０°回転させることにより復調することができる。また、図１４中の信号２の向きは図６と比べると左右反転したままであるが、これも信号処理部３で波形の左右を戻すことができ、復調することができる。 12, 14, and 15, according to the first embodiment, three signals having different frequencies can be separated and output to the signal processing unit 3. As shown in these figures, the signal 2 and the signal 3 are 180 degrees out of phase with respect to the signal 1, but this is because the signal processing unit 3 rotates the phase of the signal 1 by 180 degrees. It can be demodulated. Further, the direction of the signal 2 in FIG. 14 is left and right inverted as compared with FIG. 6, but this can also be restored by the signal processing unit 3 and demodulated.
　また、移相器２０１は、２７０°移相器としてもよい。その場合は、加算器２０２を減算器に変更することにより同様の効果を得ることができる。 Further, the phase shifter 201 may be a 270 ° phase shifter. In that case, the same effect can be obtained by changing the adder 202 to a subtracter.
　さらに、実施の形態１では、例として、分離器２０３の出力１から信号２、出力２から信号３を出力しているが、出力１から信号３、出力２から信号２を出力するように分離器２０３を構成してもよい。すなわち、図４で示した減算器３０２と加算器３０３を入れ替えることにより出力される信号が逆となる。 Further, in the first embodiment, as an example, the signal 2 is output from the output 1 of the separator 203 and the signal 3 is output from the output 2, but the output 1 is separated so that the signal 3 is output and the signal 2 is output from the output 2. The vessel 203 may be configured. That is, the signal output by replacing the subtracter 302 and the adder 303 shown in FIG. 4 is reversed.
　以上説明したように、実施の形態１の受信装置によれば、周波数の異なる三つのアナログ信号をサンプリングする第１のＡＤ変換器及び第２のＡＤ変換器と、第１のＡＤ変換器の出力を低域通過させる低域通過フィルタと、第１のＡＤ変換器の出力を高域通過させる高域通過フィルタと、低域通過フィルタ及び高域通過フィルタの出力信号を１／２の周波数とする第１の間引き処理器及び第２の間引き処理器と、第１の間引き処理器の出力信号と第２の間引き処理器の出力信号と第２のＡＤ変換器の出力信号とを用いて演算を行い、周波数の異なる三つのアナログ信号に対応した三つの信号を分離して出力する信号分離部とを備え、第２のＡＤ変換器のサンプリング周波数を第１のＡＤ変換器のサンプリング周波数の１／２とし、かつ、第１のＡＤ変換器に供給するサンプリング信号と第２のＡＤ変換器のサンプリング信号とを９０゜の位相差とすると共に、第１のＡＤ変換器及び第２のＡＤ変換器のサンプリング周波数を、三つのアナログ信号の周波数帯域と重ならない周波数に設定するようにしたので、三つのアナログ信号を受信した場合でも信号を分離することができる。 As described above, according to the receiving apparatus of the first embodiment, the first AD converter and the second AD converter that sample three analog signals having different frequencies, and the output of the first AD converter. The low-pass filter that passes the low-pass signal, the high-pass filter that passes the output of the first AD converter high-pass, and the output signals of the low-pass filter and the high-pass filter are ½ the frequency. Calculation is performed using the first thinning processor and the second thinning processor, the output signal of the first thinning processor, the output signal of the second thinning processor, and the output signal of the second AD converter. And a signal separation unit that separates and outputs three signals corresponding to three analog signals having different frequencies, and the sampling frequency of the second AD converter is set to 1 / of the sampling frequency of the first AD converter. 2 and the second The sampling signal supplied to the AD converter and the sampling signal of the second AD converter have a phase difference of 90 °, and the sampling frequencies of the first AD converter and the second AD converter are set to three Since the frequency is set so as not to overlap with the frequency band of the analog signal, the signal can be separated even when three analog signals are received.
　また、実施の形態１の受信装置によれば、信号分離部は、第１の間引き処理器の出力を９０゜移相する移相器と、移相器の出力信号と第２のＡＤ変換器の出力信号とを加算する加算器と、第２の間引き処理器の出力信号と加算器の出力信号とを入力して、二つの分離信号を出力する分離器とを備え、移相器の出力信号と分離器の二つの分離信号とを三つの信号として出力するようにしたので、三つのアナログ信号を受信した場合でも信号を分離することができる。 Further, according to the receiving apparatus of the first embodiment, the signal separation unit includes a phase shifter that shifts the output of the first decimation processor by 90 °, an output signal of the phase shifter, and the second AD converter. And an adder that adds the output signals of the second decimation processor and an output signal of the adder, and outputs two separated signals, the output of the phase shifter Since the signal and the two separated signals of the separator are output as three signals, the signals can be separated even when three analog signals are received.
　また、実施の形態１の受信装置によれば、信号分離部は、第１の間引き処理器の出力を２７０゜移相する移相器と、移相器の出力信号と前記第２のＡＤ変換器の出力信号とを減算する減算器と、第２の間引き処理器の出力信号と減算器の出力信号とを入力して、二つの分離信号を出力する分離器とを備え、移相器の出力信号と分離器の二つの分離信号とを三つの信号として出力するようにしたので、三つのアナログ信号を受信した場合でも信号を分離することができる。 Further, according to the receiving apparatus of the first embodiment, the signal separation unit includes a phase shifter that shifts the output of the first decimation processor by 270 °, the output signal of the phase shifter, and the second AD conversion. A subtractor for subtracting the output signal of the counter, and a separator for inputting the output signal of the second decimation processor and the output signal of the subtractor and outputting two separated signals, Since the output signal and the two separated signals of the separator are output as three signals, the signals can be separated even when three analog signals are received.
　また、実施の形態１の受信装置によれば、第１の間引き処理器の出力を遅延させる第１の遅延器と、第２の間引き処理器の出力を遅延させる第２の遅延器と、第２のＡＤ変換器の出力を遅延させる第３の遅延器とを備え、これら第１の遅延器、第２の遅延器及び第３の遅延器の遅延量を、第１の間引き処理器から出力された信号と、第２の遅延器から出力された信号と、第２のＡＤ変換器から出力された信号とが同じタイミングで信号分離部に入力される値としたので、信号分離部に入力される信号が時間的に同じものとなり、信号分離部でタイミングを合わせる必要がない。 Further, according to the receiving apparatus of the first embodiment, the first delay device that delays the output of the first decimation processor, the second delay device that delays the output of the second decimation processor, A third delay unit that delays the output of the second AD converter, and outputs the delay amounts of the first delay unit, the second delay unit, and the third delay unit from the first decimation processor The signal output from the second delay unit and the signal output from the second AD converter are input to the signal separation unit at the same timing. The signals to be processed are the same in time, and there is no need to match the timing in the signal separation unit.
実施の形態２．
　実施の形態１では、第２の電力分配器１０５に入力する周波数の異なる三つのアナログ信号を分離する構成について説明した。実施の形態２では、第２の電力分配器１０５に入力する周波数の異なる四つのアナログ信号を分離する構成について説明する。 Embodiment 2. FIG.
In the first embodiment, the configuration in which three analog signals having different frequencies input to the second power distributor 105 are separated has been described. In the second embodiment, a configuration in which four analog signals having different frequencies input to the second power distributor 105 are separated will be described.
　図１６は、実施の形態２のサンプリング回路２３ａの構成図である。また、図１７は、図１６に示す信号分離部１１５ａの構成図である。なお、実施の形態２の受信装置が適用される受信機の構成については図１に示した実施の形態１と同様である。 FIG. 16 is a configuration diagram of the sampling circuit 23a of the second embodiment. FIG. 17 is a configuration diagram of the signal separation unit 115a shown in FIG. The configuration of the receiver to which the receiving apparatus of the second embodiment is applied is the same as that of the first embodiment shown in FIG.
　まず、サンプリング回路２３ａにおいて、実施の形態１と異なる構成について説明する。実施の形態２のサンプリング回路２３ａでは、第２の電力分配器１０５と第２のＡＤ変換器１１３との間に第１のＬＰＦ１１６を設ける。第１のＬＰＦ１１６は、第２の電力分配器１０５が出力した信号の内、特定の周波数以下の周波数帯域を通過させ、特定の周波数以上の周波数帯域を反射させる回路である。例えば、チップインダクタ、チップキャパシタ等を用いて実装される。第１のＬＰＦ１１６は、第２の電力分配器１０５と第２のＡＤ変換器１１３に接続され、第２の電力分配器１０５が出力した信号の内、特定の周波数以下の周波数帯域を通過させ、第２のＡＤ変換器１１３へ出力する。サンプリング回路２３ａにおける信号分離部１１５ａを除くその他の構成については図２に示した実施の形態１の構成と同様であるため、対応する部分に同一符号を付してその説明を省略する。なお、実施の形態２では、ＬＰＦ１０７を第１のＬＰＦ１１６と区別するために第２のＬＰＦ１０７として説明する。 First, a configuration different from that of the first embodiment in the sampling circuit 23a will be described. In the sampling circuit 23 a according to the second embodiment, the first LPF 116 is provided between the second power distributor 105 and the second AD converter 113. The first LPF 116 is a circuit that passes a frequency band equal to or lower than a specific frequency and reflects a frequency band equal to or higher than a specific frequency among signals output from the second power distributor 105. For example, it is mounted using a chip inductor, a chip capacitor, or the like. The first LPF 116 is connected to the second power divider 105 and the second AD converter 113, and passes a frequency band equal to or lower than a specific frequency among the signals output from the second power divider 105, Output to the second AD converter 113. Since the configuration other than the signal separation unit 115a in the sampling circuit 23a is the same as that of the first embodiment shown in FIG. 2, the same reference numerals are given to the corresponding portions, and the description thereof is omitted. In the second embodiment, the LPF 107 is described as the second LPF 107 in order to distinguish it from the first LPF 116.
　次に、信号分離部１１５ａにおいて、実施の形態１の信号分離部１１５と異なる構成について説明する。実施の形態２の信号分離部１１５ａでは、実施の形態１の加算器２０２を削除し、新たに、第２の加算器４０１、第１の減算器４０２、第２の減算器４０３、第１の加算器４０４、第３の減算器４０５を設ける。第２の加算器４０１は、移相器２０１が出力した信号と第３の減算器４０５が出力した信号を加算する回路である。例えば、ＦＰＧＡの論理回路で構成される。第２の加算器４０１は、移相器２０１と第３の減算器４０５と信号処理部３に接続され、移相器２０１が出力した信号と第３の減算器４０５が出力した信号を加算し信号処理部３へ出力する。 Next, a configuration of the signal separation unit 115a that is different from the signal separation unit 115 of the first embodiment will be described. In the signal separation unit 115a of the second embodiment, the adder 202 of the first embodiment is deleted, and a second adder 401, a first subtracter 402, a second subtractor 403, a first An adder 404 and a third subtracter 405 are provided. The second adder 401 is a circuit that adds the signal output from the phase shifter 201 and the signal output from the third subtractor 405. For example, it is configured with an FPGA logic circuit. The second adder 401 is connected to the phase shifter 201, the third subtracter 405, and the signal processing unit 3, and adds the signal output from the phase shifter 201 and the signal output from the third subtractor 405. Output to the signal processing unit 3.
　第１の減算器４０２は、第３の遅延器１１４が出力した信号と分離器２０３が出力した信号を減算する回路である。例えば、ＦＰＧＡの論理回路で構成される。第１の減算器４０２は、第３の遅延器１１４と分離器２０３と第１の加算器４０４と信号処理部３に接続され、第３の遅延器１１４が出力した信号と分離器２０３が出力した信号を減算し第１の加算器４０４及び信号処理部３へ出力する。 The first subtractor 402 is a circuit that subtracts the signal output from the third delay unit 114 and the signal output from the separator 203. For example, it is configured with an FPGA logic circuit. The first subtractor 402 is connected to the third delay unit 114, the separator 203, the first adder 404 and the signal processing unit 3, and the signal output from the third delay unit 114 and the separator 203 output The obtained signals are subtracted and output to the first adder 404 and the signal processing unit 3.
　第２の減算器４０３は、第３の遅延器１１４が出力した信号と分離器２０３が出力した信号を減算する回路である。例えば、ＦＰＧＡの論理回路で構成される。第２の減算器４０３は、第３の遅延器１１４と分離器２０３と第１の加算器４０４と信号処理部３に接続され、第３の遅延器１１４が出力した信号と分離器２０３が出力した信号を減算し第１の加算器４０４及び信号処理部３へ出力する。 The second subtractor 403 is a circuit that subtracts the signal output from the third delay unit 114 and the signal output from the separator 203. For example, it is configured with an FPGA logic circuit. The second subtractor 403 is connected to the third delay unit 114, the separator 203, the first adder 404, and the signal processing unit 3, and the signal output from the third delay unit 114 and the separator 203 output The obtained signals are subtracted and output to the first adder 404 and the signal processing unit 3.
　第１の加算器４０４は、第１の減算器４０２が出力した信号と第２の減算器４０３が出力した信号を加算する回路である。例えば、ＦＰＧＡの論理回路で構成される。第１の加算器４０４は、第１の減算器４０２と第２の減算器４０３と第３の減算器４０５に接続され、第１の減算器４０２が出力した信号と第２の減算器４０３が出力した信号を加算し第３の減算器４０５へ出力する。 The first adder 404 is a circuit that adds the signal output from the first subtractor 402 and the signal output from the second subtractor 403. For example, it is configured with an FPGA logic circuit. The first adder 404 is connected to the first subtractor 402, the second subtractor 403, and the third subtracter 405, and the signal output from the first subtractor 402 and the second subtractor 403 are connected to each other. The output signals are added and output to the third subtractor 405.
　第３の減算器４０５は、第３の遅延器１１４が出力した信号と第１の加算器４０４が出力した信号を減算する回路である。例えば、ＦＰＧＡの論理回路で構成される。第３の減算器４０５は、第３の遅延器１１４と第１の加算器４０４と第２の加算器４０１と信号処理部３に接続され、第３の遅延器１１４と第１の加算器４０４が出力した信号を減算し第２の加算器４０１及び信号処理部３へ出力する。 The third subtracter 405 is a circuit that subtracts the signal output from the third delay unit 114 and the signal output from the first adder 404. For example, it is configured with an FPGA logic circuit. The third subtractor 405 is connected to the third delay unit 114, the first adder 404, the second adder 401, and the signal processing unit 3, and the third delay unit 114 and the first adder 404 are connected. Is subtracted and output to the second adder 401 and the signal processing unit 3.
　次に、実施の形態２の受信装置におけるサンプリング回路２３ａの動作について説明する。なお、以下の説明では、実施の形態１と異なる動作を中心に説明する。
　第２の電力分配器１０５は、フィルタ２２が出力した信号の電力を２分配し、第１のＡＤ変換器１０６及び第１のＬＰＦ１１６に信号を出力する。第２の電力分配器１０５に入力する信号の一例を図１８に示す。第２の電力分配器１０５に入力する信号は、信号１、信号２、信号３、信号４と周波数の異なる四つの信号とする。また、信号１、信号２、信号３、信号４は、それぞれ０から１／２ｆ０、１／２ｆ０からｆ０、ｆ０から３／２ｆ０、３／２ｆ０から２ｆ０の間に存在する。 Next, the operation of the sampling circuit 23a in the receiving apparatus according to the second embodiment will be described. In the following description, operations different from those in the first embodiment will be mainly described.
The second power distributor 105 distributes the power of the signal output from the filter 22 into two, and outputs the signal to the first AD converter 106 and the first LPF 116. An example of a signal input to the second power distributor 105 is shown in FIG. Signals input to the second power distributor 105 are four signals having frequencies different from those of the signal 1, the signal 2, the signal 3, and the signal 4. Also, signal 1, signal 2, signal 3, and signal 4 exist between 0 to 1 / 2f 0 , 1 / 2f 0 to f 0 , f 0 to 3 / 2f 0 , and 3 / 2f 0 to 2f 0 , respectively. To do.
　第１のＡＤ変換器１０６は、移相器１０４が出力した周波数２ｆ０の信号で動作し、第２の電力分配器１０５の出力信号の内、信号１、信号２をサンプリングし、信号３、信号４をアンダーサンプリングし、第２のＬＰＦ１０７及びＨＰＦ１１０へ信号を出力する。第１のＡＤ変換器１０６の出力信号を図１９に示す。第１のＡＤ変換器１０６の出力信号の内、信号１及び信号２の位相は図１８と比較して９０°遅れており、信号３及び信号４の位相は２７０°遅れている。 The first AD converter 106 operates on the signal of the frequency 2f 0 output from the phase shifter 104, samples the signal 1 and the signal 2 among the output signals of the second power divider 105, The signal 4 is undersampled, and a signal is output to the second LPF 107 and the HPF 110. An output signal of the first AD converter 106 is shown in FIG. Among the output signals of the first AD converter 106, the phases of the signals 1 and 2 are delayed by 90 ° compared to FIG. 18, and the phases of the signals 3 and 4 are delayed by 270 °.
　第２のＬＰＦ１０７は、第１のＡＤ変換器１０６が出力した信号の内、０から１／２ｆ０の範囲の信号を通過させ、第１の間引き処理器１０８へ出力する。第２のＬＰＦ１０７の出力信号を図２０に示す。第１の間引き処理器１０８では実施の形態１と同様の動作を行う。また、ＨＰＦ１１０は実施の形態１と同様の動作を行う。ＨＰＦ１１０の出力信号を図２１に示す。さらに、第２の間引き処理器１１１では実施の形態１と同様の動作を行う。第２の間引き処理器１１１の出力信号を図２２に示す。 The second LPF 107 passes a signal in the range of 0 to 1 / 2f 0 among the signals output from the first AD converter 106 and outputs the signal to the first decimation processor 108. The output signal of the second LPF 107 is shown in FIG. The first thinning processor 108 performs the same operation as in the first embodiment. The HPF 110 performs the same operation as in the first embodiment. The output signal of the HPF 110 is shown in FIG. Further, the second thinning processor 111 performs the same operation as in the first embodiment. The output signal of the second thinning processor 111 is shown in FIG.
　第１のＬＰＦ１１６は、第２の電力分配器１０５が出力した信号の内、０から３／２ｆ０の範囲の信号を通過させ、第２のＡＤ変換器１１３へ出力する。第１のＬＰＦ１１６の出力信号を図２３に示す。第２のＡＤ変換器１１３は、２分周器１０３が出力した周波数ｆ０の信号で動作し、第２の電力分配器１０５の出力信号の内、信号１をサンプリングし、信号２、信号３をアンダーサンプリングし、第３の遅延器１１４へ信号を出力する。第２のＡＤ変換器１１３の出力信号を図２４に示す。第２のＡＤ変換器１１３の出力信号の位相は、図１８と比較していずれの信号も位相は等しい。 The first LPF 116 passes a signal in the range of 0 to 3 / 2f 0 among the signals output from the second power distributor 105 and outputs the signal to the second AD converter 113. The output signal of the first LPF 116 is shown in FIG. The second AD converter 113 operates with the signal of the frequency f 0 output from the frequency divider 103, samples signal 1 out of the output signal of the second power divider 105, and outputs signal 2 and signal 3. Is undersampled and a signal is output to the third delay unit 114. The output signal of the second AD converter 113 is shown in FIG. The phase of the output signal of the second AD converter 113 is the same for all signals compared to FIG.
　第１の遅延器１０９、第２の遅延器１１２及び第３の遅延器１１４は実施の形態１と同様に動作する。 The first delay device 109, the second delay device 112, and the third delay device 114 operate in the same manner as in the first embodiment.
　次に、実施の形態２の信号分離部１１５ａの動作について説明する。
　移相器２０１は、第１の遅延器１０９の出力信号の位相を９０°遅らせ、第２の加算器４０１へ信号を出力する。移相器２０１の出力信号を図２５に示す。信号１の位相は図１８と比較して１８０°遅れており、信号４は同相である。 Next, the operation of the signal separation unit 115a according to the second embodiment will be described.
The phase shifter 201 delays the phase of the output signal of the first delay unit 109 by 90 ° and outputs a signal to the second adder 401. The output signal of the phase shifter 201 is shown in FIG. The phase of signal 1 is 180 ° behind that of FIG. 18, and signal 4 is in phase.
　分離器２０３は、図２２及び図２４でそれぞれ示した第２の遅延器１１２及び第３の遅延器１１４の出力信号を用いて、信号の分離を行い、第１の減算器４０２及び第２の減算器４０３へ信号を出力する。信号の分離は、ウェーバーアーキテクチャーまたはハートレーアーキテクチャーを含む、その他の周知の技術を用いて実行される。図１７で示した分離器２０３の出力１から信号１及び信号２、出力２から信号１及び信号３を出力する。分離器２０３の出力１及び出力２の信号をそれぞれ図２６及び図２７で示す。 The separator 203 performs signal separation using the output signals of the second delay unit 112 and the third delay unit 114 shown in FIGS. 22 and 24, respectively, and performs the first subtractor 402 and the second subtractor 402. A signal is output to the subtracter 403. Signal separation is performed using other well-known techniques, including Weber architecture or Hartley architecture. The signal 1 and the signal 2 are output from the output 1 of the separator 203 shown in FIG. 17, and the signal 1 and the signal 3 are output from the output 2. The output 1 and output 2 signals of the separator 203 are shown in FIGS. 26 and 27, respectively.
　第１の減算器４０２は、図２４と図２６でそれぞれ示した第３の遅延器１１４の出力信号と、分離器２０３における出力１の分離信号との減算を行い、その出力信号を信号処理部３及び第１の加算器４０４へ出力する。第１の減算器４０２の出力信号を図２８に示す。 The first subtractor 402 subtracts the output signal of the third delay unit 114 shown in FIGS. 24 and 26 and the separated signal of the output 1 in the separator 203, and uses the output signal as a signal processing unit. 3 and the first adder 404. The output signal of the first subtractor 402 is shown in FIG.
　第２の減算器４０３は、図２４と図２７でそれぞれ示した第３の遅延器１１４の出力信号と、分離器２０３における出力２の分離信号との減算を行い、その出力を信号処理部３及び第１の加算器４０４へ信号を出力する。第２の減算器４０３の出力信号を図２９に示す。 The second subtracter 403 performs subtraction between the output signal of the third delay unit 114 shown in FIGS. 24 and 27 and the output 2 separation signal in the separator 203, and outputs the output to the signal processing unit 3. And a signal is output to the first adder 404. The output signal of the second subtractor 403 is shown in FIG.
　第１の加算器４０４は、図２８と図２９でそれぞれ示した第１の減算器４０２の出力信号と第２の減算器４０３の出力信号とを加算し、第３の減算器４０５へ信号を出力する。第１の加算器４０４の出力信号を図３０に示す。 The first adder 404 adds the output signal of the first subtractor 402 and the output signal of the second subtractor 403 shown in FIGS. 28 and 29, respectively, and sends the signal to the third subtracter 405. Output. The output signal of the first adder 404 is shown in FIG.
　第３の減算器４０５は、図２４と図３０でそれぞれ示した第３の遅延器１１４及の出力信号と第１の加算器４０４の出力信号とを減算し、その出力信号を信号処理部３へ出力する。第３の減算器４０５の出力信号を図３１に示す。 The third subtracter 405 subtracts the output signal of the third delay unit 114 and the output signal of the first adder 404 shown in FIGS. 24 and 30, respectively, and outputs the output signal to the signal processing unit 3. Output to. The output signal of the third subtractor 405 is shown in FIG.
　第２の加算器４０１は、図２５と図３１でそれぞれ示した移相器２０１の出力信号と第３の減算器４０５の出力信号とを加算し、その出力信号を信号処理部３へ出力する。第２の加算器４０１の出力信号を図３２に示す。 The second adder 401 adds the output signal of the phase shifter 201 and the output signal of the third subtractor 405 shown in FIGS. 25 and 31 respectively, and outputs the output signal to the signal processing unit 3. . The output signal of the second adder 401 is shown in FIG.
　図２８、図２９、図３１、図３２の結果より、実施の形態２によれば、周波数の異なる四つの信号を分離し、信号処理部３へ出力することができる。 28, 29, 31 and 32, according to the second embodiment, four signals having different frequencies can be separated and output to the signal processing unit 3.
　なお、移相器２０１は、２７０°移相器としてもよい。その場合は、第２の加算器４０１を減算器に変更することにより同様の効果を得ることができる。 Note that the phase shifter 201 may be a 270 ° phase shifter. In that case, the same effect can be obtained by changing the second adder 401 to a subtracter.
　なお、第１のＬＰＦ１１６は、特定の一つの信号を除去するためのノッチフィルタに変更してもよい。上記例ではノッチフィルタとした場合、信号４の帯域を阻止することになる。 Note that the first LPF 116 may be changed to a notch filter for removing one specific signal. In the above example, when the notch filter is used, the band of the signal 4 is blocked.
　以上説明したように、実施の形態２の受信装置によれば、周波数の異なる四つのアナログ信号をサンプリングする第１のＡＤ変換器と、四つのアナログ信号を低域通過させる第１の低域通過フィルタと、第１の低域通過フィルタの出力信号をサンプリングする第２のＡＤ変換器と、第１のＡＤ変換器の出力を低域通過させる第２の低域通過フィルタと、第１のＡＤ変換器の出力を高域通過させる高域通過フィルタと、低域通過フィルタ及び高域通過フィルタの出力信号を１／２の周波数とする第１の間引き処理器及び第２の間引き処理器と、第１の間引き処理器の出力信号と第２の間引き処理器の出力信号と第２のＡＤ変換器の出力信号とを用いて演算を行い、周波数の異なる四つのアナログ信号に対応した四つの信号を分離して出力する信号分離部とを備え、第２のＡＤ変換器のサンプリング周波数を第１のＡＤ変換器のサンプリング周波数の１／２とし、かつ、第１のＡＤ変換器に供給するサンプリング信号と第２のＡＤ変換器のサンプリング信号とを９０゜の位相差とすると共に、第１のＡＤ変換器及び第２のＡＤ変換器のサンプリング周波数を、四つのアナログ信号の周波数帯域と重ならない周波数に設定するようにしたので、四つのアナログ信号を受信した場合でも信号を分離することができる。 As described above, according to the receiving apparatus of the second embodiment, the first AD converter that samples four analog signals having different frequencies and the first low-pass signal that allows the four analog signals to pass through the low-frequency signal. A filter, a second AD converter that samples the output signal of the first low-pass filter, a second low-pass filter that passes the output of the first AD converter through a low-pass, and a first AD A high-pass filter that passes the output of the converter through a high-pass, a first decimation processor and a second decimation processor that use an output signal of the low-pass filter and the high-pass filter as a half frequency, Four signals corresponding to four analog signals having different frequencies are calculated using the output signal of the first decimation processor, the output signal of the second decimation processor, and the output signal of the second AD converter. Is output separately. And a sampling signal supplied to the first AD converter and the second AD, the sampling frequency of the second AD converter is set to ½ of the sampling frequency of the first AD converter. The sampling signal of the converter is set to a phase difference of 90 °, and the sampling frequencies of the first AD converter and the second AD converter are set to frequencies that do not overlap with the frequency bands of the four analog signals. Therefore, even when four analog signals are received, the signals can be separated.
　また、実施の形態２の受信装置によれば、信号分離部は、第１の間引き処理器の出力を９０゜移相する移相器と、第２の間引き処理器の出力信号と第２のＡＤ変換器１１３の出力信号とを入力して、第１及び第２の分離信号を出力する分離器と、第１の分離信号と第２のＡＤ変換器の出力信号とを減算する第１の減算器と、第２の分離信号と第２のＡＤ変換器の出力信号とを減算する第２の減算器と、第１の減算器の出力信号と第２の減算器の出力信号とを加算する第１の加算器と、第１の加算器の出力信号と第２のＡＤ変換器の出力信号とを減算する第３の減算器と、移相器の出力信号と第３の減算器の出力信号とを加算する第２の加算器とを備え、第２の加算器の出力信号と、第１の減算器の出力信号と、第２の減算器の出力信号と、第３の減算器の出力信号とを、四つの信号として出力するようにしたので、四つのアナログ信号を受信した場合でも信号を分離することができる。 Further, according to the receiving apparatus of the second embodiment, the signal separation unit includes a phase shifter that shifts the output of the first decimation processor by 90 °, the output signal of the second decimation processor, and the second signal. A separator that inputs the output signal of the AD converter 113 and outputs the first and second separated signals, and a first that subtracts the first separated signal and the output signal of the second AD converter. A subtracter, a second subtractor for subtracting the second separated signal and the output signal of the second AD converter, and the output signal of the first subtracter and the output signal of the second subtractor are added. The first adder, the third subtracter for subtracting the output signal of the first adder and the output signal of the second AD converter, the output signal of the phase shifter and the third subtractor A second adder for adding the output signal, an output signal of the second adder, an output signal of the first subtractor, an output signal of the second subtractor, 3 of the output signal of the subtractor, since the output as four signal, it is possible to separate the signals even in the case of receiving the four analog signals.
実施の形態３．
　実施の形態３では、アンテナ１で受信したアナログ信号を周波数変換した後にサンプリング回路２３へ出力する構成について説明する。 Embodiment 3 FIG.
In the third embodiment, a configuration in which an analog signal received by the antenna 1 is frequency-converted and then output to the sampling circuit 23 will be described.
　図３３は、実施の形態３の受信装置が適用される受信機の構成図である。
　受信機は、アンテナ１とアナログ回路部２と信号処理部３とを備え、アナログ回路部２は、増幅器２１、フィルタ２２、サンプリング回路２３、周波数変換器２４を備える。実施の形態３では、フィルタ２２とサンプリング回路２３との間に周波数変換器２４を設けた点が実施の形態１とは異なる。 FIG. 33 is a configuration diagram of a receiver to which the receiving apparatus of the third embodiment is applied.
The receiver includes an antenna 1, an analog circuit unit 2, and a signal processing unit 3, and the analog circuit unit 2 includes an amplifier 21, a filter 22, a sampling circuit 23, and a frequency converter 24. The third embodiment is different from the first embodiment in that a frequency converter 24 is provided between the filter 22 and the sampling circuit 23.
　周波数変換器２４は、フィルタ２２が出力したアナログ信号の周波数を低い周波数に変換する回路である。例えば、ミクサ、フィルタ、ＩＣのＰＬＬで構成される。周波数変換器２４は、フィルタ２２が出力したアナログ信号を低い周波数に変換しサンプリング回路２３へ信号を出力する。サンプリング回路２３の構成は図２に示した実施の形態１の構成と同様であるが、第２の電力分配器１０５に対して入力される信号が周波数変換器２４の出力信号である点が実施の形態１とは異なる。 The frequency converter 24 is a circuit that converts the frequency of the analog signal output from the filter 22 to a low frequency. For example, it is composed of a mixer, a filter, and an IC PLL. The frequency converter 24 converts the analog signal output from the filter 22 into a low frequency and outputs the signal to the sampling circuit 23. The configuration of the sampling circuit 23 is the same as that of the first embodiment shown in FIG. 2 except that the signal input to the second power distributor 105 is the output signal of the frequency converter 24. This is different from the first form.
　このように、実施の形態３によれば、アンテナ１で受信したアナログ信号を周波数変換器２４で低い周波数に変換した後サンプリングするようにしたので、次のような効果がある。
　例えば、受信機が携帯電話であった場合、受信する周波数は一般的に１ＧＨｚ～２ＧＨｚである。その周波数でＡＤ変換器に直接信号を入力することも可能ではあるが、ＡＤ変換器に入力する周波数が高くなるほどＡＤ変換器のコストが高くなる。そのため、受信した信号をＡＤ変換器に入力する前に周波数変換器２４で数ＭＨｚ～数十ＭＨｚまで予め下げておき、その後、サンプリング回路２３に信号を入力する。これにより、ＡＤ変換器のコストを下げることができる。 As described above, according to the third embodiment, since the analog signal received by the antenna 1 is sampled after being converted to a low frequency by the frequency converter 24, the following effects are obtained.
For example, when the receiver is a mobile phone, the receiving frequency is generally 1 GHz to 2 GHz. Although it is possible to input a signal directly to the AD converter at that frequency, the higher the frequency input to the AD converter, the higher the cost of the AD converter. Therefore, before the received signal is input to the AD converter, the frequency converter 24 lowers it in advance from several MHz to several tens of MHz, and then the signal is input to the sampling circuit 23. As a result, the cost of the AD converter can be reduced.
　なお、上記例は実施の形態１の構成に対して周波数変換器２４を設けたが、実施の形態２の構成に対して適用してもよい。 In the above example, the frequency converter 24 is provided for the configuration of the first embodiment, but may be applied to the configuration of the second embodiment.
　以上説明したように、実施の形態３の受信装置によれば、周波数の異なる三つのアナログ信号を入力信号として、入力信号の周波数を低い周波数に変換して出力信号とする周波数変換器を備え、第１のＡＤ変換器及び第２のＡＤ変換器は、周波数変換器の出力信号をサンプリングするようにしたので、対象となる信号の周波数を低くすることができるため、受信装置としての低コスト化を図ることができる。 As described above, according to the receiving apparatus of the third embodiment, the three analog signals having different frequencies are used as input signals, and the frequency converter is provided that converts the frequency of the input signal to a low frequency to be an output signal, Since the first AD converter and the second AD converter sample the output signal of the frequency converter, the frequency of the target signal can be lowered, so that the cost of the receiving apparatus can be reduced. Can be achieved.
　なお、本願発明はその発明の範囲内において、各実施の形態の自由な組み合わせ、あるいは各実施の形態の任意の構成要素の変形、もしくは各実施の形態において任意の構成要素の省略が可能である。 In the present invention, within the scope of the invention, any combination of the embodiments, or any modification of any component in each embodiment, or omission of any component in each embodiment is possible. .
　以上のように、この発明に係る受信装置は、周波数の異なる複数のアナログ信号をデジタル信号に変換して信号処理を行う構成に関するものであり、マルチチャネル受信機に用いるのに適している。 As described above, the receiving apparatus according to the present invention relates to a configuration for performing signal processing by converting a plurality of analog signals having different frequencies into digital signals, and is suitable for use in a multi-channel receiver.
　１　アンテナ、２　アナログ回路部、３　信号処理部、２１　増幅器、２２　フィルタ、２３，２３ａ　サンプリング回路、２４　周波数変換器、１０１　発振器、１０２　第１の電力分配器、１０３　２分周器、１０４，２０１，３０１　移相器、１０５　第２の電力分配器、１０６　第１のＡＤ変換器、１０７　ＬＰＦ（第２のＬＰＦ）、１０８　第１の間引き処理器、１０９　第１の遅延器、１１０　ＨＰＦ、１１１　第２の間引き処理器、１１２　第２の遅延器、１１３　第２のＡＤ変換器、１１４　第３の遅延器、１１５，１１５ａ　信号分離部、１１６　第１のＬＰＦ、２０２，３０３　加算器、２０３　分離器、３０２　減算器、４０１　第２の加算器、４０２　第１の減算器、４０３　第２の減算器、４０４　第１の加算器、４０５　第３の減算器。 1 antenna, 2 analog circuit unit, 3 signal processing unit, 21 amplifier, 22 filter, 23, 23a sampling circuit, 24 frequency converter, 101 oscillator, 102 first power distributor, 103/2 divider, 104, 201 , 301 phase shifter, 105 second power distributor, 106 first AD converter, 107 LPF (second LPF), 108 first decimation processor, 109 first delay, 110 HPF, 111 Second decimation processor, 112 second delay unit, 113 second AD converter, 114 third delay unit, 115, 115a signal separation unit, 116 first LPF, 202, 303 adder, 203 separation , 302 subtractor, 401 second adder, 402 first subtractor, 403 second subtractor, 404 first adder , 405 third subtractor.

Claims (7)

  1. 　周波数の異なる三つのアナログ信号をサンプリングする第１のＡＤ変換器及び第２のＡＤ変換器と、
    　前記第１のＡＤ変換器の出力を低域通過させる低域通過フィルタと、
    　前記第１のＡＤ変換器の出力を高域通過させる高域通過フィルタと、
    　前記低域通過フィルタ及び前記高域通過フィルタの出力信号を１／２の周波数とする第１の間引き処理器及び第２の間引き処理器と、
    　前記第１の間引き処理器の出力信号と前記第２の間引き処理器の出力信号と前記第２のＡＤ変換器の出力信号とを用いて演算を行い、前記周波数の異なる三つのアナログ信号に対応した三つの信号を分離して出力する信号分離部とを備え、
    　前記第２のＡＤ変換器のサンプリング周波数を前記第１のＡＤ変換器のサンプリング周波数の１／２とし、かつ、前記第１のＡＤ変換器に供給するサンプリング信号と前記第２のＡＤ変換器のサンプリング信号とを９０゜の位相差とすると共に、これら第１のＡＤ変換器及び第２のＡＤ変換器のサンプリング周波数を、前記三つのアナログ信号の周波数帯域と重ならない周波数に設定することを特徴とする受信装置。     A first AD converter and a second AD converter that sample three analog signals having different frequencies;
    A low-pass filter that low-passes the output of the first AD converter;
    A high-pass filter that passes the output of the first AD converter through a high-pass,
    A first decimation processor and a second decimation processor that halves the output signal of the low-pass filter and the high-pass filter,
    Calculation is performed using the output signal of the first decimation processor, the output signal of the second decimation processor, and the output signal of the second AD converter, and supports three analog signals having different frequencies. A signal separation unit that separates and outputs the three signals,
    The sampling frequency of the second AD converter is ½ of the sampling frequency of the first AD converter, and the sampling signal supplied to the first AD converter and the second AD converter are The sampling signal has a phase difference of 90 °, and the sampling frequency of the first AD converter and the second AD converter is set to a frequency that does not overlap the frequency band of the three analog signals. A receiving device.
  2. 　前記信号分離部は、
    　前記第１の間引き処理器の出力を９０゜移相する移相器と、
    　前記移相器の出力信号と前記第２のＡＤ変換器の出力信号とを加算する加算器と、
    　前記第２の間引き処理器の出力信号と前記加算器の出力信号とを入力して、二つの分離信号を出力する分離器とを備え、
    　前記移相器の出力信号と前記分離器の二つの分離信号とを前記三つの信号として出力することを特徴とする請求項１記載の受信装置。     The signal separator is
    A phase shifter that shifts the output of the first decimation processor by 90 °;
    An adder for adding the output signal of the phase shifter and the output signal of the second AD converter;
    A separator that inputs an output signal of the second decimation processor and an output signal of the adder and outputs two separated signals;
    The receiving apparatus according to claim 1, wherein an output signal of the phase shifter and two separated signals of the separator are output as the three signals.
  3. 　前記信号分離部は、
    　前記第１の間引き処理器の出力を２７０゜移相する移相器と、
    　前記移相器の出力信号と前記第２のＡＤ変換器の出力信号とを減算する減算器と、
    　前記第２の間引き処理器の出力信号と前記減算器の出力信号とを入力して、二つの分離信号を出力する分離器とを備え、
    　前記移相器の出力信号と前記分離器の二つの分離信号とを前記三つの信号として出力することを特徴とする請求項１記載の受信装置。     The signal separator is
    A phase shifter that shifts the output of the first decimation processor by 270 °;
    A subtractor for subtracting the output signal of the phase shifter and the output signal of the second AD converter;
    A separator that inputs an output signal of the second decimation processor and an output signal of the subtractor and outputs two separated signals;
    The receiving apparatus according to claim 1, wherein an output signal of the phase shifter and two separated signals of the separator are output as the three signals.
  4. 　前記第１の間引き処理器の出力を遅延させる第１の遅延器と、前記第２の間引き処理器の出力を遅延させる第２の遅延器と、前記第２のＡＤ変換器の出力を遅延させる第３の遅延器とを備え、
    　これら第１の遅延器、第２の遅延器及び第３の遅延器の遅延量を、前記第１の間引き処理器から出力された信号と、前記第２の遅延器から出力された信号と、前記第２のＡＤ変換器から出力された信号とが同じタイミングで前記信号分離部に入力される値としたことを特徴とする請求項１記載の受信装置。     A first delay unit for delaying an output of the first decimation processor; a second delay unit for delaying an output of the second decimation processor; and an output of the second AD converter. A third delay device,
    The amount of delay of the first delay device, the second delay device, and the third delay device, the signal output from the first decimation processor, the signal output from the second delay device, The receiving apparatus according to claim 1, wherein the signal output from the second AD converter has a value input to the signal separation unit at the same timing.
  5. 　周波数の異なる四つのアナログ信号をサンプリングする第１のＡＤ変換器と、
    　前記四つのアナログ信号を低域通過させる第１の低域通過フィルタと、
    　前記第１の低域通過フィルタの出力信号をサンプリングする第２のＡＤ変換器と、
    　前記第１のＡＤ変換器の出力を低域通過させる第２の低域通過フィルタと、
    　前記第１のＡＤ変換器の出力を高域通過させる高域通過フィルタと、
    　前記低域通過フィルタ及び前記高域通過フィルタの出力信号を１／２の周波数とする第１の間引き処理器及び第２の間引き処理器と、
    　前記第１の間引き処理器の出力信号と前記第２の間引き処理器の出力信号と前記第２のＡＤ変換器の出力信号とを用いて演算を行い、前記周波数の異なる四つのアナログ信号に対応した四つの信号を分離して出力する信号分離部とを備え、
    　前記第２のＡＤ変換器のサンプリング周波数を前記第１のＡＤ変換器のサンプリング周波数の１／２とし、かつ、前記第１のＡＤ変換器に供給するサンプリング信号と前記第２のＡＤ変換器のサンプリング信号とを９０゜の位相差とすると共に、これら第１のＡＤ変換器及び第２のＡＤ変換器のサンプリング周波数を、前記四つのアナログ信号の周波数帯域と重ならない周波数に設定することを特徴とする受信装置。     A first AD converter that samples four analog signals having different frequencies;
    A first low-pass filter for low-passing the four analog signals;
    A second AD converter for sampling an output signal of the first low-pass filter;
    A second low-pass filter for low-passing the output of the first AD converter;
    A high-pass filter that passes the output of the first AD converter through a high-pass,
    A first decimation processor and a second decimation processor that halves the output signal of the low-pass filter and the high-pass filter,
    Calculation is performed using the output signal of the first decimation processor, the output signal of the second decimation processor, and the output signal of the second AD converter, and supports four analog signals having different frequencies. A signal separation unit that separates and outputs the four signals
    The sampling frequency of the second AD converter is ½ of the sampling frequency of the first AD converter, and the sampling signal supplied to the first AD converter and the second AD converter are The sampling signal has a phase difference of 90 °, and the sampling frequency of the first AD converter and the second AD converter is set to a frequency that does not overlap with the frequency bands of the four analog signals. A receiving device.
  6. 　前記信号分離部は、
    　前記第１の間引き処理器の出力を９０゜移相する移相器と、
    　前記第２の間引き処理器の出力信号と前記第２のＡＤ変換器１１３の出力信号とを入力して、第１及び第２の分離信号を出力する分離器と、
    　前記第１の分離信号と前記第２のＡＤ変換器の出力信号とを減算する第１の減算器と、
    　前記第２の分離信号と前記第２のＡＤ変換器の出力信号とを減算する第２の減算器と、
    　前記第１の減算器の出力信号と前記第２の減算器の出力信号とを加算する第１の加算器と、
    　前記第１の加算器の出力信号と前記第２のＡＤ変換器の出力信号とを減算する第３の減算器と、
    　前記移相器の出力信号と前記第３の減算器の出力信号とを加算する第２の加算器とを備え、
    　前記第２の加算器の出力信号と、前記第１の減算器の出力信号と、前記第２の減算器の出力信号と、前記第３の減算器の出力信号とを、前記四つの信号として出力することを特徴とする請求項５記載の受信装置。     The signal separator is
    A phase shifter that shifts the output of the first decimation processor by 90 °;
    A separator that inputs an output signal of the second decimation processor and an output signal of the second AD converter 113 and outputs first and second separation signals;
    A first subtractor for subtracting the first separated signal and the output signal of the second AD converter;
    A second subtractor for subtracting the second separated signal and the output signal of the second AD converter;
    A first adder for adding the output signal of the first subtracter and the output signal of the second subtractor;
    A third subtractor for subtracting the output signal of the first adder from the output signal of the second AD converter;
    A second adder for adding the output signal of the phase shifter and the output signal of the third subtractor;
    The output signal of the second adder, the output signal of the first subtractor, the output signal of the second subtractor, and the output signal of the third subtractor are used as the four signals. 6. The receiving apparatus according to claim 5, wherein the receiving apparatus outputs the received signal.
  7. 　前記周波数の異なる三つのアナログ信号を入力信号として、当該入力信号の周波数を低い周波数に変換して出力信号とする周波数変換器を備え、
    　前記第１のＡＤ変換器及び前記第２のＡＤ変換器は、前記周波数変換器の出力信号をサンプリングすることを特徴とする請求項１記載の受信装置。     A frequency converter comprising the three analog signals having different frequencies as input signals and converting the frequency of the input signals to a low frequency to be an output signal,
    The receiving apparatus according to claim 1, wherein the first AD converter and the second AD converter sample an output signal of the frequency converter.
PCT/JP2016/069622 2016-07-01 2016-07-01 Reception device WO2018003113A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002354056A (en) * 2001-05-25 2002-12-06 Toyota Central Res & Dev Lab Inc Receiver
JP2004096177A (en) * 2002-08-29 2004-03-25 Mitsubishi Heavy Ind Ltd Demodulator and receiver employing the same, on-vehicle device, and roadside device
JP2011526132A (en) * 2008-06-27 2011-09-29 エントロピック・コミュニケーションズ・インコーポレイテッド Direct orthogonal sampling apparatus and method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002354056A (en) * 2001-05-25 2002-12-06 Toyota Central Res & Dev Lab Inc Receiver
JP2004096177A (en) * 2002-08-29 2004-03-25 Mitsubishi Heavy Ind Ltd Demodulator and receiver employing the same, on-vehicle device, and roadside device
JP2011526132A (en) * 2008-06-27 2011-09-29 エントロピック・コミュニケーションズ・インコーポレイテッド Direct orthogonal sampling apparatus and method

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