WO2018000468A1

WO2018000468A1 - Timing controller and data updating method thereof, and liquid crystal display panel

Info

Publication number: WO2018000468A1
Application number: PCT/CN2016/090268
Authority: WO
Inventors: 谢剑军; 孙磊; 高剑
Original assignee: 深圳市华星光电技术有限公司
Priority date: 2016-07-01
Filing date: 2016-07-18
Publication date: 2018-01-04
Also published as: CN105976779B; CN105976779A

Abstract

Provided is a timing controller, comprising a timing control chip (100), a data memory (200), and a SPI bus (300). The SPI bus (300) comprises a first connecting end (301), a second connecting end (302), and a third connecting end (303). The first connecting end (301) is connected to the timing control chip (100). The second connecting end (302) is connected to the data memory (200). The third connecting end (303) is used to connect to a data burning fixture (400). The timing controller is characterized in that the timing control chip (100) is provided with a master mode unit (101), a slave mode unit (102), and a connection control unit (103). The connection control unit (103) is used to control the first connecting end (301) to be connected to the master mode unit (101) or the slave mode unit (102). When the first connecting end (301) is connected to the master mode unit (101), the timing control chip serves as a host of the data memory (200) and acquires data from the data memory (200). The invention further discloses a data updating method of the timing controller, and further discloses a liquid crystal display panel comprising the timing controller.

Description

Timing controller and data updating method thereof, liquid crystal display panel

Technical field

The present invention relates to the field of display technologies, and in particular, to a timing controller and a data updating method thereof, and to a liquid crystal display panel including the timing controller.

Background technique

Liquid crystal display (TFT-LCD) has the characteristics of small size, low power consumption, relatively low manufacturing cost and no radiation. It is dominant in the current flat panel display market. LCD monitors are widely used in various types of electronics. Devices, such as mobile phones, tablets, etc.

In the production process of the liquid crystal display panel, various defects are prone to occur, and some liquid crystal display panels are inevitably reworked. After rework, the relevant parameters need to be modified according to the characteristics of the liquid crystal display panel, such as in the timing controller. Drive data. As shown in FIG. 1, the timing controller 1 is provided with a timing control chip (TCON) 2 and a flash memory 3. The timing control chip 2 and the flash memory 3 pass through a SPI (Serial Peripheral Interface). Interface) Bus 4 connection. The flash memory 3 stores drive data, and the timing control chip 2 functions as a master, through which the drive data is acquired from the flash memory 3 as a slave. When it is necessary to modify the driving data, as shown in FIG. 1, the data burning fixture 5 needs to be connected to the SPI bus 4, and the data burning fixture 5 is used as the host end, and the new driving data is burned to the flash memory. 3. However, at this time, the SPI bus 4 is connected to two host terminals, that is, the timing control chip 2 and the data burning fixture 5, and when the data burning fixture 5 performs data reading and writing operations on the flash memory 3, it is simultaneously subjected to The influence of the timing control chip 2 on the host side causes a conflict, and data reading and writing to the flash memory 3 cannot be performed efficiently.

In the prior art, in order to solve the above problem, as shown in FIG. 1 , a switch chip (Switch IC) 6 is generally disposed at one end of the SPI bus 4 connected to the timing control chip 2, and the switch chip 6 is provided with an enabler. The pin En, the enable pin En is associated with the data burning fixture 5. When the SPI bus 4 is not connected to the data burning fixture 5, the switching chip 6 is in an on state, and the timing control chip 2 and the flash memory 3 are connected to each other; when the data burning fixture 5 is connected to the SPI bus 4, The trigger enable pin En controls the switch chip 6 to be disconnected, and the connection between the timing control chip 2 and the flash memory 3 is cut off. The data-recovering jig 5 can perform effective data reading and writing to the flash memory 3.

The above solutions mainly have the following problems: (1) The switching chip is added to the driving circuit, which complicates the peripheral circuit and increases the cost; (2) When the data is modified, the enable pin En and the data are enabled. The programming fixture is associated to control the switching chip to be turned on or off, which increases the complexity of the operation.

Summary of the invention

In view of this, the present invention provides a timing controller that solves the problem of conflicts between multiple host terminals when performing data update, avoids complicated peripheral circuit design, reduces cost, and when performing data update, The operation is simpler.

In order to achieve the above object, the present invention adopts the following technical solutions:

A timing controller includes a timing control chip and a data memory, wherein the timing control chip and the data memory are connected by an SPI bus, and the SPI bus includes a first connection end, a second connection end, and a third connection end The first connection end is connected to the timing control chip, the second connection end is connected to the data storage, and the third connection end is used to connect a data burning fixture; wherein the timing control chip Providing a main mode unit, a slave mode unit, and a connection control unit, the connection control unit configured to control the first connection end to be connected to the main mode unit or the slave mode unit; when the first connection end is connected to The main mode unit, the timing control chip as a host of the data memory acquires data from the data memory.

The third connection end is connected with a data burning jig for burning data to the data storage; when the data burning jig is burning data to the data storage, the connection control unit Controlling the first connection end to be connected to the slave mode unit.

Wherein, the data storage is a flash memory.

The timing control chip is further connected with a synchronous dynamic random access memory for storing data acquired by the timing control chip from the data memory.

The data update method of the timing controller as described above, comprising: controlling the first connection end to be connected to the slave mode unit, connecting a data burning fixture to the third connection end, and burning by the data Recording the fixture to burn the second data to be updated to the data storage; controlling the first connection end to be connected to the main mode unit, and removing the data burning fixture from the third connection end, by The timing control chip acquires the second data from the data memory.

The timing controller is configured to drive the display panel to display, wherein the second data is acquired in the following manner: the timing controller drives the display panel to display the first image according to the first data; and detects that the first image exists Defects; compensating the first data to eliminate defects existing in the first image, and obtaining the second data.

The present invention also provides a liquid crystal display panel comprising: a display panel; a source driver for providing a data signal to the display panel; and a gate driver for providing a scan signal to the display panel; And a timing controller for providing a timing control signal to the source driver and the gate driver, and transmitting a data signal to be displayed to the source driver.

The timing controller provided by the embodiment of the invention provides a main mode unit, a slave mode unit and a connection control unit in the timing control chip. When the data needs to be acquired from the data memory, the connection control unit controls the main mode unit to connect with the SPI bus. When the data is not required to be acquired from the data memory, the connection control unit controls the connection from the mode unit to the SPI bus, thereby avoiding the problem of conflicts between the plurality of host terminals during data update, avoiding complicated peripheral circuit design and reducing The cost. And when the data is updated, the operation is simpler and more flexible, and the stability of the data update is improved.

DRAWINGS

1 is a schematic structural diagram of a conventional timing controller;

2 is a schematic structural diagram of a liquid crystal display panel according to an embodiment of the present invention;

3 is a schematic structural diagram of a timing controller according to an embodiment of the present invention;

4 is a schematic flow chart of a data update method of a timing controller in an embodiment of the present invention;

FIG. 5 is a schematic flowchart of a method for acquiring second data in an embodiment of the present invention.

detailed description

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Examples of these preferred embodiments are illustrated in the drawings. The embodiments of the invention shown in the drawings and described in the drawings are merely exemplary, and the invention is not limited to the embodiments.

In this context, it is also to be noted that in order to avoid obscuring the invention by unnecessary detail, only the structures and/or processing steps closely related to the solution according to the invention are shown in the drawings, and the Other details that are not relevant to the present invention.

The embodiment of the present invention first provides a liquid crystal display panel. As shown in FIG. 2 , the liquid crystal display panel includes a display panel 10 , a source driver 20 , a gate driver 30 , and a timing controller 40 . Wherein, the display panel 10 is provided with criss-crossed data lines and a plurality of pixel units (not shown in the drawing) between the data lines and the scanning plane, and the source driver 20 passes through the data lines. Providing a data signal to the display panel 10, the gate driver 30 supplies a scan signal to the display panel 10 through a scan line, and the timing controller 40 is configured to the source driver 20 and the gate The driver 30 provides a timing control signal and also transmits a data signal to be displayed to the source driver 20.

The display panel 10 in the embodiment of the present invention may be, for example, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like, or any product or component having a display function.

The timing controller 40 provided in this embodiment is shown in FIG. 3. The timing controller 40 includes a timing control chip 100 and a data memory 200. The timing control chip 100 and the data memory 200 pass through an SPI bus. 300 connections. Specifically, the SPI bus 300 includes a first connection end 301, a second connection end 302, and a third connection end 303. The first connection end 301 is connected to the timing control chip 100, and the second connection end 302 is connected. Connected to the data storage 200, the third connection end 303 is used to connect the data burning fixture 400.

In the embodiment, the timing control chip 100 is provided with a main mode unit 101, a slave mode unit 102, and a connection control unit 103, and the connection control unit 103 is configured to control the first connection of the SPI bus 300. The terminal 301 is connected to the master mode unit 101 or the slave mode unit 102. When the connection control unit 103 controls the first connection terminal 301 to be connected to the main mode unit 101, the timing control chip 100 has the control of the SPI bus 300, and the timing control chip 100 functions as the data memory. The host side of 200 acquires data from the data storage 200; when the connection control unit 103 controls the first connection terminal 301 to be connected to the slave mode unit 102, the timing control chip 100 releases the SPI bus 300 control The timing control chip 100 is no longer used as the host end of the data memory 200. At this time, the data burning fixture 400 can be connected to the third connection end 303 of the SPI bus 300. 400 as a host side of the data memory 200 burns data to the data memory 200, and updates data stored in the data memory 200.

The data memory 200 is a flash memory. Further, as shown in FIG. 3, the timing control chip 100 is further connected with a Synchronous Dynamic Random Access Memory (SDRAM) 500, and the synchronous dynamic random access memory 500 is configured to store the time. The data acquired by the control chip 100 from the data memory 200.

Among them, regarding SPI bus 300, SPI (Serial Peripheral Interface) bus is a synchronous serial interface introduced by Motorola, which works in master-slave mode. This mode usually has a host (Master). And one or more slaves (Slave). SPI is used for full-duplex, synchronous serial communication between the host and slave.

Further, as shown in FIG. 4, the data update method of the timing controller provided in this embodiment includes the following steps:

Step S1: Control the first connection end to be connected to the slave mode unit, connect the data burning fixture to the third connection end, and burn the second data to be updated to the data storage by the data burning fixture.

Step S2, controlling the first connection end to be connected to the main mode unit, removing the data burning jig from the third connection end, and acquiring the second data from the data memory by the timing control chip.

More specifically, in this embodiment, the timing controller is used to drive the display panel for display, and the timing controller needs to provide driving data to the display panel, so that the display panel displays an image, and the second data as described above refers to Driver data to be updated. In this embodiment, referring to FIG. 5, the acquiring manner of the second data specifically includes the following steps:

S10. The timing controller drives the display panel to display the first image according to the first data. The first data refers to the driving data before the update.

S20. Detect a defect existing in the first image. Detection can be performed by some image detecting device, such as an optical detector.

S30. Compensating the first data to eliminate defects existing in the first image, and obtaining the second data. On the basis of the first data, the first data is compensated for the purpose of eliminating the defect of displaying the first image when driven by the first data, thereby obtaining the second data.

According to the above updating method, after the drive data in the timing controller 40 is updated to the second data, the second data is stored in the synchronous dynamic random access memory 500 connected to the timing control chip 100. In the active state (the state in which the display panel is driven), the timing controller 40 acquires the second data from the synchronous dynamic random access memory 500, and drives the display panel 10 in accordance with the second data.

In summary, the timing controller and the data updating method thereof provided by the embodiments of the present invention provide a main mode unit, a slave mode unit, and a connection control unit in the timing control chip, and are connected when data needs to be acquired from the data storage. The control unit controls the main mode unit to connect to the SPI bus. When acquiring data from the data memory, the connection control unit controls the slave mode unit to be connected to the SPI bus, thereby avoiding the problem of conflicts between multiple host terminals during data update, avoiding complicated peripheral circuit design and reducing cost. And when the data is updated, the operation is simpler and more flexible, and the stability of the data update is improved.

It should be noted that, in this context, relational terms such as first and second are used merely to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply such entities or operations. There is any such actual relationship or order between them. Furthermore, the term "comprises" or "comprises" or "comprises" or any other variations thereof is intended to encompass a non-exclusive inclusion, such that a process, method, article, or device that comprises a plurality of elements includes not only those elements but also Other elements, or elements that are inherent to such a process, method, item, or device. An element that is defined by the phrase "comprising a ..." does not exclude the presence of additional equivalent elements in the process, method, item, or device that comprises the element.

The above description is only a specific embodiment of the present application, and it should be noted that those skilled in the art can also make several improvements and retouchings without departing from the principles of the present application. It should be considered as the scope of protection of this application.

Claims

A timing controller includes a timing control chip and a data memory, wherein the timing control chip and the data memory are connected by an SPI bus, and the SPI bus includes a first connection end, a second connection end, and a third connection end The first connection end is connected to the timing control chip, the second connection end is connected to the data storage, and the third connection end is used to connect a data burning fixture; wherein the timing control chip Providing a main mode unit, a slave mode unit, and a connection control unit, the connection control unit configured to control the first connection end to be connected to the main mode unit or the slave mode unit; when the first connection end is connected to The main mode unit, the timing control chip as a host of the data memory acquires data from the data memory.
The timing controller according to claim 1, wherein said third connection terminal is connected with a data burning jig for burning data to said data storage; and said data burning fixture is said to said data The connection control unit controls the first connection terminal to be connected to the slave mode unit when the memory burns data.
The timing controller of claim 1, wherein the data memory is a flash memory.
The timing controller according to claim 3, wherein said timing control chip is further connected with a synchronous dynamic random access memory for storing data acquired by said timing control chip from said data memory.
A data update method for a timing controller, the timing controller includes a timing control chip and a data memory, and the timing control chip and the data memory are connected by an SPI bus, and the SPI bus includes a first connection end, a second connection end, wherein the first connection end is connected to the timing control chip, the second connection end is connected to the data storage, and the third connection end is used for connecting data burning and processing The main control unit, the slave mode unit, and the connection control unit are disposed in the timing control chip, and the connection control unit is configured to control the first connection end to be connected to the main mode unit or the slave mode unit; The data update method includes:

Controlling that the first connection end is connected to the slave mode unit, connecting a data burning fixture to the third connection end, and burning, by the data burning fixture, the second data to be updated to the Data storage

Controlling that the first connection end is connected to the main mode unit, removing a data burning jig from the third connection end, and acquiring, by the timing control chip, the second data from the data memory.
The data updating method according to claim 5, wherein said data memory is a flash memory.
The data updating method according to claim 6, wherein said timing control chip is further connected with a synchronous dynamic random access memory for storing data acquired by said timing control chip from said data memory.
The data updating method according to claim 5, wherein the timing controller is configured to drive the display panel to display, wherein the second data is acquired as follows:

The timing controller drives the display panel to display the first image according to the first data;

Detecting defects existing in the first image;

Compensating the first data to eliminate defects existing in the first image, and obtaining the second data.
A liquid crystal display panel comprising:

Display panel

a source driver for providing a data signal to the display panel;

a gate driver for providing a scan signal to the display panel;

a timing controller, configured to provide a timing control signal to the source driver and the gate driver, and send a data signal to be displayed to the source driver;

The timing controller includes a timing control chip and a data memory, and the timing control chip and the data memory are connected by an SPI bus, and the SPI bus includes a first connection end, a second connection end, and a third connection. End, the first connection end is connected to the timing control chip, the second connection end is connected to the data storage, and the third connection end is used to connect a data burning fixture; wherein the timing control a main mode unit, a slave mode unit and a connection control unit are provided in the chip, the connection control unit is configured to control the first connection end to be connected to the main mode unit or the slave mode unit; when the first connection end is connected To the main mode unit, the timing control chip acquires data from the data memory as a host side of the data memory.
The liquid crystal display panel according to claim 9, wherein the third connection end is connected with a data burning jig for burning data to the data storage; when the data burning jig is directed to the data When the memory burns data, the connection control unit controls the first connection end to be connected to the slave Mode unit.
The liquid crystal display panel according to claim 9, wherein the data memory is a flash memory.
The liquid crystal display panel according to claim 11, wherein the timing control chip is further connected with a synchronous dynamic random access memory for storing data acquired by the timing control chip from the data memory.