WO2017218170A1 - Procédé et appareil pour programmer des lignes de mots d'une mémoire flash nand à l'aide de schémas de codage alternes - Google Patents

Procédé et appareil pour programmer des lignes de mots d'une mémoire flash nand à l'aide de schémas de codage alternes Download PDF

Info

Publication number
WO2017218170A1
WO2017218170A1 PCT/US2017/034911 US2017034911W WO2017218170A1 WO 2017218170 A1 WO2017218170 A1 WO 2017218170A1 US 2017034911 W US2017034911 W US 2017034911W WO 2017218170 A1 WO2017218170 A1 WO 2017218170A1
Authority
WO
WIPO (PCT)
Prior art keywords
wordline
cells
memory
programmed
programming
Prior art date
Application number
PCT/US2017/034911
Other languages
English (en)
Inventor
Nuo ZHANG
Pranav Kalavade
Krishna Parat
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Publication of WO2017218170A1 publication Critical patent/WO2017218170A1/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5641—Multilevel memory having cells with different number of storage levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5648—Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant

Definitions

  • the present disclosure relates in general to the field of computer development, and more specifically, to NAND flash memory.
  • a computer system may include one or more central processing units (CPUs) coupled to one or more storage devices.
  • CPUs central processing units
  • a CPU may include a processor to execute an operating system and other software applications that utilize the storage devices coupled to the CPU.
  • the software applications may write data to the storage devices.
  • the data may be stored by the storage devices in a plurality of memory cells (e.g., NAND flash memory cells) of the storage devices.
  • FIG. 1 illustrates a block diagram of components of a computer system in accordance with certain embodiments.
  • FIG. 2 illustrates an example diagram of a portion of a NAND flash memory array in accordance with certain embodiments.
  • FIG. 3 illustrates example encoding schemes for NAND flash memory cells in accordance with certain embodiments.
  • FIG. 4 illustrates an example programming sequence of tri-level cell (TLC) NAND flash memory cells in accordance with certain embodiments.
  • FIG. 5 illustrates an example programming sequence of quad-level cell (QLC) NAND flash memory cells in accordance with certain embodiments.
  • QLC quad-level cell
  • FIG. 6 illustrates an example programming sequence of multi-level cell (MLC) and TLC NAND flash memory cells in accordance with certain embodiments.
  • FIG. 7 illustrates an example table storing configuration data for wordlines of a NAND flash memory in accordance with certain embodiments.
  • FIG. 8 illustrates an example programming sequence of QLC and TLC NAND flash memory cells in accordance with certain embodiments.
  • FIG. 9 illustrates an example flow for programming NAND flash memory cells with alternating encoding schemes in accordance with certain embodiments.
  • FIG. 1 depicts particular computer systems, the concepts of various embodiments are applicable to any suitable integrated circuits and other logic devices.
  • devices in which teachings of the present disclosure may be used include desktop computer systems, server computer systems, storage systems, handheld devices, tablets, other thin notebooks, systems on a chip (SOC) devices, and embedded applications.
  • Some examples of handheld devices include cellular phones, digital cameras, media players, personal digital assistants (PDAs), and handheld PCs.
  • Embedded applications may include a microcontroller, a digital signal processor (DSP), a system on a chip, network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can perform the functions and operations taught below.
  • DSP digital signal processor
  • NetPC network computers
  • Set-top boxes network hubs
  • WAN wide area network
  • Various embodiments of the present disclosure may be used in any suitable computing environment, such as a personal computing device, a server, a mainframe, a cloud computing service provider infrastructure, a datacenter, a communications service provider infrastructure (e.g., one or more portions of an Evolved Packet Core), or other environment comprising a group of computing devices.
  • a personal computing device such as a server, a mainframe, a cloud computing service provider infrastructure, a datacenter, a communications service provider infrastructure (e.g., one or more portions of an Evolved Packet Core), or other environment comprising a group of computing devices.
  • a communications service provider infrastructure e.g., one or more portions of an Evolved Packet Core
  • FIG. 1 illustrates a block diagram of components of a computer system 100 in accordance with certain embodiments.
  • System 100 includes a central processing unit (CPU) 102 coupled to an external input/output (I/O) controller 104, a plurality of storage devices 106, and memory device 107.
  • CPU central processing unit
  • I/O input/output
  • data may be transferred between storage devices 106 or memory device 107 and the CPU 102.
  • particular data operations involving a storage device 106 or memory device 106 may be managed by an operating system or other software application executed by processor 108.
  • a storage device 106 comprises NAND flash memory.
  • storage device 106 may be a solid state drive; a memory card; a Universal Serial Bus (USB) flash drive; or memory integrated within a device such as a smartphone, camera, media player, or other computing device.
  • storage devices with NAND flash memory are classified by the number of bits stored by each cell of the memory. For example, a single-level cell (SLC) memory has cells that each store one bit of data, a multi-level cell (MLC) memory has cells that each store two bits of data, a tri-level cell (TLC) memory has cells that each store three bits of data, and a quad-level cell (QLC) memory has cells that each store four bits of data.
  • SLC single-level cell
  • MLC multi-level cell
  • TLC tri-level cell
  • QLC quad-level cell
  • each wordline (or portion thereof such as a page) of the memory has the same type of cells. That is, all wordlines are SLC memory, or all wordlines are MLC memory, or all wordlines are TLC memory, or all wordlines are QLC memory.
  • Various embodiments of the present disclosure improve NAND flash memory performance by programming the cells of adjacent wordlines (or portions thereof such as adjacent pages) of the memory to store different numbers of bits.
  • one wordline may be programmed as MLC memory
  • the next wordline may be programmed as TLC memory
  • the next wordline may be programmed as MLC memory, and so on.
  • Such configuration of memory may effectively store 2.5 bits per cell.
  • one wordline may be programmed as TLC memory
  • the next wordline may be programmed as QLC memory
  • the next wordline may be programmed as TLC memory, and so on.
  • Such other configuration of memory may effectively store 3.5 bits per cell.
  • a single pass programming algorithm may be used for both types of wordlines (e.g., MLC and TLC wordlines or TLC and QLC wordlines) as opposed to a multi-pass programming algorithm where the cells of a wordline are partially programmed in a first pass and programming is completed in a second pass after one or more adjacent wordlines have been partially programmed.
  • Embodiments of the present disclosure may offer various technical advantages, such as improved write performance due to the use of a single pass programming algorithm. Various embodiments may also us less energy per bit by reducing the time needed to program a block of the memory. Various embodiments may also improve read performance of the storage device.
  • CPU 102 comprises a processor 108, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a co-processor, a system on a chip (SOC), or other device to execute code (i.e., software instructions).
  • processor 108 in the depicted embodiment, includes two processing elements (cores 114A and 114B in the depicted embodiment), which may include asymmetric processing elements or symmetric processing elements. However, a processor may include any number of processing elements that may be symmetric or asymmetric.
  • a processing element refers to hardware or logic to support a software thread.
  • hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and/or any other element, which is capable of holding a state for a processor, such as an execution state or architectural state.
  • a processing element in one embodiment, refers to any hardware capable of being independently associated with code, such as a software thread, operating system, application, or other code.
  • a physical processor or processor socket typically refers to an integrated circuit, which potentially includes any number of other processing elements, such as cores or hardware threads.
  • a core 114 may refer to logic located on an integrated circuit capable of maintaining an independent architectural state, wherein each independently maintained architectural state is associated with at least some dedicated execution resources.
  • a hardware thread may refer to any logic located on an integrated circuit capable of maintaining an independent architectural state, wherein the independently maintained architectural states share access to execution resources.
  • the processing elements may also include one or more arithmetic logic units (ALUs), floating point units (FPUs), caches, instruction pipelines, interrupt handling hardware, registers, or other hardware to facilitate the operations of the processing elements.
  • ALUs arithmetic logic units
  • FPUs floating point units
  • caches instruction pipelines
  • interrupt handling hardware registers, or other hardware to facilitate the operations of the processing elements.
  • I/O controller 110 is an integrated I/O controller that includes logic for communicating data between CPU 102 and I/O devices, which may refer to any suitable devices capable of transferring data to and/or receiving data from an electronic system, such as CPU 102.
  • an I/O device may comprise an audio/video (A/V) device controller such as a graphics accelerator or audio controller; a data storage device controller, such as a flash memory device, magnetic storage disk, or optical storage disk controller; a wireless transceiver; a network processor; a network interface controller; or a controller for another input devices such as a monitor, printer, mouse, keyboard, or scanner; or other suitable device.
  • A/V audio/video
  • an I/O device may comprise a storage device 106 coupled to the CPU 102 through I/O controller 110.
  • An I/O device may communicate with the I/O controller 110 of the CPU 102 using any suitable signaling protocol, such as peripheral component interconnect (PCI), PCI Express (PCIe), Universal Serial Bus (USB), Serial Attached SCSI (SAS), Serial ATA (SATA), Fibre Channel (FC), IEEE 802.3, IEEE 802.11, or other current or future signaling protocol.
  • PCI peripheral component interconnect
  • PCIe PCI Express
  • USB Universal Serial Bus
  • SAS Serial Attached SCSI
  • SAS Serial ATA
  • FC Fibre Channel
  • IEEE 802.3 IEEE 802.11, or other current or future signaling protocol.
  • I/O controller 110 and the underlying I/O device may communicate data and commands in accordance with a logical device interface specification such as Non- Volatile Memory Express (NVMe) (e.g., as described by one or more of the specifications available at www.nvmexpress.org/specifications/) or Advanced Host Controller Interface (AHCI) (e.g., as described by one or more AHCI specifications such as Serial ATA AHCI : Specification, Rev. 1.3.1 available at http://www.intel.com/content/www/us/en/io/serial- ata/serial-ata-ahci-spec-revl-3-l.html).
  • I/O devices coupled to the I/O controller may be located off-chip (i.e., not on the same chip as CPU 102) or may be integrated on the same chip as the CPU 102.
  • CPU memory controller 112 is an integrated memory controller that includes logic to control the flow of data going to and from one or more memory devices 107.
  • CPU memory controller 112 may include logic operable to read from a memory device 107, write to a memory device 107, or to request other operations from a memory device 107.
  • CPU memory controller 112 may receive write requests from cores 114 and/or I/O controller 110 and may provide data specified in these requests to a memory device 107 for storage therein.
  • CPU memory controller 112 may also read data from a memory device 107 and provide the read data to I/O controller 110 or a core 114.
  • CPU memory controller 112 may issue commands including one or more addresses of the memory device 107 in order to read data from or write data to memory (or to perform other operations).
  • CPU memory controller 112 may be implemented on the same chip as CPU 102, whereas in other embodiments, CPU memory controller 112 may be implemented on a different chip than that of CPU 102.
  • I/O controller 110 may perform similar operations with respect to one or more storage devices 106.
  • the CPU 102 may also be coupled to one or more other I/O devices through external I/O controller 104.
  • external I/O controller 104 may couple a storage device 106 to the CPU 102.
  • External I/O controller 104 may include logic to manage the flow of data between one or more CPUs 102 and I/O devices.
  • external I/O controller 104 is located on a motherboard along with the CPU 102. The external I/O controller 104 may exchange information with components of CPU 102 using point-to-point or other interfaces.
  • a memory device 107 may store any suitable data, such as data used by processors 106 to provide the functionality of computer system 100. For example, data associated with programs that are executed or files accessed by cores 110 may be stored in memory device 107. Thus, a memory device 107 may include a system memory that stores data and/or sequences of instructions that are used or executed by the cores 114. In various embodiments, a memory device 107 may store persistent data (e.g., a user's files or instruction sequences) that remains stored even after power to the memory device 107 is removed. A memory device 107 may be dedicated to a particular CPU 102 or shared with other devices (e.g., one or more other processors or other device) of computer system 100.
  • a memory device 107 may include a memory comprising any number of memory modules, a memory device controller, and other supporting logic (not shown).
  • a memory module may include non-volatile memory and/or volatile memory.
  • Non-volatile memory is a storage medium that does not require power to maintain the state of data stored by the medium.
  • Nonlimiting examples of nonvolatile memory may include any or a combination of: solid state memory (such as planar or 3D NAND flash memory or NOR flash memory), 3D crosspoint memory, memory devices that use chalcogenide phase change material (e.g., chalcogenide glass), byte addressable nonvolatile memory devices, ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, polymer memory (e.g., ferroelectric polymer memory), ferroelectric transistor random access memory (Fe-TRAM) ovonic memory, nanowire memory, electrically erasable programmable read-only memory (EEPROM), other various types of non-volatile random access memories (RAMs), and magnetic storage memory.
  • solid state memory such as planar or 3D NAND flash memory or NOR flash memory
  • 3D crosspoint memory such as planar or 3D NAND flash memory or NOR flash memory
  • memory devices that use chalcogenide phase change material e.g., chalcogenide
  • 3D crosspoint memory may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of words lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance.
  • Volatile memory is a storage medium that requires power to maintain the state of data stored by the medium. Examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM).
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • SDRAM synchronous dynamic random access memory
  • any portion of memory 107 that is volatile memory can comply with JEDEC standards including but not limited to Double Data Rate (DDR) standards, e.g., DDR3, 4, and 5, or Low Power DDR4 (LPDDR4) as well as emerging standards.
  • DDR Double Data Rate
  • LPDDR4 Low Power DDR4
  • a storage device 106 may store any suitable data, such as data used by processor 108 to provide functionality of computer system 100. For example, data associated with programs that are executed or files accessed by cores 114 may be stored in storage device 106. Thus, a storage device 106 may include a system memory that stores data and/or sequences of instructions that are used or executed by the cores 114. In various embodiments, a storage device 106 may store persistent data (e.g., a user's files or software application code) that remains stored even after power to the storage device 106 is removed. A storage device 106 may be dedicated to CPU 102 or shared with other devices (e.g., another CPU or other device) of computer system 100.
  • data such as data used by processor 108 to provide functionality of computer system 100. For example, data associated with programs that are executed or files accessed by cores 114 may be stored in storage device 106. Thus, a storage device 106 may include a system memory that stores data and/or sequences of instructions that are used or executed by the cores 114
  • storage device 106A includes a storage device controller 118 and a memory 116 comprising a plurality of memory modules 122A-D, however, a storage device may include any suitable number of memory modules 122.
  • a memory module 122 includes a plurality of memory cells that are each operable to store one or more bits.
  • the cells of a memory module 122 may be arranged in any suitable fashion, such as in rows (e.g., wordlines) and columns (e.g., bitlines), three dimensional structures, or other manner.
  • the cells may be logically grouped into banks, blocks, subblocks, wordlines, pages, frames, bytes, or other suitable groups.
  • a memory module 122 comprises one or more NAND flash memory arrays.
  • FIG. 2 illustrates an example diagram of a portion of a NAND flash memory array 200 in accordance with certain embodiments.
  • NAND flash memory array 200 may comprise a plurality of non-volatile memory cells 202 arranged in columns such as series strings 204.
  • a memory cell 202 may comprise a transistor with a floating gate that stores charge indicative of one or more bit values stored by the memory cell 202.
  • the drains of the cells 202 are each (with the exception of the top cell) coupled to a source of another cell 202.
  • the array 200 also includes wordlines 206.
  • a wordline 206 may span across multiple series strings 204 (e.g., being coupled to one memory cell of each series string 204) and are connected to the control gates of each memory cell 202 of a row of the array 200 and used to bias the control gates of the memory cells 202 in the row.
  • the bitlines 208 are each coupled to a series string 204 by a drain select gate 214 and sensing circuitry (not shown) that detects the state of each cell by sensing voltage or current on a particular bitline 208.
  • Each series string 204 of memory cells is coupled to a source line 210 by a source select gate 212 and to an individual bit line 208 by a drain select gate 214.
  • the source select gates 212 are controlled by a source select gate control line 216 and the drain select gates 214 are controlled by a drain select gate control line 218.
  • each memory cell 202 can be programmed by an SLC, MLC, TLC, a QLC, or other encoding scheme.
  • Each cell's threshold voltage (Vt) is indicative of the data that is stored in the cell.
  • FIG. 3 illustrates example encodings of bits within NAND flash memory cells 202 in accordance with certain embodiments.
  • the lower vertices of each triangle represent a range of threshold voltages that correspond to the value encoded within the cell. For example, in the SLC encoding scheme, lower threshold voltages correspond to the bit value 1 and higher threshold voltages correspond to the bit value 0.
  • the lowest range of threshold voltages corresponds to "11”
  • the next highest range of threshold voltages corresponds to "01”
  • the next highest range of threshold voltages corresponds to "00”
  • the highest range of threshold voltages correspond to "10.”
  • various ranges of threshold voltages correspond to various values of the bits encoded within each cell.
  • a memory module 122 may include non-volatile memory, such as planar or 3D NAND flash memory.
  • Non-volatile memory is a storage medium that does not require power to maintain the state of data stored by the medium.
  • a memory module 122 with non-volatile memory may comply with one or more standards for non-volatile memory promulgated by the Joint Electron Device Engineering Council (JEDEC), such as JESD218, JESD219, JESD220-1, JESD220C, JESD223C, JESD223-1, or other suitable standard (the JEDEC standards cited herein are available at www.jedec.org).
  • JEDEC Joint Electron Device Engineering Council
  • the storage device comprises NAND flash memory that complies with one or more portions of a standard promulgated by JEDEC for SDRAM memory, such as JESD79F for Double Data Rate (DDR) SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, or JESD79-4A for DDR4 SDRAM (these standards are available at www.jedec.org).
  • JESD79F Double Data Rate
  • JESD79-2F for DDR2 SDRAM
  • JESD79-3F for DDR3 SDRAM
  • JESD79-4A for DDR4 SDRAM
  • a storage device 106 comprising NAND flash memory may receive a command that has a format compliant with a DDR-based standard and may translate the command into one or more commands that are compatible with NAND flash memory of the storage device 106.
  • the storage device 106 may format results from operations performed on the NAND flash memory into a format that is compliant with a DDR-based standard before transmitting the results to the CPU 102.
  • Storage devices 106 may comprise any suitable type of memory and are not limited to a particular speed, technology, or form factor of memory in various embodiments.
  • a storage device 106 could be a disk drive (such as a solid state drive), a flash drive, memory integrated with a computing device (e.g., memory integrated on a circuit board of the computing device), a memory module (e.g., a dual in-line memory module) that may be inserted in a memory socket, or other type of storage device.
  • computer system 100 could include multiple different types of storage devices 106.
  • Storage devices 106 may include any suitable interface to communicate with CPU memory controller 112 or I/O controller 110 using any suitable communication protocol such as a DDR-based protocol, PCI, PCIe, USB, SAS, SATA, FC, System Management Bus (SMBus), or other suitable protocol.
  • Storage devices 106 may also include a communication interface to communicate with CPU memory controller 112 or I/O controller 110 in accordance with any suitable logical device interface specification such as NVMe, AHCI, or other suitable specification.
  • storage device 106 may comprise multiple communication interfaces that each communicate using a separate protocol with CPU memory controller 112 and/or I/O controller 110.
  • Storage device controller 118 may include logic to receive requests from CPU 102 (e.g., via CPU memory controller 112 or I/O controller 110), cause the requests to be carried out with respect to memory 116, and provide data associated with the requests to CPU 102 (e.g., via CPU memory controller 112 or I/O controller 110). Controller 118 may also be operable to detect and/or correct errors encountered during memory operation. In an embodiment, controller 118 also tracks the number of times particular cells (or logical groupings of cells) have been written to in order to perform wear leveling and/or to detect when cells are nearing an estimated number of times they may be reliably written to.
  • the storage device controller 118 may evenly spread out write operations among blocks of the memory 116 such that particular blocks are not written to more than other blocks. In various embodiments, controller 118 may also monitor various characteristics of the storage device 106 such as the temperature or voltage and report associated statistics to the CPU 102. Storage device controller 118 can be implemented on the same chip, board, or device as memory 116 or on a different chip, board, or device. For example, in some environments, storage device controller 118 may be a centralized storage controller that manages memory operations for multiple different memories 116 (which could each be of the same type or could be of different types) of computer system 100 (and thus could provide storage device controller functionality described herein to any of the memories to which it is coupled).
  • the storage device 106 also includes an address translation engine 120.
  • the address translation engine 120 is shown as part of the storage device controller 118, although in various embodiments, the address translation engine 120 may be separate from the storage device controller 118 and communicably coupled to the storage device controller 118. In various embodiments, the address translation engine 120 may be integrated on the same chip as the storage device controller 118 or on a different chip.
  • address translation engine 120 may include logic to store and update a mapping between a logical address space (e.g., an address space visible to a computing host coupled to the storage device 106) and the physical address space of the memory 116 (which may or may not be exposed to the computing host).
  • the logical address space may expose a plurality of logical groups of data which is physically stored on corresponding physical groups of memory addressable through the physical address space of the storage device 106.
  • a physical address of the physical address space may comprise any suitable information identifying a physical memory location (e.g., a location within memory 116) of the storage device 106, such as an identifier of the memory module 122 on which the physical memory location is located, one or more pages of the physical memory location, one or more subblocks of the physical memory location, one or more wordlines of the physical memory location, one or more bitlines of the physical memory location, or other suitable identifiers or encodings thereof.
  • a physical memory location e.g., a location within memory 116
  • an identifier of the memory module 122 on which the physical memory location is located such as an identifier of the memory module 122 on which the physical memory location is located, one or more pages of the physical memory location, one or more subblocks of the physical memory location, one or more wordlines of the physical memory location, one or more bitlines of the physical memory location, or other suitable identifiers or encodings thereof.
  • storage device controller 118 may store a programming order for portions of the memory 116.
  • the programming order may specify an order in which wordlines of the memory 116 are to be programmed.
  • storage device controller 118 may also store an indication of the encoding scheme of a wordline (e.g., how many bits are stored or should be stored within each cell of the wordline). For example, for each wordline, storage device controller 118 may store an indication of whether the wordline should be programmed as SLC, MLC, TLC, or QLC. An example of a table comprising such information will be described in connection with FIG. 7.
  • the address translation engine 120 or other portion of storage device 106 may include any suitable memory type for storing logical to physical mapping structures, programming orders, and encoding scheme indications and any suitable logic for changing values stored in the logical to physical mapping structures, programming orders, and encoding scheme indications (e.g., in response to a request from the storage device controller 118) and reading values from the logical to physical mapping structures, programming orders, and encoding scheme indications (e.g., to provide the values to the storage device controller 118 for use in memory operations).
  • any suitable memory type for storing logical to physical mapping structures, programming orders, and encoding scheme indications and any suitable logic for changing values stored in the logical to physical mapping structures, programming orders, and encoding scheme indications (e.g., in response to a request from the storage device controller 118) and reading values from the logical to physical mapping structures, programming orders, and encoding scheme indications (e.g., to provide the values to the storage device controller 118 for use in memory operations).
  • Storage media for the logical to physical mapping structures, programming orders, and encoding scheme indications may be included within the address translation engine 120 and/or storage device controller 118 or may be communicably coupled to the address translation engine and/or storage device controller. In various embodiments, storage media for the logical to physical mapping structures, programming orders, and encoding scheme indications may be integrated on the same chip as the storage device controller 118 and/or address translation engine 120 or may be implemented on a separate chip.
  • the address translation engine 120 and/or storage device controller 118 may provide wear leveling through management of the address mappings of the logical to physical mapping structures, programming orders, and encoding scheme indications. In particular embodiments, the address translation engine 120 and/or storage device controller 118 may also prevent the use of bad memory cells (or logical grouping of cells) by not allowing physical addresses for the bad cells (or logical grouping of cells) to be mapped to the logical address space.
  • all or some of the elements of system 100 are resident on (or coupled to) the same circuit board (e.g., a motherboard).
  • any suitable partitioning between the elements may exist.
  • the elements depicted in CPU 102 may be located on a single die or package (i.e., on-chip) or any of the elements of CPU 102 may be located off-chip.
  • the elements depicted in storage device 106A may be located on a single chip or on multiple chips.
  • a storage device 106 and a computing host e.g., CPU 102
  • the storage device 106 and the computing host may be located on different circuit boards or devices.
  • a bus may couple any of the components together.
  • a bus may include any known interconnect, such as a multi-drop bus, a mesh interconnect, a ring interconnect, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g. cache coherent) bus, a layered protocol architecture, a differential bus, and a Gunning transceiver logic (GTL) bus.
  • GTL Gunning transceiver logic
  • an integrated I/O subsystem includes point-to-point multiplexing logic between various components of system 100, such as cores 114, one or more CPU memory controllers 112, I/O controller 110, integrated I/O devices, direct memory access (DMA) logic (not shown), etc.
  • components of computer system 100 may be coupled together through one or more networks comprising any number of intervening network nodes, such as routers, switches, or other computing devices.
  • a computing host e.g., CPU 102
  • the storage device 106 may be communicably coupled through a network.
  • system 100 may use a battery and/or power supply outlet connector and associated system to receive power, a display to output data provided by CPU 102, or a network interface allowing the CPU 102 to communicate over a network.
  • the battery, power supply outlet connector, display, and/or network interface may be communicatively coupled to CPU 102.
  • Other sources of power can be used such as renewable energy (e.g., solar power or motion based power).
  • a programming pass may include several program loops (e.g., between three and thirty program loops depending on the number of bits to be encoded by the cell).
  • a program loop includes selecting a wordline, applying a program pulse voltage to the cells (e.g., applying the voltage to control gates of the cells of the wordline while coupling the channels of the cells to ground to allow charge to flow into the floating gates of the cells), and then applying several verify pulses to determine whether the cells have each reached the appropriate threshold voltage.
  • the program pulse voltage is stepped higher to allow cells that are to be programmed with higher threshold voltages to reach the appropriate level.
  • that cell is inhibited (e.g., by floating the channel of the cell) during subsequent program loops.
  • a memory module 122 is programmed a wordline at a time or a page at a time. That is, for a particular array of memory, a programming pass is completed on a wordline or page of the array before a programming pass may begin on another wordline or page of the array. During a pass, an entire wordline or a portion thereof (e.g., a page) may be programmed. As an example of the latter, in various 3D NAND structures, cells are programmed a page at a time (where a page is defined by a particular wordline and a subblock of that wordline). In other embodiments, any suitable portion of a wordline may be programmed during a programming pass.
  • the threshold voltage of a cell may be affected (e.g., due to floating gate interference) by the programming of a neighboring cell (e.g., a cell coupled to the same bitline and an adjacent wordline).
  • a neighboring cell e.g., a cell coupled to the same bitline and an adjacent wordline.
  • the threshold voltage of cell 202C of wordline 206B may be modified during the programming of cell 202A of wordline 206A or cell 202E of wordline 206C.
  • the threshold voltage of cell 202D of wordline 206B may be modified during the programming of cell 202B of wordline 206A or cell 202F of wordline 206C.
  • such interference may cause a threshold voltage of a programmed cell to change to a value that represents a different encoding (i.e., bit value) than the originally programmed value.
  • some systems may implement two pass programming.
  • two pass programming cells of a wordline (or portion thereof) are partially programmed in a first pass, and programming is completed in a second pass. After the first pass is completed, but before the second pass is begun, the cells of one or more adjacent wordlines (or corresponding portions thereof) are programmed (with either a first pass or a second pass).
  • FIG. 4 illustrates an example two pass programming sequence of TLC NAND flash memory cells in accordance with certain embodiments.
  • the number of triangles in FIG. 4 may represent a level of encoding.
  • the cells of wordline n are encoded to two levels and during pass 3, the programming of wordline n is completed by encoding the cells to eight levels (i.e., the number of levels used to represent three bits in a TLC encoding scheme).
  • the threshold voltages of particular cells of wordline n may be raised part of the way to their target values while in pass 3, the threshold voltages of the cells are raised the remaining amount to their target values (or inhibited if their target threshold voltages were already reached in pass 1).
  • the threshold voltages of the cells of wordline n are not deliberately changed (i.e., programmed), and relatively small changes to such threshold voltages (if any) of the cells of wordline n during these passes would be due to interference from the programming of the cells of a different wordline.
  • wordline n is programmed from an erase state (e.g., a low threshold voltage) to two levels.
  • the adjacent wordline n+1 is programmed to two levels.
  • the wordline n is then programmed to eight levels.
  • wordline n+2 is programmed to two levels.
  • pass 5 the wordline n+1 is programmed to eight levels. The effect of the programming of wordline n+1 on the cells of wordline n during pass 5 is mitigated because the threshold voltages of the cells of wordline n+1 are not changing as much as they would have changed if they had been programmed to eight levels in a single pass.
  • the encodings stored by the cells of wordline n may retain their programmed values.
  • the programming sequence could continue with wordline n+3 (not shown) being programmed to two levels in a sixth pass, and wordline n+2 being programmed to eight levels in a seventh pass, and so on. Accordingly, in this embodiment, the cells of each wordline go through two programming passes before being programmed to the target levels.
  • FIG. 5 illustrates an example programming sequence of quad-level cell (QLC) NAND flash memory cells in accordance with certain embodiments.
  • the number of triangles in FIG. 5 may represent a level of encoding.
  • the cells of wordline n are encoded to eight levels and during pass 3, the programming of wordline n is completed by encoding the cells to sixteen levels (i.e., the number of levels used to represent four bits in a QLC encoding scheme).
  • the threshold voltages of particular cells of wordline n may be raised part of the way to their target values while in pass 3, the threshold voltages of the cells are raised the remaining amount to their target values (or inhibited if their target threshold voltages were already reached in pass 1).
  • the threshold voltages of the cells of wordline n are not deliberately changed (i.e., programmed), and relatively small changes to such threshold voltages (if any) of the cells of wordline n during these passes would be due to interference from the programming of the cells of a different wordline.
  • all of the cells are programmed according to a QLC encoding scheme.
  • wordline n is programmed from an erase state (e.g., having a low threshold voltage) to eight levels.
  • the adjacent wordline n+1 is programmed to eight levels.
  • the wordline n is then programmed to sixteen levels.
  • wordline n+2 is programmed to eight levels.
  • the wordline n+1 is programmed to sixteen levels.
  • the effect of the programming of wordline n+1 on the cells of wordline n during pass 5 is mitigated because the threshold voltages of the cells of wordline n+1 are not changing as much as they would have changed if they had been programmed to sixteen levels in a single pass. Accordingly, the encodings stored by the cells of wordline n may retain their programmed values.
  • the programming sequence could continue with wordline n+3 (not shown) being programmed to eight levels in a sixth pass, and wordline n+2 being programmed to sixteen levels in a seventh pass, and so on. Accordingly, in this embodiment, the cells of each wordline undergo two programming passes before being programmed to the target levels.
  • FIG. 6 illustrates an example programming sequence of MLC and TLC NAND flash memory cells in accordance with certain embodiments.
  • various advantages may be realized by the alternate programming of MLC and TLC wordlines.
  • the cells of a wordline e.g., wordline n
  • the cells of the wordlines e.g., wordlines n-1 and n+1
  • Such embodiments may speed the programming operation by only utilizing a single programming pass to program each wordline.
  • the wordlines alternate between MLC and TLC wordlines. That is, every other wordline is programmed according to the same encoding scheme but adjacent wordlines are programmed using different encoding schemes. When the wordlines alternate between MLC and TLC, the resultant memory effectively stores 2.5 bits per cell.
  • wordline n-1 is programmed at pass 1 from an erase state (e.g., the cells may each have a threshold voltage in the lowest range) to four levels (thus the cells of wordline n-1 are programmed according to an MLC encoding scheme).
  • wordline n+1 is programmed from the erase state to four levels (thus the cells of wordline n+1 are also programmed according to the MLC encoding scheme).
  • wordline n is programmed from the erase state to eight levels (thus the cells of wordline n are programmed according to a TLC encoding scheme).
  • both the MLC wordlines (or portions thereof such as pages) and TLC wordlines (or portions thereof such as pages) are each programmed in a single pass. Because the cells that are programmed according to the MLC scheme have relatively wide threshold voltage ranges for each separate encoding, programming the cells of wordline n to eight levels in a single pass does not result in the loss of integrity of the encodings stored by the wordlines encoded using the MLC scheme (i.e., the cells of wordlines n-1 and n+1). Furthermore, by the time the TLC wordline (or portion thereof) is programmed, the adjacent wordlines (or adjacent portions thereof) have been programmed already so that there is no further floating gate interference on the TLC wordline (wordline n).
  • both MLC wordlines (or portions thereof) and TLC wordlines (or portions thereof) may each be programmed in one pass. Assuming eight program loops to program a MLC to four levels (and the aforementioned twenty programming loops to program a TLC to eight levels), twenty-eight programming loops would program five bits of data, resulting in a performance improvement of roughly 40%.
  • FIG. 7 illustrates an example table 700 storing configuration data for wordlines of a NAND flash memory in accordance with certain embodiments.
  • table 700 may be maintained by storage device controller 118, address translation engine 120, or other logic of a storage device 106.
  • Table 700 depicts configuration data associated with each wordline of a memory array.
  • the configuration data may include the type of encoding scheme used (or to be used) by the cells of the wordline (eg. SLC, MLC, TLC, QLC, etc.) and a program sequence identifier.
  • the program sequence identifiers collectively specify the order in which the wordlines are to be programmed. For example, in the embodiment depicted, wordline 5 is programmed, then wordline 4, then wordline 7, then wordline 6. In various embodiments, the ordering of the program sequence identifiers may result in TLC wordlines (that are not on the edges of the array) being programmed in between two programmed MLC wordlines.
  • Table 700 is merely an example representation of such configuration information. In various embodiments, such information may be realized using any suitable logic. For example, the sequence and encoding specified in table 700 may be realized without having to explicitly store each value in a table.
  • FIG. 8 illustrates an example programming sequence of QLC and TLC NAND flash memory cells in accordance with certain embodiments.
  • various advantages may be realized by the alternate programming of wordlines between TLC and QLC memory.
  • the cells of a wordline e.g., wordline n
  • the cells of the wordlines e.g., wordlines n-1 and n+1
  • Such embodiments may speed the programming operation by only utilizing a single programming pass to program each wordline.
  • the wordlines alternate between TLC and QLC wordlines.
  • Such a memory may effectively store 3.5 bits per cell.
  • wordline n-1 is programmed at pass 1 from an erase state to eight levels (thus the cells of wordline n-1 are programmed according to a TLC scheme).
  • wordline n+1 is programmed from the erase state to eight levels (thus the cells of wordline n+1 are also programmed according to the TLC scheme).
  • wordline n is programmed from the erase state to sixteen levels (thus the cells of wordline n are programmed according to a QLC scheme).
  • both the TLC wordlines (or portions thereof such as pages) and QLC wordlines (or portions thereof such as pages) are each programmed in a single pass. Because the cells that are programmed according to the TLC scheme have relatively wide threshold voltage ranges for each separate encoding, programming the cells of wordline n to sixteen levels (according to the QLC scheme) in one pass does not result in the loss of integrity of the encodings stored by the TLC wordlines (i.e., the cells of wordlines n-1 and n+1). Furthermore, by the time the QLC wordline (or portion thereof) is programmed, the adjacent wordlines (or adjacent portions thereof) have been programmed already so that there is no further floating gate interference on the QLC wordline (wordline n).
  • FIG. 9 illustrates an example flow 900 for programming NAND flash memory cells with alternating encoding schemes in accordance with certain embodiments.
  • the flow 900 depicts example operations that may be performed by any suitable logic, such as one or more components of a storage device 106.
  • data to be written to memory is received.
  • the data may be received via a single write command or via multiple write commands.
  • a first portion of the data is written to a first wordline using a first encoding scheme.
  • the first portion of the data may be written to cells of the first wordline that are programmed as MLCs.
  • the first portion of the data may be written to cells of the first wordline that are programmed as TLCs.
  • the first portion of the data is written to the first wordline in a single programming pass.
  • a second portion of the data is written to a second wordline using a second encoding scheme.
  • the second wordline is adjacent to the first wordline.
  • the second encoding scheme may store more bits per cell than the first encoding scheme.
  • the second portion of the data may be written to cells of the second wordline that are programmed as TLCs.
  • the second portion of the data may be written to cells of the second wordline that are programmed as QLCs.
  • a third portion of the data is written to a third wordline using the first encoding scheme.
  • a fourth portion of the data is written to a fourth wordline using the second encoding scheme.
  • the fourth wordline may be adjacent to the third wordline.
  • FIG. 9 The flow described in FIG. 9 is merely representative of operations that may occur in particular embodiments. In other embodiments, additional operations may be performed by the components of system 100. Various embodiments of the present disclosure contemplate any suitable signaling mechanisms for accomplishing the functions described herein. Some of the operations illustrated in FIG. 9 may be repeated, combined, modified or deleted where appropriate. Additionally, operations may be performed in any suitable order without departing from the scope of particular embodiments. For example, the data received to be written to memory may be received in multiple commands each occurring at any point in the flow.
  • wear leveling performed by the storage device controller 118 may include alternating the programming of a particular wordline between two different encoding schemes. For example, referring back to table 700 of FIG. 7, after the array has been programmed in accordance with the encodings specified in the table, the cells of the array may be erased and used to store other data. When the array is erased, the encodings of the wordlines may be flipped. For example, wordline 4 may now be configured as an MLC wordline, wordline 5 may now be configured as a TLC wordline, and so on. Because TLC memory is prone to wear out faster than MLC memory due to higher gate voltages being applied to the cells, such embodiments may prolong the life of the memory 116.
  • various embodiments may also improve read performance.
  • a TLC NAND memory may perform seven reads to resolve each cell (three bits) which is ⁇ 2.3 reads per bit.
  • wordlines alternate between TLC and MLC ten reads (three reads for the MLC wordlines and seven reads for the TLC wordlines) are used to resolve five bits of data which results in two reads per bit.
  • various embodiments may improve read performance by ⁇ 16%. Read performance may also improve for other configurations (e.g., alternating between TLC wordlines and QLC wordlines).
  • one or more points of the threshold voltage ranges of the different encoding schemes may be aligned, such that the same voltages may be applied during the reading of wordlines using different encoding schemes.
  • the start (i.e., lowest threshold voltage value) of the range representing "00" in the MLC scheme may be aligned with the start of the range representing "001" in the TLC scheme.
  • the end of the range representing "01" of the MLC scheme may be aligned with the end of the range representing "011” in the TLC scheme.
  • any of the points of the ranges of one encoding scheme may be aligned with any suitable points of the ranges of another encoding scheme.
  • any number of different encoding levels may be used within a memory and various different orderings for the encoding schemes of the wordlines may be used.
  • a wordline that is encoded with a higher number of bits per cell than its neighboring wordlines is programmed in a single pass after its neighboring wordlines are programmed (since the other wordlines with lower encodings are less susceptible to interference).
  • a particular wordline (e.g., WL n) may be programmed according to a TLC encoding scheme after a neighboring wordline (e.g., WL n-1) is programmed according to an SLC encoding and the other neighboring wordline (e.g., WL n+1) is programmed according to an MLC encoding (in alternative embodiments WL n+1 could be programmed first followed by the programming of WL n-1 and then the programming of WL n).
  • a particular wordline (e.g., WL n) may be programmed according to a TLC encoding scheme after a neighboring wordline (e.g., WL n-1) is programmed according to an SLC encoding and the other neighboring wordline (e.g., WL n+1) is also programmed according to an SLC encoding.
  • a neighboring wordline e.g., WL n-1
  • the other neighboring wordline e.g., WL n+1
  • a particular wordline (e.g., WL n) may be programmed according to a QLC encoding scheme after a neighboring wordline (e.g., WL n-1) is programmed according to an SLC encoding and the other neighboring wordline (e.g., WL n+1) is programmed according to an MLC or TLC encoding (in alternative embodiments, WL n+1 could be programmed first followed by the programming of WL n-1 and then the programming of WL n).
  • a particular wordline (e.g., WL n) may be programmed according to a QLC encoding scheme after its neighboring wordlines (e.g., WL n+1 and WL n-1) are both programmed according to SLC encodings (or MLC encodings).
  • any suitable pattern of encoding schemes may be used across the wordlines.
  • every third wordline may be encoded with a higher bit value.
  • WL n and WL n+1 may be programmed according to an MLC scheme, WL n+2 according to a TLC scheme, WL n+3 and WL n+4 according to an MLC scheme, WL n+5 according to a TLC scheme, and so on.
  • WL n+2 and WL n+5 (which are encoded according to the TLC scheme) may be programmed after their respective neighboring wordlines are programmed.
  • the pattern of the encoding across the wordlines is not uniform.
  • WL n, WL n+2, WL n+3, WL n+4, WL n+6, WL n+7 and WL n+9 may be programmed according to an MLC scheme and WL n+1, WL n+5, and WL n+8 programmed to a TLC scheme (with the wordlines being programmed according to the TLC scheme being programmed after their respective neighboring wordlines have been programmed). Any suitable ordering that preserves the values of the programmed cells may be used in various embodiments.
  • a design may go through various stages, from creation to simulation to fabrication.
  • Data representing a design may represent the design in a number of manners.
  • the hardware may be represented using a hardware description language (HDL) or another functional description language.
  • HDL hardware description language
  • a circuit level model with logic and/or transistor gates may be produced at some stages of the design process.
  • most designs, at some stage reach a level of data representing the physical placement of various devices in the hardware model.
  • the data representing the hardware model may be the data specifying the presence or absence of various features on different mask layers for masks used to produce the integrated circuit.
  • such data may be stored in a database file format such as Graphic Data System II (GDS II), Open Artwork System Interchange Standard (OASIS), or similar format.
  • GDS II Graphic Data System II
  • OASIS Open Artwork System Interchange Standard
  • software based hardware models, and HDL and other functional description language objects can include register transfer language (TL) files, among other examples.
  • TL register transfer language
  • Such objects can be machine-parsable such that a design tool can accept the HDL object (or model), parse the HDL object for attributes of the described hardware, and determine a physical circuit and/or on-chip layout from the object. The output of the design tool can be used to manufacture the physical device. For instance, a design tool can determine configurations of various hardware and/or firmware elements from the HDL object, such as bus widths, registers (including sizes and types), memory blocks, physical link paths, fabric topologies, among other attributes that would be implemented in order to realize the system modeled in the HDL object.
  • Design tools can include tools for determining the topology and fabric configurations of system on chip (SoC) and other hardware device.
  • SoC system on chip
  • the HDL object can be used as the basis for developing models and design files that can be used by manufacturing equipment to manufacture the described hardware.
  • an HDL object itself can be provided as an input to manufacturing system software to cause the described hardware.
  • the data may be stored in any form of a machine readable medium.
  • a memory or a magnetic or optical storage such as a disc may be the machine readable medium to store information transmitted via optical or electrical wave modulated or otherwise generated to transmit such information.
  • an electrical carrier wave indicating or carrying the code or design is transmitted, to the extent that copying, buffering, or re-transmission of the electrical signal is performed, a new copy is made.
  • a communication provider or a network provider may store on a tangible, machine-readable medium, at least temporarily, an article, such as information encoded into a carrier wave, embodying techniques of embodiments of the present disclosure.
  • a module as used herein refers to any combination of hardware, software, and/or firmware.
  • a module includes hardware, such as a micro-controller, associated with a non-transitory medium to store code adapted to be executed by the microcontroller. Therefore, reference to a module, in one embodiment, refers to the hardware, which is specifically configured to recognize and/or execute the code to be held on a non- transitory medium. Furthermore, in another embodiment, use of a module refers to the non- transitory medium including the code, which is specifically adapted to be executed by the microcontroller to perform predetermined operations.
  • module in this example, may refer to the combination of the microcontroller and the non-transitory medium. Often module boundaries that are illustrated as separate commonly vary and potentially overlap. For example, a first and a second module may share hardware, software, firmware, or a combination thereof, while potentially retaining some independent hardware, software, or firmware.
  • use of the term logic includes hardware, such as transistors, registers, or other hardware, such as programmable logic devices.
  • Logic may be used to implement any of the functionality of the various components such as CPU 102, external I/O controller 104, processor 108, core 114, I/O controller 110, CPU memory controller 112, storage device 106, memory device 107, memory 116, memory module 122, storage device controller 118, address translation engine 120, or other entity or component described herein.
  • Logic may refer to hardware, firmware, software and/or combinations of each to perform one or more functions.
  • logic may include a microprocessor or other processing element operable to execute software instructions, discrete logic such as an application specific integrated circuit (ASIC), a programmed logic device such as a field programmable gate array (FPGA), a storage device containing instructions, combinations of logic devices (e.g., as would be found on a printed circuit board), or other suitable hardware and/or software.
  • Logic may include one or more gates or other circuit components.
  • logic may also be fully embodied as software.
  • Software may be embodied as a software package, code, instructions, instruction sets and/or data recorded on non-transitory computer readable storage medium.
  • Firmware may be embodied as code, instructions or instruction sets and/or data that are hard-coded (e.g., nonvolatile) in storage devices.
  • Use of the phrase 'to' or 'configured to,' in one embodiment, refers to arranging, putting together, manufacturing, offering to sell, importing and/or designing an apparatus, hardware, logic, or element to perform a designated or determined task.
  • an apparatus or element thereof that is not operating is still 'configured to' perform a designated task if it is designed, coupled, and/or interconnected to perform said designated task.
  • a logic gate may provide a 0 or a 1 during operation. But a logic gate 'configured to' provide an enable signal to a clock does not include every potential logic gate that may provide a 1 or 0.
  • the logic gate is one coupled in some manner that during operation the 1 or 0 output is to enable the clock.
  • use of the term 'configured to' does not require operation, but instead focus on the latent state of an apparatus, hardware, and/or element, where in the latent state the apparatus, hardware, and/or element is designed to perform a particular task when the apparatus, hardware, and/or element is operating.
  • use of the phrases 'capable of/to,' and or 'operable to,' in one embodiment refers to some apparatus, logic, hardware, and/or element designed in such a way to enable use of the apparatus, logic, hardware, and/or element in a specified manner.
  • use of to, capable to, or operable to, in one embodiment refers to the latent state of an apparatus, logic, hardware, and/or element, where the apparatus, logic, hardware, and/or element is not operating but is designed in such a manner to enable use of an apparatus in a specified manner.
  • a value includes any known representation of a number, a state, a logical state, or a binary logical state. Often, the use of logic levels, logic values, or logical values is also referred to as l's and 0's, which simply represents binary logic states. For example, a 1 refers to a high logic level and 0 refers to a low logic level.
  • a storage cell such as a transistor or flash cell, may be capable of holding a single logical value or multiple logical values.
  • the decimal number ten may also be represented as a binary value of 1010 and a hexadecimal letter A. Therefore, a value includes any representation of information capable of being held in a computer system.
  • states may be represented by values or portions of values.
  • a first value such as a logical one
  • a second value such as a logical zero
  • reset and set in one embodiment, refer to a default and an updated value or state, respectively.
  • a default value potentially includes a high logical value, i.e. reset
  • an updated value potentially includes a low logical value, i.e. set.
  • any combination of values may be utilized to represent any number of states.
  • a non-transitory machine-accessible/readable medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form readable by a machine, such as a computer or electronic system.
  • a non-transitory machine- accessible medium includes random-access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage medium; flash storage devices; electrical storage devices; optical storage devices; acoustical storage devices; other form of storage devices for holding information received from transitory (propagated) signals (e.g., carrier waves, infrared signals, digital signals); etc., which are to be distinguished from the non-transitory mediums that may receive information there from.
  • RAM random-access memory
  • SRAM static RAM
  • DRAM dynamic RAM
  • ROM magnetic or optical storage medium
  • flash storage devices electrical storage devices
  • optical storage devices e.g., optical storage devices
  • acoustical storage devices e.g., optical storage devices
  • Instructions used to program logic to perform embodiments of the disclosure may be stored within a memory in the system, such as DRAM, cache, flash memory, or other storage. Furthermore, the instructions can be distributed via a network or by way of other computer readable media.
  • a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), but is not limited to, floppy diskettes, optical disks, Compact Disc, Read-Only Memory (CD-ROMs), and magneto-optical disks, Read-Only Memory (ROMs), Random Access Memory (RAM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), magnetic or optical cards, flash memory, or a tangible, machine-readable storage used in the transmission of information over the Internet via electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.). Accordingly
  • an apparatus comprises a storage device comprising a NAND flash memory, the storage device to program a plurality of cells of a first wordline of the NAND flash memory to cause a programmed cell of the first wordline to store a first number of bits; and program a plurality of cells of a second wordline that is adjacent to the first wordline to cause a programmed cell of the second wordline to store a second number of bits, wherein the first number and the second number are different.
  • the storage device is to program the plurality of cells of the first wordline in a single pass and to program the plurality of cells of the second wordline in a single pass.
  • the storage device is to program the plurality of cells of the first wordline completely prior to commencing to program the plurality of cells of the second wordline. In an embodiment, the storage device further to program a plurality of cells of a third wordline that is adjacent to the second wordline to cause a programmed cell of the third wordline to store the first number of bits. In an embodiment, the storage device is to program the plurality of cells of the second wordline after the storage device programs the plurality of cells of the first wordline and the plurality of cells of the third wordline.
  • the first number is two, such that the plurality of cells of the first wordline are programmed as multi-level cell (MLC) memory; and the second number is three, such that the plurality of cells of the first wordline are programmed as tri-level cell (TLC) memory.
  • the first number is three, such that the plurality of cells of the first wordline are programmed as tri-level cell (TLC) memory; and the second number is four, such that the plurality of cells of the first wordline are programmed as quad-level cell (QLC) memory.
  • the first number is one, such that the plurality of cells of the first wordline are programmed as single-level cell (SLC) memory; and the second number is two, such that the plurality of cells of the first wordline are programmed as multi-level cell (MLC) memory.
  • the storage device is further to erase the plurality of cells of the first wordline; and program the plurality of cells of the first wordline to cause a programmed cell of the first wordline to store the second number of bits.
  • the apparatus further comprises a data structure to specify an order in which wordlines of the NAND flash memory are to be programmed and an indication of whether the cells of the wordlines are to be programmed with the first number or the second number of bits.
  • a method comprises programming a plurality of cells of a first wordline of a NAND flash memory such that a programmed cell of the first wordline stores a first number of bits; and programming a plurality of cells of a second wordline that is adjacent to the first wordline, such that a programmed cell of the second wordline stores a second number of bits, wherein the first number and the second number are different.
  • the programming of the plurality of cells of the first wordline is performed in a single pass and the programming of the plurality of cells of the second wordline is performed in a single pass.
  • the programming of the plurality of cells of the first wordline is completed prior to the programming the plurality of cells of the second wordline being commenced.
  • the method further comprises programming a plurality of cells of a third wordline that is adjacent to the second wordline, such that a programmed cell of the third wordline stores the first number of bits.
  • the plurality of cells of the second wordline is programmed after the programming of the plurality of cells of the first wordline and the plurality of cells of the third wordline.
  • the first number is two, such that the plurality of cells of the first wordline are programmed as multi-level cell (MLC) memory; and the second number is three, such that the plurality of cells of the first wordline are programmed as tri-level cell (TLC) memory.
  • the first number is three, such that the plurality of cells of the first wordline are programmed as tri-level cell (TLC) memory; and the second number is four, such that the plurality of cells of the first wordline are programmed as quad-level cell (QLC) memory.
  • the first number is one, such that the plurality of cel ls of the first wordline are programmed as single-level cell (SLC) memory; and the second number is two, such that the plurality of cells of the first wordline are programmed as multi-level cell (MLC) memory.
  • the method further comprises erasing the plurality of cells of the first wordline; and programming the plurality of cells of the first wordline such that a programmed cell of the first wordline stores the second number of bits.
  • the method further comprises storing a data structure to specify an order in which wordlines of the NAND flash memory are to be programmed and an indication of whether the cells of the wordlines are to be programmed with the first number or the second number of bits.
  • the NAND flash memory is included in a solid state drive.
  • the plurality of cells of the first wordline are a first page of the NAND flash memory and the plurality of cells of the second wordline are a first page of the NAND flash memory.
  • a system comprises a processor to send data to a storage device and a storage device.
  • the storage device comprises a NAND flash memory; and a storage device controller to program a plurality of cells of a first wordline of the NAND flash memory to cause a programmed cell of the first wordline to store a first number of bits; and program a plurality of cells of a second wordline that is adjacent to the first wordline to cause a programmed cell of the second wordline to store a second number of bits, wherein the first number and the second number are different.
  • the storage device controller is to program the plurality of cells of the first wordline in a single pass and to program the plurality of cells of the second wordline in a single pass.
  • the first number is two, such that the plurality of cells of the first wordline are programmed as multi-level cell (MLC) memory; and the second number is three, such that the plurality of cells of the first wordline are programmed as tri- level cell (TLC) memory.
  • the first number is three, such that the plurality of cells of the first wordline are programmed as tri-level cell (TLC) memory; and the second number is four, such that the plurality of cells of the first wordline are programmed as quad- level cell (QLC) memory.
  • the system further comprises one or more of: a battery communicatively coupled to the processor, a display communicatively coupled to the processor, or a network interface communicatively coupled to the processor.
  • a system comprises means for programming a plurality of cells of a first wordline of a NAND flash memory to cause a programmed cell of the first wordline to store a first number of bits; and means for programming a plurality of cells of a second wordline that is adjacent to the first wordline to cause a programmed cell of the second wordline to store a second number of bits, wherein the first number and the second number are different.
  • the programming of the plurality of cells of the first wordline is performed in a single pass and the programming of the plurality of cells of the second wordline is performed in a single pass.
  • the system further comprises means for programming a plurality of cells of a third wordline that is adjacent to the second wordline, such that a programmed cell of the third wordline stores the first number of bits.
  • the first number is two, such that the plurality of cells of the first wordline are programmed as multi-level cell (MLC) memory; and the second number is three, such that the plurality of cells of the first wordline are programmed as tri-level cell (TLC) memory.
  • the first number is three, such that the plurality of cells of the first wordline are programmed as tri-level cell (TLC) memory; and the second number is four, such that the plurality of cells of the first wordline are programmed as quad-level cell (QLC) memory.
  • TLC tri-level cell
  • QLC quad-level cell

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)

Abstract

Dans un mode de réalisation, un appareil comprend un dispositif de stockage comprenant une mémoire flash NAND. Le dispositif de stockage est destiné à programmer une pluralité de cellules d'une première ligne de mot de la mémoire flash NAND pour amener une cellule programmée de la première ligne de mots à stocker un premier nombre de bits; et programmer une pluralité de cellules d'une seconde ligne de mots qui est adjacente à la première ligne de mots, pour amener une cellule programmée de la seconde ligne de mots à stocker un second nombre de bits, le premier nombre et le second nombre étant différents.
PCT/US2017/034911 2016-06-17 2017-05-29 Procédé et appareil pour programmer des lignes de mots d'une mémoire flash nand à l'aide de schémas de codage alternes WO2017218170A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201615185894A 2016-06-17 2016-06-17
US15/185,894 2016-06-17

Publications (1)

Publication Number Publication Date
WO2017218170A1 true WO2017218170A1 (fr) 2017-12-21

Family

ID=60664138

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2017/034911 WO2017218170A1 (fr) 2016-06-17 2017-05-29 Procédé et appareil pour programmer des lignes de mots d'une mémoire flash nand à l'aide de schémas de codage alternes

Country Status (1)

Country Link
WO (1) WO2017218170A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020047323A (ja) * 2018-09-14 2020-03-26 キオクシア株式会社 メモリシステム
EP3828891A1 (fr) * 2019-11-28 2021-06-02 Samsung Electronics Co., Ltd. Dispositif de stockage et son procédé de fonctionnement

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120023283A1 (en) * 2010-07-21 2012-01-26 Silicon Motion, Inc. Flash Memory Device and Method for Managing Flash memory Device
US20130336072A1 (en) * 2012-06-19 2013-12-19 Fusion-Io Adaptive voltage range management in non-volatile memory
US20140006688A1 (en) * 2012-07-02 2014-01-02 Super Talent Technology, Corp. Endurance and Retention Flash Controller with Programmable Binary-Levels-Per-Cell Bits Identifying Pages or Blocks as having Triple, Multi, or Single-Level Flash-Memory Cells
US20140198570A1 (en) * 2013-01-16 2014-07-17 Macronix International Co., Ltd. Programming multibit memory cells
US20150162086A1 (en) * 2013-12-05 2015-06-11 Sandisk Technologies Inc. Systems and Methods for Partial Page Programming of Multi Level Cells

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120023283A1 (en) * 2010-07-21 2012-01-26 Silicon Motion, Inc. Flash Memory Device and Method for Managing Flash memory Device
US20130336072A1 (en) * 2012-06-19 2013-12-19 Fusion-Io Adaptive voltage range management in non-volatile memory
US20140006688A1 (en) * 2012-07-02 2014-01-02 Super Talent Technology, Corp. Endurance and Retention Flash Controller with Programmable Binary-Levels-Per-Cell Bits Identifying Pages or Blocks as having Triple, Multi, or Single-Level Flash-Memory Cells
US20140198570A1 (en) * 2013-01-16 2014-07-17 Macronix International Co., Ltd. Programming multibit memory cells
US20150162086A1 (en) * 2013-12-05 2015-06-11 Sandisk Technologies Inc. Systems and Methods for Partial Page Programming of Multi Level Cells

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020047323A (ja) * 2018-09-14 2020-03-26 キオクシア株式会社 メモリシステム
EP3828891A1 (fr) * 2019-11-28 2021-06-02 Samsung Electronics Co., Ltd. Dispositif de stockage et son procédé de fonctionnement
US11322206B2 (en) 2019-11-28 2022-05-03 Samsung Electronics Co., Ltd. Storage device and operating method thereof

Similar Documents

Publication Publication Date Title
US10289313B2 (en) Method and apparatus for improving sequential reading in NAND flash
US10268407B1 (en) Method and apparatus for specifying read voltage offsets for a read command
US10714186B2 (en) Method and apparatus for dynamically determining start program voltages for a memory device
US9703494B1 (en) Method and apparatus for protecting lower page data during programming in NAND flash
US10186325B2 (en) Method and apparatus for shielded read to reduce parasitic capacitive coupling
US11693582B2 (en) Automatic read calibration operations
US20190102104A1 (en) Method and apparatus for per-deck erase verify and dynamic inhibit in 3d nand
US10331345B2 (en) Method and apparatus for reducing silent data errors in non-volatile memory systems
US10777271B2 (en) Method and apparatus for adjusting demarcation voltages based on cycle count metrics
US11200961B1 (en) Apparatus, system and method to log memory commands and associated addresses of a memory array
US9823880B1 (en) Method and apparatus for initiating pre-read operation before completion of data load operation
US10725933B2 (en) Method and apparatus for redirecting memory access commands sent to unusable memory partitions
US9852065B1 (en) Method and apparatus for reducing data program completion overhead in NAND flash
US20220114115A1 (en) Interleaving of heterogeneous memory targets
US20200313722A1 (en) Transmit crosstalk cancellation system
WO2017218170A1 (fr) Procédé et appareil pour programmer des lignes de mots d'une mémoire flash nand à l'aide de schémas de codage alternes
US10049752B1 (en) Method and apparatus for process corner compensation for memory state sensing
US20230064007A1 (en) Encoding additional states in a three-dimensional crosspoint memory architecture
US11139027B1 (en) Apparatus, system and method to reduce a read voltage across a memory cell and improve read sense margin
CN114078526A (zh) 在三维交叉点存储器架构中浮置用于取消选定地址线的解码器的设备、系统和方法
US20230154539A1 (en) Method and apparatus for improving write uniformity in a memory device
US11315644B2 (en) String current reduction during multistrobe sensing to reduce read disturb
US10229057B2 (en) Method and apparatus for avoiding bus contention after initialization failure
US12119057B2 (en) Read algorithms for three-dimensional crosspoint memory architectures

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17813770

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17813770

Country of ref document: EP

Kind code of ref document: A1