WO2017215377A1 - Procédé et dispositif de traitement d'erreur de mémoire permanente - Google Patents

Procédé et dispositif de traitement d'erreur de mémoire permanente Download PDF

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Publication number
WO2017215377A1
WO2017215377A1 PCT/CN2017/083815 CN2017083815W WO2017215377A1 WO 2017215377 A1 WO2017215377 A1 WO 2017215377A1 CN 2017083815 W CN2017083815 W CN 2017083815W WO 2017215377 A1 WO2017215377 A1 WO 2017215377A1
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Prior art keywords
address
memory
error
information
access instruction
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PCT/CN2017/083815
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English (en)
Chinese (zh)
Inventor
张晔
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中兴通讯股份有限公司
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Publication of WO2017215377A1 publication Critical patent/WO2017215377A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check

Definitions

  • the present application relates to, but is not limited to, the field of communications, and in particular, to a method and apparatus for processing hard memory errors.
  • a system's memory entity is generally composed of several memory particles. There are several memory cells in the particle, and each cell stores one bit (bit) of data. When there is an error in the memory, there may be 1 bit or multiple bits. Memory errors are generally classified into soft errors and hard errors according to the cause. Soft errors occur randomly. For example, factors such as sudden occurrence of electronic interference near the memory may cause memory soft errors.
  • ECC Error Checking and Correcting
  • the hard error is caused by hardware damage or defects, so the data is always incorrect, and such errors cannot be corrected.
  • Memory usually supports ECC checksum error correction function, which can automatically correct error in soft error of memory. It can be found but can not be corrected for hard errors.
  • core carrier-class routers/switches It always carries a large amount of user services. If there is a memory failure in the system (here, mainly a memory hard error), there is generally no other way, and the memory must be replaced again. However, this will interrupt the business for a period of time, and the consequences will be more serious.
  • the embodiment of the invention provides a method and a device for processing a memory hard error, so as to achieve Correct the hard error of the memory in case of interrupting the service.
  • a method for processing a memory hard error including: determining that a hard error of the first address of the memory occurs; correcting the memory information in the first address, and correcting the error
  • the latter memory information is stored in the non-faulty second address in the memory; a hardware breakpoint is inserted at the first address, wherein the hardware breakpoint is used to monitor whether the first address is accessed, And jumping from an access instruction to the first address to an access instruction to the second address.
  • determining that the first address of the memory has a hard error fault comprises: receiving the error detection correction ECC interrupt signal reported by the memory; searching for the corresponding one according to the ECC interrupt signal in the ECC error capture address register First address.
  • the method further includes: performing memory information of the first address for a predetermined number of times. And reading and writing a test to determine whether the first address is faulty; and when the test result indicates that the first address is faulty, determining that the first address has a hard error fault.
  • jumping from the access instruction to the first address to the access instruction to the second address comprises: receiving a break triggered by the access operation of the hardware breakpoint for the first address Pointing up abnormal information; performing at least one of: the breakpoint abnormality information characterizing the memory information of the first address is instruction information, jumping from an access instruction to the instruction information for reading the first address And the access instruction to the second address; when the breakpoint abnormality information indicates that the memory information of the first address is data information, jumping from an access instruction for reading data information of the first address And an access instruction to the second address; the breakpoint abnormality information represents that the memory information of the first address is data information, and jumps from an access instruction to write data information of the first address to a pair The access instruction of the second address.
  • jumping from the access instruction to the first address to the access instruction to the second address comprises: receiving an access instruction to the first address; calculating the first address to Deviation of the second address; correcting the deviation by the first address to obtain the second address, and jumping to an access instruction of the second address.
  • the method further comprises: jumping to a next instruction of an access instruction to the first address.
  • a memory hard error processing apparatus including: a determining module configured to determine that a first address of a memory has a hard error fault; and an error correction module configured to be the first address
  • the memory information is error-corrected, and the error-corrected memory information is stored in the memory-free second address;
  • the jump module is configured to insert a hardware breakpoint at the first address, wherein The hardware breakpoint is for monitoring whether the first address is accessed and jumping from an access instruction to the first address to an access instruction to the second address.
  • the determining module includes: a first receiving unit configured to receive the error detection correcting ECC interrupt signal reported by the memory; and a searching unit configured to be in the ECC error trapping address register according to the ECC interrupt signal Finding the corresponding first address.
  • the determining module further includes: a testing unit, configured to: after the searching unit searches for the corresponding first address in the ECC error trapping address register according to the ECC interrupt signal, The memory information of the first address is subjected to a predetermined number of read and write tests to determine whether the first address is faulty; and the determining unit is configured to determine that the first address has a hard error when the test result indicates that the first address is faulty .
  • the jump module further includes: a second receiving unit, configured to receive breakpoint abnormality information triggered by the access operation of the hardware breakpoint for the first address; first jump unit, setting In order to represent the memory information of the first address when the breakpoint abnormality information is instruction information, jump from an access instruction to the instruction information that reads the first address to an access instruction to the second address.
  • a second jump unit configured to: when the memory information indicating the first address is data information, the at least one of: performing operation on reading data information of the first address The access instruction jumps to an access instruction to the second address; jumps from an access instruction to the data information that writes the first address to an access instruction to the second address.
  • a storage medium is also provided.
  • the storage medium is arranged to store program code for performing the following steps:
  • the embodiment of the present invention first determines that a hard error fault occurs in the first address of the memory, and then performs error correction on the memory information in the first address, and stores the error-corrected memory information in the memory. a second address of the fault, and finally a hardware breakpoint is inserted at the first address, wherein the hardware breakpoint is used to monitor whether the first address is accessed and from an access instruction to the first address Jump to the access instruction to the second address.
  • the memory information of the first address with a hard error fault in the memory is transferred to the second address of the memory, and the access instruction for accessing the original first address is jumped to the access instruction of the second address, so that the access can be accessed.
  • FIG. 1 is a flow chart of a method for processing a memory hard error according to an embodiment of the present invention
  • FIG. 2 is a block diagram showing the structure of a memory hard error processing apparatus according to an embodiment of the present invention
  • FIG. 3 is a structural block diagram 1 of a memory hard error processing apparatus according to an embodiment of the present invention.
  • FIG. 4 is a structural block diagram 2 of a memory hard error processing apparatus according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a process of generating a device according to an embodiment of the present invention.
  • FIG. 6 is a flow chart of creating a special hardware data breakpoint exception handling function Vector1 in FIG. 5;
  • FIG. 7 is a flow chart of creating a special hardware instruction breakpoint exception handling function Vector2 in FIG. 5;
  • FIG. 8 is a flow chart of the original hardware breakpoint exception handling function Vector of the modified system of FIG. 5;
  • FIG. 9 is a flowchart of creating a memory ECC interrupt processing function vector_ecc in FIG. 5;
  • FIG. 10 is a flow chart of an ECC check error occurring in accordance with an embodiment of the present invention.
  • FIG. 11 is a process flow diagram of a hardware breakpoint exception occurring in accordance with an embodiment of the present invention.
  • FIG. 1 is a flowchart of a method for processing a memory hard error according to an embodiment of the present invention. As shown in FIG. 1, the process includes the following steps:
  • Step S102 determining that a hard error occurs in the first address of the memory
  • Step S104 performing error correction on the memory information in the first address, and storing the error-corrected memory information in the second address in the memory without failure;
  • Step S106 inserting a hardware breakpoint at the first address, wherein the hardware breakpoint is used to monitor whether the first address is accessed, and jumps from the access instruction to the first address to the access instruction to the second address.
  • the instruction of the second address so that the memory information in the first address where the hard error occurs can be accessed without interrupting the service and replacing the memory, avoiding the uncorrectable memory storage unit, and avoiding the program error or the system crash Such serious consequences have improved the stability of the system.
  • the execution body of the above steps may be a processor, a CPU, or Save the management unit, etc., but is not limited to this.
  • determining that the first address of the memory has a hard error fault includes:
  • the storage function of the first address may be detected, and after step S12, the method may further include:
  • test result indicates that the first address is faulty
  • jumping from an access instruction to the first address to an access instruction to the second address comprises:
  • the breakpoint abnormality information represents that the memory information of the first address is instruction information, and jumps from an access instruction to the instruction information that reads the first address to an access instruction to the second address.
  • the breakpoint abnormality information characterizing the memory information of the first address is data information, jumping from an access instruction for reading data information of the first address to an access instruction to the second address;
  • the breakpoint exception information characterizes the memory information of the first address as data information, jumping from an access instruction to the data information writing the first address to an access instruction to the second address.
  • jumping from an access instruction to the first address to an access instruction to the second address comprises:
  • the jump to the next instruction of the instruction that generates the breakpoint exception ie, the operation instruction of the first address access
  • the jump operation can be implemented in software by different functions, and can be constructed in the form of assembly language or binary code, and in which language (eg, C language, java, etc.) is used to construct the jump.
  • the transfer function is not limited in this embodiment:
  • A_ok (specified fault-free special memory address) is used to save the error-corrected data D_ok.
  • A1_code1 Vector1 entry address
  • A1_code2 corrected data read/write instruction address
  • A1_stack Vetor1 stack frame address
  • the function content is: 1. Save the value of each register of the breakpoint exception to A1_stack. 2. Analyze the instruction code C1_old that triggers the hardware breakpoint, calculate the specified memory address A_ok that retains the correct data, and the memory address A_error deviation of the ECC error.
  • A2_code Vector2 entry address
  • A2_stack Vetor2 stack frame address
  • the sink code C2_new is such an instruction: jump from the address of the sink code C2_new (the length of the sink code represented by the data D_ok at the A_ok+A_ok address) to the next sink code address of the trigger data breakpoint command C_old (C_old+C_old length). 2 from the address A2_stack restores the register values of the breakpoint exception field. 3. Jump to A_ok.
  • the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, by hardware, but in many cases, the former is A better implementation.
  • the technical solution of the present application can be embodied in the form of a software product stored in a storage medium (such as a ROM/RAM, a magnetic disk, an optical disk), and includes a plurality of instructions for making a terminal.
  • the device (which may be a cell phone, computer, server, or network device, etc.) performs the methods of various embodiments of the present invention.
  • a memory hard error processing device is also provided, which is used to implement the foregoing embodiments and implementation manners, and has not been described again.
  • the term "module” may implement a combination of software and/or hardware of a predetermined function.
  • the devices described in the following embodiments may be implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.
  • FIG. 2 is a structural block diagram of a memory hard error processing apparatus according to an embodiment of the present invention. As shown in FIG. 2, the apparatus includes:
  • the determining module 20 is configured to determine that the first address of the memory has a hard error fault
  • the error correction module 22 is configured to perform error correction on the memory information in the first address, and store the error-corrected memory information in the second address in the memory without failure;
  • the jump module 24 is configured to insert a hardware breakpoint at the first address, wherein the hardware breakpoint is used to monitor whether the first address is accessed, and jump from the access instruction to the first address to the second address Access to the instruction.
  • FIG. 3 is a block diagram showing the structure of a memory hard error processing apparatus according to an embodiment of the present invention.
  • the determining module 20 includes:
  • the first receiving unit 30 is configured to receive an error detection correction ECC interrupt signal reported by the memory
  • the searching unit 32 is configured to look up the corresponding first address in the ECC error trapping address register according to the ECC interrupt signal.
  • the determining module 20 further includes:
  • the test unit 34 is configured to: after the search unit searches for the corresponding first address in the ECC error trap address register according to the ECC interrupt signal, perform a predetermined number of read and write tests on the memory information of the first address to determine whether the first address is faulty. ;
  • the determining unit 36 is configured to determine that a hard error fault occurs at the first address when the test result indicates that the first address is faulty.
  • the device includes, in addition to all the modules shown in FIG. 2, the jump module 24 further includes:
  • the second receiving unit 40 is configured to receive breakpoint abnormality information triggered by an access operation of the hardware breakpoint for the first address;
  • the first jump unit 42 is configured to jump from the access instruction to the instruction information for reading the first address to the second when the memory information indicating the first address of the breakpoint abnormality information is instruction information Address access instruction;
  • the second jump unit 44 is configured to: when the memory information indicating that the first address is the data information, the at least one of: performing an operation from the access instruction for reading the data information of the first address Up to an access instruction to the second address; jumping from an access instruction to the data information writing the first address to an access instruction to the second address.
  • each of the above modules may be implemented by software or hardware.
  • the foregoing may be implemented by, but not limited to, the foregoing modules are all located in the same processor; or, the above modules are in any combination.
  • the forms are located in different processors.
  • the embodiment relates to a method for ensuring normal operation of the system under the premise of ensuring that the system does not restart when the storage unit in the memory granules has irreparable hardware damage in the embedded system.
  • the embodiment provides a method and device: when an uncorrectable hard error occurs in the memory of the embedded system, the system can continue to operate normally without restarting the system, and the data communication product can be significantly improved in the market application. Stability.
  • the memory controller supports ECC checksum error correction capabilities, as long as I
  • the memory used by us also supports the ECC check function, which can report an ECC interrupt to the CPU when an error occurs in the memory. After the ECC error occurs, the CPU gives the error address in the ECC error capture address register. At this time, the operating system can handle this ECC interrupt accordingly.
  • the CPU provides a hardware breakpoint function to monitor whether it is reading/writing the specified memory address. This type of read/write includes data read/write and instruction read, either of them, once The specified memory address is read/written and an exception is reported to the operating system. This application utilizes the above two functions provided by the CPU.
  • Breakpoint There are two kinds of hardware breakpoints: one is the instruction breakpoint, which is a breakpoint exception triggered when the CPU fetches the memory. When the breakpoint is abnormal, the address of the instruction itself is equal to the breakpoint address. One is the data breakpoint, which is when the CPU performs a read/write data operation on the address memory, which triggers a breakpoint exception. The result of the breakpoint exception is that the object address of the instruction operation is equal to the breakpoint address. Once the subsequent program triggers the memory address again, it enters a special processing flow to circumvent the wrong memory address.
  • FIG. 5 is a schematic diagram of a process of generating a device according to an embodiment of the present invention. As shown in FIG. 5, the implementation steps of this embodiment include:
  • step S501 the system starts.
  • step S502 A_ok (specified non-faulty special memory address) is used to save the error-corrected data D_ok.
  • Step S503 creating a special hardware data breakpoint exception handling function Vector1.
  • step S601 three special non-faulty memories A1_code1 (Vector1 entry address), A1_code2 (corrected data read/write instruction address) and A1_stack (Vetor1 stack frame address) are specified.
  • Step S602 placing a function in the form of assembly code at A1_code1, the function content is: 1, saving the register values of the breakpoint exception field to A1_stack.
  • Analyze the instruction code C1_old that triggers the hardware breakpoint calculate the specified memory address A_ok that retains the correct data, and the memory address A_error deviation of the ECC error. Correct and recreate the instruction code C1_new1 with this deviation (corrected data read and write) instruction). 3, then put the newly created instruction C1_new1 at a specified memory address A1_code2. 4.
  • add a branch code C1_new2 that jumps to the next assembly code address (C_old+C_old length) of the trigger instruction breakpoint instruction C_old. 5, recover the breakpoint exception field register values from the address A1_stack . 6, jump to the newly created instruction C1_new1.
  • step S603 Vector1 is created.
  • Step S504 creating a special hardware instruction breakpoint exception handling function Vector2.
  • Step S701 after the system is started, two special memory A2_code (Vector2 entry address) and A2_stack (Vetor2 stack frame address) are specified.
  • A2_code Vector2 entry address
  • A2_stack Vetor2 stack frame address
  • Step S702 placing a function in the form of a binary code at A2_code, the function content is: 1, the specified correct data storage address A_ok (specified non-faulty special memory address) is added to the sink code C2_new (corrected A_error)
  • the sink code C2_new is such an instruction: jump from the address of the sink code C2_new (the length of the sink code represented by the data D_ok at the address of A_ok+A_ok) to the next one of the trigger data breakpoint command C_old The code address (C_old+C_old length).
  • the code address (C_old+C_old length).
  • step S703 Vector2 is created.
  • Step S505 modifying the original hardware breakpoint exception processing function Vector of the system.
  • Step S801 determining whether the currently interrupted instruction is that the CPU has accessed the faulty memory address A_error, and if so, continues to determine whether the hardware breakpoint is an instruction breakpoint or a data breakpoint. If it is a data breakpoint, it jumps directly to the special data breakpoint exception handling function Vector1 created in step S503. If it is determined that the hardware breakpoint is an instruction breakpoint, then jump to the special created in step S504. The special hardware instruction breakpoint processing function Vector2. If the currently interrupted instruction is independent of the failed memory address A_error, it is executed according to the normal hardware breakpoint exception handling function Vector.
  • step S802 the Vector is modified.
  • step S506 a memory ECC interrupt processing function vector_ecc is created.
  • Step S901 after the CPU reports an ECC check error, it is determined whether it is a true hard error, and the soft error is excluded.
  • the method is: in the ECC interrupt handler, the memory address A_error of the error occurrence is obtained by the ECC error capture address register of the memory controller, and the data D_error is obtained by the ECC error capture data register of the memory controller, and is obtained by the ECC symptom register of the memory controller. Symptom code D_syndrome and translate to get which bit is faulty, calculate the correct data D_ok. Then, the memory address A_error with the ECC error is subjected to a certain number of 0/1 read/write tests to determine whether the memory address is still faulty.
  • the fault does not occur, it is judged as a soft error, and the previously calculated data D_ok is written back to the address. After A_error, the ECC interrupt processing is exited and the process ends. A fault is confirmed if the fault persists. Save the correct data D_ok to the specified special address A_ok. Make a hardware breakpoint at the faulty memory address A_error. Since a memory address may store data or store code, the address of the stored code may also be treated as data access. Therefore, A1 must simultaneously issue the instruction breakpoint Bc and the data breakpoint Bd.
  • step S902 the vector_ecc is modified.
  • step S507 the device is created.
  • the above steps S501 to S507 are the generation of the device or the creation process of the software.
  • FIG. 10 is a flowchart of a process in which an ECC check error occurs according to an embodiment of the present invention, including the following steps:
  • step S1001 an ECC check error occurs.
  • step S1002 the ECC interrupt processing vector_ecc is entered, and the A_error address is tested.
  • the data D_error is obtained through the ECC error capture data register of the memory controller, and the symptom code D_syndrome is obtained through the ECC symptom register of the memory controller and translated to obtain which bit is faulty, and the correct data D_ok is calculated.
  • Step S1003 performing a certain number of 0/1 readings on the memory address A_error where the ECC error occurs.
  • the write test determines whether the memory address is still faulty. If the fault does not occur, it is judged as a soft error.
  • the previously calculated data D_ok is written back to the address A_error and then exits the ECC interrupt processing, and step S1006 is performed. A fault is confirmed if the fault persists.
  • step S1004 the obtained correct data D_ok is saved to the specified special address A_ok.
  • step S1005 a hardware breakpoint is made at the fault memory address A_error.
  • step S1006 the process ends.
  • FIG. 11 is a flowchart of a process in which a hardware breakpoint exception occurs, including the following steps, according to an embodiment of the present invention:
  • step S1101 a hardware breakpoint exception occurs.
  • step S1102 the hardware breakpoint exception processing function Vector is entered to determine the cause of the interruption.
  • step S1103 it is determined whether the currently interrupted instruction is that the CPU has accessed the faulty memory address A_error, and if so, step S1105 is performed, and if no, step S1104 is performed.
  • Step S1104 is performed according to the normal hardware breakpoint exception processing function Vector, and step S1110 is performed.
  • step S1105 it is determined whether the hardware breakpoint cause is an instruction breakpoint or a data breakpoint. If it is a data breakpoint, step S1108 is performed, and if it is an instruction breakpoint, step S1106 is performed.
  • step S1107 the instruction C2_new is created and jumped to A_ok, and step S1110 is performed.
  • step S1108 a special data breakpoint exception handling function Vector1 is entered.
  • step S1109 new data access instructions C2_new1 and C2_new2 are created and jump to C2_new1.
  • step S1110 the program returns to the original process and continues to execute.
  • Embodiments of the present invention also provide a storage medium.
  • the above storage medium may be configured to store program code for performing the following steps:
  • the foregoing storage medium may include, but not limited to, a U disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.
  • ROM Read-Only Memory
  • RAM Random Access Memory
  • mobile hard disk a magnetic disk
  • magnetic disk a magnetic disk
  • optical disk a variety of media that can store program code.
  • the processor performs a hard error failure to determine the first address of the memory according to the stored program code in the storage medium
  • the processor performs error correction on the memory information in the first address according to the stored program code in the storage medium, and stores the error-corrected memory information in the second address in the memory without failure;
  • the processor performs a hardware breakpoint insertion at the first address according to the stored program code in the storage medium, wherein the hardware breakpoint is used to monitor whether the first address is accessed, and from the first address The access instruction jumps to the access instruction to the second address.
  • the modules or steps of the above embodiments of the present invention may be implemented by a general-purpose computing device, which may be centralized on a single computing device or distributed over a network of multiple computing devices, which may be implemented by computing devices.
  • the executed program code is implemented such that they can be stored in a storage device by a computing device, and in some cases, the steps shown or described can be performed in a different order than here, or they can be Separately made into individual integrated circuit modules, or make multiple modules or steps of them into a single integrated circuit module achieve.
  • embodiments of the invention are not limited to any specific combination of hardware and software.
  • the memory information in the first address where the hard error occurs can be accessed without interrupting the service and replacing the memory, and the memory unit that is not error-corrected is avoided, thereby avoiding the program error or the system crash. Serious consequences have improved the stability of the system.

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Abstract

La présente invention concerne un procédé et un dispositif qui permettent de traiter une erreur de mémoire permanente, le procédé consistant : à déterminer qu'une défaillance d'erreur permanente persistante se produit à une première adresse d'une mémoire (S102); à effectuer une correction d'erreur sur des informations de mémoire dans la première adresse, et à stocker les informations de mémoire après correction d'erreur dans une seconde adresse sans défaillance dans la mémoire (S104); à insérer un point d'interruption de matériel à la première adresse, le point d'interruption de matériel étant utilisé pour surveiller si un accès à la première adresse est effectué, et saute d'une instruction d'accès pour la première adresse à une instruction d'accès pour la seconde adresse (S106).
PCT/CN2017/083815 2016-06-16 2017-05-10 Procédé et dispositif de traitement d'erreur de mémoire permanente WO2017215377A1 (fr)

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CN201610436762.5A CN107516547A (zh) 2016-06-16 2016-06-16 内存硬错误的处理方法及装置

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