WO2017215373A1 - 输出时钟生成方法及装置 - Google Patents

输出时钟生成方法及装置 Download PDF

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Publication number
WO2017215373A1
WO2017215373A1 PCT/CN2017/083763 CN2017083763W WO2017215373A1 WO 2017215373 A1 WO2017215373 A1 WO 2017215373A1 CN 2017083763 W CN2017083763 W CN 2017083763W WO 2017215373 A1 WO2017215373 A1 WO 2017215373A1
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Prior art keywords
clock
sampling
fifo memory
input
value
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PCT/CN2017/083763
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English (en)
French (fr)
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胡大江
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中兴通讯股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
    • G06F11/2005—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication controllers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques

Definitions

  • the present invention relates to the field of optical transmission technologies, and in particular, to an output clock generation method and apparatus.
  • wavelength division equipment is required to achieve high-precision clock time transmission.
  • the time synchronization requirement of the wireless service is on the order of microseconds.
  • NTP Network Time Protocol
  • an Optical Transport Network (OTN) device is required to support a more accurate IEEE 1588 protocol, which is called a precision clock synchronization protocol standard for network measurement and control systems, commonly referred to as PTP. protocol.
  • the whole network clock synchronization can greatly improve the accuracy of the time transfer time.
  • the SSM algorithm is used between each node to determine the clock synchronization topology and the clock master-slave synchronization relationship to complete the clock extraction and transmission. If a node has two or more available clock source ports, you need to use the SSM algorithm to determine which port with the higher priority is used as the synchronization port.
  • the network node where the OTN device is located often has multiple available clock source ports, and when the currently selected clock source fails, the node is required to quickly detect the failure state and switch to the next alternative clock source, which involves Multi-channel clock source detection, selection and switching.
  • the clock boards of the OTN equipment often adopt the working mode of active and standby redundancy backup.
  • the main clock board fails, the device system clock needs to be quickly switched to the standby clock board. In this case, it also involves the detection, selection and switching of multiple clock sources.
  • the embodiment of the invention provides a method and a device for generating an output clock, so as to at least solve the problem that the clock source cannot be seamlessly switched in the related art.
  • an output clock generating method including: detecting that a current input clock is Whether it is valid; in the case that the current input clock is detected to be invalid, one of the plurality of sample values corresponding to the plurality of input clocks stored in advance is selected, wherein the plurality of sample values are local clocks for the plurality of input clocks The value obtained by sampling the sample; the output clock is generated according to the selected specified sample value and the local clock.
  • selecting one of the plurality of sample values corresponding to the respective input clocks stored in advance includes: selecting a first-in first-out FIFO memory corresponding to the input clock according to an active state and/or a priority of the plurality of input clocks Wherein, the FIFO memory pre-stores a sample value of the local clock pair input clock corresponding to the FIFO memory; and acquires the specified sample value from the selected FIFO memory.
  • the maximum value of the jitter of the corresponding input clock is:
  • the method further includes: if the valid states of the plurality of input clocks are all invalid, the specified sampling value is a preset standard sampling value.
  • the method before detecting whether the current input clock is valid, further includes: sampling and counting a plurality of input clocks by using a local clock to obtain a plurality of sample values; and storing the plurality of sample values in correspondence with the plurality of input clocks.
  • the FIFO memory In the FIFO memory.
  • the ratio of the frequency of each of the plurality of input clocks to the frequency of the local clock is less than a predetermined threshold.
  • detecting whether the current input clock is valid includes: determining whether a sampling value obtained by sampling the current input clock by the local clock exceeds a preset clock source sampling range; wherein, if the clock source sampling range is exceeded, determining the current input The clock is invalid; if the clock source sampling range is not exceeded, it is determined that the current input clock is valid.
  • the clock source sampling range is: [(Ftco/Fin)*(1-J1), (Ftco/Fin)*(1+J1)], where Ftco is the frequency of the local clock; Fin is the current input clock.
  • the frequency, J1 is the standard or specified maximum value of the current input clock jitter.
  • the local clock is a local temperature compensated crystal oscillator.
  • an output clock generating apparatus comprising: a detecting module configured to detect whether a current input clock is valid; and a selecting module configured to, in case detecting that a current input clock is invalid, from a pre- One of the plurality of sampling values corresponding to the stored input clocks is selected to be a specified sampling value; wherein, the plurality of sampling values are values obtained by sampling and counting a plurality of input clocks by the local clock; and the regeneration module is set to be selected according to the selected sampling The value and local clock generate the output clock.
  • the selection module is further configured to select a first-in first-out FIFO memory corresponding to the input clock according to an active state and/or a priority of the multiple input clocks; wherein the local clock pair corresponding to the FIFO memory is pre-stored in the FIFO memory The sampled value of the input clock; and the specified sample value is obtained from the selected FIFO memory.
  • the maximum value of the jitter of the corresponding input clock is:
  • the specified sampling value is a preset standard sampling value.
  • the device further includes: a sampling module, configured to sample and count a plurality of input clocks by using a local clock to obtain a plurality of sampling values; and the storage module is configured to store the plurality of sampling values in correspondence with the plurality of input clocks FIFO storage In the device.
  • a sampling module configured to sample and count a plurality of input clocks by using a local clock to obtain a plurality of sampling values
  • the storage module is configured to store the plurality of sampling values in correspondence with the plurality of input clocks FIFO storage In the device.
  • the detecting module is further configured to determine whether the sampling value obtained by sampling the current input clock by the local clock exceeds a preset clock source sampling range; wherein, if the sampling range of the clock source is exceeded, determining that the current input clock is invalid; It is determined that the current input clock is valid without exceeding the sampling range of the clock source.
  • the clock source sampling range is: [(Ftco/Fin)*(1-J1), (Ftco/Fin)*(1+J1)], where Ftco is the frequency of the local clock; Fin is the current input clock.
  • the frequency, J1 is the standard or specified maximum value of the current input clock jitter.
  • the local clock is a local temperature compensated crystal oscillator.
  • a storage medium is also provided.
  • the storage medium is configured to store program code for performing the steps of: detecting whether the current input clock is valid; and selecting one of a plurality of sample values corresponding to the plurality of input clocks stored in advance, in case detecting that the current input clock is invalid
  • the sampling value is specified; wherein, the plurality of sampling values are values obtained by sampling and counting a plurality of input clocks by the local clock; and generating an output clock according to the selected specified sampling value and the local clock.
  • the present invention since a specified sampling value is directly selected from a plurality of sampling values corresponding to a plurality of input clocks stored in advance in the case where the current input clock is detected to be invalid, an output clock is generated according to the selected specified sampling value and the local clock. Therefore, the output clock is glitch-free, and there is no periodicity missing, so that the clock can be seamlessly switched. Therefore, the problem that the clock source cannot be seamlessly switched can be solved.
  • FIG. 1 is a structural block diagram of an operational architecture of an output clock generation method according to an embodiment of the present invention
  • FIG. 2 is a flow chart of an output clock generation method according to an embodiment of the present invention.
  • FIG. 3 is a flow chart of a method for implementing a clock source failure detection and seamless switching circuit according to a preferred embodiment of the present invention
  • FIG. 4 is a circuit block diagram of an output clock provided in accordance with a preferred embodiment of the present invention.
  • FIG. 5 is a structural block diagram of an output clock generating apparatus according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of an input clock cycle sample counting module of a device according to a preferred embodiment of the present invention.
  • FIG. 8 is an algorithm state machine ASMD diagram of a failure detection module in accordance with a preferred embodiment of the present invention.
  • FIG. 9 is a block diagram showing the structure of a clock regeneration circuit module in accordance with a preferred embodiment of the present invention.
  • FIG. 1 is a structural block diagram of an operation architecture of an output clock generation method according to an embodiment of the present invention.
  • the architecture includes: a central processing unit CPU, a field editable gate array FPGA, a plurality of client ports, a plurality of line side ports, and a frequency multiplication module, wherein the FPGA is from each client port and/or line side.
  • the predetermined rule may be a priority of each service recovery clock, the priority The level can be configured by the CPU, and in order to adapt to the service processing of each client port and/or line side port, the output clock may need to be multiplied.
  • the embodiment of the present application can be applied to the scenario of multiple clock source selection and active/standby clock switching in the OTN device clock transmission scheme, but is not limited thereto.
  • FIG. 2 is a flowchart of an output clock generation method according to an embodiment of the present invention. As shown in FIG. 2, the flow includes the following steps:
  • Step S202 detecting whether the current input clock is valid
  • Step S204 in the case that the current input clock is detected to be invalid, select one of the plurality of sample values corresponding to the plurality of input clocks stored in advance, wherein the plurality of sample values are local clocks for the plurality of input clocks. The value obtained by sampling the count;
  • Step S206 generating an output clock according to the selected specified sample value and the local clock.
  • the foregoing step S204 may be performed to select a first-in first-out FIFO memory corresponding to an input clock according to an active state and/or a priority of the plurality of input clocks; wherein the FIFO memory is pre-stored locally Clock sample value of the input clock corresponding to the FIFO memory; the specified sample value is obtained from the selected FIFO memory.
  • the priority of the plurality of input clocks may be preset, and each of the plurality of input clocks corresponds to a FIFO memory, and the FIFO may buffer the jitter of the input clock itself.
  • the FIFO memory corresponding to an input clock is selected according to the effective state and priority of a plurality of input clocks. For example, there are four input clocks, and the states of the input clock 1, the input clock 2, the input clock 3, and the input clock 4 are respectively It is: invalid, valid, valid, and effective; the priority of the four input clocks is from high to low: input clock 1, input clock 2, input clock 3, and input clock 4. When the current input clock fails, the status is valid.
  • the input clocks are: input clock 2, input clock 3, and input clock 4; and input clock 2, input clock 3, and input clock 4 have the highest priority, so the selected FIFO memory is the FIFO memory corresponding to input clock 2. . For multiple losses based on The active state or priority of the incoming clock selects the FIFO memory corresponding to an input clock, and will not be described here.
  • the priority of the multiple input clocks may be dynamically updated by the application software through the SSM algorithm and/or flexibly configured by the underlying memory provided by the logic, but is not limited thereto.
  • the FIFO has an empty/full exception, which in turn causes the output clock frequency to be distorted.
  • the frequency of multiple input clocks is usually obtained by dividing the recovery clock Ft of each service port. Therefore, it can be considered that the jitter of the input clock does not exceed the jitter of Ft at most; usually carried by OTN
  • the service for example, SDH service
  • the depth of the FIFO memory can be obtained as 6, and the FIFO memory corresponding to the input clock in the standby state needs to buffer at least 3 data to satisfy the buffer requirement.
  • the specified sampling value is a preset standard sampling value, that is, in a case where all clocks are invalid, a standard may be provided.
  • the sampled value is used to generate an output clock, which means that even if all clocks fail, there is still a local clock output available for downstream modules.
  • the method may further include: sampling and counting a plurality of input clocks by using a local clock to obtain a plurality of sample values; storing the plurality of sample values in the plurality of inputs
  • the clock corresponds to the FIFO memory.
  • the sampling data of the input clock is temporarily stored by the FIFO memory.
  • the ratio of the frequency of each of the plurality of input clocks to the frequency of the local clock is less than a predetermined threshold, and may be based on a ratio of the frequency of the input clock to the frequency of the local clock of each of the plurality of input clocks.
  • the above-mentioned local clock and input clock are selected on the principle of less than a predetermined threshold, so that the selected local clock and input clock are such that the noise introduced by quantization is small, and thus is almost negligible for the OTN transmission device.
  • the step S202 may be performed as follows: determining whether the sampling value obtained by sampling the current input clock by the local clock exceeds a preset sampling range of the clock source; wherein, when the sampling range of the clock source is exceeded Determines that the current input clock is invalid; if the clock source sampling range is not exceeded, it determines that the current input clock is valid.
  • the input clock can be restored to the active state after the failure state needs to pass a plurality of consecutive legal sample values.
  • sampling range of the above clock source may be: [(Ftco/Fin)*(1-J1), (Ftco/Fin)*(1+J1)], where Ftco is the frequency of the local clock; Fin is The frequency of the current input clock, J1 is the maximum value of the standard or specified current input clock jitter.
  • the sampling range of the clock source is [69, 131].
  • the local clock may be a local temperature-compensated crystal oscillator having a relatively high frequency and relatively stable accuracy.
  • the above method can realize the seamless switching of the clock, and can also solve the service flashing caused by the clock source switching. Clock time drive jitter and other issues.
  • execution body of the foregoing method may be the FPGA module in the architecture shown in FIG. 2 above, but is not limited thereto.
  • the preferred embodiment of the present invention provides a method for implementing multi-channel clock source failure detection and seamless handover, and is particularly suitable for a multi-channel source selection and a master-slave clock switching scenario in an OTN device clock time transmission scheme, which is inexpensive and effective. Solve the problem of service flashing, clock time transmission jitter caused by clock source switching.
  • the solution includes: input clock cycle sampling and counting module and related parameter setting method, sampling and counting result storage method; failure detecting module and related parameter setting method; clock selection and seamless switching circuit module; clock regeneration module; and the above module
  • the connection between the two. 3 is a flowchart of a method for implementing a clock source failure detection and seamless switching circuit according to a preferred embodiment of the present invention. As shown in FIG. 3, the method includes:
  • Judgment judge whether it is invalid according to the count value
  • Cache store valid sample values into the corresponding FIFO
  • Choice select the appropriate FIFO read sample value according to the current state, and seamlessly switch as needed;
  • Clock regeneration The output clock is regenerated using the local clock and the sampled values read.
  • the input clock cycle sampling method is mainly: using a high-precision stable clock with a frequency of Ftco and a frequency inputting a Fin input clock. Perform periodic sampling and counting; the jitter (quantization noise) introduced by this module is Fin/Ftco (unit UI), which is used as the basis for selecting Ftco and Fin.
  • the parameter selection Ftco is 100 times that of Fin, which is introduced by quantization.
  • the noise is 0.01 UI, which is almost negligible for OTN transmission equipment.
  • the frequency is the Ftco clock using a local temperature compensated crystal.
  • the failure detecting method mainly includes: configuring a clock walking range according to a standard or a specified input clock source jitter maximum value J (unit: UI): [(Ftco/Fin)*(1-J), (Ftco/Fin )*(1+J)], according to the above formula and appropriate rounding of the result, when the value exceeds the range, it is judged as a clock failure immediately, and in the case of a failure state, the clock source can be passed after a plurality of consecutive legal sample values. Return to a valid state.
  • the sampling result storage method mainly includes: using a FIFO to temporarily store sampling data and setting basis of related parameters such as FIFO depth and water level.
  • the FIFO is used to buffer the jitter of the input clock itself.
  • the purpose and basis of the FIFO-related parameter selection are: avoiding the jitter and causing the FIFO to have an empty/full exception, which in turn causes the output clock frequency to be distorted. For example, set the reasonable maximum jitter of the clock source to J (unit: UI).
  • the multi-channel clock source Fin of the solution is usually obtained by dividing the recovery clock Ft of each service port, so it can be considered that the jitter of the Fin does not exceed the jitter of the Ft at the maximum.
  • the service carried by the OTN for example, SDH service
  • the depth of the FIFO can be obtained as 6, and the FIFO corresponding to the clock source in the standby state needs to cache at least 3 data, thereby satisfying the buffer. Claim.
  • the clock regeneration method mainly includes: sampling values taken from a FIFO corresponding to the currently selected clock, and regenerating an output clock Fout by using the local crystal clock Ftco, that is, ensuring that Fout is consistent with the selected input clock frequency.
  • the clock seamless switching method mainly includes: according to the current configuration of the input clock detection state and the clock source priority, selecting a corresponding FIFO for the clock regeneration module to obtain the sampling value M; when the currently selected clock fails, the module does not immediately execute the M value. Switching of the source until the regeneration module completes the regeneration of this clock cycle to achieve seamless switching; when all clocks fail, the module provides a preset M value for the regeneration module to use, so even if all clock sources are In the event of a failure, there is still a local clock output for use by downstream modules.
  • the priority of each clock source is dynamically updated by the application software through the SSM algorithm and flexibly configured through the underlying registers provided by the logic.
  • the method described in the preferred embodiment can quickly switch to an alternate clock source when the currently selected clock fails, while not introducing the least-failed clock into the output clock.
  • the output clock is guaranteed to have no glitch and no period missing, that is, the clock is seamlessly switched.
  • a local clock output can still be provided for use by downstream modules when all clock sources fail.
  • the relevant performance parameters are theoretically controllable. It is especially applicable to the scenario of multi-channel service recovery clock source selection and active/standby clock switching in the OTN device clock time transmission scheme. It is inexpensive and effective to solve the problems of service flashing and clock time transmission jitter caused by clock source switching. And with some inspiration, it can be extended to other scenarios.
  • the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, by hardware, but in many cases, the former is A better implementation.
  • the technical solution of the present invention which is essential or contributes to the prior art, may be embodied in the form of a software product stored in a storage medium (such as ROM/RAM, disk,
  • the optical disc includes a number of instructions for causing a terminal device (which may be a cell phone, a computer, a server, or a network device, etc.) to perform the methods described in various embodiments of the present invention.
  • an output clock generating device is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments, and has not been described again.
  • the term "module” may implement a combination of software and/or hardware of a predetermined function.
  • the apparatus described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.
  • FIG. 5 is a structural block diagram of an output clock generating apparatus according to an embodiment of the present invention. As shown in FIG. 5, the apparatus includes:
  • the detecting module 52 is configured to detect whether the current input clock is valid
  • the selecting module 54 is connected to the detecting module 52, and configured to select one of the plurality of sampling values corresponding to the plurality of input clocks stored in advance, in the case that the current input clock is detected to be invalid; wherein, the plurality of samplings The value obtained by sampling and counting multiple input clocks by the local clock;
  • the regeneration module 56 is coupled to the selection module 54 for generating an output clock based on the selected designated sample value and the local clock.
  • the selection module 54 directly selects one of the plurality of sample values corresponding to the plurality of input clocks stored in advance, and the regeneration module 56 selects according to the selected one. Specify the sampled value and the local clock to generate the output clock, so that the output clock has no glitch, no periodic missing, The clock can be seamlessly switched, so that the problem of seamless switching of the clock source cannot be solved.
  • the selecting module 54 is further configured to select a first-in first-out FIFO memory corresponding to an input clock according to an active state and/or a priority of the plurality of input clocks; wherein the FIFO memory is pre-stored There is a sample value of the input clock corresponding to the FIFO memory by the local clock; and the specified sample value is obtained from the selected FIFO memory.
  • the priority of the plurality of input clocks may be preset, and each of the plurality of input clocks corresponds to a FIFO memory, and the FIFO may buffer the jitter of the input clock itself. It should be noted that the priority of the multiple input clocks may be dynamically updated by the application software through the SSM algorithm and/or flexibly configured by the underlying memory provided by the logic, but is not limited thereto.
  • the FIFO has an empty/full exception, which in turn causes the output clock frequency to be distorted.
  • the specified sampling value is a preset standard sampling value, that is, in a case where all the clocks are invalid, the selection module 54 is used.
  • a standard sample value can be provided for use by the regeneration module 56 to generate an output clock, i.e., even if all clocks fail, there can still be a local clock output for use by the downstream module.
  • the apparatus further includes: a sampling module, configured to sample and count a plurality of input clocks by using a local clock to obtain a plurality of sampling values; and the storage module is connected to the sampling module and the selection module 54. Used to store multiple sample values in a FIFO memory corresponding to multiple input clocks.
  • the ratio of the frequency of each of the plurality of input clocks to the frequency of the local clock is less than a predetermined threshold, and may be based on a ratio of the frequency of the input clock to the frequency of the local clock of each of the plurality of input clocks.
  • the above-mentioned local clock and input clock are selected on the principle of less than a predetermined threshold, so that the selected local clock and input clock are such that the noise introduced by quantization is small, and thus is almost negligible for the OTN transmission device.
  • the detecting module 52 may be further configured to determine whether the sampling value obtained by sampling the current input clock by the local clock exceeds a preset sampling range of the clock source; wherein, when the sampling range of the clock source is exceeded Next, determine that the current input clock is invalid; if the clock source sampling range is not exceeded, determine that the current input clock is valid.
  • the input clock can be restored to the active state after the failure state needs to pass a plurality of consecutive legal sample values.
  • sampling range of the above clock source is: [(Ftco/Fin)*(1-J1), (Ftco/Fin)*(1+J1)], where Ftco is the frequency of the local clock; Fin is the current Enter the frequency of the clock, J1 is the standard or the maximum value of the current input clock jitter specified.
  • the local clock may be a relatively high frequency and a relatively stable local temperature. Fill the crystal.
  • the above device can realize the seamless switching of the clock, and can also solve the problems of service flashing, clock time transmission jitter and the like caused by clock source switching.
  • the above output clock generating device may be located in the FPGA in the running architecture shown in FIG. 2, but is not limited thereto.
  • the preferred embodiment is applied in the scenario where the active/standby clock board switching and the SSM clock source selection algorithm are implemented in the OTN device clock time transmission scheme.
  • the block diagram of the seamless switching circuit for clock failure detection is shown in Figure 4.
  • the relevant circuit modules are written in Verilog HDL language and implemented on the FPGA. Since the Verilog code is too long and does not show detailed code, only the implementation points of each module and parameters are elaborated separately.
  • FIG. 6 is a schematic diagram of an input clock cycle sampling and counting module of a device according to a preferred embodiment of the present invention, as shown in FIG. 6: Fin is selected to be 1.944 Mhz during implementation, and Ftco is selected as a local temperature-compensated crystal oscillator of 194.4 Mhz. According to the Fin/Ftco calculation formula, it can be concluded that the jitter introduced by the system due to quantization is at most 0.01 UI. First, the input clock signal Fin is synchronized to the Ftco clock domain, and a rising edge pulse is generated. The D flip-flop chain is used to eliminate the asynchronous clock domain metastable problem. The counter clearing edge is driven by the rising edge of Fin, so that each cycle of Fin is counted under the Ftco clock.
  • the above-mentioned input clock cycle adopts a counting module corresponding to the sampling module in the above embodiment.
  • the sampling count result is stored in the FIFO.
  • the purpose is to buffer the jitter of the input clock.
  • the write end of the FIFO is driven by the sampling counter module.
  • the read end of the FIFO is mainly controlled by the clock regeneration module and the FIFO water level.
  • 7 is an algorithm state machine ASMD diagram of a FIFO read end, as shown in FIG. 7, mainly composed of two states: a Backup state and a Selected state, in accordance with a preferred embodiment of the present invention.
  • the read signal of the FIFO in the Backup state is controlled by the water level of the FIFO. According to the calculation formula and the calculation result, the FIFO water level control of the Backup state is optimal at 3, and is read and discarded when it exceeds 3.
  • the FIFO read signal is mainly controlled by the clock regeneration module.
  • the module completes one clock cycle generation, it reads a data from the selected FIFO, that is, whether an external request signal (Rd_req) is received.
  • Rd_req an external request signal
  • the failure detection module (corresponding to the detection module 52 in the above embodiment), the service jitter carried by the OTN usually does not exceed 0.3 UI (for example, SDH service).
  • the range of the selected clock is [69, 131], and when the sampled value exceeds the range, the clock is judged as being invalid.
  • the clock source can be passed after a plurality of consecutive legal samples.
  • the ASMD diagram is shown in Figure 8.
  • the clock regeneration module (corresponding to the regeneration module 86 in the above embodiment) mainly includes: taking the sampling value from the FIFO corresponding to the currently selected clock, and regenerating an output clock Fout by using the local crystal clock Ftco, that is, ensuring Fout and selecting The input clock frequency is the same.
  • the edge trigger counter counts under the clock Ftco, and when the count value cnt is less than or equal to half of the sample value read by the FIFO (the half value is obtained by shifting in the implementation circuit), the regenerative clock outputs a high level period. On the contrary, the regenerative clock outputs a low period.
  • the cnt is equal to the value, the counter is cleared, and the new M is read from the FIFO and the next generation cycle is entered.
  • the clock seamless switching circuit module (corresponding to the selecting module 54 in the above embodiment) is mainly responsible for the coordinated control of the above modules, and according to the detection state of the input clock source and the current configuration of the priority, the corresponding FIFO is selected for the clock regeneration module to obtain.
  • Sample value M When the currently selected clock fails, the module does not immediately switch the M value source until the regeneration module completes the regeneration of the clock cycle, thereby achieving the purpose of lossless switching; when all clocks fail, the module provides a pre- Let the M value be used by the regenerative module. In the implementation process, the value is chosen to be 100. Therefore, even if all clock sources fail, there is still a local clock output of 1.944Mhz clock for the downstream module.
  • the priority of each clock source is dynamically updated by the application software through the SSM algorithm, and configured by the underlying registers provided by the logic, thereby achieving flexible configuration.
  • each of the above modules may be implemented by software or hardware.
  • the foregoing may be implemented by, but not limited to, the foregoing modules are all located in the same processor; or, the above modules are in any combination.
  • the forms are located in different processors.
  • Embodiments of the present invention also provide a storage medium.
  • the above storage medium may be set to store program code for executing the steps of the method in Embodiment 1.
  • the foregoing storage medium may include, but not limited to, a USB flash drive, a Read-Only Memory (ROM), a Random Access Memory (RAM), a mobile hard disk, and a magnetic memory.
  • ROM Read-Only Memory
  • RAM Random Access Memory
  • a mobile hard disk e.g., a hard disk
  • magnetic memory e.g., a hard disk
  • the processor performs the steps of the method in Embodiment 1 according to the stored program code in the storage medium.
  • modules or steps of the present invention described above can be implemented by a general-purpose computing device that can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein.
  • the steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof are fabricated as a single integrated circuit module.
  • the invention is not limited to any specific combination of hardware and software.
  • the present disclosure is applicable to the field of optical transmission technology, so that the output clock is glitch-free and has no periodicity missing, thereby enabling seamless switching of the clock. Therefore, the problem of seamless switching of the clock source cannot be solved.

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Abstract

一种输出时钟生成方法及装置；其中，该方法包括：检测当前输入时钟是否有效（S202）；在检测到当前输入时钟失效的情况下，从预先存储的多个输入时钟对应的多个采样值中选择一个指定采样值；其中，多个采样值为本地时钟对多个输入时钟进行采样计数得到的值（S204）；根据选择的指定采样值和本地时钟生成输出时钟（S206）。上述方法解决了无法实现时钟源的无缝切换的问题。

Description

输出时钟生成方法及装置 技术领域
本发明涉及光传输技术领域，具体而言，涉及一种输出时钟生成方法及装置。
背景技术
随着无线业务4G及LTE的发展，以及波分设备的下沉组网应用，要求波分设备可以实现高精度的时钟时间传送。无线业务对时间同步的要求在微秒量级，采用基本纯软件方式实现的网络时间协议(Network Time Protocol，简称NTP)无法满足应用的要求。为了达到无线业务时间同步的精度，要求光传送网(Optical Transport Network，简称OTN)设备能够支持更精确的IEEE 1588协议，其全称为：网络测量和控制系统的精密时钟同步协议标准，通常简称PTP协议。
在实现PTP协议的过程中，全网时钟同步可以大大提高时间传送时间的精度。在构建时钟同步网络的时候，各节点之间采用SSM算法确定时钟同步的拓扑结构以及时钟主从同步关系从而完成时钟的抽取与传递。如果节点有两个或者更多的可用时钟来源端口，则需要用SSM算法确定使用优先级更高的端口作为同步端口。OTN设备所在的网络节点往往就存在多路可用时钟源端口，并且当前所选时钟源失效时，要求节点快速的检测到这一失效状态并切换到下个备选的时钟源上去，这就涉及到多路时钟源检测、选择与切换。
同时为了满足设备长期稳定运行的需求，OTN设备的时钟板往往采用主备冗余备份的工作方式。当主时钟板出现故障的时候，需要把设备系统时钟迅速切换到备用时钟板上。这种情况下，也涉及到多路时钟源的检测、选择与切换。
在上述两种多路时钟源选择切换的场景中，为了不影响业务传输以及时钟时间传输性能。均需要迅速检测当前所选时钟失效状态，并切换到下个备选的时钟源上去，且要求在执行切换过程中不引入毛刺，时钟周期缺失，大抖动等副作用。现有技术解决方案往往采用专用的时钟管理芯片来解决上述问题，这无疑是添加了设备成本。在现有的技术文献中，也无整套的低成本解决方案。例如：有专门描述无毛刺时钟切换电路的专利，但该电路仅仅滤除了时钟切换过程中的毛刺，但无法保证不引入时钟周期缺失和较大抖动。
因此，如何采用一种廉价且有效的解决方案来实现上述场景中多路时钟源失效检测及无缝切换的需求，是亟待关注和解决的问题。
针对相关技术中的上述技术问题，目前尚未提出有效的解决方案。
发明内容
本发明实施例提供了一种输出时钟生成方法及装置，以至少解决相关技术中无法实现时钟源的无缝切换的问题。
根据本发明的一个实施例，提供了一种输出时钟生成方法，包括：检测当前输入时钟是 否有效；在检测到当前输入时钟失效的情况下，从预先存储的多个输入时钟对应的多个采样值中选择一个指定采样值；其中，多个采样值为本地时钟对多个输入时钟进行采样计数得到的值；根据选择的指定采样值和本地时钟生成输出时钟。
可选地，从预先存储的各个输入时钟对应的多个采样值中选择一个指定采样值包括：根据多个输入时钟的有效状态和/或优先级，选择一个输入时钟对应的先入先出FIFO存储器；其中，FIFO存储器中预先存储有本地时钟对与FIFO存储器对应的输入时钟的采样值；从选择的FIFO存储器中获取指定采样值。
可选地，FIFO存储器的水位为：N＝ceiling(1/(1-J)+1)；FIFO存储器的深度为2N；其中，ceiling()为向上取整函数，J为预定的与FIFO存储器对应的输入时钟的抖动的最大值。
可选地，该方法还包括，在多个输入时钟的有效状态都为失效的情况下，指定采样值为预先设置的标准采样值。
可选地，在检测当前输入时钟是否有效之前，该方法还包括：采用本地时钟对多个输入时钟进行采样计数，得到多个采样值；将多个采样值存储在与多个输入时钟对应的FIFO存储器中。
可选地，多个输入时钟中的每一个输入时钟的频率与本地时钟的频率之比小于预定阈值。
可选地，检测当前输入时钟是否有效包括：判断本地时钟对当前输入时钟进行采样得到的采样值是否超过预先设置的时钟源采样范围；其中，在超过时钟源采样范围的情况下，确定当前输入时钟失效；在没有超过时钟源采样范围的情况下，确定当前输入时钟有效。
可选地，时钟源采样范围为：[(Ftco/Fin)*(1-J1)，(Ftco/Fin)*(1+J1)]，其中，Ftco为本地时钟的频率；Fin为当前输入时钟的频率，J1为标准或者规定的当前输入时钟抖动的最大值。
可选地，本地时钟为本地温补晶振。
根据本发明的另一个实施例，提供了一种输出时钟生成装置，包括：检测模块，设置为检测当前输入时钟是否有效；选择模块，设置为在检测到当前输入时钟失效的情况下，从预先存储的多个输入时钟对应的多个采样值中选择一个指定采样值；其中，多个采样值为本地时钟对多个输入时钟进行采样计数得到的值；再生模块，设置为根据选择的指定采样值和本地时钟生成输出时钟。
可选地，选择模块还设置为根据多个输入时钟的有效状态和/或优先级，选择一个输入时钟对应的先入先出FIFO存储器；其中，FIFO存储器中预先存储有本地时钟对与FIFO存储器对应的输入时钟的采样值；以及从选择的FIFO存储器中获取指定采样值。
可选地，FIFO存储器的水位为：N＝ceiling(1/(1-J)+1)；FIFO存储器的深度为2N；其中，ceiling()为向上取整函数，J为预定的与FIFO存储器对应的输入时钟的抖动的最大值。
可选地，在多个输入时钟的有效状态都为失效的情况下，指定采样值为预先设置的标准采样值。
可选地，该装置还包括：采样模块，设置为采用本地时钟对多个输入时钟进行采样计数，得到多个采样值；存储模块，设置为将多个采样值存储在与多个输入时钟对应的FIFO存储 器中。
可选地，检测模块还设置为判断本地时钟对当前输入时钟进行采样得到的采样值是否超过预先设置的时钟源采样范围；其中，在超过时钟源采样范围的情况下，确定当前输入时钟失效；在没有超过时钟源采样范围的情况下，确定当前输入时钟有效。
可选地，时钟源采样范围为：[(Ftco/Fin)*(1-J1)，(Ftco/Fin)*(1+J1)]，其中，Ftco为本地时钟的频率；Fin为当前输入时钟的频率，J1为标准或者规定的当前输入时钟抖动的最大值。
可选地，本地时钟为本地温补晶振。
根据本发明的又一个实施例，还提供了一种存储介质。该存储介质设置为存储用于执行以下步骤的程序代码：检测当前输入时钟是否有效；在检测到当前输入时钟失效的情况下，从预先存储的多个输入时钟对应的多个采样值中选择一个指定采样值；其中，多个采样值为本地时钟对多个输入时钟进行采样计数得到的值；根据选择的指定采样值和本地时钟生成输出时钟。
通过本发明，由于在检测到当前输入时钟失效的情况下，直接从预先存储的多个输入时钟对应的多个采样值中选择一个指定采样值，根据选择的指定采样值和本地时钟生成输出时钟，进而使得输出时钟无毛刺，无周期性缺失，进而能够实现时钟的无缝切换，因此，可以解决无法实现时钟源的无缝切换的问题。
附图说明
此处所说明的附图用来提供对本发明的进一步理解，构成本申请的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1是本发明实施例的一种输出时钟生成方法的运行架构的结构框图；
图2是根据本发明实施例的输出时钟生成方法的流程图；
图3是根据本发明优选实施例提供的实现时钟源失效检测及无缝切换电路的方法流程图；
图4是根据本发明优选实施例提供的输出时钟的电路原理框图；
图5是根据本发明实施例的输出时钟生成装置的结构框图；
图6是根据本发明优选实施例提供的装置的输入时钟周期采样计数模块的示意图；
图7是根据本发明优选实施例的FIFO读出端的算法状态机ASMD图；
图8是根据本发明优选实施例的失效检测模块的算法状态机ASMD图；
图9是根据本发明优选实施例的时钟再生电路模块的结构示意图。
具体实施方式
下文中将参考附图并结合实施例来详细说明本发明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
需要说明的是，本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
实施例1
本申请实施例1所提供的方法实施例可以运行于图1所示的架构中，图1是本发明实施例的一种输出时钟生成方法的运行架构的结构框图。如图1所示，该架构包括：中央处理器CPU，现场可编辑门阵列FPGA，多个客户口，多个线路侧口以及倍频模块，其中，该FPGA从各个客户口和/或线路侧口处接收各个业务恢复时钟(输入时钟)，然后从获取的各个业务恢复时钟中按照预定的规则选择一个业务恢复时钟作为输出时钟，该预定的规则可以是各个业务恢复时钟的优先级，该优先级可以是CPU进行配置的，并且为了适应各客户口和/或线路侧口的业务处理，可能需要对输出时钟进行倍频处理。
本申请实施例可以应用于OTN设备时钟传送方案中多路时钟源选择以及主备时钟倒换的场景，但并不限于此。
在本实施例中提供了一种运行于运行架构的输出时钟生成方法，图2是根据本发明实施例的输出时钟生成方法的流程图，如图2所示，该流程包括如下步骤：
步骤S202，检测当前输入时钟是否有效；
步骤S204，在检测到当前输入时钟失效的情况下，从预先存储的多个输入时钟对应的多个采样值中选择一个指定采样值；其中，多个采样值为本地时钟对多个输入时钟进行采样计数得到的值；
步骤S206，根据选择的指定采样值和本地时钟生成输出时钟。
通过上述步骤，由于在检测到当前输入时钟失效的情况下，直接从预先存储的多个输入时钟对应的多个采样值中选择一个指定采样值，根据选择的指定采样值和本地时钟生成输出时钟，进而使得输出时钟无毛刺，无周期性缺失，进而能够实现时钟的无缝切换，因此，可以解决无法实现时钟源的无缝切换的问题。
需要说明的是，当当前输入时钟失效时，并不立刻执行采样值来源的切换，直到完成本次时钟周期的再生。生成的输出时钟的频率与选择的指定采样值对应的输入时钟的频率一致。
在本发明的一个实施例中，上述步骤S204可以表现为根据多个输入时钟的有效状态和/或优先级，选择一个输入时钟对应的先入先出FIFO存储器；其中，FIFO存储器中预先存储有本地时钟对与FIFO存储器对应的输入时钟的采样值；从选择的FIFO存储器中获取指定采样值。
需要说明的是，上述多个输入时钟的优先级可以是预先设置好的，上述多个输入时钟中的每一个输入时钟对应一个FIFO存储器，采用该FIFO可以缓冲输入时钟自身带有的抖动。
以根据多个输入时钟的有效状态和优先级选择一个输入时钟对应的FIFO存储器为例进行说明，比如存在4个输入时钟，输入时钟1、输入时钟2、输入时钟3和输入时钟4的状态分别为：失效、有效、有效、有效；该4个输入时钟的优先级从高到低为：输入时钟1、输入时钟2、输入时钟3和输入时钟4，当当前输入时钟失效时，状态为有效的输入时钟为：输入时钟2、输入时钟3和输入时钟4；而输入时钟2、输入时钟3和输入时钟4中输入时钟2优先级最高，因而选择的FIFO存储器是输入时钟2对应的FIFO存储器。对于根据多个输 入时钟的有效状态或者优先级选择一个输入时钟对应的FIFO存储器，此处不再赘述。
需要说明的是，上述多个输入时钟的优先级可以由应用软件通过SSM算法动态更新和/或通过逻辑提供的底层存储器进行灵活配置，但并不限于此。
为了避免抖动导致FIFO出现空/满异常，进而导致输出时钟频率失真，在本发明的一个实施例中，上述FIFO存储器的水位为：N＝ceiling(1/(1-J)+1)；FIFO存储器的深度为2N；其中，J为预定的与FIFO存储器对应的输入时钟的抖动的最大值；celing()为向上取值函数。
比如：考虑到在OTN时钟时间传输场景中，多个输入时钟的频率通常由各个业务端口的恢复时钟Ft分频得到，因此可以认为输入时钟的抖动最大不会超过Ft的抖动；通常OTN所承载的业务(例如SDH业务)，最大抖动为0.3UI，根据上述公式计算可以得到FIFO存储器的深度为6，处于备用状态的输入时钟对应的FIFO存储器至少要缓存3个数据，即可满足缓冲要求。
在本发明的一个实施例中，在上述多个输入时钟的有效状态都为失效的情况下，指定采样值为预先设置的标准采样值，即在所有时钟均失效的情况下，可以提供一个标准采样值进行使用，生成一个输出时钟，即即使所有时钟均失效的情况下，也仍然能够有一个本地时钟输出供下游模块使用。
在本发明的一个实施例中，在上述步骤S202之前，上述方法还可以包括：采用本地时钟对多个输入时钟进行采样计数，得到多个采样值；将多个采样值存储在与多个输入时钟对应的FIFO存储器中。通过FIFO存储器来暂存输入时钟的采样数据。
需要说明的是，上述多个输入时钟中的每一个输入时钟的频率与本地时钟的频率之比小于预定阈值，可以根据多个输入时钟中的每一个输入时钟的频率与本地时钟的频率之比小于预定阈值的原则来选择上述本地时钟和输入时钟，这样选择的本地时钟和输入时钟，使得因量化引入的噪声较小，进而对OTN传输设备来讲几乎可以忽略不计。
在本发明的一个实施例中，上述步骤S202可以表现为：判断本地时钟对当前输入时钟进行采样得到的采样值是否超过预先设置的时钟源采样范围；其中，在超过时钟源采样范围的情况下，确定当前输入时钟失效；在没有超过时钟源采样范围的情况下，确定当前输入时钟有效。
需要说明的是，在当前输入时钟判断为失效的情况下，在失效状态需要经过连续多个合法采样值后该输入时钟才能恢复为有效状态。
需要说明的是，上述时钟源采样范围可以为：[(Ftco/Fin)*(1-J1)，(Ftco/Fin)*(1+J1)]，其中，Ftco为本地时钟的频率；Fin为当前输入时钟的频率，J1为标准或者规定的当前输入时钟抖动的最大值。
比如在OTN所承载的业务抖动不会超过0.3UI的情况下，根据上述公式可知上述时钟源采样范围为[69,131]。
在本发明的一个实施例中，上述本地时钟可以是频率相对较高，精度相对稳定的本地温补晶振。
通过上述方法在实现时钟的无缝切换的同时，也能解决因时钟源切换导致的业务闪断、 时钟时间传动抖动等问题。
需要说明的是，上述方法的执行主体可以是上述图2所示架构中的FPGA模块，但并不限于此。
为了更好地理解本发明以下结合优选的实施例对本发明做进一步解释。
本发明优选实施例提供了一种实现多路时钟源失效检测以及无缝切换的方法，特别适用于OTN设备时钟时间传送方案中多路钟源选择以及主备时钟倒换的场景，廉价且有效的解决由时钟源切换导致的业务闪断、时钟时间传送抖动等问题。
实现该解决方案包括：输入时钟周期采样计数模块及相关参数设置方法、采样计数结果存储方法；失效检测模块及相关参数设置方法；时钟选择及无缝切换电路模块；时钟再生模块；及上述模块之间的连接配合。图3是根据本发明优选实施例提供的实现时钟源失效检测及无缝切换电路的方法流程图，如图3所示，包括：
采样：利用本地时钟对输入时钟采样计数；
判断：根据计数值判断是否失效；
缓存：把有效采样值存入到对应的FIFO中；
选择：根据当前状态选择合适的FIFO读出采样值，并根据需要进行无缝切换；
时钟再生：利用本地时钟和读出的采样值，重新生成输出时钟。
图4是根据本发明优选实施例提供的输出时钟的电路原理框图，如图4所示，所述的输入时钟周期采样方法主要为：采用频率为Ftco的高精度稳定时钟对频率为Fin输入时钟进行周期采样计数；该模块引入的抖动(量化噪声)为Fin/Ftco(单位UI)，以此作为选择Ftco和Fin的依据，例如：实践中参数选择Ftco为Fin的100倍，因量化引入的噪声为0.01UI，对OTN传输设备来讲几乎可以忽略不计。
优选地，频率为Ftco时钟采用本地温补晶振。
所述失效检测方法主要包括：根据标准或规定的输入时钟源抖动最大值J(单位：UI)，来配置时钟走采用范围：[(Ftco/Fin)*(1-J),(Ftco/Fin)*(1+J)]，根据上述公式并对结果进行适当取整，当采值超出该范围时立即判断为时钟失效，在失效状态时需经过连续多个合法采样值后该时钟源才能恢复为有效状态。
所述采样结果存储方法主要包括：采用FIFO来暂存采样数据以及FIFO深度、水位等相关参数的设置依据。采用FIFO是为了缓冲输入时钟自身带有的抖动，FIFO相关参数选择的目的及依据为：避免抖动导致FIFO出现空/满异常，进而导致输出时钟频率失真。例如：设时钟源合理最大抖动为J(单位：UI)，未选中时钟源对应的FIFO至少要缓存N个数据以避免FIFO读空，其中N＝1/(1-J)+1(向上取整)；FIFO的深度至少要设置为2N以避免FIFO工作过程中出写满。
优选地，考虑到在OTN时钟时间传输场景中，该方案的多路时钟源Fin通常由各个业务端口的恢复时钟Ft分频得到，因此可以认为Fin的抖动最大不会超过Ft的抖动。通常OTN所承载的业务(例如SDH业务)，最大抖动为0.3UI，根据前述公式计算可以得到FIFO的深度为6，处于备用状态的时钟源对应的FIFO至少要缓存3个数据，即可满足缓冲要求。
所述时钟再生方法主要包括：从当前所选时钟对应的FIFO中取的采样值，并利用本地晶振时钟Ftco重新生成一个输出时钟Fout，即保证Fout与所选输入时钟频率一致。
时钟无缝切换方法主要包括：根据输入时钟检测状态和时钟源优先级的当前配置，选择相应的FIFO供时钟再生模块取得采样值M；当前所选时钟失效时，该模块并不立刻执行M值来源的切换，直到再生模块完成本次时钟周期的再生，从而达到无缝切换的目的；当所有时钟均失效的时候，该模块提供一个预设M值供再生模块使用，因此即使所有时钟源均失效的情况下，仍然有一个本地时钟输出供下游模块使用。
优选地，各个时钟源的优先级由应用软件通过SSM算法动态更新，并通过逻辑提供的底层寄存器进行灵活配置。
本优选实施例所描述的方法能做到当前所选时钟失效时，迅速切换到备选时钟源，同时不把丝毫失效时钟引入到输出时钟中。并且在切换的过程中保证输出时钟无毛刺、无周期缺失即到达时钟无缝切换的目的。同时当所有时钟源都失效时仍然可以提供一个本地时钟输出供下游模块使用。并且相关性能参数理论上可控。特别适用于OTN设备时钟时间传送方案中多路业务恢复钟源选择以及主备时钟倒换的场景，廉价且有效的解决由时钟源切换导致的业务闪断、时钟时间传送抖动等问题。并且带有一定的启发性，从而扩展应用于其它场景。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到根据上述实施例的方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是手机，计算机，服务器，或者网络设备等)执行本发明各个实施例所述的方法。
实施例2
在本实施例中还提供了一种输出时钟生成装置，该装置用于实现上述实施例及优选实施方式，已经进行过说明的不再赘述。如以下所使用的，术语“模块”可以实现预定功能的软件和/或硬件的组合。尽管以下实施例所描述的装置较佳地以软件来实现，但是硬件，或者软件和硬件的组合的实现也是可能并被构想的。
图5是根据本发明实施例的输出时钟生成装置的结构框图，如图5所示，该装置包括：
检测模块52，用于检测当前输入时钟是否有效；
选择模块54，与上述检测模块52连接，用于在检测到当前输入时钟失效的情况下，从预先存储的多个输入时钟对应的多个采样值中选择一个指定采样值；其中，多个采样值为本地时钟对多个输入时钟进行采样计数得到的值；
再生模块56，与上述选择模块54连接，用于根据选择的指定采样值和本地时钟生成输出时钟。
通过上述装置，由于在检测模块52检测到当前输入时钟失效的情况下，选择模块54直接从预先存储的多个输入时钟对应的多个采样值中选择一个指定采样值，再生模块56根据选择的指定采样值和本地时钟生成输出时钟，进而使得输出时钟无毛刺，无周期性缺失，进 而能够实现时钟的无缝切换，因此，可以解决无法实现时钟源的无缝切换的问题。
需要说明的是，当当前输入时钟失效时，并不立刻执行采样值来源的切换，直到完成本次时钟周期的再生。生成的输出时钟的频率与选择的指定采样值对应的输入时钟的频率一致。
在本发明的一个实施例中，上述选择模块54还可以用于根据多个输入时钟的有效状态和/或优先级，选择一个输入时钟对应的先入先出FIFO存储器；其中，FIFO存储器中预先存储有本地时钟对与FIFO存储器对应的输入时钟的采样值；以及从选择的FIFO存储器中获取指定采样值。
需要说明的是，上述多个输入时钟的优先级可以是预先设置好的，上述多个输入时钟中的每一个输入时钟对应一个FIFO存储器，采用该FIFO可以缓冲输入时钟自身带有的抖动。需要说明的是，上述多个输入时钟的优先级可以由应用软件通过SSM算法动态更新和/或通过逻辑提供的底层存储器进行灵活配置，但并不限于此。
为了避免抖动导致FIFO出现空/满异常，进而导致输出时钟频率失真，在本发明的一个实施例中，上述FIFO存储器的水位为：N＝ceiling(1/(1-J)+1)；FIFO存储器的深度为2N；其中，J为预定的与FIFO存储器对应的输入时钟的抖动的最大值；celing()为向上取值函数。
在本发明的一个实施例中，在上述多个输入时钟的有效状态都为失效的情况下，指定采样值为预先设置的标准采样值，即在所有时钟均失效的情况下，上述选择模块54可以提供一个标准采样值供再生模块56进行使用生成一个输出时钟，即即使所有时钟均失效的情况下，也仍然能够有一个本地时钟输出供下游模块使用。
在本发明的一个实施例中，上述装置还包括：采样模块，用于采用本地时钟对多个输入时钟进行采样计数，得到多个采样值；存储模块，与上述采样模块和选择模块54连接，用于将多个采样值存储在与多个输入时钟对应的FIFO存储器中。
需要说明的是，上述多个输入时钟中的每一个输入时钟的频率与本地时钟的频率之比小于预定阈值，可以根据多个输入时钟中的每一个输入时钟的频率与本地时钟的频率之比小于预定阈值的原则来选择上述本地时钟和输入时钟，这样选择的本地时钟和输入时钟，使得因量化引入的噪声较小，进而对OTN传输设备来讲几乎可以忽略不计。
在本发明的一个实施例中，上述检测模块52还可以用于判断本地时钟对当前输入时钟进行采样得到的采样值是否超过预先设置的时钟源采样范围；其中，在超过时钟源采样范围的情况下，确定当前输入时钟失效；在没有超过时钟源采样范围的情况下，确定当前输入时钟有效。
需要说明的是，在当前输入时钟判断为失效的情况下，在失效状态需要经过连续多个合法采样值后该输入时钟才能恢复为有效状态。
需要说明的是，上述时钟源采样范围为：[(Ftco/Fin)*(1-J1)，(Ftco/Fin)*(1+J1)]，其中，Ftco为本地时钟的频率；Fin为当前输入时钟的频率，J1为标准或者规定的当前输入时钟抖动的最大值。
在本发明的一个实施例中，上述本地时钟可以是频率相对较高，精度相对稳定的本地温 补晶振。
通过上述装置在实现时钟的无缝切换的同时，也能解决因时钟源切换导致的业务闪断、时钟时间传动抖动等问题。
需要说明的是，上述输出时钟生成装置可以位于图2所示的运行架构中的FPGA中，但并不限于此。
为了更好地理解本发明，以下结合优选的实施例对本发明做进一步解释。
本优选实施例应用在OTN设备时钟时间传送方案中主备时钟板倒换和SSM时钟选源算法实施的场景中。实现时钟失效检测无缝切换电路的原理框图如图4所示，采用Verilog HDL语言编写相关电路模块，并在FPGA上实现。由于Verilog代码过于冗长，不再出示详细代码，仅分别对各个模块以及参数的实施要点进行详细阐述。
图6是根据本发明优选实施例提供的装置的输入时钟周期采样计数模块的示意图，如图6所示：在实施过程中Fin选择为1.944Mhz，Ftco选择为194.4Mhz的本地温补晶振。根据Fin/Ftco计算公式，可以得出该系统因采用量化引入的抖动最大为0.01UI。首先把输入时钟信号Fin同步到Ftco时钟域下，并产生一个上升沿脉冲，其中采用的D触发器链是为了消除异步时钟域亚稳态问题。利用Fin的上升沿驱动计数器清零端，从而实现在Ftco时钟下对Fin每个周期进行计数。
需要说明的是，上述输入时钟周期采用计数模块相当于上述实施例中的采样模块。
采样计数结果存入FIFO，目的是为了缓冲输入时钟自带的抖动，FIFO的写入端由采样计数模块驱动，FIFO的读出端主要由时钟再生模块与FIFO水位控制。图7是根据本发明优选实施例的FIFO读出端的算法状态机ASMD图，如图7所示，主要由两个状态组成：未选中(Backup)状态和选中(Selected)状态。在Backup状态FIFO的读取信号由FIFO的水位控制，根据前文的计算公式以及计算结果，Backup状态的FIFO水位控制在3为最佳，超过3时读取并丢弃。在Selected状态时，FIFO的读取信号主要由时钟再生模块控制，每当该模块完成一个时钟周期的生成，就从所选FIFO中读取一个数据，即是否接收到外部的请求信号(Rd_req)，在接收到请求信号时，开始读取。
失效检测模块(相当于上述实施例中的检测模块52)，OTN所承载的业务抖动通常不会超过0.3UI(例如SDH业务)。根据本发明上述的参数计算公式选定时钟采用的范围为[69,131]，当采样值超出该范围时立即判断为时钟失效，在时钟失效状态时需经过连续多个合法采样值后该时钟源才能恢复为有效状态(在实际实现过程中该值选择为10)，ASMD图如图8所示。
时钟再生模块(相当于上述实施例中的再生模块86)主要包括：从当前所选时钟对应的FIFO中取得采样值，并利用本地晶振时钟Ftco重新生成一个输出时钟Fout，即保证Fout与所选输入时钟频率一致。如图9所示，沿触发计数器在时钟Ftco下计数，当计数值cnt小于等于FIFO读出的采样值的一半时(实施电路中采用移位的方式得到半数值)再生时钟输出高电平周期，反之再生时钟输出低电平周期。当cnt等于采用值时清零计数器，同时从FIFO中读取新的M并进入下个生成周期。
时钟无缝切换电路模块(相当于上述实施例中的选择模块54)主要负责上述各模块的协调控制，根据输入时钟源的检测状态和优先级的当前配置，选择相应的FIFO供时钟再生模块取得采样值M。当前所选时钟失效时，该模块并不立刻执行M值来源的切换，直到再生模块完成本次时钟周期的再生，从而达到无损切换的目的；当所有时钟均失效的时候，该模块提供一个预设M值供再生模块使用，在实施过程中该值选择为100，因此即使所有时钟源均失效的情况下，仍然有一个本地时钟输出的1.944Mhz的时钟供下游模块使用。各个时钟源的优先级由应用软件通过SSM算法动态更新，并通过逻辑提供的底层寄存器进行配置，从而达到灵活配置的目的。
需要说明的是，上述各个模块是可以通过软件或硬件来实现的，对于后者，可以通过以下方式实现，但不限于此：上述模块均位于同一处理器中；或者，上述各个模块以任意组合的形式分别位于不同的处理器中。
实施例3
本发明的实施例还提供了一种存储介质。可选地，在本实施例中，上述存储介质可以被设置为存储用于执行实施例1中的方法的步骤的程序代码。
可选地，在本实施例中，上述存储介质可以包括但不限于：U盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。
可选地，在本实施例中，处理器根据存储介质中已存储的程序代码执行实施例1中的方法的步骤。
可选地，本实施例中的具体示例可以参考上述实施例及可选实施方式中所描述的示例，本实施例在此不再赘述。
显然，本领域的技术人员应该明白，上述的本发明的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本发明不限制于任何特定的硬件和软件结合。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。
工业实用性
本公开适用于光传输技术领域，用以使得输出时钟无毛刺，无周期性缺失，进而能够实现时钟的无缝切换，因此，可以解决无法实现时钟源的无缝切换的问题。

Claims (17)

  1. 一种输出时钟生成方法，包括：
    检测当前输入时钟是否有效；
    在检测到所述当前输入时钟失效的情况下，从预先存储的多个输入时钟对应的多个采样值中选择一个指定采样值；其中，所述多个采样值为本地时钟对所述多个输入时钟进行采样计数得到的值；
    根据选择的所述指定采样值和所述本地时钟生成输出时钟。
  2. 根据权利要求1所述的方法，其中，从预先存储的各个输入时钟对应的多个采样值中选择一个指定采样值包括：
    根据所述多个输入时钟的有效状态和/或优先级，选择一个输入时钟对应的先入先出FIFO存储器；其中，所述FIFO存储器中预先存储有所述本地时钟对与所述FIFO存储器对应的输入时钟的采样值；
    从选择的所述FIFO存储器中获取所述指定采样值。
  3. 根据权利要求2所述的方法，其中，所述FIFO存储器的水位为：N＝ceiling(1/(1-J)+1)；所述FIFO存储器的深度为2N；其中，ceiling()为向上取整函数，J为预定的与所述FIFO存储器对应的输入时钟的抖动的最大值。
  4. 根据权利要求2所述的方法，还包括，
    在所述多个输入时钟的有效状态都为失效的情况下，所述指定采样值为预先设置的标准采样值。
  5. 根据权利要求1所述的方法，其中，在检测当前输入时钟是否有效之前，还包括：
    采用所述本地时钟对所述多个输入时钟进行采样计数，得到多个所述采样值；
    将所述多个采样值存储在与所述多个输入时钟对应的FIFO存储器中。
  6. 根据权利要求5所述的方法，其中，所述多个输入时钟中的每一个输入时钟的频率与所述本地时钟的频率之比小于预定阈值。
  7. 根据权利要求1所述的方法，其中，检测当前输入时钟是否有效包括：
    判断所述本地时钟对所述当前输入时钟进行采样得到的采样值是否超过预先设置的时钟源采样范围；其中，在超过所述时钟源采样范围的情况下，确定所述当前输入时钟失效；在没有超过所述时钟源采样范围的情况下，确定所述当前输入时钟有效。
  8. 根据权利要求7所述的方法，其中，所述时钟源采样范围为：[(Ftco/Fin)*(1-J1)，(Ftco/Fin)*(1+J1)]，其中，Ftco为所述本地时钟的频率；所述Fin为所述当前输入时钟的频率，J1为标准或者规定的所述当前输入时钟抖动的最大值。
  9. 根据权利要求1至8中任一项所述的方法，其中，所述本地时钟为本地温补晶振。
  10. 一种输出时钟生成装置，包括：
    检测模块，设置为检测当前输入时钟是否有效；
    选择模块，设置为在检测到所述当前输入时钟失效的情况下，从预先存储的多个输入 时钟对应的多个采样值中选择一个指定采样值；其中，所述多个采样值为本地时钟对所述多个输入时钟进行采样计数得到的值；
    再生模块，设置为根据选择的所述指定采样值和所述本地时钟生成输出时钟。
  11. 根据权利要求10所述的装置，其中，所述选择模块还设置为根据所述多个输入时钟的有效状态和/或优先级，选择一个输入时钟对应的先入先出FIFO存储器；其中，所述FIFO存储器中预先存储有所述本地时钟对与所述FIFO存储器对应的输入时钟的采样值；以及从选择的所述FIFO存储器中获取所述指定采样值。
  12. 根据权利要求11所述的装置，其中，所述FIFO存储器的水位为：N＝ceiling(1/(1-J)+1)；所述FIFO存储器的深度为2N；其中，ceiling()为向上取整函数，J为预定的与所述FIFO存储器对应的输入时钟的抖动的最大值。
  13. 根据权利要求11所述的装置，其中，
    在所述多个输入时钟的有效状态都为失效的情况下，所述指定采样值为预先设置的标准采样值。
  14. 根据权利要求10所述的装置，还包括：
    采样模块，设置为采用所述本地时钟对所述多个输入时钟进行采样计数，得到多个所述采样值；
    存储模块，设置为将所述多个采样值存储在与所述多个输入时钟对应的FIFO存储器中。
  15. 根据权利要求10所述的装置，其中，所述检测模块还设置为判断所述本地时钟对所述当前输入时钟进行采样得到的采样值是否超过预先设置的时钟源采样范围；其中，在超过所述时钟源采样范围的情况下，确定所述当前输入时钟失效；在没有超过所述时钟源采样范围的情况下，确定所述当前输入时钟有效。
  16. 根据权利要求15所述的装置，其中，所述时钟源采样范围为：[(Ftco/Fin)*(1-J1)，(Ftco/Fin)*(1+J1)]，其中，Ftco为所述本地时钟的频率；所述Fin为所述当前输入时钟的频率，J1为标准或者规定的所述当前输入时钟抖动的最大值。
  17. 根据权利要求10至16中任一项所述的装置，其中，所述本地时钟为本地温补晶振。
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