WO2017215274A1 - 关机残影消除电路及其驱动方法、显示装置 - Google Patents

关机残影消除电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2017215274A1
WO2017215274A1 PCT/CN2017/072951 CN2017072951W WO2017215274A1 WO 2017215274 A1 WO2017215274 A1 WO 2017215274A1 CN 2017072951 W CN2017072951 W CN 2017072951W WO 2017215274 A1 WO2017215274 A1 WO 2017215274A1
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Prior art keywords
voltage
level
transistor
terminal
output
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PCT/CN2017/072951
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English (en)
French (fr)
Inventor
杨钰婷
胡凌霄
叶纯
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US15/552,286 priority Critical patent/US10438546B2/en
Publication of WO2017215274A1 publication Critical patent/WO2017215274A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/027—Arrangements or methods related to powering off a display

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shutdown image sticking elimination circuit, a driving method thereof, and a display device.
  • the monitor When the monitor is turned off, it usually leaves a part of the image displayed before the shutdown. This is because when the monitor is in normal lighting state, the pixel electrode in each pixel has a certain amount of charge. If it is turned off, it cannot be turned off. The charge on the pixel electrode is derived in time, and the charge in the pixel electrode gradually disappears. Before the charge on the pixel electrode does not completely disappear, the user still observes the image on the display, that is, the phenomenon of shutdown afterimage.
  • the control signal When the main circuit voltage output of the analog circuit is lower than a certain value, the control signal is low, and the gate drive circuit is in the Under the control of the control signal, the TFTs in all the pixels are simultaneously turned on, the charges in the pixel electrodes are led out through the corresponding TFTs, and the charges in the respective pixel electrodes are neutralized with each other, thereby eliminating the phenomenon of shutdown and afterimage.
  • the control signal of the input gate driving circuit is low, so the output voltage of the gate driving circuit is likely to be pulled down, and the TFT of some pixels is turned off again after turning on the pixel, thereby causing the pixel.
  • the charge in the electrode cannot be exported in time, which affects the effect of removing the afterimage.
  • the embodiment of the present disclosure provides a shutdown image removal circuit and a driving method thereof, and a display device for at least partially preventing the TFT of the pixel from being turned off again after opening, thereby improving the effect of eliminating the afterimage of the shutdown.
  • a shutdown afterimage removal circuit including: a comparator, a control module, and an output module;
  • the opposite end of the comparator is connected to the first level end, the opposite end of the comparator is connected to the control voltage input end; and the comparator is used when the input voltage of the same end is greater than the input voltage of the reverse end Outputting a high level voltage at an output end of the comparator, and outputting a low level voltage at an output end of the comparator when an input voltage of the same end is less than or equal to an input voltage of the opposite end;
  • the control module is connected to the second level end, the third level end, the control node, and the output end of the comparator, for outputting the voltage of the control node when the output of the comparator outputs a high level voltage And the voltage of the second level terminal is aligned, and the voltage of the control node is aligned with the voltage of the third level terminal when the output of the comparator outputs a low level voltage;
  • the output module is connected to the fourth level end, the fifth level end, the signal output end, and the control node, and is configured to: when the voltage of the control node is a voltage of the third level end, the voltage of the fourth level end Outputting at the signal output end, when the voltage of the control node is a voltage of the second level terminal, outputting the voltage of the fifth level terminal at the signal output end;
  • the voltage at the fourth level terminal is a high level voltage, and the voltage at the fifth level terminal is a low level voltage.
  • the shutdown afterimage removal circuit further includes: a voltage dividing module
  • the voltage dividing module is connected to the input voltage terminal, the second level terminal, and the control voltage input terminal; and is configured to adjust a voltage of the control voltage input terminal.
  • the shutdown afterimage removal circuit further includes: filtering the module fast;
  • the filtering module is connected to the control node and the second level terminal for filtering a voltage of the control node.
  • control module includes: a first transistor
  • a first end of the first transistor is connected to the control node and the third level end, a second end of the first transistor is connected to the second level end, and a gate of the first transistor is connected to the The output of the comparator.
  • the output module includes: a second transistor and a third transistor;
  • a first end of the second transistor is connected to the fourth level end, a second end of the second transistor is connected to the signal output end, and a gate of the second transistor is connected to the control node;
  • the first end of the third transistor is connected to the signal output end, the second end of the third transistor is connected to the fifth level end, and the gate of the third transistor is connected to the control node;
  • the second transistor is an N-type transistor, and the three transistors are P-type transistors.
  • the output module includes: an inverting unit, a fourth transistor, and a fifth transistor;
  • An input end of the inverting unit is connected to the control node, an output end of the inverting unit is connected to a gate of the fourth transistor, and the inverting unit is configured to output and output at an output end of the inverting unit a voltage of an opposite phase of a voltage input to an input terminal of the inverting unit;
  • a first end of the fourth transistor is connected to the fourth level end, and a second end of the fourth transistor is connected to the signal output end;
  • a first end of the fifth transistor is connected to the signal output end, a second end of the fifth transistor is connected to the fifth level end, and a gate of the fifth transistor is connected to the control node;
  • the fourth transistor and the fifth transistor are both N-type transistors.
  • the inverting unit is an inverter or a NOT gate.
  • the output module includes: an inverting unit, a fourth transistor, and a fifth transistor;
  • An input end of the inverting unit is connected to the control node, an output end of the inverting unit is connected to a gate of the fifth transistor, and the inverting unit is configured to output at an output end of the inverting unit a voltage of an opposite phase of the voltage input to the input terminal of the inverting unit;
  • a first end of the fourth transistor is connected to the fourth level end, a second end of the fourth transistor is connected to the signal output end, and a gate of the fourth transistor is connected to the control node;
  • a first end of the fifth transistor is connected to the signal output end, and a second end of the fifth transistor is connected to the fifth level end;
  • the fourth transistor and the fifth transistor are both P-type transistors.
  • the inverting unit is an inverter or a NOT gate.
  • the voltage dividing module includes: a first resistor and a second resistor;
  • the first end of the first resistor is connected to the input voltage end, and the second end of the first resistor is connected to the control voltage input end;
  • the first end of the second resistor is connected to the control voltage input end, and the second end of the second resistor is connected to the second level end.
  • the filtering module includes: at least one capacitor
  • a first pole of at least one of the capacitors is coupled to the control node, and a second pole of at least one of the capacitors is coupled to the second level terminal.
  • a method for driving the shutdown afterimage removal circuit of any of the first aspects comprising:
  • the comparator If yes, the comparator outputs a high level voltage, and the control unit pulls the voltage of the control node and the voltage of the second level terminal under the control of the high level of the output of the comparator, and the voltage of the output unit at the control node Controlling, at the signal output end, a voltage at a fifth level terminal;
  • the comparator If not, the comparator outputs a low level voltage, and the control unit pulls the voltage of the control node and the voltage of the third level terminal under the control of the low level output by the comparator, and the voltage of the output unit at the control node Controlling, at the signal output end, a voltage of the fourth level terminal;
  • the voltage of the fourth level terminal is a high level voltage
  • the voltage of the fifth level end is a low level voltage
  • the voltage at the fourth level terminal is a high level voltage, and the voltage at the fifth level terminal is a low level voltage.
  • a display device comprising the shutdown afterimage removal circuit of any of the first aspects.
  • the display device includes a plurality of gate driving chips, and each of the plurality of gate driving chips is connected to a signal output end of the shutdown afterimage removing circuit.
  • FIG. 1 is a schematic structural diagram of a shutdown image sticking elimination circuit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram 2 of a shutdown image sticking elimination circuit according to an embodiment of the present disclosure
  • FIG. 3 is a third schematic structural diagram of a shutdown image sticking elimination circuit according to an embodiment of the present disclosure.
  • FIG. 4 is a circuit diagram of a shutdown image sticking elimination circuit according to an embodiment of the present disclosure.
  • FIG. 5 is a second circuit diagram of a shutdown image sticking elimination circuit according to an embodiment of the present disclosure.
  • FIG. 6 is a circuit diagram of an inverter according to an embodiment of the present disclosure.
  • FIG. 7 is a third circuit diagram of a shutdown afterimage removal circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a flowchart of steps of a method for driving a shutdown afterimage removal circuit according to an embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • the transistors employed in all of the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices having the same characteristics.
  • the transistors employed in the embodiments of the present disclosure are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and the drain are interchangeable.
  • the source is referred to as a first pole, and the drain is referred to as a second pole.
  • the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain.
  • the switching transistor used in the embodiment of the present disclosure includes a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level, and the N-type switching transistor is turned off. It is turned on when the gate is high and turned off when the gate is low.
  • the embodiment of the present disclosure provides a shutdown afterimage removal circuit.
  • the shutdown afterimage removal circuit includes a comparator 11 , a control module 12 , and an output module 13 .
  • the opposite end 1 of the comparator 11 is connected to the first level terminal V1, the same end 2 of the comparator is connected to the control voltage input terminal Vxon; and the comparator 11 is used for the input voltage at the same end 2 is greater than the input voltage of the opposite terminal 1.
  • the output terminal 3 of the comparator 11 outputs a high-level voltage, the output at the same end 2
  • a low level voltage is outputted at the output terminal 3 of the comparator 11.
  • the control module 12 is connected to the second level terminal V2, the third level terminal V4, the control node a and the output terminal 3 of the comparator 11 for controlling the voltage of the node a when the output terminal 3 of the comparator 11 outputs a high level voltage.
  • the voltage of the control node a is aligned with the voltage of the third level terminal V3 when the voltage of the second level terminal V2 is aligned and the low voltage is outputted at the output terminal 3 of the comparator 11.
  • the output module 13 is connected to the fourth level terminal V4, the fifth level terminal V5, the signal output terminal Output, and the control node a for outputting the fourth power at the signal output end when the voltage of the control node a is the voltage of the third level terminal V3.
  • the voltage of the flat terminal V4 outputs a voltage of the fifth level terminal V5 at the signal output terminal when the voltage of the control node a is the voltage of the second level terminal V2.
  • the voltage of the fourth level terminal V4 is a high level voltage
  • the voltage of the fifth level terminal V5 is a low level voltage
  • the high-level voltage and the low-level voltage in the embodiments of the present disclosure are relative, and the determination of the high-level voltage and the low-level voltage is based on the TFT of the circuit, when a voltage acts on the circuit N
  • the gate of the transistor can turn on the N-type transistor, and the voltage is a high level voltage; conversely, when a voltage is applied to the gate of the N-type transistor in the circuit, the N-type transistor is turned off, the voltage is low.
  • Flat voltage Similarly, if the transistor is a P-type transistor, the voltage acts on its gate, and the transistor is turned on, then the voltage is a low level voltage; when the voltage acts on its gate and the transistor is turned off, the voltage is a high level voltage.
  • the specific voltage values of the high-level voltage and the low-level voltage are not limited in the embodiment of the present disclosure, so as to be able to satisfy the above-mentioned control of turning on and off the transistor. Further, preferably, the high level voltage is greater than 5V. By making the high-level voltage greater than 5 V, the TFT in the display device can be sufficiently turned on, thereby avoiding the influence of insufficient TFT conduction in the display device.
  • the shutdown afterimage removal circuit includes: a comparator, a control module, and an output module, wherein the comparator can output a high level at the output end when the input voltage of the same end is greater than the input voltage of the reverse end When the input voltage of the forward terminal is less than or equal to the input voltage of the reverse terminal, the output terminal outputs a low level, and the control module can pull the voltage of the control node and the voltage of the second level terminal when the output of the comparator outputs a high level.
  • the output module can output the fourth level end at the signal output end when the voltage of the control node is the voltage of the third level terminal.
  • High level The voltage, when the voltage of the control node is the voltage of the second level terminal, outputs a low level voltage of the fifth level end at the signal output end, that is, the shutdown image sticking elimination circuit provided by the embodiment of the present disclosure can be high at the control voltage input end.
  • the low level voltage of the fifth level end is output at the signal output end, and when the control voltage input end is low level, the high level voltage of the fourth level end is output at the signal output end, compared to the prior art when the power is turned off.
  • the technology of inputting a low level control signal to the gate driving circuit can input a high level voltage of the fourth level terminal to the gate driving circuit when the power is turned off, so the embodiment of the present disclosure can avoid the TFT in the pixel Turn it on again after turning it on, which will improve the effect of eliminating the afterimage.
  • the shutdown afterimage removal circuit in the above embodiment further includes: a voltage dividing module 14;
  • the voltage dividing module 14 is connected to the input voltage terminal Input, the second level terminal V2, and the control voltage input terminal Vxon; and is used for adjusting the voltage of the control voltage input terminal Vxon.
  • the voltage of the first level terminal V1 connected to the opposite end 1 of the comparator 11 is a fixed value, and the shutdown image sticking elimination circuit is applied to the input terminal of the input voltage terminal of different products.
  • the voltage may be different.
  • the requirements for the trigger voltage of the output level change of the output terminal 3 of the comparator 11 may also be different in different usage environments.
  • the voltage input to the input voltage terminal Input is performed by the voltage dividing module 14.
  • the voltage division adjustment can improve the compatibility of the shutdown afterimage removal circuit provided by the embodiment of the present disclosure, and can adjust the trigger voltage of the output level change of the output terminal 3 of the comparator 11 according to the use environment.
  • the shutdown afterimage removal circuit further includes: a filter mode fast 15;
  • the filter mode 15 is connected to the control node a and the second level terminal V2 for filtering the voltage of the control node a.
  • the shutdown afterimage removal circuit may be interfered by other electromagnetic signals during use, resulting in an abnormality in the voltage of the control node a, which may cause the shutdown image removal circuit to malfunction and affect the normal display of the display device.
  • the voltage of the control node a is filtered by the filter module 15, which can reduce the interference of the external electromagnetic signal on the voltage of the control node a, thereby avoiding the malfunction of the shutdown image stick elimination circuit.
  • Embodiments of the present disclosure provide a specific circuit diagram of the above-described shutdown afterimage removal circuit.
  • the control module 12 in the above embodiment includes: a first transistor T1;
  • the first end of the first transistor T1 is connected to the control node a and the third level terminal V3.
  • the second end of the first transistor T1 is connected to the second level terminal V2, and the gate of the first transistor T1 is connected to the output terminal 3 of the comparator 11.
  • the output module 13 includes: a second transistor T2 and a third transistor T3;
  • the second end of the second transistor T2 is connected to the fourth level terminal V4, the second end of the second transistor T2 is connected to the signal output terminal Output, the gate of the second transistor T2 is connected to the control node a;
  • the first end of the third transistor T3 is connected to the signal output terminal Output, the second end of the third transistor T3 is connected to the fifth level terminal V5, and the gate of the third transistor T3 is connected to the control node a;
  • the second transistor T2 is an N-type transistor
  • the third transistor T3 is a P-type transistor
  • the second transistor T2 is a P-type transistor
  • the third transistor T3 is an N-type transistor
  • the voltage dividing module 14 includes: a first resistor R1 and a second resistor R2;
  • the first end of the first resistor R1 is connected to the input voltage terminal Input, and the second end of the first resistor is connected to the control voltage input terminal Vxon;
  • the first end of the second resistor R2 is connected to the control voltage input terminal Vxon, and the second end of the second resistor R2 is connected to the second level terminal V2.
  • the filtering module 15 includes: at least one capacitor C;
  • the first pole of the at least one capacitor C is connected to the control node a, and the second pole of the at least one capacitor C is connected to the second level terminal V2.
  • the filter module in the embodiment of the present disclosure may further include other capacitors. For example: 1, 3, etc.
  • the first transistor T1 and the second transistor T2 in the shutdown afterimage removal circuit shown in FIG. 4 are N-type transistors that are turned on when the gate is high level and turned off when the low level is low, and the third transistor T3 is low in the gate.
  • the P-type which is normally turned on and turned off at a high level is taken as an example to explain the working principle of the shutdown afterimage removal circuit provided in the above embodiment.
  • the first level terminal V1, the second level terminal V2, the third level terminal V3, the fourth level terminal V4, and the fifth level terminal V5 each provide a stable voltage.
  • the third level terminal V3 and the fourth level terminal V4 provide a high level voltage, and the second level terminal V2 and the fifth level terminal V5 provide a low level voltage.
  • the voltage of the fourth level terminal V4 can be To display the common voltage Vcom in the device or the analog circuit main power output voltage Vin, the voltage of the second level terminal V2 may be a ground voltage.
  • the output terminal 3 of comparator 11 outputs a high level. Because T1 is an N-type transistor that is turned on when the gate is high level, T1 is turned on, control node a is connected to the second level terminal through T1, control node a is low level, and capacitor C in the filtering unit can absorb electromagnetic interference. The interference voltage is brought about, and the control node a maintains a stable level.
  • the control node a is low level
  • the second transistor T2 is an N-type transistor that is turned on when the gate is high level
  • the third transistor T3 is a P-type transistor that is turned off when the gate is high level, T3 is turned on, and T2 is turned off.
  • Output outputs the voltage of the fifth level terminal V5. That is, when the display device is normally displayed, the Output outputs a low level, and the shutdown afterimage removal circuit does not function when the display device is normally displayed.
  • the voltage of the input voltage terminal Input decreased, R1, R2 on the Input of the input voltage V in is further reduced after the partial pressure of a control voltage input terminal Vxon voltage V XON; if a control voltage input terminal Vxon voltage V When xon is less than or equal to the output voltage of the first level terminal V1, the input voltage Vxon of the same end 1 of the comparator 11 is less than or equal to the input voltage V1 of the inverting terminal 2 of the comparator 11, and the output terminal 3 of the comparator 11
  • the output low level, the first transistor T1 is turned off, the control node a is disconnected from the second level terminal V2, so the control node a outputs the voltage of the third level terminal V3, and the control node a is at the high level.
  • T2 is turned on
  • T3 is turned off
  • Output outputs a high level voltage of the fourth level terminal V4. That is, when the display device is turned off, the Output outputs a high level, and the shutdown afterimage removal circuit turns on the TFTs in the respective pixels through the output high level control gate driving circuit, so the embodiment of the present disclosure can prevent the TFT in the pixel from being turned on again. Turn off, which improves the effect of eliminating the afterimage of the shutdown.
  • the output voltage of each level terminal may be divided by a resistor and then output to the shutdown afterimage.
  • a resistor may be connected in series between the third level terminal V3 and the control node a and/or a resistor may be connected in series between the fourth level terminal V4 and the output terminal Output.
  • the embodiment of the present disclosure provides another specific circuit diagram of the above-mentioned shutdown afterimage removal circuit.
  • the control module 12, the voltage dividing module 14, and the filter mode fast 15 are the same as those in the second embodiment. To avoid redundancy, the details are not described in detail in this embodiment. The difference is that the output module 13 includes: an inverting unit 131, a fourth transistor T4, and a fifth transistor T5;
  • the input end of the inverting unit 131 is connected to the control node a, the output end of the inverting unit 131 is connected to the gate of the fifth transistor T5, and the inverting unit 131 is used to output the input of the inverting unit 131 at the output end of the inverting unit 131.
  • the first terminal of the fourth transistor T4 is connected to the fourth level terminal V4, and the second terminal T4 of the fourth transistor is connected to the signal output terminal Output;
  • the first end of the fifth transistor T5 is connected to the signal output terminal Output, the second end of the fifth transistor T5 is connected to the fifth level terminal V5, and the gate of the fifth transistor T5 is connected to the control node a.
  • the fourth transistor T4 and the fifth transistor T5 are all N-type transistors.
  • the first transistor T1 in the shutdown image-removing circuit shown in FIG. 5 is an N-type transistor that is turned on when the gate is high level and turned off when the gate is at a low level, for example, the shutdown image sticking elimination circuit provided in the above embodiment is used as an example.
  • the working principle is explained.
  • the first level terminal V1, the second level terminal V2, the third level terminal V3, the fourth level terminal V4, and the fifth level terminal V5 each provide a stable voltage.
  • the third level terminal V3 and the fourth level terminal V4 provide a high level voltage
  • the second level terminal V2 and the fifth level terminal provide a low level voltage.
  • the voltage of the fourth level terminal V4 may be a common voltage Vcom in the display device or an analog circuit main power output voltage Vin.
  • the voltage of the second level terminal V2 may be a ground voltage.
  • the input voltage V xon of the same end 1 of the comparator 11 is greater than that of the opposite terminal 2 of the comparator 11.
  • the output terminal 3 of the comparator 11 outputs a high level.
  • T1 is an N-type transistor that is turned on when the gate is high level, T1 is turned on, and the control node a is connected to the second level terminal V2 through T1, and the control node a is at a low level, and the capacitor C in the filtering unit can absorb the electromagnetic The interference voltage caused by the interference, the control node a maintains a stable low level.
  • the control node a is at a low level
  • the input terminal of the inverting unit 131 is at a low level
  • the output terminal of the inverting unit 131 outputs a high level
  • T4 is turned off
  • T5 is turned on
  • Output is outputted at a low level of the fifth level terminal V5.
  • Level that is, when the display device is normally displayed, the Output outputs a low level, and the shutdown afterimage removal circuit does not function when the display device is normally displayed.
  • the voltage of the input voltage terminal Input decreased, R1, R2 on the Input of the input voltage V in is further reduced after the partial pressure of a control voltage input terminal Vxon voltage V XON; if a control voltage input terminal Vxon voltage V When xon is less than or equal to the output voltage of the first level terminal V1, the input voltage Vxon of the non-directional terminal 1 of the comparator 11 is less than or equal to the input voltage of the inverting terminal 2 of the comparator 11, and the output terminal 3 of the comparator 11 outputs Low level, the first transistor T1 is turned off, the control node a is disconnected from the second level terminal V2, so the control node a outputs the voltage of the third level terminal V3, and the control node a is at a high level.
  • the control node a is at a high level, the input terminal of the inverting unit 131 is at a high level, the output terminal of the inverting unit 131 outputs a low level, T4 is turned on, T5 is turned off, and the output is outputted at a fourth level end V4.
  • Level voltage that is, when the display device is turned off, the Output outputs a high level, and the shutdown afterimage removal circuit turns on the TFTs in the respective pixels through the output high level control gate driving circuit, so the embodiment of the present disclosure can prevent the TFT in the pixel from being turned on again. Turn off, which improves the effect of eliminating the afterimage of the shutdown.
  • the inverting unit 131 in the above embodiment may be an inverter or a NOT gate.
  • the inverter is usually used for analog circuits, and the non-gate is usually used in digital circuits.
  • the common feature of both is that the phase of the input signal can be inverted by 180 degrees and output at the output.
  • the inverter in the above embodiment may specifically include: an inverting module A, a third resistor R3, a fourth resistor R4, and a fifth resistor R5; and a third resistor R3.
  • One end is connected to the control node a, the second end of the third resistor R3 is connected to the first output end of the inverting module A, the first end of the fourth resistor R4 is connected to the second end of the third resistor R3, and the fourth resistor R4 is The second end is connected to the output end of the inverting module A, the first end of the fifth resistor R5 is connected to the second output end of the inverting module A, the second end of the fifth resistor R5 is grounded, and the output end of the inverting module A is connected.
  • the inverter circuit can not only output the inverted voltage of the input voltage V i , but also adjust the resistance of the resistor according to the use requirement, thereby adjusting the value of the output voltage V 0 .
  • the embodiment of the present disclosure provides another specific circuit diagram of the above-mentioned shutdown afterimage removal circuit.
  • the control module 12 the voltage dividing module 14 , and the filtering module 15 are the same as those in the second embodiment. To avoid redundancy, the details are not described in detail in this embodiment. The difference is that the output module 13 includes: an inverting unit 131, a fourth transistor T4, and a fifth transistor T5;
  • the input end of the inverting unit 131 is connected to the control node a, the output end of the inverting unit 131 is connected to the gate of the fourth transistor T4, and the inverting unit 131 is used to output the output end of the inverting unit 131 and the input end of the inverting unit 131.
  • the voltage of the input voltage is opposite in phase;
  • the first end of the fourth transistor T4 is connected to the fourth level terminal V4, the second end of the fourth transistor T4 is connected to the signal output terminal Output, and the gate of the fourth transistor T4 is connected to the output end of the inverting unit 131;
  • the first end of the fifth transistor T5 is connected to the signal output terminal Output, and the second end of the fifth transistor T5 is connected to the fifth level terminal V5.
  • the fourth transistor T4 and the fifth transistor T5 are both P-type transistors.
  • the working principle of the shutdown afterimage elimination circuit is similar to the working principle of the shutdown afterimage removal circuit in the third embodiment, and the difference is that: during normal display, the control section Point a is low level, the gate of the fourth transistor T4 is at a high level, and the gate of the fifth transistor T5 is at a low level, so T4 is turned off, T5 is turned on, and Output outputs a low level voltage of the fifth level terminal V5;
  • the display device is turned off, when the control node a is at a high level, the gate of the fourth transistor T4 is at a low level, and the gate of the fifth transistor T5 is at a high level, so T4 is turned on, T5 is turned off, and Output is outputted at the fourth level end.
  • the high level control gate drive circuit turns on the TFTs in each pixel. Therefore, the embodiment of the present disclosure can prevent the TFT in the pixel from being turned off again after being turned on, thereby improving the effect of eliminating the afterimage of the shutdown.
  • the active layer doping materials of different types of transistors are different. Therefore, the use of a uniform type of transistor in the shutdown afterimage removal circuit is more advantageous for the process of the shutdown image sticking elimination circuit, so it is preferred to adopt A unified type of transistor is used to implement the present disclosure.
  • the inverting unit 131 in the embodiment of the present disclosure may be an inverter or a NOT gate.
  • the circuit diagram of the inverter can also be as shown in FIG. 6.
  • An embodiment of the present disclosure provides a method for driving the shutdown afterimage removal circuit provided by any of the above embodiments. Specifically, referring to FIG. 8, the method includes the following steps:
  • step S81 if the voltage of the control voltage input terminal is greater than the voltage of the first level terminal, step S82 is performed. If the voltage of the control voltage input terminal is less than or equal to the voltage of the first level terminal, step S83 is performed.
  • the comparator outputs a high level voltage
  • the control unit pulls the voltage of the control node and the voltage of the second level terminal under the control of the high level of the output of the comparator, and the output unit is under the control of the voltage of the control node.
  • the output outputs the voltage at the fifth level terminal.
  • the comparator outputs a low level voltage
  • the control unit pulls the voltage of the control node and the voltage of the third level terminal under the control of the low level of the comparator output, and the output unit is under the control of the voltage of the control node.
  • the output outputs the voltage at the fourth level terminal.
  • the voltage at the fourth level terminal is a high level voltage, and the voltage at the fifth level terminal is a low level voltage.
  • the comparator when the voltage of the control voltage input terminal is greater than the voltage of the first level terminal, the comparator outputs a high level voltage, and the control unit outputs a high level at the comparator. Under control, the voltage of the control node is aligned with the voltage of the second level terminal, and the output unit outputs the voltage of the fifth level terminal at the signal output end under the control of the voltage of the control node, so that the normal display of the display device can be ensured, and the control is performed.
  • the comparator When the voltage at the voltage input terminal is less than or equal to the voltage at the first level terminal, the comparator outputs a low level voltage, and the control unit pulls the voltage of the control node and the voltage at the third level terminal under the control of the low level of the comparator output.
  • the output unit outputs a high level voltage of the fourth level terminal at the signal output end under the control of the voltage of the control node, so the embodiment of the present disclosure can input the high level voltage of the fourth level end to the gate driving circuit when the power is turned off. Therefore, the embodiment of the present disclosure can prevent the TFT in the pixel from being turned off again after being turned on, thereby improving the effect of eliminating the afterimage of the shutdown.
  • a further embodiment of the present disclosure provides a display device, which includes the shutdown afterimage removal circuit provided by any of the above embodiments.
  • the display device may be: electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc., any product or component having a display function.
  • the display device 90 includes a plurality of gate driving chips 90 connected to the signal output terminal Output of the same shutdown afterimage removing circuit 92.
  • the output current of the signal output terminal of the shutdown afterimage removing circuit can be shunted, thereby avoiding the output current of the signal output terminal of the shutdown image sticking elimination circuit. Too large, causing damage to components in the display device, thereby improving the reliability of the display device.

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Abstract

一种关机残影消除电路及其驱动方法、显示装置。该关机残影消除电路包括：比较器、控制模块以及输出模块；比较器用于在同向端电压大于反向端电压时输出高电平电压、在同向端的输入电压小于或等于反向端的输入电压时输出低电平电压；控制模块用于在比较器输出高电平电压时将控制节点的电压与第二电平端的电压拉齐、在比较器输出低电平电压时将控制节点的电压与第三电平端的电压拉齐；输出模块用于在控制节点的电压为第三电平端的电压时在信号输出端输出第四电平端的电压、在控制节点的电压为第二电平端的电压时在信号输出端输出第五电平端的电压。

Description

关机残影消除电路及其驱动方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种关机残影消除电路及其驱动方法、显示装置。
背景技术
显示器在关闭电源时通常还会残留一部分关闭前所显示的图像，这是因为显示器在正常点亮状态时，每一个像素中的像素电极上都带有一定的电荷量，若在关机时不能将像素电极上的电荷及时导出，而任随像素电极内的电荷逐渐消失，则在像素电极上的电荷未完全消失之前，用户仍会在显示器上观察到图像，即关机残影现象。为了解决关机残影显现，现有技术中在通过使显示器中的模拟电路主电源的出端连接至栅极驱动芯片并作用为控制信号控制栅极驱动电路进行输出，当显示器正常进行工作时，该控制信号为高电平，栅极驱动电路在该控制信号的控制下逐行对各栅线进行扫描，各像素中的场效应薄膜晶体管(英文全称：Thin Film Transistor，简称：TFT)逐行打开，显示器正常进行显示；当显示器关机时，模拟电路主电源电压的输出电压逐渐降低，当模拟电路主电源电压输出低于一定数值时，该控制信号为低电平，栅极驱动电路在该控制信号的控制下同时将所有像素中的TFT打开，像素电极内的电荷通过对应TFT导出，各像素电极内的电荷相互进行中和，从而消除关机残影现象。然而，在显示器关机时，输入栅极驱动电路的控制信号为低电平，所以很可能会拉低栅极驱动电路的输出电压，进而导致部分像素的TFT打开后还会再次关闭，进而导致像素电极中的电荷无法及时导出，影响关机残影消除效果。
发明内容
本公开的实施例提供一种关机残影消除电路及其驱动方法、显示装置，用于至少部分地避免像素的TFT打开后再次关闭，进而提升消除关机残影的效果。
根据本公开实施例的第一方面，提供一种关机残影消除电路，包括：比较器、控制模块以及输出模块；
所述比较器的反向端连接第一电平端，所述比较器的同向端连接控制电压输入端；所述比较器用于在所述同向端的输入电压大于所述反向端的输入电压时在所述比较器的输出端输出高电平电压、在所述同向端的输入电压小于或等于所述反向端的输入电压时在所述比较器的输出端输出低电平电压；
所述控制模块连接第二电平端、第三电平端、控制节点以及所述比较器的输出端，用于在所述比较器的输出端输出高电平电压时将所述控制节点的电压与所述第二电平端的电压拉齐、在所述比较器的输出端输出低电平电压时将所述控制节点的电压与所述第三电平端的电压拉齐；
所述输出模块连接第四电平端、第五电平端、信号输出端以及所述控制节点，用于在所述控制节点的电压为第三电平端的电压时将所述第四电平端的电压在所述信号输出端输出、在所述控制节点的电压为第二电平端的电压时将所述第五电平端的电压在所述信号输出端输出；
其中，第四电平端的电压为高电平电压，第五电平端的电压为低电平电压。
可选的，所述关机残影消除电路还包括：分压模块；
所述分压模块连接输入电压端、所述第二电平端以及所述控制电压输入端；用于调节所述控制电压输入端的电压。
可选的，所述关机残影消除电路还包括：滤波模快；
所述滤波模块连接所述控制节点和所述第二电平端，用于对所述控制节点的电压进行滤波。
可选的，所述控制模块包括：第一晶体管；
所述第一晶体管的第一端连接所述控制节点以及所述第三电平端，所述第一晶体管的第二端连接所述第二电平端，所述第一晶体管的栅极连接所述比较器的输出端。
可选的，所述输出模块包括：第二晶体管和第三晶体管；
所述第二晶体管的第一端连接所述第四电平端，所述第二晶体管的第二端连接所述信号输出端，所述第二晶体管的栅极连接所述控制节点；
所述第三晶体管的第一端连接所述信号输出端，所述第三晶体管的第二端连接所述第五电平端，所述第三晶体管的栅极连接所述控制节点；
其中，所述第二晶体管为N型晶体管，所述三晶体管为P型晶体管。
可选的，所述输出模块包括：反相单元、第四晶体管以及第五晶体管；
所述反相单元的输入端连接所述控制节点，所述反相单元的输出端连接所述第四晶体管的栅极，所述反相单元用于在所述反相单元的输出端输出与所述反相单元的输入端输入的电压的相位相反的电压；
所述第四晶体管的第一端连接所述第四电平端，所述第四晶体管的第二端连接所述信号输出端；
所述第五晶体管的第一端连接所述信号输出端，所述第五晶体管的第二端连接所述第五电平端，所述第五晶体管的栅极连接所述控制节点；
其中，所述第四晶体管和所述第五晶体管均为N型晶体管。
可选的，所述反相单元为反相器或者非门。
可选的，所述输出模块包括：反相单元、第四晶体管以及第五晶体管；
所述反相单元的输入端连接所述控制节点，所述反相单元的输出端连接所述第五晶体管的栅极，所述反相单元用于在所述反相单元的输出端输出与所述反相单元输入端输入的电压的相位相反的电压；
所述第四晶体管的第一端连接所述第四电平端，所述第四晶体管的第二端连接所述信号输出端，所述第四晶体管的栅极连接所述控制节点；
所述第五晶体管的第一端连接所述信号输出端，所述第五晶体管的第二端连接所述第五电平端；
其中，所述第四晶体管和所述第五晶体管均为P型晶体管。
可选的，所述反相单元为反相器或者非门。
可选的，所述分压模块包括：第一电阻和第二电阻；
所述第一电阻的第一端连接所述输入电压端，所述第一电阻的第二端连接所述控制电压输入端；
所述第二电阻的第一端连接所述控制电压输入端，所述第二电阻的第二端连接所述第二电平端。
可选的，所述滤波模块包括：至少一个电容；
至少一个所述电容的第一极连接所述控制节点，至少一个所述电容的第二极连接所述第二电平端。
根据本公开实施例的第二方面，提供一种用于驱动第一方面任一项所述关机残影消除电路的方法，包括：
判断所述控制电压输入端的电压是否大于所述第一电平端的电压；
若是，比较器输出高电平电压，控制单元在所述比较器输出的高电平的控制下将所述控制节点的电压与第二电平端的电压拉齐，输出单元在控制节点的电压的控制下在所述信号输出端输出第五电平端的电压；
若否，比较器输出低电平电压，控制单元在所述比较器输出的低电平的控制下将所述控制节点的电压与第三电平端的电压拉齐，输出单元在控制节点的电压的控制下在所述信号输出端输出第四电平端的电压；
其中，所述第四电平端的电压为高电平电压，所述第五电平端的电压为低电平电压；
其中，第四电平端的电压为高电平电压，第五电平端的电压为低电平电压。
根据本公开实施例的第三方面，提供一种显示装置，包括第一方面任一项所述的关机残影消除电路。
可选的，所述显示装置包括多个栅极驱动芯片，多个所述栅极驱动芯片中的每一个均连接于所述关机残影消除电路的信号输出端。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的关机残影消除电路的示意性结构图之一；
图2为本公开实施例提供的关机残影消除电路的示意性结构图之二；
图3为本公开实施例提供的关机残影消除电路的示意性结构图之三；
图4为本公开实施例提供的关机残影消除电路的电路图之一；
图5为本公开实施例提供的关机残影消除电路的电路图之二；
图6为本公开实施例提供的反相器的电路图；
图7为本公开实施例提供的关机残影消除电路的电路图之三；
图8为本公开实施例提供的关机残影消除电路的驱动方法的步骤流程图；
图9为本公开实施例提供的显示装置的示意性结构图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用，本公开的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中源极称为第一极，漏极称为第二极。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外本公开实施例所采用的开关晶体管包括P型开关晶体管和N型开关晶体管两种，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
此外，还需要说明的是，本公开中的“第一”、“第二”等字样仅仅是为了对功能和作用基本相同的相同项或相似项进行区分，“第一”、“第二”等字样并不是在对数量和执行次序进行限定。
实施例一、
本公开的实施例提供一种关机残影消除电路，参照图1所示，该关机残影消除电路包括：比较器11、控制模块12以及输出模块13。
比较器11的反向端1连接第一电平端V1，比较器的同向端2连接控制电压输入端Vxon；比较器11用于在同向端2的输入电压大于反向端1的输入电压时在比较器11的输出端3输出高电平电压、在同向端2的输 入电压小于或等于反向端1的输入电压时在比较器11的输出端3输出低电平电压。
控制模块12连接第二电平端V2、第三电平端V4、控制节点a以及比较器11的输出端3，用于在比较器11的输出端3输出高电平电压时将控制节点a的电压与第二电平端V2的电压拉齐、在比较器11的输出端3输出低电平电压时将控制节点a的电压与第三电平端V3的电压拉齐。
输出模块13连接第四电平端V4、第五电平端V5、信号输出端Output以及控制节点a，用于在控制节点a的电压为第三电平端V3的电压时在信号输出端输出第四电平端V4的电压、在控制节点a的电压为第二电平端V2的电压时在信号输出端输出第五电平端V5的电压。
其中，第四电平端V4的电压为高电平电压，第五电平端V5的电压为低电平电压。
需要说明的是，本公开实施例中的高电平电压和低电平电压是相对的，高电平电压和低电平电压的判定是基于电路的TFT晶体管，当一个电压作用于电路中N型晶体管的栅极可以使该N型晶体管导通，则该电压为高电平电压；反之，当一个电压作用于电路中N型晶体管的栅极该N型晶体管截止，则该电压为低电平电压。同理，若晶体管为P型晶体管，电压作用于其栅极，晶体管导通，则该电压为低电平电压；电压作用于其栅极，晶体管截止，则该电压为高电平电压。本公开实施例中对高电平电压和低电平电压的具体电压值不做限定，以能够满足上述对晶体管导通和截止的控制为准。此外，优选的，高电平电压大于5V。通过使高电平电压大于5V可以充分导通显示装置中的TFT，进而避免显示装置中的TFT导通不充分造成的影响。
本公开实施例提供的关机残影消除电路包括：比较器、控制模块以及输出模块，其中，比较器可以在同向端的输入电压大于反向端的输入电压时在输出端输出高电平、在同向端的输入电压小于或等于反向端的输入电压时在输出端输出低电平，控制模块能够在比较器的输出端输出高电平时将控制节点的电压与第二电平端的电压拉齐、在比较器的输出端输出低电平时将控制节点的电压与第三电平端的电压拉齐，输出模块能够在控制节点的电压为第三电平端的电压时在信号输出端输出第四电平端的高电平 电压、在控制节点的电压为第二电平端的电压时在信号输出端输出第五电平端的低电平电压，即本公开实施例提供的关机残影消除电路可以在控制电压输入端为高电平时在信号输出端输出第五电平端的低电平电压，在控制电压输入端为低电平时在信号输出端输出第四电平端的高电平电压，相比于现有技术中关机时向栅极驱动电路输入低电平的控制信号的技术，本公开实施例可以在关机时向栅极驱动电路输入第四电平端的高电平电压，所以本公开实施例可以避免像素中的TFT打开后再次关闭，进而提升消除关机残影的效果。
可选的，参照图2所示，上述实施例中的关机残影消除电路还包括：分压模块14；
分压模块14连接输入电压端Input、第二电平端V2以及控制电压输入端Vxon；用于调节控制电压输入端Vxon的电压。
上述关机残影消除电路在实际使用中通常与比较器11的反向端1连接的第一电平端V1的电压为固定值，而关机残影消除电路应用于不同产品时输入电压端Input输入的电压可能会不同，不同使用环境下对比较器11的输出端3输出电平变化的触发电压的要求也可能会不同，本公开实施例中通过分压模块14对输入电压端Input输入的电压进行分压调节，因此可以提高本公开实施例提供的关机残影消除电路的兼容性，且可以根据使用环境对比较器11的输出端3输出电平变化的触发电压进行调节。
进一步的，可选的，参照图3所示，上述关机残影消除电路还包括：滤波模快15；
滤波模15块连接控制节点a和第二电平端V2，用于对控制节点a的电压进行滤波。
关机残影消除电路在使用可能会受到其他电磁信号的干扰，导致控制节点a的电压出现异常，进而导致关机残影消除电路误动作，影响显示装置的正常显示。本公开实施例中通过滤波模15对控制节点a的电压进行滤波，可以减小外界电磁信号对控制节点a的电压的干扰，进而避免关机残影消除电路误动作。
实施例二、
本公开实施例提供一种上述关机残影消除电路的具体电路图。
具体的，参照图4所示，上述实施例中的控制模块12包括：第一晶体管T1；
第一晶体管T1的第一端连接控制节点a以及第三电平端V3，第一晶体管T1的第二端连接第二电平端V2，第一晶体管T1的栅极连接比较器11的输出端3。
输出模块13包括：第二晶体管T2和第三晶体管T3；
第二晶体管T2的第一端连接第四电平端V4，第二晶体管T2的第二端连接信号输出端Output，第二晶体管T2的栅极连接控制节点a；
第三晶体管T3的第一端连接信号输出端Output，第三晶体管T3的第二端连接第五电平端V5，第三晶体管T3的栅极连接控制节点a；
其中，第二晶体管T2为N型晶体管，三晶体管T3为P型晶体管；或者第二晶体管T2为P型晶体管，三晶体管T3为N型晶体管。
分压模块14包括：第一电阻R1和第二电阻R2；
第一电阻R1的第一端连接输入电压端Input，第一电阻的第二端连接控制电压输入端Vxon；
第二电阻R2的第一端连接控制电压输入端Vxon，第二电阻R2的第二端连接第二电平端V2。
滤波模块15包括：至少一个电容C；
至少一个电容C的第一极连接控制节点a，至少一个电容C的第二极连接第二电平端V2。
其中，图4中以滤波模快15中包含两个电容为例进行说明，但本公开实施例并不限定于此，本公开实施例中的滤波模块还可以包括其他数量的电容。例如：1个、3个等。
以下，以图4所示关机残影消除电路中的第一晶体管T1和第二晶体管T2为栅极高电平时导通、低电平时截止的N型晶体管，第三晶体管T3为栅极低电平时导通、高电平时截止的P型为例对上述实施例中提供的关机残影消除电路的工作原理进行说明。其中，第一电平端V1、第二电平端V2、第三电平端V3、第四电平端V4和第五电平端V5均提供稳定电压。第三电平端V3、第四电平端V4提供高电平电压，第二电平端V2、第五电平端V5提供低电平电压。示例性的，第四电平端V4的电压可以 为显示装置中的公共电压Vcom或者模拟电路主电源输出电压Vin，第二电平端V2的电压可以为接地电压。
首先，当显示装置正常显示时，Input输入高电平，电阻R1、R2对Input的输入电压进行分压后控制电压输入端Vxon的电压为：
Figure PCTCN2017072951-appb-000001
其中，Vxon为控制电压输入端Vxon的电压；Vin为输入电压端Input的输入电压；V2为第二电平端V2的输出电压值；R1为第一电阻R1的阻值；R2为第二电阻R2的阻值。
此时，通过对第一电平端V1的输出电压进行设定，使Vxon大于第一电平端V1的输出电压，比较器11的同向端1的输入电压Vxon大于比较器11的反向端2的输入电压，比较器11的输出端3输出高电平。因为T1为栅极高电平时导通的N型晶体管，所以T1导通，控制节点a通过T1连接第二电平端，控制节点a为低电平，同时滤波单元中的电容C可以吸收电磁干扰带来的干扰电压，控制节点a保持稳定的电平。因为控制节点a为低电平，且第二晶体管T2为栅极高电平时导通的N型晶体管，第三晶体管T3为栅极高电平时截止的P型晶体管，所以T3导通、T2截止，Output输出第五电平端V5的电压。即在显示装置正常显示时，Output输出低电平，关机残影消除电路在显示装置正常显示时不起作用。
在显示装置关机时，输入电压端Input的电压逐渐降低，R1、R2对Input的输入电压Vin进行分压后进一步降低控制电压输入端Vxon的电压Vxon；当控制电压输入端Vxon的电压Vxon小于或等于第一电平端V1的输出电压时，比较器11的同向端1的输入电压Vxon小于或等于比较器11的反向端2的输入电压V1，比较器11的输出端3输出低电平，第一晶体管T1截止，控制节点a与第二电平端V2断开，因此控制节点a输出第三电平端V3的电压，控制节点a为高电平。因为控制节点a为高电平，所以T2导通、T3截止，Output输出第四电平端V4的高电平电压。即在显示装置关机时，Output输出高电平，关机残影消除电路通过输出的高电平控制栅极驱动电路打开各个像素中的TFT，因此本公开实施例可以避免像素中的TFT打开后再次关闭，进而提升消除关机残影的效果。
进一步的，为了避免各个电平端输出电压过大，进而损坏电路中的器件，在上述实施例的基础上，还可以通过电阻对各个电平端的输出电压进行分压后再输出到关机残影消除电路中。具体的，可以在第三电平端V3与控制节点a之间串联一电阻和/或在第四电平端V4与输出端Output之间串联一电阻。
实施例三、
本公开实施例提供另一种上述关机残影消除电路的具体电路图。
具体的，参照图5所示，其中，控制模块12、分压模块14以及滤波模快15与实施例二相同，为避免赘述，本实施例中不再详细说明。不同之处在于，输出模块13包括：反相单元131、第四晶体管T4以及第五晶体管T5；
反相单元131的输入端连接控制节点a，反相单元131的输出端连接第五晶体管T5的栅极，反相单元131用于在反相单元的131输出端输出与反相单元131的输入端输入的电压的相位相反的电压；
第四晶体管T4的第一端连接第四电平端V4，第四晶体管的第二端T4连接信号输出端Output；
第五晶体管T5的第一端连接信号输出端Output，第五晶体管T5的第二端连接第五电平端V5，第五晶体管T5的栅极连接控制节点a。
其中，第四晶体管T4、第五晶体管T5均为N型晶体管。
以下，以图5所示关机残影消除电路中的第一晶体管T1为栅极高电平时导通、低电平时截止的N型晶体管，为例对上述实施例中提供的关机残影消除电路的工作原理进行说明。第一电平端V1、第二电平端V2、第三电平端V3、第四电平端V4和第五电平端V5均提供稳定电压。其中，第三电平端V3、第四电平端V4提供高电平电压，第二电平端V2、第五电平端提供低电平电压。示例性的，第四电平端V4的电压可以为显示装置中的公共电压Vcom或者模拟电路主电源输出电压Vin。第二电平端V2的电压可以为接地电压。
首先，当显示装置正常显示时，控制电压输入端Vxon的电压为：
Figure PCTCN2017072951-appb-000002
其中，Vxon为控制电压输入端Vxon的电压；Vin为输入电压端Input的输入电压；V2为第二电平端V2的输出电压值；R1为第一电阻R1的阻值；R2为第二电阻R2的阻值。
通过对第一电平端V1的输出电压进行设定，使Vxon大于第一电平端V1的输出电压，比较器11的同向端1的输入电压Vxon大于比较器11的反向端2的输入电压，比较器11的输出端3输出高电平。因为T1为栅极高电平时导通的N型晶体管，所以T1导通，控制节点a通过T1连接第二电平端V2，控制节点a为低电平，同时滤波单元中的电容C可以吸收电磁干扰带来的干扰电压，控制节点a保持稳定的低电平。因为控制节点a为低电平，所以反相单元131的输入端为低电平，反相单元131的输出端输出高电平，T4截止、T5导通，Output输出第五电平端V5的低电平，即在显示装置正常显示时，Output输出低电平，关机残影消除电路在显示装置正常显示时不起作用。
在显示装置关机时，输入电压端Input的电压逐渐降低，R1、R2对Input的输入电压Vin进行分压后进一步降低控制电压输入端Vxon的电压Vxon；当控制电压输入端Vxon的电压Vxon小于或等于第一电平端V1的输出电压时，比较器11的同向端1的输入电压Vxon小于或等于比较器11的反向端2的输入电压，比较器11的输出端3输出低电平，第一晶体管T1截止，控制节点a与第二电平端V2断开，因此控制节点a输出第三电平端V3的电压，控制节点a为高电平。因为控制节点a为高电平，所以反相单元131的输入端为高电平，反相单元131的输出端输出低电平，T4导通、T5截止，Output输出第四电平端V4的高电平电压。即在显示装置关机时，Output输出高电平，关机残影消除电路通过输出的高电平控制栅极驱动电路打开各个像素中的TFT，因此本公开实施例可以避免像素中的TFT打开后再次关闭，进而提升消除关机残影的效果。
上述实施例中的反相单元131可以为反相器或者非门。其中，反相器通常用于模拟电路，而非门通常用于数字电路中，二者的共同之处在于均可以将输入信号的相位反转180度后在输出端输出。
示例性的，上述实施例中的反相器具体可以如图6所示，包括：反相模块A，第三电阻R3、第四电阻R4以及第五电阻R5；第三电阻R3的第 一端连接控制节点a，第三电阻R3的第二端连接反相模块A的第一输出入端，第四电阻R4的第一端连接第三电阻R3的第二端，第四电阻R4的第二端连接反相模块A的输出端，第五电阻R5的第一端连接反相模块A的第二输出入端，第五电阻R5的第二端接地，反相模块A的输出端连接第五晶体管T5的栅极。
在反相器的电路中有：
Figure PCTCN2017072951-appb-000003
其中，I3为流经第三电阻R3的电流；I4为流经第四电阻R4的电流；V0为反相器的输出电压；R3为第三电阻的阻值；R4为第四电阻的阻值；Vi为控制节点a的电压。通过上述反相器电路不但可以输出输入电压Vi的反相电压，而且还可以根据使用需求调节电阻的阻值，进而对输出电压V0的值进行调节。
实施例四、
本公开实施例提供另一种上述关机残影消除电路的具体电路图。
具体的，参照图7所示，其中，控制模块12、分压模块14以及滤波模快15与实施例二相同，为避免赘述，本实施例中不再详细说明。不同之处在于，输出模块13包括：反相单元131、第四晶体管T4以及第五晶体管T5；
反相单元131的输入端连接控制节点a，反相单元131的输出端连接第四晶体管T4的栅极，反相单元131用于在反相单元131的输出端输出与反相单元131输入端输入的电压的相位相反的电压；
第四晶体管T4的第一端连接第四电平端V4，第四晶体管T4的第二端连接信号输出端Output，第四晶体管T4的栅极连接反相单元131的输出端；
第五晶体管T5的第一端连接信号输出端Output，第五晶体管T5的第二端连接第五电平端V5。
其中，第四晶体管T4和第五晶体管T5均为P型晶体管。
本公开实施例提供的关机残影消除电路的工作原理与实施例三中的关机残影消除电路的工作原理类似，不同之处在于：正常显示时，控制节 点a为低电平，第四晶体管T4的栅极为高电平、第五晶体管T5的栅极为低电平，所以T4截止、T5导通，Output输出第五电平端V5的低电平电压；在显示装置关机时，控制节点a为高电平时，第四晶体管T4的栅极为低电平、第五晶体管T5的栅极为高电平，所以T4导通、T5截止，Output输出第四电平端V4的高电平电压。即，在显示装置正常显示时，Output输出低电平电压，关机残影消除电路在显示装置正常显示时不起作用，在显示装置关机时，Output输出高电平，关机残影消除电路通过输出的高电平控制栅极驱动电路打开各个像素中的TFT。因此本公开实施例可以避免像素中的TFT打开后再次关闭，进而提升消除关机残影的效果。
此外，考虑到晶体管的制程工艺，不同类型的晶体管的有源层掺杂材料不相同，因此关机残影消除电路中采用统一类型的晶体管更有利于关机残影消除电路的制程工艺，因此优选采用统一类型的晶体管来实现本公开。
同样，本公开实施例中的反相单元131可以为反相器或者非门。其中，反相器的电路图也可以如图6所示。
实施例五、
本公开的实施例提供一种用于驱动上述任一实施例提供的关机残影消除电路的方法，具体的，参照图8所示，该方法包括如下步骤：
S81、判断控制电压输入端的电压是否小于第一电平端的电压。
在步骤S81中，若控制电压输入端的电压大于第一电平端的电压，则执行步骤S82，若控制电压输入端的电压小于或等于第一电平端的电压，则执行步骤S83。
S82、比较器输出高电平电压，控制单元在比较器输出的高电平的控制下将控制节点的电压与第二电平端的电压拉齐，输出单元在控制节点的电压的控制下在信号输出端输出第五电平端的电压。
S83、比较器输出低电平电压，控制单元在比较器输出的低电平的控制下将控制节点的电压与第三电平端的电压拉齐，输出单元在控制节点的电压的控制下在信号输出端输出第四电平端的电压。
其中，第四电平端的电压为高电平电压，第五电平端的电压为低电平电压。
根据本公开实施例提供的关机残影消除电路的驱动方法，在控制电压输入端的电压大于第一电平端的电压时，比较器输出高电平电压，控制单元在比较器输出的高电平的控制下将控制节点的电压与第二电平端的电压拉齐，输出单元在控制节点的电压的控制下在信号输出端输出第五电平端的电压，所以可以保证显示装置的正常显示，在控制电压输入端的电压小于或等于第一电平端的电压时，比较器输出低电平电压，控制单元在比较器输出的低电平的控制下将控制节点的电压与第三电平端的电压拉齐，输出单元在控制节点的电压的控制下在信号输出端输出第四电平端的高电平电压，所以本公开实施例可以在关机时向栅极驱动电路输入第四电平端的高电平电压，因此本公开实施例可以避免像素中的TFT打开后再次关闭，进而提升消除关机残影的效果。
实施例六、
本公开再一实施例提供一种显示装置，该显示装置包括上述任一实施例提供的关机残影消除电路。
另外，显示装置可以为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
进一步的，参照图9所示，显示装置90包括多个栅极驱动芯片90，多个栅极驱动芯片91连接于同一个关机残影消除电路92的信号输出端Output。
通过将多个栅极驱动芯片连接于同一个关机残影消除电路的信号输出端可以对关机残影消除电路的信号输出端输出电流进行分流，从而避免关机残影消除电路的信号输出端输出电流过大，造成显示装置中元器件的损坏，进而提高显示装置的可靠性。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (14)

  1. 一种关机残影消除电路，包括：
    比较器，所述比较器的反向端连接第一电平端，所述比较器的同向端连接控制电压输入端；所述比较器用于在所述同向端的输入电压大于所述反向端的输入电压时在所述比较器的输出端输出高电平电压、在所述同向端的输入电压小于或等于所述反向端的输入电压时在所述比较器的输出端输出低电平电压；
    控制模块，所述控制模块连接第二电平端、第三电平端、控制节点以及所述比较器的输出端，用于在所述比较器的输出端输出高电平电压时将所述控制节点的电压与所述第二电平端的电压拉齐、在所述比较器的输出端输出低电平电压时将所述控制节点的电压与所述第三电平端的电压拉齐；以及
    输出模块，所述输出模块连接第四电平端、第五电平端、信号输出端以及所述控制节点，用于在所述控制节点的电压为第三电平端的电压时在所述信号输出端输出所述第四电平端的电压、在所述控制节点的电压为第二电平端的电压时在所述信号输出端输出所述第五电平端的电压；
    其中，所述第四电平端的电压为高电平电压，所述第五电平端的电压为低电平电压。
  2. 根据权利要求1所述的关机残影消除电路，还包括：分压模块；
    所述分压模块连接输入电压端、所述第二电平端以及所述控制电压输入端；用于调节所述控制电压输入端的电压。
  3. 根据权利要求1所述的关机残影消除电路，还包括：滤波模快；
    所述滤波模块连接所述控制节点和所述第二电平端，用于对所述控制节点的电压进行滤波。
  4. 根据权利要求1-3任一项所述的关机残影消除电路，其中，所述控制模块包括：第一晶体管；
    所述第一晶体管的第一端连接所述控制节点以及所述第三电平端，所述第一晶体管的第二端连接所述第二电平端，所述第一晶体管的栅极连接所述比较器的输出端。
  5. 根据权利要求1-3任一项所述的关机残影消除电路，其中，所述输出模块包括：第二晶体管和第三晶体管；
    所述第二晶体管的第一端连接所述第四电平端，所述第二晶体管的第二端连接所述信号输出端，所述第二晶体管的栅极连接所述控制节点；
    所述第三晶体管的第一端连接所述信号输出端，所述第三晶体管的第二端连接所述第五电平端，所述第三晶体管的栅极连接所述控制节点；
    其中，所述第二晶体管为N型晶体管，所述第三晶体管为P型晶体管。
  6. 根据权利要求1-3任一项所述的关机残影消除电路，其中，所述输出模块包括：反相单元、第四晶体管以及第五晶体管；
    所述反相单元的输入端连接所述控制节点，所述反相单元的输出端连接所述第四晶体管的栅极，所述反相单元用于在所述反相单元的输出端输出与所述反相单元的输入端输入的电压的相位相反的电压；
    所述第四晶体管的第一端连接所述第四电平端，所述第四晶体管的第二端连接所述信号输出端；
    所述第五晶体管的第一端连接所述信号输出端，所述第五晶体管的第二端连接所述第五电平端，所述第五晶体管的栅极连接所述控制节点；
    其中，所述第四晶体管和所述第五晶体管均为P型晶体管。
  7. 根据权利要求6所述的关机残影消除电路，其中，所述反相单元为反相器或者非门。
  8. 根据权利要求1-3任一项所述的关机残影消除电路，其中，所述输出模块包括：反相单元、第四晶体管以及第五晶体管；
    所述反相单元的输入端连接所述控制节点，所述反相单元的输出端连接所述第五晶体管的栅极，所述反相单元用于在所述反相单元的输出端输出与所述反相单元输入端输入的电压的相位相反的电压；
    所述第四晶体管的第一端连接所述第四电平端，所述第四晶体管的第二端连接所述信号输出端，所述第四晶体管的栅极连接所述控制节点；
    所述第五晶体管的第一端连接所述信号输出端，所述第五晶体管的第二端连接所述第五电平端；
    其中，所述第四晶体管和所述第五晶体管均为N型晶体管。
  9. 根据权利要求8所述的关机残影消除电路，其中，所述反相单元为反相器或者非门。
  10. 根据权利要求2所述的关机残影消除电路，其中，所述分压模块包括：第一电阻和第二电阻；
    所述第一电阻的第一端连接所述输入电压端，所述第一电阻的第二端连接所述控制电压输入端；
    所述第二电阻的第一端连接所述控制电压输入端，所述第二电阻的第二端连接所述第二电平端。
  11. 根据权利要求3所述的关机残影消除电路，其中，所述滤波模块包括：至少一个电容；
    至少一个所述电容的第一极连接所述控制节点，至少一个所述电容的第二极连接所述第二电平端。
  12. 一种用于驱动权利要求1-11任一项所述关机残影消除电路的方法，包括：
    判断控制电压输入端的电压是否大于第一电平端的电压；
    若是，比较器输出高电平电压，控制单元在所述比较器输出的高电平的控制下将控制节点的电压与第二电平端的电压拉齐，输出单元在所述控制节点的电压的控制下在信号输出端输出第五电平端的电压；
    若否，比较器输出低电平电压，控制单元在所述比较器输出的低电平的控制下将控制节点的电压与第三电平端的电压拉齐，输出单元在所述控制节点的电压的控制下在信号输出端输出第四电平端的电压；
    其中，所述第四电平端的电压为高电平电压，所述第五电平端的电压为低电平电压。
  13. 一种显示装置，包括权利要求1-11任一项所述的关机残影消除电路。
  14. 根据权利要求13所述的显示装置，其中，所述显示装置包括多个栅极驱动芯片，多个所述栅极驱动芯片中的每一个均连接于所述关机残影消除电路的信号输出端。
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