WO2017202368A1 - 同频同时的数字信号处理方法及装置 - Google Patents

同频同时的数字信号处理方法及装置 Download PDF

Info

Publication number
WO2017202368A1
WO2017202368A1 PCT/CN2017/085961 CN2017085961W WO2017202368A1 WO 2017202368 A1 WO2017202368 A1 WO 2017202368A1 CN 2017085961 W CN2017085961 W CN 2017085961W WO 2017202368 A1 WO2017202368 A1 WO 2017202368A1
Authority
WO
WIPO (PCT)
Prior art keywords
digital signal
signal
transmitted
interference
received
Prior art date
Application number
PCT/CN2017/085961
Other languages
English (en)
French (fr)
Inventor
宋莲香
Original Assignee
中兴通讯股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Publication of WO2017202368A1 publication Critical patent/WO2017202368A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03178—Arrangements involving sequence estimation techniques
    • H04L25/03248—Arrangements for operating in conjunction with other apparatus
    • H04L25/03254—Operation with other circuitry for removing intersymbol interference

Definitions

  • the present disclosure relates to the field of digital signal processing technologies, for example, to a digital signal processing method and apparatus at the same time.
  • Full-duplex also known as two-way simultaneous communication, is an information interaction method in which both sides of communication can simultaneously send and receive information.
  • the communication theory and engineering technology research involved in the same-frequency full-duplex system has been fully developed, forming a self-interference suppression technology route combining airspace, radio frequency domain and digital domain.
  • the industry has researched and evaluated key technologies such as application scenarios, full-duplex networking, self-interference suppression, and radio resource management. It has built a full-duplex Long Term Evolution (LTE) and wireless LAN (WLAN).
  • LTE Long Term Evolution
  • WLAN wireless LAN
  • the system test platform can achieve self-interference suppression capability of more than 110dB, and is trying to expand from point-to-point full-duplex communication to multi-site multi-user real-world network environment.
  • the problems and technical challenges that need to be solved include: suppression of high-power dynamic self-interference signals, miniaturization of multi-antenna RF domain self-interference suppression circuit, and new network architecture under full-duplex system Coexistence and evolution strategies with interference cancellation mechanisms and FDD/TDD half-duplex systems.
  • Full-duplex maximizes the freedom of network and device transceiving design, eliminates the difference between FDD and TDD, and has the potential for network spectrum efficiency improvement. It can apply multiple scenarios, but the complexity and application conditions are different. The related chip industry is still not mature enough and needs to be promoted step by step.
  • FIG. 1 is a schematic diagram of a receiving interference problem caused by a transmitting-receiving co-frequency transceiver provided by the related art.
  • a receiver and a transmitter simultaneously use the same frequency resource, and both sides of the communication are on the uplink and In the downlink, the same frequency can be used for communication at the same time.
  • TX is the transmitter.
  • the effect of the transmitted signal on the received signal is mainly that the transmit signal of the antenna port is spatially coupled into the receive channel.
  • the signal at point B in 1 consists of two parts, namely the received signal and the interference signal S TX1 , and S TX1 mainly includes the transmitted signal S TX , the transmitted noise floor and the intermodulation interference. Since the full-duplex system transmits and receives the same frequency, the transmitted signal will seriously affect the reception of the received signal.
  • a digital signal processing method simultaneously with the same frequency comprising:
  • a digital signal processing device with simultaneous frequency comprising:
  • Receiving a digital signal acquisition module configured to acquire a received digital signal from a receive link
  • the interference cancellation module is configured to cancel the same-frequency transmit interference signal mixed in the received digital signal by using the transmitted digital signal.
  • a computer readable storage medium storing computer executable instructions arranged to perform the above method.
  • a communication device comprising:
  • At least one signal processor At least one signal processor
  • the memory stores instructions executable by the at least one signal processor, the instructions being executed by the at least one signal processor to cause the at least one signal processor to perform the method described above.
  • FIG. 1 is a schematic diagram of a receiving interference problem caused by a transmitting-receiving co-frequency transceiver provided by the related art
  • FIG. 2 is a flow chart of a digital signal processing method for simultaneous frequency matching according to an embodiment
  • FIG. 3 is a block diagram of a digital signal processing apparatus of the same frequency provided by an embodiment
  • FIG. 4 is a schematic block diagram of a full duplex technical solution provided by an embodiment
  • FIG. 5 is a schematic diagram of a transmission interference cancellation scheme in a digital link according to an embodiment
  • FIG. 6 is a flowchart of overall processing of an interference cancellation algorithm according to an embodiment
  • FIG. 7 is a schematic structural diagram of hardware of a communication device according to an embodiment.
  • FIG. 2 is a flowchart of a digital signal processing method at the same time as the same frequency provided in this embodiment.
  • step 110 the signal acquired from the transmit link is converted to a transmitted digital signal and the received digital signal is acquired from the receive link.
  • the transmit signal is obtained from the output of the circulator connected to the power amplifier in the transmit link, and the coupled transmit signal is subjected to RF sound table filtering, local oscillator mixing, anti-aliasing filtering, and variable gain amplifier ( After the variable Gain Amplifier, VGA) gain adjustment, low-pass filtering and analog-to-digital conversion processing, the transmitted digital signal is obtained. It is also possible to perform self-spurs cancellation processing on the transmitted digital signal to obtain a transmitted digital signal that eliminates spurious emissions. Among them, the spurious offset processing can be performed on the transmitted digital signal by the chip having the function of eliminating the spurious.
  • the received digital signal obtained from the receiving link is a signal obtained after self-blocking cancellation processing.
  • the antenna performs self-blocking cancellation processing on the received signal in the analog domain to reduce the transmitted interference signal in the receiving channel, and performs amplification processing and mode on the received signal of the self-blocking cancellation process.
  • the received digital signal subjected to the self-blocking cancellation process is obtained.
  • step 120 using the transmitted digital signal, the same mixed in the received digital signal The frequency emission interference signal is cancelled.
  • the interference cancellation parameter may include a delay between the received digital signal and the transmitted digital signal, a phase amplitude gain, and an equalization filter coefficient. Acquiring the same-frequency transmit interference signal in the received digital signal by using the interference cancellation parameter.
  • delaying compensation of the transmitted digital signal by using the first delay to obtain a compensated transmitted digital signal using a first between the compensated transmitted digital signal and the received digital signal
  • Two delays, a phase amplitude gain, and an equalization filter coefficient perform delay compensation and phase amplitude compensation on the received digital signal to obtain a compensated received digital signal
  • the compensated received digital signal is filtered to obtain a received digital signal that cancels the same frequency transmitted interference signal.
  • the storage medium may be a read-only memory (ROM), a random access memory (RAM), a magnetic disk, an optical disk, or the like.
  • FIG. 3 is a block diagram of a digital signal processing apparatus at the same time as the same frequency provided in the embodiment. As shown in FIG. 3, the apparatus includes a transmitting digital signal acquiring module, a receiving digital signal acquiring module, and an interference canceling module.
  • the transmit digital signal acquisition module is configured to convert the signal acquired from the transmit link to a transmit digital signal.
  • the transmitting digital signal acquiring module is configured to: obtain a transmitting signal from a circulator connected to the power amplifier in the transmitting link, perform RF link, low-pass filtering, and analog-to-digital conversion on the coupled transmitting signal. , get a digital signal.
  • the transmitted digital signal may be subjected to self-spurs cancellation processing after analog-to-digital conversion to obtain a transmitted digital signal that eliminates self-spurs.
  • the receive digital signal acquisition module is configured to acquire a received digital signal from the receive link.
  • the receiving digital signal blocks the low noise amplifier and the entire receiving link, and obtains from the receiving link.
  • the received digital signal may be a signal obtained after self-blocking cancellation processing.
  • the interference cancellation module is configured to cancel the same-frequency transmit interference signal mixed in the received digital signal by using the transmitted digital signal.
  • the interference cancellation module may determine an interference cancellation parameter according to the transmitted digital signal and the received digital signal, and use the interference cancellation parameter to cancel the same-frequency emission interference signal in the received digital signal.
  • the interference cancellation parameter may include a first delay, a phase amplitude gain, and an equalization filter coefficient between the received digital signal and the transmitted digital signal.
  • the interference cancellation module can be configured to:
  • the compensated received digital signal is filtered to obtain a received digital signal that cancels the same frequency transmitted interference signal.
  • This embodiment provides a digital signal cancellation method and apparatus implemented by software and hardware, and a digital signal cancellation method and apparatus will be described with reference to FIGS. 4 to 6.
  • FIG. 4 is a schematic block diagram of a full duplex technical solution provided by this embodiment.
  • a full-duplex schematic block diagram of FIG. 4 is proposed.
  • the downlink transmission channel includes a channel between an input of a digital to analog converter (DAC) and an output of a power amplifier (PA).
  • the upstream receive channel includes a channel between the Low Noise Amplifier (LNA) output and the output of the analog-to-digital converter ADC2.
  • LNA Low Noise Amplifier
  • the transmit interference digital cancellation reference channel is the channel through which the coupling point passes through the analog-to-digital converter ADC1 to the self-spur offset portion.
  • Transmitting Interference Signal The RF cancellation channel is the channel from the coupling point through the RF equalizer to the analog to digital converter to the LNA input.
  • the full-duplex technical solution architecture provided in this embodiment adds two cancellation channels, namely, a transmit interference digital cancellation reference channel and a transmit interference signal RF cancellation channel, and the two cancellation channels. Used separately In addition to receiving the same frequency transmission interference signal. As shown in FIG.
  • the radio frequency cancellation point of the transmitting interference signal is located before the reception, for example, the signal processing before the Low Noise Amplifier (LNA), which belongs to the analog signal cancellation, and the analog signal cancellation can reduce the transmission interference signal in the receiving channel.
  • LNA Low Noise Amplifier
  • the transmit interference digital cancellation reference channel can receive the transmit signal (ie, the coupled transmit signal) output from the circulator connected to the power amplifier in the transmit link, and the received signal can be received by the digital processing algorithm in the logic processing unit. The interference signal is cancelled.
  • the transmit signal mixed in the receive band and the interference signal such as the ground noise can be processed in the digital domain.
  • an accurate offset method is required, so processing in the digital domain can be prioritized.
  • a receiving link can be introduced as a reference channel, and the signal source of the receiving reference link is a signal coupled back from the circulator connected to the power amplifier in the transmitting channel (also called the transmitting link).
  • the received signal received by the receiving reference link and the receiving link can receive the digital signal, and the interference cancellation signal received by the receiving link is cancelled by the interference cancellation algorithm, thereby reducing the interference power of the receiving link.
  • FIG. 5 is a schematic diagram of a transmission interference cancellation scheme in the digital link provided by this embodiment.
  • the digital signal cancellation apparatus implemented by the software and hardware provided in this embodiment includes a logic processing unit and a signal processor.
  • the logic processing unit receives the transmitted signal from the reference channel through RF sound table filtering, local oscillator mixing, anti-aliasing filtering, VGA gain adjustment, low-pass filtering, and analog to digital converter (ADC) ADC1 sampling.
  • ADC analog to digital converter
  • the logic processing unit acquires the received digital signal sampled by the ADC2 from the receiving channel, and transmits the collected transmitted digital signal and the received digital signal to the signal processor.
  • the signal processor performs a delay search according to the obtained transmitted digital signal and the received digital signal, and determines a delay capable of aligning the data of the transmitted digital signal and the received digital signal; and according to the determined delay, transmitting the digital signal and Receiving a digital signal for phase amplitude gain alignment processing to obtain a phase amplitude gain; calculating an equalization filter coefficient and the like according to the aligned transmitted digital signal and the received digital signal; and transmitting the delay, the phase amplitude gain parameter, and the equalization filter coefficient to Logical processing unit.
  • the logic processing unit performs corresponding processing including delay compensation on the transmitted digital signal and the received digital signal according to the received delay, the phase amplitude gain parameter and the equalization filter coefficient, and realizes the same-frequency emission interference signal in the received digital signal. eliminate.
  • Simultaneous digital signal processing methods include:
  • the logic processing unit collects data samples, wherein the data samples include samples and connections that transmit digital signals a sample of the digital signal received;
  • the signal processor performs model optimization based on the data in the sample, and finds the optimal time delay of data alignment in the sample;
  • the signal processor performs phase amplitude gain alignment on the collected sample data according to the calculated delay
  • the signal processor uses the sample data after alignment to obtain an equalization filter coefficient
  • the signal processor configures the obtained delay, phase amplitude gain, and equalization filter coefficients to the logic processing unit;
  • the logic processing unit performs digital signal cancellation processing.
  • the transmit interference digital link cancellation scheme is shown in Figure 5.
  • the digital offset processing is performed by the receive reference channel (ie, the reference channel), the logic processing unit, and the signal processor.
  • the receive reference channel can couple the transmit signal from the output of the transmit link to the power amplifier to the circulator, and the coupled transmit signal is converted to a digital signal via a radio frequency link, low pass filtering, and analog to digital conversion on the logical processor.
  • a digital processing algorithm that implements interference cancellation.
  • the interference cancellation algorithm utilizes the characteristics of the homologous signal of the transmitting signal and the interference signal received by the receiving channel as the transmitting signal, and performs a series of algorithm processing on the digital signal received by the receiving reference channel and the signal received by the receiving channel.
  • the digital signal received by the receiving reference channel is obtained as a channel distortion parameter that receives the interference signal through a series of transmission channels.
  • the implementation framework of the interference cancellation algorithm is shown in Figure 5.
  • the implementation of the algorithm can be divided into two parts: the signal processor and the logic processing unit.
  • the signal processor implements parameter extraction, and performs algorithm processing on the transmitted digital signal and the received digital signal collected by the logic processing unit, extracts delay and phase amplitude gain between the transmitted digital signal and the received digital signal, and calculates an equalization filter coefficient.
  • the delay, the phase amplitude gain, and the equalization filter coefficient are sent to the interference cancellation algorithm processing module of the logic processing unit, and the real-time interference cancellation is performed by the logic processing unit.
  • the logic processing unit can implement interference cancellation real-time processing, and the interference cancellation real-time processing can include receiving data acquisition, delay compensation, gain phase compensation, equalization filtering processing, and interference cancellation processing of the reference link and the receiving link.
  • FIG. 6 is a flowchart of the interference cancellation algorithm provided by this embodiment.
  • the digital signal cancellation includes the following steps.
  • step 210 the signal processor instructs the logic processing unit to perform sample acquisition.
  • step 220 the logic processing unit performs sample collection.
  • step 230 the signal processor reads the acquired sample data.
  • step 240 the signal processor performs a delay search on the collected sample data.
  • step 250 after the sample data is time aligned, the signal processor performs phase amplitude gain alignment.
  • step 260 the signal processor performs equalization filter coefficient determination based on the sample data after processing.
  • step 270 the signal processor performs a data check.
  • step 280 the signal processor updates the quantization model parameters to the logic processing unit for the logic processing unit to perform signal cancellation processing.
  • the signal processor may be a digital signal processor (DSP), and the logic processing unit may be a logical processor, such as a Field Programmable Gate Array (FPGA).
  • DSP digital signal processor
  • FPGA Field Programmable Gate Array
  • the present embodiment provides a computer readable storage medium storing computer executable instructions arranged to perform the method of any of the above embodiments.
  • the communication device includes:
  • a processor 70, and a memory 71 and a logical processor 72, which are respectively communicatively coupled to the signal processor 70, may further include a communication interface 73 and a bus 74.
  • the signal processor 70, the memory 71, the logical processor 72, and the communication interface 73 can complete communication with each other through the bus 74.
  • Communication interface 73 can be used for information transmission.
  • the Communications Interface 73 includes a downlink transmit channel and an uplink receive channel.
  • Signal processor 70 can invoke logic instructions in memory 71 to perform the methods of the above-described embodiments.
  • logic instructions in the memory 71 described above may be implemented in the form of a software functional unit and sold or used as a stand-alone product, and may be stored in a computer readable storage medium.
  • the memory 71 is a computer readable storage medium and can be used to store software programs, computer executable programs, such as program instructions or modules corresponding to the methods in the above embodiments.
  • the signal processor 70 performs the function application and the data processing by executing a software program, an instruction or a module stored in the memory 71, that is, the method in the above embodiment is implemented.
  • the memory 71 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application required for at least one function; the storage data area may store data created according to usage of the terminal device, and the like. Further, the memory 71 may include a high speed random access memory, and may also include a nonvolatile memory.
  • the above technical solution may be embodied in the form of a software product stored in a storage medium, including one or more instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to execute All or part of the steps of the method in the above embodiments.
  • the foregoing storage medium may be a non-transitory storage medium, including: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Noise Elimination (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

一种同频同时的数字信号处理方法及装置，该方法包括：将从发射链路获取的信号转换为发射数字信号；从接收链路获取接收数字信号；以及利用所述发射数字信号，对所述接收数字信号中混入的同频发射干扰信号进行抵消。

Description

同频同时的数字信号处理方法及装置 技术领域
本公开涉及数字信号处理技术领域，例如涉及一种同频同时的数字信号处理方法及装置。
背景技术
无线通信业务的推广引发了需求激增与频谱资源紧缺的外在矛盾，正驱动无线通信标准的内在变革。提升频分双工(Frequency Division Duplex，FDD)与时分双工(Time Division Duplexing，TDD)的频谱效率，并消除FDD和TDD对频谱资源利用方式的差异性，成为第五代移动通信系统(5th generation mobile networks，5G)通信革新的一个目标。基于自干扰抑制理论和技术的同频同时全双工成为实现这一目标的解决方案，它从理论极限上可提升一倍的频谱效率。
全双工又称为双向同时通信，是一种通信的双方可以同时发送和接收信息的信息交互方式。同时同频全双工体制涉及的通信理论与工程技术研究已全面展开，形成了空域、射频域、数字域联合的自干扰抑制技术路线。业界对应用场景、全双工组网、自干扰抑制、无线资源管理等关键技术方向进行了研究和评估；搭建了全双工长期演进(Long Term Evolution，LTE)和无线局域网(Wireless LAN，WLAN)系统测试平台，能够实现110dB以上的自干扰抑制能力，正在努力尝试从点对点全双工通信向多站多用户现实网络环境拓展。
全双工技术的实用化进程中，尚需解决的问题和技术挑战包括：大功率动态自干扰信号的抑制，多天线射频域自干扰抑制电路的小型化，全双工体制下的网络新架构与干扰消除机制，与FDD/TDD半双工体制的共存和演进策略。
全双工最大限度的提升了网络和设备收发设计的自由度，可消除FDD和TDD差异性，具备潜在的网络频谱效率提升能力，它可应用多种场景，但复杂度和应用条件不尽相同，相关芯片产业还不够成熟，需要逐阶段推进。
图1是相关技术提供的发射-接收同频收发带来的接收干扰问题示意图，同频同时全双工通信系统中，接收机和发射机同时使用相同的频率资源，通信双方在上行链路和下行链路中可以在相同的时间使用相同的频率进行通信，如图1 所示，TX为发射机，发射信号对接收信号的影响主要是天线口的发射信号从空间耦合进入接收通道，在图1中B点的信号由两部分组成，即接收信号和干扰信号STX1，STX1主要包括发射信号STX、发射底噪和互调干扰。由于全双工系统收发同频，发射信号会严重影响到接收信号的接收。
发明内容
以下技术方案避免了全双工系统收发同频而导致发射信号严重影响接收信号的接收。
一种同频同时的数字信号处理方法，包括：
将从发射链路获取的信号转换为发射数字信号；
从接收链路获取接收数字信号；以及
利用所述发射数字信号，对所述接收数字信号中混入的同频发射干扰信号进行抵消。
一种同频同时的数字信号处理装置，包括：
发射数字信号获取模块，设置为将从发射链路获取的信号转换为发射数字信号；
接收数字信号获取模块，设置为从接收链路获取接收数字信号；以及
干扰消除模块，设置为利用所述发射数字信号，对所述接收数字信号中混入的同频发射干扰信号进行抵消。
一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令设置为执行上述方法。
一种通信设备，包括：
至少一个信号处理器；以及
分别与所述至少一个信号处理器通信连接的存储器和逻辑处理器；其中，
所述存储器存储有可被所述至少一个信号处理器执行的指令，所述指令被所述至少一个信号处理器执行，以使所述至少一个信号处理器执行上述的方法。
通过对同频发射干扰信号进行抵消，避免了全双工系统收发同频而导致的发射信号严重影响接收信号接收的问题。
附图说明
图1是相关技术提供的发射-接收同频收发带来的接收干扰问题示意图；
图2是一实施例提供的同频同时的数字信号处理方法流程图；
图3是一实施例提供的同频同时的数字信号处理装置框图；
图4是一实施例提供的全双工技术方案原理框图；
图5是一实施例提供的数字链路中发射干扰抵消方案示意图；
图6是一实施例提供的干扰抵消算法总体处理流程图；以及
图7是一实施例提供的通信设备的硬件结构示意图。
具体实施方式
以下结合附图对可选实施例进行详细说明，以下所说明的可选实施例仅用于说明和解释技术方案，并不用于限定技术方案。在不冲突的情况下，以下实施例以及实施例中的技术特征可以相互任意组合。
图2是本实施例提供的同频同时的数字信号处理方法流程图。
在步骤110中，将从发射链路获取的信号转换为发射数字信号，并从接收链路获取接收数字信号。
可选的，从发射链路中与功率放大器连接的环形器的输出端获取发射信号，对耦合回来的发射信号进行射频声表滤波、本振混频、抗混叠滤波、可变增益放大器(Variable Gain Amplifier，VGA)增益调整、低通滤波及模数转换处理后，得到发射数字信号。还可以对所述发射数字信号进行自杂散抵消处理，得到消除自杂散的发射数字信号。其中，可以通过具有消除自杂散功能的芯片对发射数字信号进行自杂散抵消处理。
可选的，从接收链路获取的接收数字信号是经过自阻塞抵消处理后得到的信号。例如，天线收到接收信号后，通过在模拟域对该接收信号进行自阻塞抵消处理，降低接收通道中的发射干扰信号，对经自阻塞抵消处理的接收信号进行低噪声放大器的放大处理和模数转换器的转换处理后，得到经自阻塞抵消处理的接收数字信号。
在步骤120中，利用所述发射数字信号，对所述接收数字信号中混入的同 频发射干扰信号进行抵消。
可选的，根据所述发射数字信号和所述接收数字信号，确定干扰抵消参数，并利用所述干扰抵消参数，对所述接收数字信号中的同频发射干扰信号进行消除。
所述干扰抵消参数可以包括所述接收数字信号和所述发射数字信号之间的时延、相位幅度增益和均衡滤波系数。利用所述干扰抵消参数，对所述接收数字信号中的同频发射干扰信号进行消除。
可选的，利用所述第一时延，对所述发射数字信号进行时延补偿，得到经过补偿的发射数字信号；利用所述经过补偿的发射数字信号和所述接收数字信号之间的第二时延、相位幅度增益和均衡滤波系数对所述接收数字信号进行时延补偿和相位幅度补偿，得到经过补偿的接收数字信号；以及
对所述经过补偿的接收数字信号进行滤波处理，得到消除同频发射干扰信号的接收数字信号。
实现上述实施例方法中的全部或部分步骤是可以通过程序来配合相关的硬件来完成，所述的程序可以存储于计算机可读取存储介质中，该程序可执行以上实施例中的方法。其中，所述的存储介质可以为只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟、光盘等。
图3是本实施例提供的同频同时的数字信号处理装置框图，如图3所示，所述装置包括发射数字信号获取模块、接收数字信号获取模块和干扰消除模块。
发射数字信号获取模块设置为将从发射链路获取的信号转换为发射数字信号。
可选的，所述发射数字信号获取模块设置为：从发射链路中与功率放大器连接的环形器获取发射信号，对耦合回来的发射信号进行射频链路、低通滤波及模数转换等处理，得到发射数字信号。为提高后续处理过程中的干扰消除质量，还可以在模数转换之后对所述发射数字信号进行自杂散抵消处理，得到消除自杂散的发射数字信号。
接收数字信号获取模块设置为从接收链路获取接收数字信号。为避免后续处理过程中，接收数字信号阻塞低噪声放大器和整个接收链路，从接收链路获 取的接收数字信号可以是经过自阻塞抵消处理后得到的信号。
干扰消除模块设置为利用所述发射数字信号，对所述接收数字信号中混入的同频发射干扰信号进行抵消。所述干扰消除模块可以根据所述发射数字信号和所述接收数字信号，确定干扰抵消参数，并利用所述干扰抵消参数，对所述接收数字信号中的同频发射干扰信号进行消除。
可选的，所述干扰抵消参数可以包括所述接收数字信号和所述发射数字信号之间的第一时延、相位幅度增益和均衡滤波系数。
所述干扰消除模块可以设置为：
利用所述第一时延，对所述发射数字信号进行时延补偿，得到经过补偿的发射数字信号；
利用所述经过补偿的发射数字信号和所述接收数字信号之间的第二时延、所述相位幅度增益和所述均衡滤波参数，对所述接收数字信号进行时延补偿和相位幅度增益补偿，得到经过补偿的接收数字信号；以及
对所述经过补偿的接收数字信号进行滤波处理，得到消除同频发射干扰信号的接收数字信号。
本实施例提供软件和硬件实现的数字信号抵消方法和装置，结合图4至图6对数字信号抵消方法和装置进行描述。
图4是本实施例提供的全双工技术方案原理框图。如图4所示，为了消除图1所示的干扰信号，提出了图4的全双工的原理框图，图4中，从上往下依次有4个通道，分别是下行发射通道、发射干扰数字抵消参考通道(接收参考通道)、发射干扰信号射频抵消通道和上行接收通道(接收通道)。其中，下行发射通道包括数字模拟转换器(Digital to Analog Converter，DAC)的输入端至功率放大器(Power Amplifier，PA)的输出端之间的通道。上行接收通道包括低噪声放大器(Low Noise Amplifier，LNA)输出端至模拟数字转换器ADC2输出端之间的通道。发射干扰数字抵消参考通道是耦合点经模拟数字转换器ADC1至自杂散抵消部分的通道。发射干扰信号射频抵消通道是从耦合点经射频均衡器至模拟数字转换器至LNA输入端之间的通道。与相关技术中的收发信机架构相比，本实施例提供的全双工技术方案架构增加了两个抵消通道，即发射干扰数字抵消参考通道和发射干扰信号射频抵消通道，这两个抵消通道分别用于消 除接收的同频发射干扰信号。如图4所示，发射干扰信号射频抵消点位于接收之前，例如在低噪声放大器(Low Noise Amplifier，LNA)之前的信号处理，属于模拟信号抵消，模拟信号抵消可以降低接收通道中的发射干扰信号，以避免发射干扰信号阻塞低噪声放大器和整个接收链路。发射干扰数字抵消参考通道可以接收发射链路中与功率放大器连接的环形器输出的发射信号(即耦合回来的发射信号)，在逻辑处理单元中可以利用数字处理算法对接收链路接收进来的发射干扰信号进行抵消。
在发射干扰数字抵消链路中，可以在数字域处理接收频带内混入的发射信号和发射底噪等干扰信号。为了不影响接收信号，需要精确的抵消方式，所以可以优先考虑在数字域进行处理。发射干扰数字抵消过程中，可以引入一个接收链路作为参考通道，该接收参考链路的信号源是从发射通道(也称发射链路)中与功率放大器连接的环行器之后耦合回来的信号。在逻辑处理单元中可以根据接收参考链路接收回来的发射信号与接收链路接收到数字信号，通过干扰抵消算法把接收链路接收到的发射干扰信号抵消掉，降低接收链路的干扰功率。
图5是本实施例提供的数字链路中发射干扰抵消方案示意图，如图5所示，本实施例提供的软件和硬件共同实现的数字信号抵消装置包括逻辑处理单元和信号处理器。逻辑处理单元从接收参考通道得到的发射信号经过射频声表滤波、本振混频、抗混叠滤波、VGA增益调整、低通滤波及模数转换器(Analog to Digital Converter，ADC)ADC1采样，变为数字信号(即发射数字信号)，逻辑处理单元从接收通道获取经由ADC2采样的接收数字信号，将采集的发射数字信号和接收数字信号发送给信号处理器。信号处理器根据得到的发射数字信号和接收数字信号，进行时延搜索，确定能够使发射数字信号和接收数字信号的数据对齐最优的时延；根据所确定的时延，对发射数字信号和接收数字信号进行相位幅度增益的对齐处理，得到相位幅度增益；根据对齐后的发射数字信号和接收数字信号，计算均衡滤波系数等参数；以及将时延、相位幅度增益参数、均衡滤波系数发送至逻辑处理单元。逻辑处理单元根据收到的时延、相位幅度增益参数和均衡滤波系数，对发射数字信号和接收数字信号进行相应的包括时延补偿的处理，实现对接收数字信号中的同频发射干扰信号的消除。
同频同时的数字信号处理方法包括：
逻辑处理单元采集数据样本，其中数据样本包括发射数字信号的样本和接 收数字信号的样本；
信号处理器根据样本中的数据，进行模型寻优，找到样本中的数据对齐最优的时延；
信号处理器根据计算的时延，对采集的样本数据进行相位幅度增益对齐；
信号处理器利用对齐之后的样本数据，求取均衡滤波系数；
信号处理器将求取的时延、相位幅度增益、均衡滤波系数配置到逻辑处理单元；以及
逻辑处理单元进行数字信号抵消处理。
发射干扰数字链路抵消方案如图5所示，由接收参考通道(即参考通道)、逻辑处理单元和信号处理器共同完成数字抵消处理。接收参考通道可以从发射链路中与功率放大器连接环形器的输出端把发射信号耦合回来，耦合回来的发射信号经过射频链路、低通滤波及模数转换转换成数字信号，在逻辑处理器中实现干扰抵消的数字处理算法。
干扰抵消算法利用接收参考通道的发射数字信号与接收通道接收到的干扰信号均为发射信号的同源信号的特性，把接收参考通道接收的数字信号与接收通道接收的信号进行一系列算法处理，求取接收参考通道接收的数字信号经过一系列传输信道变为接收干扰信号的信道失真参数。
干扰抵消算法的实现方案框架如图5所示，该算法的实现可以分为两个部分：信号处理器和逻辑处理单元。其中，信号处理器实现参数提取，通过对逻辑处理单元采集的发射数字信号和接收数字信号进行算法处理，提取发射数字信号和接收数字信号之间的时延、相位幅度增益，并计算均衡滤波系数，将延、相位幅度增益以及均衡滤波系数发送给逻辑处理单元的干扰抵消算法处理模块，并由逻辑处理单元完成实时干扰抵消。逻辑处理单元可以实现干扰抵消实时处理，干扰抵消实时处理可以包括接收参考链路和接收链路的数据采集，时延补偿，增益相位补偿，均衡滤波处理及干扰抵消处理。
图6是本实施例提供的干扰抵消算法流程图，在图4的基础上，数字信号抵消包括以下步骤。
在步骤210中，信号处理器指示逻辑处理单元进行样本采集。
在步骤220中，逻辑处理单元进行样本采集。
在步骤230中，信号处理器读取采集的样本数据。
在步骤240中，信号处理器对采集的样本数据进行时延搜索。
在步骤250中，样本数据时延对齐之后，信号处理器进行相位幅度增益对齐。
在步骤260中，信号处理器根据处理之后的样本数据，进行均衡滤波系数求取。
在步骤270中，信号处理器进行数据校验。
在步骤280中，信号处理器将量化模型参数更新到逻辑处理单元中，以供逻辑处理单元进行信号抵消处理。
其中，所述信号处理器可以是数字信号处理器(Digital Signal Processing，DSP)，逻辑处理单元可以是逻辑处理器，例如现场可编程逻辑阵列(Field Programmable Gate Array，FPGA)。
本实施例提供了一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令设置为执行上述任一实施例中的方法。
本实施例提供了一种通信设备的硬件结构示意图。参见图7，该通信设备包括：
信号处理器(processor)70，以及分别与信号处理器70通信连接的存储器(memory)71和逻辑处理器72，还可以包括通信接口(Communications Interface)73和总线74。其中，信号处理器70、存储器71、逻辑处理器72以及通信接口73可以通过总线74完成相互间的通信。通信接口73可以用于信息传输。通信接口(Communications Interface)73包括下行发射通道和上行接收通道。信号处理器70可以调用存储器71中的逻辑指令，以执行上述实施例的方法。
此外，上述的存储器71中的逻辑指令可以通过软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。
存储器71作为一种计算机可读存储介质，可用于存储软件程序、计算机可执行程序，如上述实施例中的方法对应的程序指令或模块。信号处理器70通过运行存储在存储器71中的软件程序、指令或模块，从而执行功能应用以及数据处理，即实现上述实施例中的方法。
存储器71可包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序；存储数据区可存储根据终端设备的使用所创建的数据等。此外，存储器71可以包括高速随机存取存储器，还可以包括非易失性存储器。
以上技术方案可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括一个或多个指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行上述实施例中方法的全部步骤或部分步骤。而前述的存储介质可以是非暂态存储介质，包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等多种可以存储程序代码的介质，也可以是暂态存储介质。

Claims (13)

  1. 一种同频同时的数字信号处理方法，包括：
    将从发射链路获取的信号转换为发射数字信号；
    从接收链路获取接收数字信号；以及
    利用所述发射数字信号，对所述接收数字信号中混入的同频发射干扰信号进行抵消。
  2. 根据权利要求1所述的方法，其中，所述将从发射链路获取的信号转换为发射数字信号包括：
    从发射链路中与功率放大器连接的环形器获取发射信号；以及
    将所述发射信号进行包括模数转换的处理，得到发射数字信号。
  3. 根据权利要求2所述的方法，其中，将所述发射信号进行包括模数转换的处理，得到发射数字信号之后，所述方法还包括：
    对所述发射数字信号进行自杂散抵消处理，得到消除自杂散的发射数字信号。
  4. 根据权利要求1所述的方法，其中，从接收链路获取的接收数字信号是经过自阻塞抵消处理后得到的信号。
  5. 根据权利要求1所述的方法，其中，所述利用所述发射数字信号，对所述接收数字信号中混入的同频发射干扰信号进行抵消包括：
    根据所述发射数字信号和所述接收数字信号，确定干扰抵消参数；以及
    利用所述干扰抵消参数，对所述接收数字信号中的同频发射干扰信号进行消除。
  6. 根据权利要求5所述的方法，其中，所述干扰抵消参数包括所述接收数字信号和所述发射数字信号之间的第一时延、相位幅度增益和均衡滤波系数；
    所述利用所述干扰抵消参数，对所述接收数字信号中的同频发射干扰信号 进行消除包括：
    利用所述第一时延，对所述发射数字信号进行时延补偿，得到经过补偿的发射数字信号；
    利用所述经过补偿的发射数字信号和所述接收数字信号之间的第二时延、所述相位幅度增益和所述均衡滤波系数，对所述接收数字信号进行时延补偿和相位幅度增益补偿，得到经过补偿的接收数字信号；以及
    对所述经过补偿的接收数字信号进行滤波处理，得到消除同频发射干扰信号的接收数字信号。
  7. 一种同频同时的数字信号处理装置，包括：
    发射数字信号获取模块，设置为将从发射链路获取的信号转换为发射数字信号；
    接收数字信号获取模块，设置为从接收链路获取接收数字信号；以及
    干扰消除模块，设置为利用所述发射数字信号，对所述接收数字信号中混入的同频发射干扰信号进行抵消。
  8. 根据权利要求7所述的装置，其中，所述发射数字信号获取模块设置为：从发射链路中与功率放大器连接的环形器获取发射信号，并将所述发射信号进行包括模数转换的处理，得到发射数字信号。
  9. 根据权利要求8所述的装置，其中，所述发射数字信号获取模块设置为将所述发射信号进行包括模数转换的处理，得到发射数字信号之后，对所述发射数字信号进行自杂散抵消处理，得到消除自杂散的发射数字信号。
  10. 根据权利要求7所述的装置，其中，所述接收数字信号获取模块从接收链路获取的接收数字信号是经过自阻塞抵消处理后得到的信号。
  11. 根据权利要求7所述的装置，其中，所述干扰消除模块设置为：根据 所述发射数字信号和所述接收数字信号，确定干扰抵消参数，并利用所述干扰抵消参数，对所述接收数字信号中的同频发射干扰信号进行消除。
  12. 根据权利要求11所述的装置，其中，所述干扰抵消参数包括所述接收数字信号和所述发射数字信号之间的第一时延、相位幅度增益和均衡滤波系数，
    所述干扰消除模块设置为：
    利用所述第一时延，对所述发射数字信号进行时延补偿，得到经过补偿的发射数字信号；
    利用所述经过补偿的发射数字信号和所述接收数字信号之间的第二时延、所述相位幅度增益和所述均衡滤波参数，对所述接收数字信号进行时延补偿和相位幅度增益补偿，得到经过补偿的接收数字信号；
    对所述经过补偿的接收数字信号进行滤波处理，得到消除同频发射干扰信号的接收数字信号。
  13. 一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令设置为执行权利要求1-6中任一项的方法。
PCT/CN2017/085961 2016-05-25 2017-05-25 同频同时的数字信号处理方法及装置 WO2017202368A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610352703.X 2016-05-25
CN201610352703.XA CN107438039A (zh) 2016-05-25 2016-05-25 一种同频同时的数字信号抵消方法及装置

Publications (1)

Publication Number Publication Date
WO2017202368A1 true WO2017202368A1 (zh) 2017-11-30

Family

ID=60411066

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/085961 WO2017202368A1 (zh) 2016-05-25 2017-05-25 同频同时的数字信号处理方法及装置

Country Status (2)

Country Link
CN (1) CN107438039A (zh)
WO (1) WO2017202368A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110912582A (zh) * 2018-09-17 2020-03-24 西安中兴新软件有限责任公司 同时同频全双工自干扰信号消除方法、设备和存储介质
CN111107027A (zh) * 2019-12-05 2020-05-05 北京航空航天大学杭州创新研究院 一种高性能同频全双工自干扰抵消方法
CN112401868A (zh) * 2019-08-21 2021-02-26 西门子(深圳)磁共振有限公司 呼吸检测装置、方法及磁共振成像系统

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109428624B (zh) * 2017-08-29 2021-01-08 维沃移动通信有限公司 信号处理方法、网络设备、终端及计算机可读存储介质
CN108599789A (zh) * 2018-03-30 2018-09-28 清华大学 全双工射频自干扰抑制方法及装置
CN109639322B (zh) * 2019-01-30 2021-07-23 北京慧通微电科技有限公司 基于数模联合分频的电力线载波通信系统及全双工方法
CN112468239B (zh) * 2020-10-29 2022-05-24 西安空间无线电技术研究所 多维度光电联合的同时同频全双工自干扰抑制系统及方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103338172A (zh) * 2013-07-24 2013-10-02 电子科技大学 一种多径环境下同时同频全双工自干扰抵消方法
CN104518808A (zh) * 2013-09-29 2015-04-15 华为技术有限公司 自干扰信号消除设备及方法
CN104811213A (zh) * 2014-01-28 2015-07-29 华为技术有限公司 自干扰信号消除设备及方法
CN104935540A (zh) * 2015-05-21 2015-09-23 电子科技大学 一种同时同频全双工极限自干扰抵消方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101170321B (zh) * 2006-10-25 2010-11-10 杭州华三通信技术有限公司 一种以太网传输装置
US9136883B1 (en) * 2014-08-20 2015-09-15 Futurewei Technologies, Inc. Analog compensation circuit and method
CN105119629B (zh) * 2015-07-10 2018-04-06 惠州Tcl移动通信有限公司 同时同频全双工终端和系统
CN105099495B (zh) * 2015-08-06 2018-05-08 惠州Tcl移动通信有限公司 一种收发共用天线的同时同频全双工终端及其通信方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103338172A (zh) * 2013-07-24 2013-10-02 电子科技大学 一种多径环境下同时同频全双工自干扰抵消方法
CN104518808A (zh) * 2013-09-29 2015-04-15 华为技术有限公司 自干扰信号消除设备及方法
CN104811213A (zh) * 2014-01-28 2015-07-29 华为技术有限公司 自干扰信号消除设备及方法
CN104935540A (zh) * 2015-05-21 2015-09-23 电子科技大学 一种同时同频全双工极限自干扰抵消方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110912582A (zh) * 2018-09-17 2020-03-24 西安中兴新软件有限责任公司 同时同频全双工自干扰信号消除方法、设备和存储介质
CN110912582B (zh) * 2018-09-17 2023-04-07 西安中兴新软件有限责任公司 同时同频全双工自干扰信号消除方法、设备和存储介质
CN112401868A (zh) * 2019-08-21 2021-02-26 西门子(深圳)磁共振有限公司 呼吸检测装置、方法及磁共振成像系统
CN111107027A (zh) * 2019-12-05 2020-05-05 北京航空航天大学杭州创新研究院 一种高性能同频全双工自干扰抵消方法
CN111107027B (zh) * 2019-12-05 2022-06-28 北京航空航天大学杭州创新研究院 一种高性能同频全双工自干扰抵消方法

Also Published As

Publication number Publication date
CN107438039A (zh) 2017-12-05

Similar Documents

Publication Publication Date Title
WO2017202368A1 (zh) 同频同时的数字信号处理方法及装置
US11283530B2 (en) Wideband remote unit for distributed antenna system
WO2015127816A1 (zh) 一种减少邻频干扰的方法及中继设备
US9813168B2 (en) Self-interference signal cancellation device and method
US9973233B2 (en) Interference cancellation apparatus and method
WO2018076373A1 (zh) 一种塔顶设备及无源互调消除方法
Askar et al. Active self-interference cancellation mechanism for full-duplex wireless transceivers
CN104716972A (zh) 提高接收器灵敏度
EP2775681B1 (en) Method, device and base station system for transceiving and processing radio frequency signal
US9813140B2 (en) Radio frequency transmitter
EP3866422B1 (en) Method, device and system for interference elimination
US9432063B2 (en) Radio frequency signal transceiving and processing method, device, and base station system
WO2020220196A1 (zh) 控制谐波干扰的方法和装置
CN104243059B (zh) 一种基于无线局域网的中继传输系统及优化方法
US20210175858A1 (en) Radio transceiver arrangement and method
CN110061759B (zh) 一种电磁频谱伞罩射频域自干扰抑制方法及系统
CN110677216B (zh) 面向电子对抗的数字射频前端及射频信号频率检测方法
US9887714B2 (en) Remote radio head and associated method
CN104283826A (zh) 一种数字补偿方法、装置及双工器
CN207166490U (zh) 一种lte数字直放站
CN108886405B (zh) 一种信号滤波的方法、设备及系统
TW201545490A (zh) 同時通訊的增強接收靈敏度
CN220067407U (zh) 基于宽带接收机的模数混合数字域干扰抵消电路
WO2023109856A1 (zh) 通信收发器、信号收发方法、电子设备及存储介质
WO2020051798A1 (zh) 辐射杂散信号的对消方法和装置

Legal Events

Date Code Title Description
NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17802214

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 17802214

Country of ref document: EP

Kind code of ref document: A1