WO2017201947A1

WO2017201947A1 - Transistor having field plate and lightly-doped drain region

Info

Publication number: WO2017201947A1
Application number: PCT/CN2016/101838
Authority: WO
Inventors: 王佳佳; 丁庆
Original assignee: 华讯方舟科技有限公司; 深圳市华讯方舟微电子科技有限公司
Priority date: 2016-05-25
Filing date: 2016-10-12
Publication date: 2017-11-30
Also published as: CN105826370A

Abstract

A transistor having a field plate (140) and a lightly-doped drain region (112), the lightly-doped drain region being provided in a potential energy barrier layer (110) of the transistor. The lightly-doped drain region has a different electronegativity from other regions of the potential energy barrier layer excluding the lightly-doped drain region, and therefore, the lightly-doped drain region can regulate a two-dimensional electron gas in the potential energy barrier layer to change the electrical field strength of a depletion layer below a gate (120) and in the potential energy barrier layer, thus re-distributing the electrical field, reducing the peak value of the electrical field, reducing the trapping effect, and accordingly increasing the breakdown voltage. The present invention also introduces the field plate to lower the curvature of a border of the depletion layer at a periphery of the gate and modulate the distribution of the electrical field, thus reducing the peak value of the electrical field, reducing the trapping effect, and further increasing the breakdown voltage. Under action of both the lightly-doped drain region and the field plate, the present invention greatly increases the breakdown voltage of the transistor and improves operational stability of the transistor.

Description

Transistor with field plate and low doped drain

[Technical Field]

The present invention relates to the field of electronic device technology, and more particularly to a transistor having a field plate and a low doped drain region.

【Background technique】

GaN material has a wide band gap, high breakdown electric field, high thermal conductivity, radiation resistance, corrosion resistance and other good electrical properties. It is the first generation semiconductor material Ge, Si, second generation compound semiconductor material. Typical representatives of third-generation semiconductor materials after GaAs and InP are ideal materials for making high-frequency, high-temperature, high-voltage, high-power electronic devices and high-power optoelectronic devices. More importantly, the GaN material can form an AlGaN/GaN structure, and under the action of spontaneous polarization and piezoelectric polarization, a two-dimensional electron gas (two-dimensional) having a higher heterojunction concentration than the second-generation compound semiconductor can be obtained. Electron gas, 2DEG), which has high electron mobility, extremely high peak electron velocity and electron saturation velocity. Therefore, AlGaN /GaN high electron mobility transistors (AlGaN/GaN HEMT) have good prospects for high-power microwave devices. The structure of the AlGaN/GaN HEMT is shown in Figure 1.

AlGaN/GaN The structure not only has significant advantages in high-temperature and high-power microwave devices, but also shows great advantages in high-performance high-voltage, low-loss, anti-irradiation power switching devices. However, there is still a problem that the breakdown voltage VBR is low. AlGaN/GaN The low breakdown voltage of the HEMT seriously affects the stability of the device operation.

[Summary of the Invention]

Based on this, it is necessary to provide a transistor having a field plate and a low doped drain region in view of the problem that the existing high electron mobility transistor has a low breakdown voltage.

A transistor having a field plate and a low doped drain region, comprising: a barrier layer, a gate, a drain, a field plate, and a low doped drain region;

The low doped drain region is disposed inside the barrier layer between the gate and the drain, and one end of the low doped drain region coincides with the edge of the drain, and the other end of the low doped drain region does not coincide with the edge of the gate. ;

The field plate is connected to the gate and the field plate is between the gate and the drain.

A transistor having a field plate and a low doped drain region, including a barrier layer, a gate, a source, a drain, a field plate, and a low doped drain region;

The field plate is connected to the gate and the field plate is located between the gate and the source.

The field plate is connected to the source, and the field plate is located between the gate and the source.

A transistor having a field plate and a low doped drain region includes a barrier layer, a gate, a source, a drain, a first field plate, a second field plate, and a low doped drain region;

The first field plate is connected to the gate, and the first field plate is located between the gate and the drain;

The second field plate is connected to the gate, the second field plate is between the gate and the source, or the second field plate is connected to the source, and the second field plate is between the gate and the source.

According to the above-described transistor of the present invention having a field plate and a low doped drain region, a low doping drain region is provided in the barrier layer of the transistor due to low doping leakage in the low doped drain region and the barrier layer The difference in electronegativity of the region outside the region, the presence of the low doping drain region can adjust the two-dimensional electron gas in the barrier layer, change the electric field strength of the depletion layer under the gate in the barrier layer, and redistribute the electric field. The electric field peak is reduced, the trap effect is reduced, the breakdown voltage is increased, and the field plate is introduced. The curvature of the boundary of the gate edge depletion layer is weakened, the electric field distribution is modulated, the peak electric field is reduced, and the trap effect is reduced, which further improves. The breakdown voltage greatly reduces the breakdown voltage of the transistor and increases the stability of the transistor operation under the combined action of the low doped drain region and the field plate.

[Description of the Drawings]

1 is a schematic structural view of a device of an AlGaN/GaN HEMT in a conventional art;

2 is a schematic view showing the structure of a device having a field plate and a low doped drain region in one embodiment;

3 is a schematic view showing the structure of a device having a field plate and a low doped drain region in one embodiment;

4 is a schematic diagram of electric field distribution of a depletion layer of an AlGaN/GaN HEMT in a conventional art;

5 is a schematic view showing an electric field distribution of a depletion layer of an AlGaN/GaN HEMT in one embodiment;

6 is a schematic diagram of simulation of an AlGaN/GaN HEMT in a conventional technology;

7 is a schematic diagram of simulation of an AlGaN/GaN HEMT in one embodiment;

8 is a schematic diagram of electric field distribution of an AlGaN/GaN HEMT device with or without an LDD region;

9 is a schematic diagram showing the structure of an electric field distribution of an AlGaN/GaN HEMT device having an LDD region under different drain-source voltages;

10 is a schematic diagram of electric field distribution of an AlGaN/GaN HEMT device using both a field plate and an LDD;

11 is a schematic view showing the structure of a device having a field plate and a low doped drain region in one embodiment;

12 is a schematic view showing the structure of a device having a field plate and a low doped drain region in one embodiment;

Figure 13 is a block diagram showing the structure of a device having a field plate and a low doped drain region in one embodiment;

Figure 14 is a block diagram showing the structure of a device having a field plate and a low doped drain region in one of the embodiments.

【detailed description】

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the scope of the invention.

Referring to Figure 2, an embodiment of a transistor having a field plate and a low doped drain region of the present invention is shown. The transistor having the field plate and the low doped drain region in this embodiment includes a barrier layer 110, a gate 120, a drain 130, a field plate 140, and a low doped drain region 112;

The low doped drain region 112 is disposed inside the barrier layer between the gate 120 and the drain 130, and one end of the low doped drain region 112 coincides with the edge of the drain 130, and the other end of the low doped drain region 112 is The edges of the gate 120 do not coincide;

Field plate 140 is coupled to gate 120, which is located between gate 120 and drain 130.

In the present embodiment, a low doping drain region 112 is provided in the barrier layer 110 of the transistor due to the electronegativity of the low doped drain region 112 and the region of the barrier layer 110 other than the low doped drain region 112. The difference, the presence of the low-doping drain region 112 can adjust the two-dimensional electron gas in the barrier layer 110, change the electric field strength of the depletion layer in the region below the gate 120 in the barrier layer 110, and redistribute the electric field and reduce The peak of the electric field reduces the trapping effect, thereby increasing the breakdown voltage. At the same time, the field plate 140 is introduced, the bending degree of the boundary of the edge depletion layer of the gate 120 is weakened, the electric field distribution is modulated, the peak electric field is reduced, and the trap effect is lowered, which further improves. The breakdown voltage, under the combined action of the low doping drain region 112 and the field plate 140, greatly increases the breakdown voltage of the transistor and increases the stability of the transistor operation.

Preferably, the low doped drain region 112 is a doped region in the barrier layer 110 adjacent to the corresponding drain region, and the region contains a doping material. Unlike the material of the barrier layer 110 itself, the barrier layer 110 may be changed. The two-dimensional electron gas concentration and the electric field strength of the depletion layer do not affect the functional characteristics of the transistor itself. Low doped drain regions are a concept known to those skilled in the art, also referred to as LDD structures or lightly doped drain structures, and those skilled in the art will know how to use them when seeing the technical term of low doped drain regions. This technical means.

In one of the embodiments, the low doped drain region 112 is obtained by injecting a plasma having a higher electronegativity than a predetermined value in a corresponding region of the barrier layer 110.

In this embodiment, the position of the region of the low-doping drain region 112 in the barrier layer 110 may be determined in advance, and the plasma material is implanted at the region, which is the low-doped drain region 112, wherein the plasma material The electronegativity intensity needs to be higher than a preset value, and the preset value may be selected according to the characteristics of the material other than the low doping drain region 112 in the barrier layer 110, as long as the electronegativity intensity of the plasma material is higher than the preset. The plasma can adsorb electrons negatively, thereby changing the two-dimensional electron gas concentration of the barrier layer 110 and the electric field strength of the depletion layer.

In one of the embodiments, the plasma material is a fluorine plasma.

In this embodiment, the plasma uses a fluorine plasma, and the electronegativity of the fluorine plasma is high, which meets the electronegativity requirement of the material of the low doping drain region 112, and can well adsorb electrons with negative charge, which can be greatly The two-dimensional electron gas concentration of the barrier layer 110 and the electric field strength of the depletion layer are changed.

In one of the embodiments, the field plate 140 is parallel to the barrier layer 110.

In the present embodiment, the field plate 140 is parallel to the barrier layer 110, which is advantageous for reducing the degree of bending of the boundary of the edge depletion layer of the gate 120, modulating the electric field distribution, and increasing the breakdown voltage.

In one of the embodiments, field plate 140 is integrally formed with gate 120.

In the present embodiment, the integrally formed field plate 140 and gate 120 can avoid the effect of the junction of the field plate 140 and the gate 120 on the electric field distribution in the depletion layer.

In one of the embodiments, the material of the field plate 140 is the same as the material of the gate 120.

In the present embodiment, the material of the field plate 140 is the same as the material of the gate 120, which avoids adversely affecting the adjustment of the electric field distribution in the depletion layer due to the difference in material of the field plate 140 from the gate electrode 120.

In one of the embodiments, the orthographic projection of the field plate 140 on the surface of the barrier layer 110 does not coincide with the orthographic projection of the low doped drain region 112 on the surface of the barrier layer 110.

In the present embodiment, the orthographic projection of the field plate 140 on the surface of the barrier layer 110 does not coincide with the orthographic projection of the low doping drain region 112 on the surface of the barrier layer 110, and the field plate 140 can be reduced in the depletion layer. The adjustment of the electric field distribution and the interaction between the low-doping drain region 112 and the adjustment of the electric field distribution in the depletion layer optimize the adjustment of the electric field distribution.

In a specific embodiment, as shown in FIG. 3, the transistor having the field plate and the low doped drain region further includes a buffer layer 150, the barrier layer 110 is AlGaN, and the buffer layer 150 is GaN.

In essence, the transistor having the field plate and the low doping drain region in the present embodiment is an AlGaN/GaN transistor.

4 is an electric field distribution of an AlGaN depletion layer in a conventional GaN-based HEMT device. The electric field lines in the depletion layer directly under the gate (G) are straight, the boundary of the depletion layer at the edge is curved, and the curvature is relatively high. Large, resulting in a relatively concentrated electric field line at the gate edge. When the gate voltage is the same, the electric field strength in the edge depletion layer is much larger than the electric field intensity directly under the gate.

In the present invention, after the field plate (FP) is introduced, the curvature of the boundary of the gate edge depletion layer is weakened, the electric field distribution is modulated, the peak electric field is reduced, and the trap effect is reduced, thereby increasing the breakdown voltage, as shown in FIG. The root cause is that a new depletion layer is formed below the field plate.

A fluorine-plasma is implanted between the gate (G) and the drain (D) by ion implantation to form a low-doped drain region, because the fluoride ion has a strong electronegativity, and the adsorbed electron is negatively charged, and the gate can be depleted. The two-dimensional electronic gas. Fluoride ions in the low doped drain region (LDD region) provide a fixed negative charge that modulates the electric field strength and 2DEG concentration, allowing the electric field to redistribute and reduce the electric field peak. The LDD region functions similarly to the metal field plate in increasing the breakdown voltage.

The present invention also employs silvaco software to simulate the effects of field plates and LDD regions on the breakdown voltage of AlGaN/GaN HEMT devices. The structure of the device without field plate is shown in Figure 6. The device structure of the field plate is shown in Figure 7. In the simulation, the area of AlGaN in the longitudinal direction is 0~0.01, and the area of GaN is 0.01~2. Since the AlGaN layer is only 0.01 μm, it is not clearly shown in FIGS. 6 and 7, but the AlGaN layer is real. The device length of this simulation design is 8μm, the gate length is 1μm, LGS=1μm, LGD=4μm, the doping concentration is 1×10 ¹⁵ cm ^-3 , and the simulated 2DEG concentration is 1×10 ¹³ cm ^-2 . The critical breakdown electric field strength of this simulation is 3 MV/cm. When the electric field strength just reaches the critical breakdown electric field strength, the device is considered to have been broken down. The voltage at this time is called the breakdown voltage of the device.

Figure 8 is a schematic diagram showing the electric field distribution of an AlGaN/GaN HEMT device with or without an LDD region when the drain-source voltage is 100 V. "noFP-device-100" is the electric field distribution of an AlGaN/GaN HEMT device without a field plate structure and an LDD region. "noFP-LDD-1e12-1-device-100" is an electric field distribution of an AlGaN/GaN HEMT device having no field plate structure and having an LDD region, and the LDD region is a region of X=3 to X=4, and the concentration of 2DEG is 1 ×10 ¹² cm ^-2 .

It can be seen from Fig. 8 that the electric field distribution has an electric field peak at the edge of the drain side gate. When the LDD region is introduced, a new electric field peak is generated at the edge of the drain side LDD region, but it is much smaller than the electric field peak at the drain side gate edge. Therefore, breakdown is most likely to occur at the drain side gate edge, and the electric field peak at the gate edge is greatly reduced. AlGaN/GaN without LDD region when the drain-source voltage is 100V The electric field peak of the HEMT device reaches 3.9 MV/cm, which is greater than 3 MV/cm, indicating that the device has been broken down, that is, AlGaN/GaN without LDD region. The breakdown voltage of the HEMT device is less than 100V; and the AlGaN/GaN introduced into the LDD region The maximum electric field peak of the HEMT device is only 1.8 MV/cm, which is much smaller than 3 MV/cm, and the device is not broken down. Therefore, the breakdown voltage of the HEMT can be improved by using the LDD.

When the drain-source voltage is 200V and 300V, the LDD region is in the region of X=3 to X=5, and the electric field distribution of the AlGaN/GaN HEMT device having a concentration of 2×10 ¹² cm ^-2 in 2DEG is shown in Fig. 9.

It can be seen from Fig. 9 that when the drain-source voltage is 200V, the highest electric field strength is 2.5 MV/cm, which is less than the critical breakdown voltage of 3 MV/cm, indicating that the device is not broken down; when the drain-source voltage is 300 V, the highest electric field strength is 3.5. MV/cm, which is greater than the critical breakdown voltage of 3 MV/cm, indicates that the device has broken down. Therefore, AlGaN/GaN after LDD is used The breakdown voltage of the HEMT device is increased from less than 100V to between 200V and 300V.

When the drain-source voltage is 200V, the electric field distribution of the AlGaN/GaN HEMT device using both the field plate and the LDD is as shown in Fig. 10 (the area of the field plate is X=2 to X=4, and the LDD area is X=3 to X=). In the region of 5, the concentration of 2DEG is 1 × 10 ¹² cm ^-2 ), and "noFP-LDD-1e12-2-device-200v" is the electric field intensity curve when there is no field plate and LDD, "FP2-LDD-1e12- 2-device-200v" is the electric field strength curve of the field plate and LDD at the same time. It can be seen from Fig. 9 that a new electric field peak is introduced at the edge of the field plate and the edge of the LDD, respectively, but the electric field peak at the edge of the gate is lowered. The highest electric field strength when using only LDD is 2.5 MV/cm, and the highest electric field strength at the time of field plate and LDD is 2 MV/cm, which greatly reduces the maximum electric field strength and further increases the breakdown voltage.

The field plate and LDD can be used to introduce a new electric field peak at the edge of the field plate and the LDD, and the electric field peak at the gate edge is reduced, which greatly reduces the maximum electric field peak of the active region, so it can be greatly improved. AlGaN/GaN The breakdown voltage of the HEMT device.

The field plate in the above solution may also be disposed between the gate and the source, and the field plate is connected to the gate or the source.

In one embodiment, as shown in FIG. 11, a transistor having a field plate and a low doped drain region includes a barrier layer 110, a gate 120, a source 160, a drain 130, a field plate 140, and a low Doping the drain region 112;

Field plate 140 is coupled to gate 120, which is located between gate 120 and source 160.

In one embodiment, as shown in FIG. 12, a transistor having a field plate and a low doped drain region includes a barrier layer 110, a gate 120, a source 160, a drain 130, a field plate 140, and a low Doping the drain region 112;

Field plate 140 is coupled to source 160 and field plate 140 is located between gate 120 and source 160.

In the present embodiment, a low doping drain region 112 is provided in the barrier layer 110 of the transistor due to the electronegativity of the low doped drain region 112 and the region of the barrier layer 110 other than the low doped drain region 112. The difference, the presence of the low-doping drain region 112 can adjust the two-dimensional electron gas in the barrier layer 110, change the electric field strength of the depletion layer in the region below the gate 120 in the barrier layer 110, and redistribute the electric field and reduce The electric field peaks, reducing the trap effect, thereby increasing the breakdown voltage, while introducing the field plate 140, although the field plate 140 It is connected to the source 160, but it is also located between the gate 120 and the source 160. Similarly, the boundary of the edge depletion layer of the gate 120 is weakened, the electric field distribution is modulated, the peak electric field is reduced, and the trap effect is reduced. Further, the breakdown voltage is further improved. Under the joint action of the low doping drain region 112 and the field plate 140, the breakdown voltage of the transistor is greatly improved, and the stability of the transistor operation is increased.

In one embodiment, as shown in FIG. 13, a transistor having a field plate and a low doped drain region includes a barrier layer 110, a gate 120, a source 160, a drain 130, and a first field plate 170. a second field plate 180 and a low doped drain region 112;

The first field plate 170 is connected to the gate 120, and the first field plate 170 is located between the gate 120 and the drain 130;

The second field plate 180 is coupled to the gate 120 and the second field plate 180 is positioned between the gate 120 and the source 160.

In the present embodiment, a low doping drain region 112 is provided in the barrier layer 110 of the transistor due to the electronegativity of the low doped drain region 112 and the region of the barrier layer 110 other than the low doped drain region 112. The difference, the presence of the low-doping drain region 112 can adjust the two-dimensional electron gas in the barrier layer 110, change the electric field strength of the depletion layer in the region below the gate 120 in the barrier layer 110, and redistribute the electric field and reduce The peak of the electric field reduces the trapping effect, thereby increasing the breakdown voltage. At the same time, the first field plate 170 and the second field plate 180 are introduced, so that the curvature of both sides of the edge depletion layer of the gate 120 is weakened, and the electric field distribution is modulated. The peak electric field is reduced, the trap effect is reduced, and the breakdown voltage is further increased. Under the action of the low doping drain region 112, the first field plate 170 and the second field plate 180, the breakdown voltage of the transistor is greatly improved. Increased stability of transistor operation.

In one embodiment, as shown in FIG. 14, a transistor having a field plate and a low doped drain region includes a barrier layer 110, a gate 120, a source 160, a drain 130, and a first field plate 170. a second field plate 180 and a low doped drain region 112;

The second field plate 180 is coupled to the source 160 and the second field plate 180 is positioned between the gate 120 and the source 160.

In the present embodiment, a low doping drain region 112 is provided in the barrier layer 110 of the transistor due to the electronegativity of the low doped drain region 112 and the region of the barrier layer 110 other than the low doped drain region 112. The difference, the presence of the low-doping drain region 112 can adjust the two-dimensional electron gas in the barrier layer 110, change the electric field strength of the depletion layer in the region below the gate 120 in the barrier layer 110, and redistribute the electric field and reduce The electric field peaks, reducing the trapping effect, thereby increasing the breakdown voltage, while introducing the first field plate 170 and the second field plate 180. Although the second field plate 180 is connected to the source 160, it is also located at the gate 120 and the source. Between the poles 160, the bending degree of the boundary of the edge depletion layer of the gate 120 can also be weakened, and the first field plate 170 and the second field plate 180 can weaken the boundary of the boundary of the edge depletion layer of the gate 120, and the electric field is weakened. The distribution is modulated, the peak electric field is reduced, the trap effect is reduced, and the breakdown voltage is further increased. Under the action of the low doping drain region 112, the first field plate 170 and the second field plate 180, the transistor is greatly improved. Breakdown voltage increases the stability of transistor operation

The field plate of the present invention is similar to the transistor in which the transistor between the gate and the source is disposed between the gate and the drain, and the transistor in the field plate is disposed between the gate and the drain. The technical features set forth therein and their beneficial effects are all applicable to embodiments of a transistor in which a field plate is disposed between a gate and a source.

The technical features of the above-described embodiments may be arbitrarily combined. For the sake of brevity of description, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction between the combinations of these technical features, All should be considered as the scope of this manual.

The above-described embodiments are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but is not to be construed as limiting the scope of the invention. It should be noted that a number of variations and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be determined by the appended claims.

Claims

A transistor having a field plate and a low doped drain region, comprising: a barrier layer, a gate, a drain, a field plate, and a low doped drain region;

The low doped drain region is disposed inside the barrier layer between the gate and the drain, and one end of the low doped drain region coincides with an edge of the drain, the low doped drain region The other end does not coincide with the edge of the gate;

The field plate is coupled to the gate, the field plate being located between the gate and the drain.
The transistor having a field plate and a low doped drain region according to claim 1, wherein the low doped drain region is such that an electronegativity intensity is higher than a preset value in a corresponding region of the barrier layer. The plasma is obtained.
The transistor having a field plate and a low doped drain region according to claim 2, wherein the plasma is a fluorine plasma.
The transistor of claim 1 wherein the field plate is parallel to the barrier layer.
The transistor having a field plate and a low doped drain region according to claim 1, wherein the field plate is integrally formed with the gate.
The transistor having a field plate and a low doped drain region according to claim 1, wherein an orthographic projection of said field plate on a surface of said barrier layer and said low doped drain region are in said The orthographic projections on the surface of the barrier layer do not coincide.
The transistor having a field plate and a low doped drain region according to any one of claims 1 to 6, further comprising a buffer layer; the barrier layer is AlGaN, and the buffer layer is GaN.
A transistor having a field plate and a low doped drain region, comprising: a barrier layer, a gate, a source, a drain, a field plate, and a low doped drain region;

The low doped drain region is disposed inside the barrier layer between the gate and the drain, and one end of the low doped drain region coincides with an edge of the drain, the low doped drain region The other end does not coincide with the edge of the gate;

The field plate is coupled to the gate, the field plate being located between the gate and the source.
A transistor having a field plate and a low doped drain region, comprising: a barrier layer, a gate, a source, a drain, a field plate, and a low doped drain region;

The low doped drain region is disposed inside the barrier layer between the gate and the drain, and one end of the low doped drain region coincides with an edge of the drain, the low doped drain region The other end does not coincide with the edge of the gate;

The field plate is coupled to the source, and the field plate is between the gate and the source.
A transistor having a field plate and a low doped drain region, comprising: a barrier layer, a gate, a source, a drain, a first field plate, a second field plate, and a low doped drain region;

The low doped drain region is disposed inside the barrier layer between the gate and the drain, and one end of the low doped drain region coincides with an edge of the drain, the low doped drain region The other end does not coincide with the edge of the gate;

The first field plate is connected to the gate, and the first field plate is located between the gate and the drain;

The second field plate is connected to the gate, the second field plate is located between the gate and the source, or the second field plate is connected to the source, the A two field plate is located between the gate and the source.