CN113066726B - Method for realizing field effect transistor - Google Patents
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
Abstract
The invention provides a method for realizing a novel embedded transistor, which comprises the following steps: setting an embedded channel in the target transistor to enable a drain electrode region and a source electrode region in the target transistor to be separated from a grid electrode boundary by a preset distance; establishing doping concentration in corresponding embedded channels between the grid boundary and the source electrode and between the grid boundary and the source electrode to form a novel embedded transistor; verifying the novel embedded transistor to determine whether the novel embedded transistor is qualified; if the channel is qualified, keeping the embedded channel currently set and the established doping concentration unchanged; otherwise, adjusting the embedded channel currently set and the established doping concentration. By setting the embedded channel and establishing the doping concentration in the embedded channel, a novel embedded transistor is constructed and verified, the nonuniformity of a local electric field in the transistor can be effectively improved, and the possibility of breakdown is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for realizing a field effect transistor.
Background
Known designs of field effect transistors (MOSFETs) having metal gates have embedded channel, source, and drain regions on a substrate having the opposite conductivity type. The breakdown voltage between the drain-source regions of a MOSFET depends substantially on the strength of the electric field where the source and drain regions overlap the gate boundary. As shown in fig. 1, at these places, since the concentration of impurities in the source region and the drain region is high, the internal electric field strength in the semiconductor structure is much higher than the electric field strength at the place far from the gate boundary, and thus local breakdown of the semiconductor structure is likely to occur. Particularly when a drain-source reverse voltage is applied between the source and drain of the field effect transistor, a "hot" charge carrier effect is created, which leads to a further reduction of the breakdown voltage of the transistor.
It is clear that this design has the following technical problems:
1) the presence of the metal gate limits the size of the minimum channel length due to the use of a non-self-aligned process for forming the source and drain regions;
2) the presence of metal gates complicates the manufacturing process of transistors with thin gate oxides;
3) the high electric field strength of the highly doped drain region results in a low breakdown voltage of the drain-source of the transistor.
Therefore, the present invention provides a method for implementing a field effect transistor.
Disclosure of Invention
The invention provides a method for realizing a field effect transistor, which is used for constructing an embedded transistor by arranging an embedded channel and respectively establishing corresponding doping concentrations between a grid boundary and a source electrode and between the grid boundary and a drain electrode, and verifying the embedded transistor, so that the nonuniformity of a local electric field in the transistor can be effectively improved, and the possibility of breakdown is reduced.
The invention provides a method for realizing an embedded transistor, which comprises the following steps:
step 1: setting an embedded channel in a target transistor to space drain and source regions in the target transistor a preset distance from a gate boundary;
step 2: respectively establishing corresponding doping concentrations between the gate boundary and the source electrode and between the gate boundary and the drain electrode to form an embedded transistor;
and step 3: verifying the embedded transistor to determine whether the embedded transistor is qualified;
if the channel is qualified, keeping the embedded channel currently set and the established doping concentration unchanged;
otherwise, adjusting the embedded channel currently set and the established doping concentration.
In one possible implementation, the length of the embedded channel is greater than the gate length.
In one possible implementation, the embedded transistor has a structural formula as follows:
wherein the content of the first and second substances,
representing a channel length of the embedded transistor;
representing a gate length of the embedded transistor; a represents the distance between the gate to the source or the gate to the drain of the embedded transistor.
In a possible implementation manner, step 1 includes, before the setting of the embedded channel in the target transistor:
determining the model of the target transistor, and calling standard electric field intensity of a source electrode region, a drain electrode region and a grid electrode boundary overlapping region corresponding to different input voltages based on the model;
when the distance between the grid and the source and the drain is a first distance, inputting different target voltages to the target transistor according to the interval time, measuring the actual electric field intensity of the overlapped region of the corresponding source and drain regions and the grid boundary, and monitoring a working parameter set of the target transistor in the process of measuring the actual electric field intensity, wherein the working parameter set comprises: current operating temperature, current operating power;
determining the attenuation coefficient of the target transistor according to the standard electric field intensity and the actual electric field intensity, and simultaneously determining the working stability of the target transistor according to the working parameter set;
increasing the distance according to a distance increasing rule on the basis of the first distance to obtain a second distance, and monitoring the current electric field intensity of corresponding different target voltages when the grid electrode is at the second distance from the source electrode to the drain electrode;
determining an optimal electric field intensity set from all current electric field intensities, and judging whether only one electric field intensity data exists in the optimal electric field intensity set;
if yes, determining a corresponding second distance based on one stored electric field intensity data;
if not, screening the optimal electric field intensity from the optimal electric field intensity set based on the attenuation coefficient and the working stability, and determining a corresponding second distance;
wherein the second distance is a preset distance.
In a possible implementation manner, in step 1, before the setting of the embedded channel in the target transistor, the method further includes: compensating the target transistor, wherein the compensating step comprises:
scanning a source region in the target transistor, acquiring region information of the source region, and constructing a corresponding three-dimensional structure according to the region information;
determining pits and bumps of a first plane and a second plane in the three-dimensional structure, performing first calibration on the pits, determining first position distribution of the pits in the first plane and second position distribution of the pits in the second plane, determining the concave depth of each pit, performing second calibration on the bumps, determining third position distribution of the bumps in the first plane and fourth position distribution of the bumps in the second plane, and determining the convex height of each bump;
respectively establishing a first horizontal line, a second horizontal line, a third horizontal line and a fourth horizontal line which penetrate through the three-dimensional structure based on the first position distribution, the second position distribution, the third position distribution and the fourth position distribution;
judging whether an overlapped horizontal line exists in the first horizontal line, the second horizontal line, the third horizontal line and the fourth horizontal line;
if the conductive influence values Y exist, judging the concave-convex conditions corresponding to the initial end and the tail end of the overlapped horizontal line, and calculating the conductive influence values Y corresponding to all the overlapped horizontal lines according to the following formula;
wherein k represents the total number of overlapping horizontal lines;
a three-dimensional stereo structure-based current position weight representing an ith overlapping horizontal line;
indicating the dent depth or the prominent height of the initial end of the ith overlapped horizontal line;
the initial end of the ith overlapping horizontal line is a concave point, the value is-1, and the initial end of the ith overlapping horizontal line is a convex point, the value is 1;
a depression depth or a protrusion height indicating an end of the ith overlapping horizontal line;
the value is-1 when the tail end of the ith overlapping horizontal line is a concave point, and the value is 1 when the tail end of the ith overlapping horizontal line is a convex point;
the conductive influence function of the initial end of the ith overlapped horizontal line is represented, and the value range is [0,1]]；
The conductive influence function of the tail end of the ith overlapped horizontal line is represented, and the value range is [0,1]]；
Showing the influence factor of the current position of the ith overlapping horizontal line under the standard condition, and the value range is [0.9, 1%](ii) a Wherein x has a value of
、
(ii) a y takes a value of 1 or-1, and takes a value of 1 when the corresponding end is a convex point, and takes a value of-1 when the corresponding end is a concave point; g represents corresponding conductive influence factor and has a value range of [0,1]]；
Determining a first voltage transmission effect based on all the overlapped horizontal lines according to the conductive influence value Y;
otherwise, respectively determining a second voltage transmission effect based on each residual horizontal line;
when the first voltage transmission effect is lower than the preset transmission effect and the second voltage transmission effect is lower than the preset transmission effect, extracting a corresponding horizontal line, determining the corresponding conductive performance, and marking the convex points and the concave points corresponding to the conductive performance which is lower than the preset performance;
based on the same plane, regarding the corresponding area of the marked salient point and the marked concave point as a first area, and determining a first breakdown possibility of the first area;
meanwhile, determining a second breakdown possibility of a second region corresponding to the gate region;
and calling a corresponding compensation scheme from a preset database according to the first area, the first breakdown possibility, the second area and the second breakdown possibility, and reminding to compensate the first area and the second area.
In one possible implementation, establishing a first horizontal line, a second horizontal line, a third horizontal line, and a fourth horizontal line that intersect the three-dimensional volumetric structure based on the first location distribution, the second location distribution, the third location distribution, and the fourth location distribution, respectively, includes:
determining initial ends of the first plane concave points distributed at the first position, and establishing first horizontal lines with the number equal to that of the first plane concave points by penetrating the three-dimensional structure;
determining the initial ends of the concave points in the second plane distributed at the second position, and establishing second horizontal lines with the number equal to that of the concave points in the second plane by penetrating the three-dimensional structure;
determining the tail ends of the salient points in the first plane distributed at the third position and penetrating through the three-dimensional structure to establish third horizontal lines with the number equal to that of the salient points in the first plane;
determining the tail ends of the salient points in the second plane distributed at the fourth position, and establishing fourth horizontal lines with the number equal to that of the salient points in the second plane by penetrating the three-dimensional structure;
wherein the first plane and the second plane are symmetrically arranged.
In one possible implementation manner, step 2, after establishing the corresponding doping concentrations between the gate boundary and the source and between the gate boundary and the drain respectively, includes:
acquiring a voltage signal of an embedded channel with doping concentration acted by a reverse voltage, and processing the voltage signal;
acquiring an input voltage based on the target transistor, acquiring a forward signal of the input voltage, and judging a real-time change rule of the forward signal;
monitoring in real time the charge carrier effect generated by the target transistor based on the input voltage;
acquiring a preset first reverse voltage applied to the target transistor, determining to perform voltage compensation on the first reverse voltage at the next moment based on the real-time change rule and the charge carrier effect, and judging whether the compensation degree of the voltage compensation at the current moment and the next moment exceeds a maximum compensation range;
if so, controlling the target transistor to stop working;
otherwise, judging whether the voltage compensation performed by the first reverse voltage is positive voltage compensation or negative voltage compensation;
if the voltage compensation is positive voltage compensation, increasing the voltage value of the first reverse voltage to obtain a second reverse voltage, and applying the second reverse voltage to the drain electrode and the source electrode of the target transistor;
and if the reverse voltage is compensated, reducing the voltage value of the first reverse voltage to obtain a third reverse voltage, and applying the third reverse voltage to the drain electrode and the source electrode of the target transistor.
In a possible implementation manner, in step 3, the verifying the embedded transistor to determine whether the embedded transistor is qualified includes:
performing standard work under preset conditions based on the embedded transistor, acquiring corresponding working parameters, and performing classification processing on the working parameters to obtain multiple types of sub data;
acquiring a historical verification set of a verification tool, performing pre-analysis, determining the successful verification times and the failed verification times of the verification tool, and further determining the corresponding verification accuracy;
giving a corresponding verification authority and a weight value of the verification authority to each verification tool;
calling a verification tool matched with the subdata according to verification permission, and verifying the corresponding subdata according to the matched verification tool to obtain a first verification result;
according to the verification accuracy rate of each verification tool and the corresponding weight value, performing weighted summation on the first verification result to generate a second verification result;
when the second verification result is larger than a preset verification value, judging that the embedded transistor is unqualified, judging that the working parameters have data defects, extracting defect parameters in the working parameters, and performing logic verification on defect events formed by the defect parameters;
comparing the logic verification result with a preset verification result, and acquiring a corresponding result to be adjusted according to the preset verification result;
determining information to be adjusted related to the currently set embedded channel and the established doping concentration according to the result to be adjusted, and outputting a prompt;
and when the second verification result is smaller than a preset verification value, judging that the embedded transistor is qualified.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram of an embedded channel FET in accordance with an embodiment of the present invention;
FIG. 2 is a topology of a metal oxide field effect transistor (MOSFET) with an embedded channel in an embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view of an embedded MOSFET in an embodiment of the present invention;
FIG. 4 is a graph comparing the dependence of the drain current Ic on the drain-source reverse voltage Uds for the improved device and the prototype device according to the embodiment of the present invention;
FIG. 5 is a cross-sectional view of an embedded MOSFET with a built-in N-channel in accordance with an embodiment of the present invention;
FIG. 6 is a graph showing the dependence of the source-drain current Ids on the drain-source reverse voltage Vds of the embedded channel MOS transistor according to the embodiment of the present invention;
fig. 7 is a flowchart of a method for implementing a field effect transistor according to an embodiment of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
In example 1:
the invention provides a method for realizing an embedded transistor, as shown in fig. 7, comprising the following steps:
step 1: setting an embedded channel in a target transistor to space drain and source regions in the target transistor a preset distance from a gate boundary;
step 2: respectively establishing corresponding doping concentrations between the gate boundary and the source electrode and between the gate boundary and the drain electrode to form an embedded transistor;
and step 3: verifying the embedded transistor to determine whether the embedded transistor is qualified;
if the channel is qualified, keeping the embedded channel currently set and the established doping concentration unchanged;
otherwise, adjusting the embedded channel currently set and the established doping concentration.
In one possible implementation, the length of the embedded channel is greater than the gate length.
In one possible implementation, the embedded transistor has a structural formula as follows:
wherein the content of the first and second substances,
representing a channel length of the embedded transistor;
representing a gate length of the embedded transistor; a represents the distance between the gate to the source or the gate to the drain of the embedded transistor.
The solution proposed by the present invention is detailed as follows: in a field effect transistor (MOSFET) having a structure comprising a drain, a source and an embedded channel, in a region having a conductivity type opposite to that of the region, in order to ensure that a constant drain current is applied to a target transistor in a given reverse voltage range (e.g., 0-12V), a novel device structure is designed such that the drain and source regions of the target transistor are spaced apart from the gate boundary by a certain distance and the embedded channel length of the target transistor is ensured to exceed the length of the gate thereof. Since the breakdown voltage between the drain-source regions of a field effect transistor (MOSFET) is substantially dependent on the electric field strength where the source and drain regions overlap the gate boundary, increasing the distance between the gate and the source and drain will effectively reduce the electric field strength where the source and drain regions overlap the gate boundary.
In these regions, since the concentration of impurities in the source region and the drain region is high, the internal electric field strength in the semiconductor structure is much higher than that at a place far from the gate boundary, and thus local breakdown of the semiconductor structure is likely to occur. Designing a weakly doped buried channel in the MOSFET near the gate boundary significantly improves the local electric field non-uniformity, thereby reducing the likelihood of local breakdown. This can also be explained by the reduction of the internal electric field strength near the gate boundary due to the lower impurity concentration of the built-in channel region near the gate region, as compared to the source or drain as shown in fig. 1. The coincidence of the boundaries of the heavily doped regions of the source and drain with the boundaries of the gate results in an abnormally high internal local electric field strength in the MOSFET structure.
In addition, when a reverse voltage is applied to the drain and source of a field effect transistor, a "hot" charge carrier effect will be generated, which will result in a further reduction of the breakdown voltage of the transistor, whereas when the gate boundary is far away from the heavily doped source and drain regions (e.g. over 1 μm) and there is a weakly doped channel near the gate boundary, i.e. the gradient of doping concentration is reduced near the gate boundary, the electric field strength at the gate boundary drops sharply, the generated "hot" charge carrier effect is significantly reduced and the breakdown voltage between the drain and source will increase significantly. As a result, the novel device structure will ensure a constant leakage current over a given range of drain-source reverse voltages supplied to the transistor structure.
Therefore, the key of the invention is that: in a metal oxide field effect transistor (MOSFET), a special embedded channel is designed such that the drain and source regions are spaced a certain distance (e.g. 1 μm) from the gate boundary and the length of the embedded channel exceeds the gate length, an optimal distribution of the gradient of doping concentration is established between the gate boundary and the source and between the gate boundary and the drain to obtain an optimal device performance, as a result of which the drain current of the transistor is kept constant within a given range (e.g. 0-12V) of the drain-source reverse voltage supplied to the transistor structure, and verification of the new structure to qualify.
The structure of a MOSFET with a buried channel as shown in fig. 1 is known, but after comparing the performance of the proposed solution with the known solutions, it was found that an increase in the length of the buried channel over the gate length makes it possible to obtain a constant drain current value within a given range for a given drain-source reverse voltage applied to the transistor structure.
Fig. 2 shows the topology of a metal oxide field effect transistor (MOSFET) with an embedded channel according to the proposed technical solution, the channel length L of which exceeds the gate length starting from the left and right borders of the gate
A value of a (in total, exceeding a value of 2 a);
FIG. 3 shows a vertical structure of a MOSFET of the present invention having a first type formed in a region of a second type of conductivity (hole conductivity: P-type)Conductive (electron conductive: N-type) embedded channel with channel length L exceeding the length of transistor gate by a value of 2a
。
Fig. 4 shows the dependence of the drain current Ic on the drain-source reverse voltage Uds of the prototype sample, in which the prototype device is a MOSFET with an integrated channel and a polysilicon gate (prototype device curve in the figure), and the improved device is a novel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with an integrated channel proposed by the present invention, and the length of the built-in channel exceeds the length of the gate thereof. (modified device curves in the figure), the gate is separated from the channel region by the gate oxide, and the region between the heavily doped N + source and N + drain is a low doped N-buried channel;
fig. 5 shows the structure of a MOSFET with a built-in N-channel according to the present invention obtained in a process fabrication, the N-channel being formed in a P-type buried layer formed in an N-type substrate, a polysilicon gate being isolated from a low doping concentration N-channel region by a gate oxide, the source and drain regions having a highly doped N + type conductivity being spaced from the gate by a distance a;
fig. 6 shows the dependence of the drain current Ic on the drain-source reverse voltage Vds of a MOSFET sample with an integrated channel as shown in fig. 5.
The increase in the length of the MOSFET buried channel over the gate length allows a constant drain current value to be obtained over a given range for a given drain-source reverse voltage applied to the transistor structure.
Fig. 5 also shows a cross-sectional view of the structure of a MOSFET obtained during the manufacturing process with an embedded channel 1, which is an integral part of the integrated circuit. And in the setting process, for example, the gate length l of the resulting transistor is 78 μm, and the distances from the boundary of the gate to the boundaries of the regions of the source and drain are each 1 μm, that is, the embedded channel length is 80 μm. The thickness of the gate oxide obtained during the formation of the structure of the transistor was 25 nm, the gate width W = 18 μm, and the ion dopant amount of phosphorus during the formation of the built-in channel was 5E 11/cm 2.
In the process of forming the structure shown in fig. 5, a P-type buried layer is obtained on an N-type substrate by photolithography, boron ion doping and subsequent diffusion, and then a built-in N-type channel is formed in the P-type buried layer by performing phosphorus ion doping, the geometric parameters of which are obtained by a corresponding photolithography process, and N + type source and drain are formed in the P-type by conventional photolithography, ion implantation and annealing processes.
Fig. 6 shows the dependence of the drain current on the drain-source reverse voltage of the mosfet shown in fig. 5. In the resulting experimental MOSFET samples, the drain current started to increase after exceeding 14 volts as the reverse voltage was applied to the drain-source region, indicating that the novel embedded channel can ensure the operability of the circuit in the required supply voltage range (0-12V). In the prototype of the invention, the length of the buried channel is identical to the length of the gate, as shown in fig. 1, and the drain current of the structure increases greatly after applying a reverse voltage (5-7V) to the drain-source region.
The illustrations for the above-described FIGS. 1-6 are as follows: 01 denotes a gate polysilicon layer, 02 denotes a gate oxide layer, 03 denotes a drain, 04 denotes a source, 06 denotes a distance a between a gate edge and the drain, and 07 denotes a distance a between a gate edge and the source; 08 denotes the channel length L; 09 denotes the gate length
(ii) a 10 denotes an embedded channel; and 11 denotes a gate region.
Therefore, the design of the embedded transistor implementation method provided by the invention ensures the reliable operation of the circuit in the given voltage range of 0 to 12V, and the new structure finally increases the yield of the corresponding integrated circuit by about 70%.
Compared with the prototype, the proposed design of the MOSFET with embedded channel can increase the operating range of the drain-source reverse voltage of the transistor, the drain current of which will remain constant, thus ensuring reliable operation of the integrated circuit in the required supply voltage range (e.g. 0-12V).
More importantly, the method adopted by the invention can be not only used for silicon-based metal oxide semiconductor field effect transistors and related integrated circuits, but also popularized and applied to other types of semiconductor devices and integrated circuits, such as compound semiconductor devices and integrated circuits.
The beneficial effects of the above technical scheme are: by setting the embedded channel and respectively establishing corresponding doping concentrations between the gate boundary and the source electrode and between the gate boundary and the drain electrode, a novel embedded transistor is constructed and verified, the nonuniformity of a local electric field in the transistor can be effectively improved, and the possibility of breakdown is reduced.
Example 2:
based on embodiment 1, step 1, before the step of providing the embedded channel in the target transistor, includes:
determining the model of the target transistor, and calling standard electric field intensity of a source electrode region, a drain electrode region and a grid electrode boundary overlapping region corresponding to different input voltages based on the model;
when the distance between the grid and the source and the drain is a first distance, inputting different target voltages to the target transistor according to the interval time, measuring the actual electric field intensity of the overlapped region of the corresponding source and drain regions and the grid boundary, and monitoring a working parameter set of the target transistor in the process of measuring the actual electric field intensity, wherein the working parameter set comprises: current operating temperature, current operating power;
determining the attenuation coefficient of the target transistor according to the standard electric field intensity and the actual electric field intensity, and simultaneously determining the working stability of the target transistor according to the working parameter set;
increasing the distance according to a distance increasing rule on the basis of the first distance to obtain a second distance, and monitoring the current electric field intensity of corresponding different target voltages when the grid electrode is at the second distance from the source electrode to the drain electrode;
determining an optimal electric field intensity set from all current electric field intensities, and judging whether only one electric field intensity data exists in the optimal electric field intensity set;
if yes, determining a corresponding second distance based on one stored electric field intensity data;
if not, screening the optimal electric field intensity from the optimal electric field intensity set based on the attenuation coefficient and the working stability, and determining a corresponding second distance;
wherein the second distance is a preset distance.
In this embodiment, the operation stability is determined, for example, based on the stabilization time of the operation temperature and the stabilization time of the operation power.
In this embodiment, the distance increasing rule is preset, for example, the distance is continuously increased by 1 um.
The beneficial effects of the above technical scheme are: the attenuation coefficient is determined according to the standard electric field strength and the actual electric field strength, the working stability is determined through the working parameter set, and then the corresponding second distance is determined by screening the optimal electric field strength from the electric field strength set, so that an effective basis is provided for determining the preset distance of the transistor, and the breakdown voltage of the transistor is conveniently and effectively reduced.
Example 3:
based on embodiment 1, step 1, before the embedded channel is disposed in the target transistor, further includes: compensating the target transistor, wherein the compensating step comprises:
scanning a source region in the target transistor, acquiring region information of the source region, and constructing a corresponding three-dimensional structure according to the region information;
determining pits and bumps of a first plane and a second plane in the three-dimensional structure, performing first calibration on the pits, determining first position distribution of the pits in the first plane and second position distribution of the pits in the second plane, determining the concave depth of each pit, performing second calibration on the bumps, determining third position distribution of the bumps in the first plane and fourth position distribution of the bumps in the second plane, and determining the convex height of each bump;
respectively establishing a first horizontal line, a second horizontal line, a third horizontal line and a fourth horizontal line which penetrate through the three-dimensional structure based on the first position distribution, the second position distribution, the third position distribution and the fourth position distribution;
judging whether an overlapped horizontal line exists in the first horizontal line, the second horizontal line, the third horizontal line and the fourth horizontal line;
if the conductive influence values Y exist, judging the concave-convex conditions corresponding to the initial end and the tail end of the overlapped horizontal line, and calculating the conductive influence values Y corresponding to all the overlapped horizontal lines according to the following formula;
wherein k represents the total number of overlapping horizontal lines;
a three-dimensional stereo structure-based current position weight representing an ith overlapping horizontal line;
indicating the dent depth or the prominent height of the initial end of the ith overlapped horizontal line;
the initial end of the ith overlapping horizontal line is a concave point, the value is-1, and the initial end of the ith overlapping horizontal line is a convex point, the value is 1;
a depression depth or a protrusion height indicating an end of the ith overlapping horizontal line;
the value is-1 when the tail end of the ith overlapping horizontal line is a concave point, and the value is 1 when the tail end of the ith overlapping horizontal line is a convex point;
the conductive influence function of the initial end of the ith overlapped horizontal line is represented, and the value range is [0,1]]；
The conductive influence function of the tail end of the ith overlapped horizontal line is represented, and the value range is [0,1]]；
Showing the influence factor of the current position of the ith overlapping horizontal line under the standard condition, and the value range is [0.9, 1%](ii) a Wherein x has a value of
、
(ii) a y takes a value of 1 or-1, and takes a value of 1 when the corresponding end is a convex point, and takes a value of-1 when the corresponding end is a concave point; g represents corresponding conductive influence factor and has a value range of [0,1]]；
Determining a first voltage transmission effect based on all the overlapped horizontal lines according to the conductive influence value Y;
otherwise, respectively determining a second voltage transmission effect based on each residual horizontal line;
when the first voltage transmission effect is lower than the preset transmission effect and the second voltage transmission effect is lower than the preset transmission effect, extracting a corresponding horizontal line, determining the corresponding conductive performance, and marking the convex points and the concave points corresponding to the conductive performance which is lower than the preset performance;
based on the same plane, regarding the corresponding area of the marked salient point and the marked concave point as a first area, and determining a first breakdown possibility of the first area;
meanwhile, determining a second breakdown possibility of a second region corresponding to the gate region;
and calling a corresponding compensation scheme from a preset database according to the first area, the first breakdown possibility, the second area and the second breakdown possibility, and reminding to compensate the first area and the second area.
In this embodiment, the compensation scheme is, for example, to dig out or fill pits or bumps on a horizontal line.
In this embodiment, the first plane and the second plane are symmetrically disposed.
In this embodiment, the voltage transfer effect is, for example, high voltage transfer efficiency.
The beneficial effects of the above technical scheme are: the target transistor is compensated, so that the possibility of breakdown is effectively reduced, and the effective use value of the transistor is improved.
Example 4:
based on embodiment 3, respectively establishing a first horizontal line, a second horizontal line, a third horizontal line, and a fourth horizontal line that run through the three-dimensional structure based on the first position distribution, the second position distribution, the third position distribution, and the fourth position distribution includes:
determining initial ends of the first plane concave points distributed at the first position, and establishing first horizontal lines with the number equal to that of the first plane concave points by penetrating the three-dimensional structure;
determining the initial ends of the concave points in the second plane distributed at the second position, and establishing second horizontal lines with the number equal to that of the concave points in the second plane by penetrating the three-dimensional structure;
determining the tail ends of the salient points in the first plane distributed at the third position and penetrating through the three-dimensional structure to establish third horizontal lines with the number equal to that of the salient points in the first plane;
determining the tail ends of the salient points in the second plane distributed at the fourth position, and establishing fourth horizontal lines with the number equal to that of the salient points in the second plane by penetrating the three-dimensional structure;
wherein the first plane and the second plane are symmetrically arranged.
The beneficial effects of the above technical scheme are: by effectively establishing corresponding horizontal lines according to the position distribution, an effective basis is provided for subsequent determination of voltage effects, and an effective basis is further provided for a compensation scheme.
Example 5:
based on embodiment 1, step 2, after establishing the corresponding doping concentrations between the gate boundary and the source and between the gate boundary and the drain, respectively, includes:
acquiring a voltage signal of an embedded channel with doping concentration acted by a reverse voltage, and processing the voltage signal;
acquiring an input voltage based on the target transistor, acquiring a forward signal of the input voltage, and judging a real-time change rule of the forward signal;
monitoring in real time the charge carrier effect generated by the target transistor based on the input voltage;
acquiring a preset first reverse voltage applied to the target transistor, determining to perform voltage compensation on the first reverse voltage at the next moment based on the real-time change rule and the charge carrier effect, and judging whether the compensation degree of the voltage compensation at the current moment and the next moment exceeds a maximum compensation range;
if so, controlling the target transistor to stop working;
otherwise, judging whether the voltage compensation performed by the first reverse voltage is positive voltage compensation or negative voltage compensation;
if the voltage compensation is positive voltage compensation, increasing the voltage value of the first reverse voltage to obtain a second reverse voltage, and applying the second reverse voltage to the drain electrode and the source electrode of the target transistor;
and if the reverse voltage is compensated, reducing the voltage value of the first reverse voltage to obtain a third reverse voltage, and applying the third reverse voltage to the drain electrode and the source electrode of the target transistor.
In the embodiment, the transistor can be conveniently and effectively detected by acquiring the input voltage and the reverse voltage;
in this embodiment, the compensation degree is, for example, a difference between the voltage at the next time and the voltage at the present time is a1, at this time, a1 is the compensation degree, and if the value of a1 exceeds the maximum compensation range c1, the transistor is controlled to stop operating.
The beneficial effects of the above technical scheme are: the reverse voltage is input into the embedded channel which is used for establishing the doping concentration, so that the embedded channel is convenient to detect and protect, and secondly, the compensation degree of voltage compensation is convenient to determine by determining the real-time change rule of a forward signal and the corresponding charge carrier effect, the effective operation of a transistor is convenient to guarantee, and the possibility of breakdown is avoided.
Example 6:
based on embodiment 1, in step 3, verifying the embedded transistor to determine whether the embedded transistor is qualified includes:
performing standard work under preset conditions based on the embedded transistor, acquiring corresponding working parameters, and performing classification processing on the working parameters to obtain multiple types of sub data;
acquiring a historical verification set of a verification tool, performing pre-analysis, determining the successful verification times and the failed verification times of the verification tool, and further determining the corresponding verification accuracy;
giving a corresponding verification authority and a weight value of the verification authority to each verification tool;
calling a verification tool matched with the subdata according to verification permission, and verifying the corresponding subdata according to the matched verification tool to obtain a first verification result;
according to the verification accuracy rate of each verification tool and the corresponding weight value, performing weighted summation on the first verification result to generate a second verification result;
when the second verification result is larger than a preset verification value, judging that the embedded transistor is unqualified, judging that the working parameters have data defects, extracting defect parameters in the working parameters, and performing logic verification on defect events formed by the defect parameters;
comparing the logic verification result with a preset verification result, and acquiring a corresponding result to be adjusted according to the preset verification result;
determining information to be adjusted related to the currently set embedded channel and the established doping concentration according to the result to be adjusted, and outputting a prompt;
and when the second verification result is smaller than a preset verification value, judging that the embedded transistor is qualified.
In this embodiment, the operating parameters include, for example, operating temperature, operating current, and operating voltage.
In this embodiment, the historical verification set of the verification tool includes various historical verification logs.
In this embodiment, the verification accuracy is obtained based on the ratio of the number of successful verifications to the sum of the number of successful verifications and the number of failed verifications.
In this embodiment, the first verification result may be a verification value, and the range of the verification value is [0,1], and a smaller verification value indicates that the corresponding parameter is more qualified.
In this embodiment, the second verification result is also a numerical value, and the preset verification value is preset.
In this embodiment, the data defect may be a defect in voltage, current, temperature, or the like.
In this embodiment, the defect event is, for example, a temperature event caused by a temperature defect, and the logic verification is performed on the defect event to obtain a change condition of the temperature event in the transistor operation process, for example, a change of a temperature difference or the like, so as to obtain a logic verification result, and further obtain a result to be adjusted, that is, to adjust the temperature difference, so as to output a prompt.
The beneficial effects of the above technical scheme are: through carrying out classification processing to working parameter, be convenient for carry out the management that becomes more meticulous, through confirming the rate of accuracy of verifying the instrument and the weighted value that gives, be convenient for carry out the effective weighting of verification result, and through carrying out the comparison, be convenient for judge whether embedded transistor is qualified, when unqualified, through drawing parameter, logic check-up, acquire the information of treating the adjustment, remind, guarantee the qualification of embedded transistor.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (4)
1. A method for implementing an embedded transistor, comprising:
step 1: setting an embedded channel in a target transistor to space drain and source regions in the target transistor a preset distance from a gate boundary;
step 2: respectively establishing corresponding doping concentrations between the gate boundary and the source electrode and between the gate boundary and the drain electrode to form an embedded transistor;
the structure formula of the embedded transistor is as follows:
wherein the content of the first and second substances,
representing a channel length of the embedded transistor;
representing a gate length of the embedded transistor; a represents the distance between the grid and the source or the drain of the embedded transistor;
meanwhile, a region between the heavily doped N + source electrode and the N + drain electrode is a low-doped N-embedded channel, and the length of the N-embedded channel is greater than that of the grid electrode;
and step 3: verifying the embedded transistor to determine whether the embedded transistor is qualified;
if the channel is qualified, keeping the embedded channel currently set and the established doping concentration unchanged;
otherwise, adjusting the currently set embedded channel and the established doping concentration;
verifying the embedded transistor to determine whether the embedded transistor is qualified, comprising:
performing standard work under preset conditions based on the embedded transistor, acquiring corresponding working parameters, and performing classification processing on the working parameters to obtain multiple types of sub data;
acquiring a historical verification set of a verification tool, performing pre-analysis, determining the successful verification times and the failed verification times of the verification tool, and further determining the corresponding verification accuracy;
giving a corresponding verification authority and a weight value of the verification authority to each verification tool;
calling a verification tool matched with the subdata according to verification permission, and verifying the corresponding subdata according to the matched verification tool to obtain a first verification result;
according to the verification accuracy rate of each verification tool and the corresponding weight value, performing weighted summation on the first verification result to generate a second verification result;
when the second verification result is larger than a preset verification value, judging that the embedded transistor is unqualified, judging that the working parameters have data defects, extracting defect parameters in the working parameters, and performing logic verification on defect events formed by the defect parameters;
comparing the logic verification result with a preset verification result, and acquiring a corresponding result to be adjusted according to the preset verification result;
determining information to be adjusted related to the currently set embedded channel and the established doping concentration according to the result to be adjusted, and outputting a prompt;
and when the second verification result is smaller than a preset verification value, judging that the embedded transistor is qualified.
2. The method of claim 1, wherein step 1, before the step of providing the embedded channel in the target transistor, comprises:
determining the model of the target transistor, and calling standard electric field intensity of a source electrode region, a drain electrode region and a grid electrode boundary overlapping region corresponding to different input voltages based on the model;
when the distance between the grid and the source and the drain is a first distance, inputting different target voltages to the target transistor according to the interval time, measuring the actual electric field intensity of the overlapped region of the corresponding source and drain regions and the grid boundary, and monitoring a working parameter set of the target transistor in the process of measuring the actual electric field intensity, wherein the working parameter set comprises: current operating temperature, current operating power;
determining the attenuation coefficient of the target transistor according to the standard electric field intensity and the actual electric field intensity, and simultaneously determining the working stability of the target transistor according to the working parameter set;
increasing the distance according to a distance increasing rule on the basis of the first distance to obtain a second distance, and monitoring the current electric field intensity of corresponding different target voltages when the grid electrode is at the second distance from the source electrode to the drain electrode;
determining an optimal electric field intensity set from all current electric field intensities, and judging whether only one electric field intensity data exists in the optimal electric field intensity set;
if yes, determining a corresponding second distance based on one stored electric field intensity data;
if not, screening the optimal electric field intensity from the optimal electric field intensity set based on the attenuation coefficient and the working stability, and determining a corresponding second distance;
wherein the second distance is a preset distance.
3. The method of claim 1, wherein step 1, before the step of providing the embedded channel in the target transistor, further comprises: compensating the target transistor, wherein the compensating step comprises:
scanning a source region in the target transistor, acquiring region information of the source region, and constructing a corresponding three-dimensional structure according to the region information;
determining pits and bumps of a first plane and a second plane in the three-dimensional structure, performing first calibration on the pits, determining first position distribution of the pits in the first plane and second position distribution of the pits in the second plane, determining the concave depth of each pit, performing second calibration on the bumps, determining third position distribution of the bumps in the first plane and fourth position distribution of the bumps in the second plane, and determining the convex height of each bump;
respectively establishing a first horizontal line, a second horizontal line, a third horizontal line and a fourth horizontal line which penetrate through the three-dimensional structure based on the first position distribution, the second position distribution, the third position distribution and the fourth position distribution;
judging whether an overlapped horizontal line exists in the first horizontal line, the second horizontal line, the third horizontal line and the fourth horizontal line;
if the conductive influence values Y exist, judging the concave-convex conditions corresponding to the initial end and the tail end of the overlapped horizontal line, and calculating the conductive influence values Y corresponding to all the overlapped horizontal lines according to the following formula;
wherein k represents the total number of overlapping horizontal lines;
a three-dimensional stereo structure-based current position weight representing an ith overlapping horizontal line;
indicating the dent depth or the prominent height of the initial end of the ith overlapped horizontal line;
the initial end of the ith overlapping horizontal line is a concave point, the value is-1, and the initial end of the ith overlapping horizontal line is a convex point, the value is 1;
a depression depth or a protrusion height indicating an end of the ith overlapping horizontal line;
the value is-1 when the tail end of the ith overlapping horizontal line is a concave point, and the value is 1 when the tail end of the ith overlapping horizontal line is a convex point;
the conductive influence function of the initial end of the ith overlapped horizontal line is represented, and the value range is [0,1]]；
Indicating the end of the ith overlapping horizontal lineAnd the value range of the conductive influence function is [0,1]]；
Showing the influence factor of the current position of the ith overlapping horizontal line under the standard condition, and the value range is [0.9, 1%](ii) a Wherein x has a value of
、
(ii) a y takes a value of 1 or-1, and takes a value of 1 when the corresponding end is a convex point, and takes a value of-1 when the corresponding end is a concave point; g represents corresponding conductive influence factor and has a value range of [0,1]]；
Determining a first voltage transmission effect based on all the overlapped horizontal lines according to the conductive influence value Y;
otherwise, respectively determining a second voltage transmission effect based on each residual horizontal line;
when the first voltage transmission effect is lower than the preset transmission effect and the second voltage transmission effect is lower than the preset transmission effect, extracting a corresponding horizontal line, determining the corresponding conductive performance, and marking the convex points and the concave points corresponding to the conductive performance which is lower than the preset performance;
based on the same plane, regarding the corresponding area of the marked salient point and the marked concave point as a first area, and determining a first breakdown possibility of the first area;
meanwhile, determining a second breakdown possibility of a second region corresponding to the gate region;
according to the first region, the first breakdown possibility, the second region and the second breakdown possibility, calling a corresponding compensation scheme from a preset database, and reminding to compensate the first region and the second region;
establishing a first horizontal line, a second horizontal line, a third horizontal line, and a fourth horizontal line that run through the three-dimensional structure based on the first position distribution, the second position distribution, the third position distribution, and the fourth position distribution, respectively, comprises:
determining initial ends of the first plane concave points distributed at the first position, and establishing first horizontal lines with the number equal to that of the first plane concave points by penetrating the three-dimensional structure;
determining the initial ends of the concave points in the second plane distributed at the second position, and establishing second horizontal lines with the number equal to that of the concave points in the second plane by penetrating the three-dimensional structure;
determining the tail ends of the salient points in the first plane distributed at the third position and penetrating through the three-dimensional structure to establish third horizontal lines with the number equal to that of the salient points in the first plane;
determining the tail ends of the salient points in the second plane distributed at the fourth position, and establishing fourth horizontal lines with the number equal to that of the salient points in the second plane by penetrating the three-dimensional structure;
wherein the first plane and the second plane are symmetrically arranged.
4. The method of claim 1, wherein the step 2, after establishing the corresponding doping concentrations between the gate boundary and the source and between the gate boundary and the drain respectively, comprises:
acquiring a voltage signal of an embedded channel with doping concentration acted by a reverse voltage, and processing the voltage signal;
acquiring an input voltage based on the target transistor, acquiring a forward signal of the input voltage, and judging a real-time change rule of the forward signal;
monitoring in real time the charge carrier effect generated by the target transistor based on the input voltage;
acquiring a preset first reverse voltage applied to the target transistor, determining to perform voltage compensation on the first reverse voltage at the next moment based on the real-time change rule and the charge carrier effect, and judging whether the compensation degree of the voltage compensation at the current moment and the next moment exceeds a maximum compensation range;
if so, controlling the target transistor to stop working;
otherwise, judging whether the voltage compensation performed by the first reverse voltage is positive voltage compensation or negative voltage compensation;
if the voltage compensation is positive voltage compensation, increasing the voltage value of the first reverse voltage to obtain a second reverse voltage, and applying the second reverse voltage to the drain electrode and the source electrode of the target transistor;
and if the reverse voltage is compensated, reducing the voltage value of the first reverse voltage to obtain a third reverse voltage, and applying the third reverse voltage to the drain electrode and the source electrode of the target transistor.
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