WO2011054280A1 - Ldmos device with multiple field plates and manufacturing method thereof - Google Patents

Ldmos device with multiple field plates and manufacturing method thereof Download PDF

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WO2011054280A1
WO2011054280A1 PCT/CN2010/078342 CN2010078342W WO2011054280A1 WO 2011054280 A1 WO2011054280 A1 WO 2011054280A1 CN 2010078342 W CN2010078342 W CN 2010078342W WO 2011054280 A1 WO2011054280 A1 WO 2011054280A1
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semiconductor body
field plate
field plates
ldmos device
horizontal portion
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PCT/CN2010/078342
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French (fr)
Chinese (zh)
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陈强
马强
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苏州远创达科技有限公司
远创达科技(香港)有限公司
远创达科技(开曼)有限公司
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Publication of WO2011054280A1 publication Critical patent/WO2011054280A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole

Definitions

  • the present invention relates to a multiple field plate LDMOS device and a method of processing the same.
  • the object of the present invention is to provide a multiple field plate LDMOS
  • the device and its processing method can better alleviate the contradiction between the source-drain breakdown voltage and the optimization requirements of the on-resistance, and improve the performance of the LDMOS device.
  • the technical solution of the present invention is: a multiple field plate LDMOS
  • the device includes a semiconductor body having at least two field plates on the surface thereof, each of the field plates having a horizontal portion parallel to the surface of the semiconductor body, the distance between the horizontal portion of the different field plates and the surface of the semiconductor body is not Wait.
  • all of the field plates are located above the drain drift region of the semiconductor body.
  • the distance between the horizontal portion of the at least two field plates and the surface of the semiconductor body is successively increased. That is, the first field plate is disposed closest to the surface of the semiconductor body, the second field plate is slightly farther, and so on.
  • This successive increment may be a linear increment or a non-uniform increment, but is preferably a uniform linear successive increment.
  • the horizontal portions of the field plates may or may not overlap in the lateral position.
  • a method of processing a multiple field plate LDMOS device comprising the following steps:
  • step 3) Repeat step 3) according to the number of field plates you need to make. For example, when only two field plates need to be processed, there is no need to repeat step 3 ); when it is necessary to process three field plates, repeat step 3), and so on.
  • the advantages of the present invention are: device simulation calculations show that the optimized design of single-field LDMOS devices with the same on-resistance and the optimized design of multiple field plates under the same conditions of all other device structural parameters LDMOS devices, multiple field plate LDMOS devices have higher source-drain breakdown voltages than single-field LDMOS devices (such as dual field plates with grounded LDMOS under the above conditions)
  • the device has a source-drain breakdown voltage of 73V and a grounded single-field LDMOS device with a source-drain breakdown voltage of 61V). This indicates that LDMOS using multiple field plates is required under the same source-drain breakdown voltage requirements.
  • the device can significantly increase the doping concentration of the N-type drift region, and the on-resistance of the device can be significantly improved.
  • FIG. 1 is a schematic structural view of a prior art single field plate LDMOS device
  • FIG. 2 is a schematic structural view of a specific embodiment of the present invention.
  • FIG. 3 is a schematic view showing the connection of a first field plate according to another embodiment of the present invention.
  • FIG. 4 is a schematic diagram of connection of a second field plate according to another embodiment of the present invention.
  • Embodiment As shown in FIG. 2, a multiple field plate LDMOS with a source-drain breakdown voltage between 60V and 120V.
  • the device includes a semiconductor body 1 including a lowermost P-type heavily doped substrate 12, a P-type epitaxial layer 13 on a P-type heavily doped substrate 12, and a P-type epitaxial layer 13 formed on the P-type heavily doped source region 15, the P-type doped channel region 16, the N-type doped drain drift region 11 and the N-type heavily doped drain region 18, wherein the P-type heavily doped region 15 and An N-type heavily doped source region 17 is formed at a position where the P-type doped channel region 16 is connected.
  • the source ohmic contact region 111 is disposed on the upper surface of the P-type heavily doped source region 15 and the N-type heavily doped source region 17, and the drain ohmic contact region 110 is disposed on N-type heavily doped drain region 18 upper surface.
  • a gate 19 is also formed on the semiconductor body 1.
  • the surface of the semiconductor body 1 is provided with three field plates 2, each of which has a semiconductor body 1
  • the horizontal portion 21 parallel to the surface, the distance between the horizontal portion 21 of each field plate 2 and the surface of the semiconductor body 1 is uniformly linearly successively increased.
  • the field plate 2 is situated above the drain drift region 11 of the semiconductor body 1.
  • FIG. 3 and FIG. 4 are schematic structural diagrams of another embodiment, the semiconductor body 1
  • the structure is the same as that of the previous embodiment, but the field plate 2 is provided with two, and the horizontal portion 21 of the first field plate 2a is spaced from the surface of the semiconductor body 1 by 0.06 ⁇ m to 0.5. Between microns, the horizontal lateral extension distance is between 0.4 microns and 2 microns.
  • the horizontal portion of the second field plate 2b is at a distance of 0.1 ⁇ m to 1 from the surface of the semiconductor body 1 Between the micrometers (regardless of the value, the horizontal portion of the second field plate is farther from the surface of the semiconductor body 1 than the first field plate), and the horizontal lateral expansion distance is between 0.4 microns and 2 microns.
  • Each field plate 2 may be comprised of a metal or other form of electrical conductor (e.g., doped polysilicon, silicide, etc.) having a thickness between 0.05 microns and 0.5 microns.
  • electrical conductor e.g., doped polysilicon, silicide, etc.
  • the length of the drain drift region 11 is between 2 micrometers and 6 micrometers, and the surface doping concentration of the drift region is 1 to 6E12/cm 2 between.
  • a method of processing a multiple field plate LDMOS device comprising the following steps:
  • step 4) Repeat step 3) according to the number of field plates you need to make.
  • LDMOS with one or more metal interconnects For example, in the case of two field plates in the process, one possible method of grounding the field plate is:
  • the ground connection can also be made through the second metal 5b and the second through hole 4b.
  • the field plates can be connected to different DC voltages or grounded.
  • the grounding effect of each field plate is better.
  • the field plate is generally only grounded, and the connection method of the field plate of the present invention is more flexible.
  • the invention is particularly suitable for use in LDMOS devices with source-drain breakdown voltages greater than 40-50V, which alleviates the contradiction between source-drain breakdown voltage and on-resistance optimization requirements, and improves the performance of LDMOS devices.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

An LDMOS device with multiple field plates and manufacturing method thereof are provided. The LDMOS device with multiple field plates comprises a semiconductor body (1) on the surface of which at least two field plates (2) are arranged. Each of the field plates (2) is provided with a horizontal portion (21) that is parallel with the surface of the semiconductor body (1). Distances between the horizontal portions (21) of different field plates (2) and the surface of the semiconductor body (1) are different. Using the LDMOS device with multiple field plates, dosage concentration of an N-type drift region can be obviously increased so that the device's on-resistance under the same source drain breakdown voltage requirement can be obviously decreased.

Description

多重场板LDMOS器件及其加工方法Multiple field plate LDMOS device and processing method thereof
技术领域 Technical field
本发明涉及一种多重场板 LDMOS 器件及其加工方法。 The present invention relates to a multiple field plate LDMOS device and a method of processing the same.
背景技术 Background technique
在功率 LDMOS 器件中，要求在满足源漏击穿电压 BVdss 的前提下，尽可能地降低器件的源漏导通电阻 Rds,on 以降低器件的功率消耗，提高器件的工作效率。但是源漏击穿电压和导通电阻的优化要求却是相互矛盾的，在射频（ RF ） LDMOS 功率器件中，常采用场板（ field plate ）技术来缓和这一矛盾。常用的单一场板技术有着较大的局限性，因为场板的水平部分与半导体表面间的距离恒定，如图 1 所示，但是理想的场板要求离开器件表面的距离不应是单一的。 In power LDMOS devices, it is required to meet the source-drain breakdown voltage BVdss Under the premise, reduce the source-drain on-resistance Rds, on of the device as much as possible to reduce the power consumption of the device and improve the working efficiency of the device. However, the optimization requirements for source-drain breakdown voltage and on-resistance are contradictory, in RF ( Field plate is often used in LDMOS power devices. ) Technology to alleviate this contradiction. The commonly used single field plate technology has great limitations because the distance between the horizontal portion of the field plate and the semiconductor surface is constant, as shown in Figure 1. As shown, the ideal field plate requires that the distance from the surface of the device should not be singular.
发明内容 Summary of the invention
本发明目的是提供一种多重场板 LDMOS 器件及其加工方法，更好的缓解了源漏击穿电压与导通电阻的优化要求之间的矛盾，改善 LDMOS 器件的性能。 The object of the present invention is to provide a multiple field plate LDMOS The device and its processing method can better alleviate the contradiction between the source-drain breakdown voltage and the optimization requirements of the on-resistance, and improve the performance of the LDMOS device.
本发明的技术方案是：一种多重场板 LDMOS 器件，包括半导体本体，所述半导体本体表面设有至少两个场板，所述每个场板具有与半导体本体表面平行的水平部分，不同场板的水平部分与半导体本体表面之间的距离不等。 The technical solution of the present invention is: a multiple field plate LDMOS The device includes a semiconductor body having at least two field plates on the surface thereof, each of the field plates having a horizontal portion parallel to the surface of the semiconductor body, the distance between the horizontal portion of the different field plates and the surface of the semiconductor body is not Wait.
进一步的，所述所有的场板都位于半导体本体的漏漂移区的上方。 Further, all of the field plates are located above the drain drift region of the semiconductor body.
进一步的，所述至少两个场板的水平部分与半导体本体表面的距离逐次递增。即第一个场板最靠近半导体本体表面设置，第二个场板略远，依次类推。该逐次递增可以是线性递增，也可以是非均匀的递增，但是较佳的为均匀线性逐次递增。各场板的水平部分间在横向位置上可以有交叠，也可以没有。 Further, the distance between the horizontal portion of the at least two field plates and the surface of the semiconductor body is successively increased. That is, the first field plate is disposed closest to the surface of the semiconductor body, the second field plate is slightly farther, and so on. This successive increment may be a linear increment or a non-uniform increment, but is preferably a uniform linear successive increment. The horizontal portions of the field plates may or may not overlap in the lateral position.
一种多重场板 LDMOS 器件的加工方法，包括以下步骤： A method of processing a multiple field plate LDMOS device, comprising the following steps:
1 ）加工半导体本体，包括了栅的形成； 1) processing the semiconductor body, including the formation of a gate;
2 ）于半导体本体的表面沉积一个介质层，再于该介质层上沉积一导电薄膜，所述导电膜经由光刻和腐蚀工艺形成第一个场板； 2 Depositing a dielectric layer on the surface of the semiconductor body, and depositing a conductive film on the dielectric layer, the conductive film forming a first field plate via photolithography and etching processes;
3 ）随后再依次沉积一个介质层和导电薄膜，并经由光刻和腐蚀工艺形成第二个场板； 3) subsequently depositing a dielectric layer and a conductive film in sequence, and forming a second field plate via photolithography and etching processes;
4 ）根据需要制作的场板的个数重复步骤 3 ）。如：当只需要加工两个场板时，就不需要重复步骤 3 ）；当需要加工三个场板时，就将步骤 3 ）重复一次，依次类推。 4) Repeat step 3) according to the number of field plates you need to make. For example, when only two field plates need to be processed, there is no need to repeat step 3 ); when it is necessary to process three field plates, repeat step 3), and so on.
本发明优点是：器件仿真计算表明，在所有其它的器件结构参数相同的条件下，对于具有相同的导通电阻的最优化设计的单重场板 LDMOS 器件和最优化设计的多重场板 LDMOS 器件，多重场板 LDMOS 器件的源漏击穿电压要高于单重场板 LDMOS 器件（如在上述条件下，具有接地的双重场板 LDMOS 器件的源漏击穿电压为 73V ，具有接地的单重场板 LDMOS 器件的源漏击穿电压为 61V ）。这表明在相同的源漏击穿电压要求下，运用多重场板的 LDMOS 器件可以显著增加 N 型漂移区的掺杂浓度，器件的导通电阻因而可以得到显著的改善。 The advantages of the present invention are: device simulation calculations show that the optimized design of single-field LDMOS devices with the same on-resistance and the optimized design of multiple field plates under the same conditions of all other device structural parameters LDMOS devices, multiple field plate LDMOS devices have higher source-drain breakdown voltages than single-field LDMOS devices (such as dual field plates with grounded LDMOS under the above conditions) The device has a source-drain breakdown voltage of 73V and a grounded single-field LDMOS device with a source-drain breakdown voltage of 61V). This indicates that LDMOS using multiple field plates is required under the same source-drain breakdown voltage requirements. The device can significantly increase the doping concentration of the N-type drift region, and the on-resistance of the device can be significantly improved.
附图说明 DRAWINGS
图 1 为现有技术单重场板 LDMOS 器件的结构示意图； 1 is a schematic structural view of a prior art single field plate LDMOS device;
图 2 为本发明具体实施例的结构示意图； 2 is a schematic structural view of a specific embodiment of the present invention;
图 3 为本发明另一具体实施例第一个场板的连接示意图； 3 is a schematic view showing the connection of a first field plate according to another embodiment of the present invention;
图 4 为本发明另一具体实施例第二个场板的连接示意图。 FIG. 4 is a schematic diagram of connection of a second field plate according to another embodiment of the present invention.
其中： 1 半导体本体； 11 漏漂移区； 12 P 型重掺杂衬底； 13 P 型外延层； 14P 型掺杂连接或用导电物填充的沟槽； 15 P 型重掺杂源区； 16 P 型掺杂沟道区； 17 N 型重掺杂源区； 18 N 型重掺杂漏区； 19 栅； 110 漏欧姆接触区； 111 源欧姆接触区； 2 场板； 2a 第一个场板； 2b 第二个场板； 21 水平部分； 3 介质层； 4a 第一通孔； 4b 第二通孔； 5a 第一金属； 5b 第二金属。 Wherein: 1 semiconductor body; 11 leakage drift region; 12 P-type heavily doped substrate; 13 P-type epitaxial layer; 14P Type doped connection or trench filled with conductive material; 15 P type heavily doped source region; 16 P type doped channel region; 17 N type heavily doped source region; 18 N type heavily doped drain region; Grid; 110 Leakage ohmic contact area; 111 source ohmic contact area; 2 field plate; 2a first field plate; 2b second field plate; 21 horizontal portion; 3 dielectric layer; 4a first through hole; 4b second through hole; 5a first metal; 5b second metal.
具体实施方式 detailed description
下面结合附图及实施例对本发明作进一步描述： The present invention is further described below in conjunction with the accompanying drawings and embodiments:
实施例：如图 2 所示，一种源漏击穿电压在 60V ～ 120V 之间的多重场板 LDMOS 器件，包括半导体本体 1 ，所述半导体本体 1 包括最下层的 P 型重掺杂衬底 12 ， P 型重掺杂衬底 12 上的 P 型外延层 13 ， P 型外延层 13 上形成的 P 型重掺杂源区 15 、 P 型掺杂沟道区 16 、 N 型掺杂漏漂移区 11 和 N 型重掺杂漏区 18 ，其中 P 型重掺杂区 15 和 P 型掺杂沟道区 16 相连的位置上形成有 N 型重掺杂源区 17 。 P 型重掺杂源区 15 和 P 型重掺杂衬底 12 之间还可设置 P 型掺杂连接或用导电物填充的沟槽 14 ，该沟槽 14 内的 P 型掺杂或导电物与 P 型重掺杂衬底 12 相接触；该沟槽还可以为用导电物填充的通孔。源欧姆接触区 111 设于 P 型重掺杂源区 15 和 N 型重掺杂源区 17 的上表面，漏欧姆接触区 110 设于 N 型重掺杂漏区 18 上表面。所述半导体本体 1 上还形成有栅 19 。 Embodiment: As shown in FIG. 2, a multiple field plate LDMOS with a source-drain breakdown voltage between 60V and 120V. The device includes a semiconductor body 1 including a lowermost P-type heavily doped substrate 12, a P-type epitaxial layer 13 on a P-type heavily doped substrate 12, and a P-type epitaxial layer 13 formed on the P-type heavily doped source region 15, the P-type doped channel region 16, the N-type doped drain drift region 11 and the N-type heavily doped drain region 18, wherein the P-type heavily doped region 15 and An N-type heavily doped source region 17 is formed at a position where the P-type doped channel region 16 is connected. P can also be placed between the P-type heavily doped source region 15 and the P-type heavily doped substrate 12. A type doped connection or trench 14 filled with a conductive material, a P-type doped or conductive material in the trench 14 and a P-type heavily doped substrate 12 Contacting; the trench may also be a via filled with a conductive material. The source ohmic contact region 111 is disposed on the upper surface of the P-type heavily doped source region 15 and the N-type heavily doped source region 17, and the drain ohmic contact region 110 is disposed on N-type heavily doped drain region 18 upper surface. A gate 19 is also formed on the semiconductor body 1.
如图 2 所示，所述半导体本体 1 表面设有三个场板 2 ，所述每个场板 2 具有与半导体本体 1 表面平行的水平部分 21 ，各场板 2 的水平部分 21 与半导体本体 1 表面之间的距离成均匀线性逐次递增。 As shown in FIG. 2, the surface of the semiconductor body 1 is provided with three field plates 2, each of which has a semiconductor body 1 The horizontal portion 21 parallel to the surface, the distance between the horizontal portion 21 of each field plate 2 and the surface of the semiconductor body 1 is uniformly linearly successively increased.
所述场板 2 位于半导体本体 1 的漏漂移区 11 的上方。 The field plate 2 is situated above the drain drift region 11 of the semiconductor body 1.
如图 3 和图 4 所示为另一具体实施例的结构示意图，其半导体本体 1 的结构与上一实施例相同，但是场板 2 设有两个，第一个场板 2a 的水平部分 21 距半导体本体 1 表面的距离在 0.06 微米～ 0.5 微米之间，水平的横向扩展距离在 0.4 微米～ 2 微米之间。第二个场板 2b 的水平部分距半导体本体 1 表面的距离在 0.1 微米～ 1 微米之间（无论取值如何，第二场板的水平部分距离半导体本体 1 表面的距离要远于第一场板），水平的横向扩展距离在 0.4 微米～ 2 微米之间。各场板 2 的水平部分间在横向位置上有零交叠。各场板 2 可由金属或其它形式的导电物（如掺杂的多晶硅，硅化物等）组成，厚度在 0.05 微米 -0.5 微米间。 3 and FIG. 4 are schematic structural diagrams of another embodiment, the semiconductor body 1 The structure is the same as that of the previous embodiment, but the field plate 2 is provided with two, and the horizontal portion 21 of the first field plate 2a is spaced from the surface of the semiconductor body 1 by 0.06 μm to 0.5. Between microns, the horizontal lateral extension distance is between 0.4 microns and 2 microns. The horizontal portion of the second field plate 2b is at a distance of 0.1 μm to 1 from the surface of the semiconductor body 1 Between the micrometers (regardless of the value, the horizontal portion of the second field plate is farther from the surface of the semiconductor body 1 than the first field plate), and the horizontal lateral expansion distance is between 0.4 microns and 2 microns. Field board 2 There is a zero overlap between the horizontal portions in the lateral position. Each field plate 2 may be comprised of a metal or other form of electrical conductor (e.g., doped polysilicon, silicide, etc.) having a thickness between 0.05 microns and 0.5 microns.
所述漏漂移区 11 的长度在 2 微米～ 6 微米之间，漂移区的面掺杂浓度在 1 ～ 6E12/cm The length of the drain drift region 11 is between 2 micrometers and 6 micrometers, and the surface doping concentration of the drift region is 1 to 6E12/cm 22 之间。 between.
一种多重场板 LDMOS 器件的加工方法，包括以下步骤： A method of processing a multiple field plate LDMOS device, comprising the following steps:
1 ）加工半导体本体 1 ，包括形成栅 19 ； 1) processing the semiconductor body 1 , including forming the gate 19 ;
2 ）于半导体本体 1 的表面沉积一个介质层 3 ，该介质层的厚度与沉积该介质层前原有的介质层的厚度之和即为第一个场板水平部分距半导体本体表面的距离，再于该介质层 3 上沉积一导电薄膜，所述导电膜经由光刻和腐蚀工艺形成第一个场板 2a ； 2) depositing a dielectric layer on the surface of the semiconductor body 1 The sum of the thickness of the dielectric layer and the thickness of the original dielectric layer before depositing the dielectric layer is the distance between the horizontal portion of the first field plate and the surface of the semiconductor body, and then the dielectric layer 3 Depositing a conductive film thereon, the conductive film forming a first field plate 2a via photolithography and etching processes;
3 ）随后再依次沉积一个介质层 3 和导电薄膜，并经由光刻和腐蚀工艺形成第二个场板 2b ； 3) subsequently depositing a dielectric layer 3 and a conductive film in sequence, and forming a second field plate 2b via photolithography and etching processes;
4 ）根据需要制作的场板的个数重复步骤 3 ）。 4) Repeat step 3) according to the number of field plates you need to make.
以具有一层或一层以上金属互连的 LDMOS 工艺中二个场板的情形为例，一个可能的场板接地方法为： LDMOS with one or more metal interconnects For example, in the case of two field plates in the process, one possible method of grounding the field plate is:
1) 沿着栅宽方向每隔 20 微米～ 200 微米距离安排一个如图 3 或图 4 所示的从场板一或场板二到第一金属 5a 的连接； 1) Arrange a distance of 20 μm to 200 μm along the width of the gate as shown in Figure 3 or Figure 4 The connection from the field plate one or field plate two to the first metal 5a is shown;
2) 这些连接再通过第一金属 5a 和第一通孔 4a 连接到 N 型重掺杂源区 17 和 / 或 P 型重掺杂源区 15 和 / 或源欧姆接触区 111 ，从而实现了场板 2 与地即重掺杂衬底 12 的连接； 2) These connections are then connected to the N-type heavily doped source region 17 and/or P through the first metal 5a and the first via 4a. The heavily doped source region 15 and/or the source ohmic contact region 111, thereby effecting the connection of the field plate 2 to the ground, ie, the heavily doped substrate 12;
3 ）同样也可通过第二金属 5b 和第二通孔 4b 进行接地连接。 3) The ground connection can also be made through the second metal 5b and the second through hole 4b.
所述各场板可以接不同的直流电压，也可以均接地，其中以各场板均接地效果为佳。而在普通的具有单个场板的 LDMOS 器件中，场板一般只接地，本发明场板的连接方法更加灵活些。 The field plates can be connected to different DC voltages or grounded. The grounding effect of each field plate is better. And in the ordinary with a single field plate In the LDMOS device, the field plate is generally only grounded, and the connection method of the field plate of the present invention is more flexible.
本发明尤其适合源漏击穿电压大于40－50V的LDMOS器件使用，缓解了源漏击穿电压与导通电阻的优化要求之间的矛盾，改善LDMOS器件的性能。The invention is particularly suitable for use in LDMOS devices with source-drain breakdown voltages greater than 40-50V, which alleviates the contradiction between source-drain breakdown voltage and on-resistance optimization requirements, and improves the performance of LDMOS devices.

Claims (1)

  1. 1. 一种多重场板 LDMOS 器件，包括半导体本体（ 1 ），其特征在于：所述半导体本体（ 1 ）表面设有至少两个场板（ 2 ），所述每个场板（ 2 ）具有与半导体本体（ 1 ）表面平行的水平部分（ 21 ），不同场板（ 2 ）的水平部分（ 21 ）与半导体本体（ 1 ）表面之间的距离不等。 A multiple field plate LDMOS device comprising a semiconductor body (1) characterized by: said semiconductor body (1) The surface is provided with at least two field plates (2), each of which has a horizontal portion (21) parallel to the surface of the semiconductor body (1), a horizontal portion of the different field plates (2) (21) The distance from the surface of the semiconductor body (1) is not equal.
    2. 根据权利要求 1 所述的多重场板 LDMOS 器件，其特征在于：所述场板（ 2 ）位于半导体本体（ 1 ）的漏漂移区（ 11 ）的上方。 2. The multiple field plate LDMOS device according to claim 1, wherein the field plate (2) is located on the semiconductor body (1) Above the drain drift region (11).
    3. 根据权利要求 1 或 2 所述的多重场板 LDMOS 器件，其特征在于：所述至少两个场板（ 2 ）的水平部分（ 21 ）与半导体本体（ 1 ）表面的距离逐次递增。 3. The multiple field plate LDMOS device according to claim 1 or 2, wherein: at least two field plates (2 The distance between the horizontal portion (21) and the surface of the semiconductor body (1) is successively increased.
    4. 根据权利要求 3 所述的多重场板 LDMOS 器件，其特征在于：所述至少两个场板（ 2 ）的水平部分（ 21 ）与半导体本体（ 1 ）表面的距离成均匀线性逐次递增。 4. The multiple field plate LDMOS device according to claim 3, characterized in that the horizontal portion of the at least two field plates (2) (21) The distance from the surface of the semiconductor body (1) increases uniformly linearly.
    5. 一种多重场板 LDMOS 器件的加工方法，其特征在于包括以下步骤： 5. A method of processing a multiple field plate LDMOS device, comprising the steps of:
    1 ）加工半导体本体（ 1 ），包括了栅（ 19 ）的形成； 1) processing the semiconductor body (1), including the formation of the gate (19);
    2 ）于半导体本体（ 1 ）的表面沉积一个介质层（ 3 ），再于该介质层（ 3 ）上沉积一导电薄膜，所述导电膜经由光刻和腐蚀工艺形成第一个场板（ 2a ）； 2) depositing a dielectric layer (3) on the surface of the semiconductor body (1), and then on the dielectric layer (3) Depositing a conductive film thereon, the conductive film forming a first field plate (2a) via photolithography and etching processes;
    3 ）随后再依次沉积一个介质层（ 3 ）和导电薄膜，并经由光刻和腐蚀工艺形成第二个场板（ 2b ）； 3) subsequently depositing a dielectric layer (3) and a conductive film in sequence, and forming a second field plate (2b) via photolithography and etching processes;
    4）根据需要制作的场板的个数重复步骤3）。4) Repeat step 3) according to the number of field plates that need to be made.
PCT/CN2010/078342 2009-11-03 2010-11-02 Ldmos device with multiple field plates and manufacturing method thereof WO2011054280A1 (en)

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