WO2017197698A1 - 稳压装置 - Google Patents

稳压装置 Download PDF

Info

Publication number
WO2017197698A1
WO2017197698A1 PCT/CN2016/086330 CN2016086330W WO2017197698A1 WO 2017197698 A1 WO2017197698 A1 WO 2017197698A1 CN 2016086330 W CN2016086330 W CN 2016086330W WO 2017197698 A1 WO2017197698 A1 WO 2017197698A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
mos transistor
resistor
voltage signal
logic processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/086330
Other languages
English (en)
French (fr)
Inventor
张先明
曹丹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US15/118,813 priority Critical patent/US10062344B2/en
Publication of WO2017197698A1 publication Critical patent/WO2017197698A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness

Definitions

  • the invention relates to a voltage regulator device under light and heavy load variation, and the voltage regulator device can be applied to the fields of backlighting and driving of liquid crystal displays.
  • an exemplary embodiment of the present invention provides a device for controlling and changing the magnitude of a feedback voltage such that different feedback voltages can be changed under light and heavy load variations, and the stability of the output voltage is maintained as much as possible. Reduce the ripple size.
  • a voltage stabilizing apparatus for a function circuit, the voltage stabilizing apparatus comprising: a signal detecting and amplifying circuit, a feedback voltage signal generating circuit, and a logic processing circuit.
  • the signal detecting and amplifying circuit is configured to detect the working voltage of the function circuit, perform operation amplification on the detected working voltage, and output the calculated and amplified voltage signal to the logic processing circuit.
  • the logic processing circuit is configured to adjust the first control signal according to the calculated amplified voltage signal, and output the adjusted first control signal to the feedback voltage signal generating circuit.
  • the feedback voltage signal generating circuit is configured to adjust the feedback voltage signal according to the adjusted first control signal, and output the adjusted feedback voltage signal to the logic processing circuit.
  • the logic processing circuit is further configured to adjust the second control signal according to the adjusted feedback voltage signal, and output the adjusted second control signal to the function circuit, so that the output voltage of the control function circuit remains stable.
  • the logic processes the electrical The path reduces the amplitude of the feedback voltage signal, thereby causing the output voltage of the functional circuit controlled by the second control signal to drop.
  • the logic processing circuit increases the amplitude of the feedback voltage signal to increase the output voltage of the functional circuit controlled by the second control signal.
  • the signal detection and amplifying circuit comprises: an operational amplifier, a first resistor, and a second resistor.
  • the non-inverting input of the operational amplifier is used to detect the operating voltage of the functional circuit.
  • the inverting input of the operational amplifier is electrically grounded through the first resistor, the output of the operational amplifier is connected to the logic processing circuit, and the second resistor is connected to the operation. Between the inverting input and the output of the amplifier.
  • the feedback voltage signal generating circuit comprises: a first MOS transistor and a second MOS transistor. a gate of the first MOS transistor and a gate of the second MOS transistor are connected to the logic processing circuit for receiving the first control signal, the source of the first MOS transistor and the source of the second MOS transistor are both connected to the functional circuit
  • the output terminal is configured to receive an output voltage of the functional circuit, the drain of the first MOS transistor is coupled to the logic processing circuit for outputting the feedback voltage signal to the logic processing circuit, and the drain of the second MOS transistor is electrically grounded.
  • the logic processing circuit controls the conduction of the first MOS transistor and the second MOS transistor by a first control signal applied to a gate of the first MOS transistor and a gate of the second MOS transistor according to an amplitude of the amplified voltage signal Pass and cutoff to adjust the amplitude of the feedback voltage signal.
  • the logic processing circuit turns off the first MOS transistor according to the first control signal and turns on the second MOS transistor, thereby making the feedback voltage signal The amplitude is decreased; if the amplitude of the operationally amplified voltage signal is lower than the first threshold, the logic processing circuit turns on the first MOS transistor and turns off the second MOS transistor according to the first control signal, thereby causing the feedback voltage signal The magnitude of the increase.
  • the feedback voltage signal generating circuit further includes: a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor.
  • the source of the first MOS transistor is connected to the output of the functional circuit through a sixth resistor, and the source of the second MOS transistor is connected to the output of the functional circuit through a third resistor and a fourth resistor connected in series, the second MOS
  • the drain of the transistor is electrically grounded through a seventh resistor, one end of the fifth resistor is connected to the source of the second MOS transistor, and the other end of the fifth resistor is electrically grounded.
  • the functional circuit is a boost circuit
  • the boost circuit includes: a third MOS transistor and an inductor, a diode, and a capacitor connected in series.
  • a gate of the third MOS transistor is coupled to the logic processing circuit for receiving a second control signal from the logic processing circuit
  • a drain of the third MOS transistor is coupled between the inductor and the diode
  • a source of the third MOS transistor is electrically Ground. If the amplitude of the feedback voltage signal is lower than the second threshold, the logic processing circuit increases the on-duty of the third MOS transistor by adjusting the duty ratio of the second control signal, thereby controlling the output voltage of the control circuit to rise. If the amplitude of the feedback voltage signal is higher than the second threshold, the logic processing circuit reduces the on-duty of the third MOS transistor by adjusting the duty ratio of the second control signal, thereby controlling the output voltage of the functional circuit decline.
  • FIG. 1 is a block diagram showing the structure of applying a voltage stabilizing device to a functional circuit according to an exemplary embodiment of the present invention
  • FIG. 2 is a circuit diagram showing a voltage stabilizing device for a booster circuit according to an exemplary embodiment of the present invention.
  • the voltage stabilizing device includes a signal detecting and amplifying circuit, a feedback voltage signal generating circuit, and a logic processing circuit.
  • the signal detecting and amplifying circuit is configured to detect the working voltage of the function circuit, perform operation amplification on the detected working voltage, and output the calculated and amplified voltage signal to the logic processing circuit.
  • the logic processing circuit is configured to adjust the first control signal according to the calculated amplified voltage signal, and output the adjusted first control signal to the feedback voltage signal generating circuit.
  • the feedback voltage signal generating circuit is configured to adjust the feedback voltage signal according to the adjusted first control signal, and output the adjusted feedback voltage signal to the logic processing circuit. Further, a feedback voltage signal generating circuit may be connected to the functional circuit to receive an output voltage signal of the functional circuit.
  • the logic processing circuit is further configured to adjust the second control signal according to the adjusted feedback voltage signal, and output the adjusted second control signal to the function circuit, so that the output voltage of the control function circuit remains stable.
  • the logic processing circuit reduces the amplitude of the feedback voltage signal such that the output voltage of the functional circuit controlled by the second control signal decreases.
  • the logic processing circuit increases the amplitude of the feedback voltage signal to increase the output voltage of the functional circuit controlled by the second control signal.
  • the above-mentioned voltage stabilizing device can be applied or integrated into a driving circuit of an electronic device such as a liquid crystal display to achieve voltage stabilization and ripple reduction.
  • FIG. 2 is a circuit diagram showing a voltage stabilizing device for a booster circuit according to an exemplary embodiment of the present invention.
  • a boosting (BOOST) circuit is taken as an example of a functional circuit, and a voltage stabilizing device for a boosting circuit is shown.
  • the voltage stabilizing device comprises a signal detecting and amplifying circuit, a feedback voltage signal generating circuit and a logic processing circuit.
  • the signal detecting and amplifying circuit includes an operational amplifier, a first resistor R1, and a second resistor R2.
  • the non-inverting input of the operational amplifier is used to detect the operating voltage of the boosting circuit.
  • the inverting input of the operational amplifier is electrically grounded through the first resistor R1, and the output of the operational amplifier is connected to the logic processing circuit.
  • a second resistor R2 is coupled between the inverting input and the output of the operational amplifier.
  • the signal detecting and amplifying circuit performs operational amplification on the detected operating voltage, and outputs the amplified and amplified voltage signal to the logic processing circuit.
  • the feedback voltage signal generating circuit includes a first MOS transistor Q1 and a second MOS transistor Q2.
  • a gate of the first MOS transistor Q1 and a gate of the second MOS transistor Q2 are coupled to the logic processing circuit to receive a first control signal from the logic processing circuit, the first control signal being applied to the first MOS by the logic processing circuit, respectively
  • the gates of the transistor Q1 and the gates of the gates of the second MOS transistor Q2 drive the signals G1 and G2, so that the logic processing circuit can control the first MOS transistor Q1 and the second MOS transistor Q2, respectively, through the gate drive signals G1 and G2.
  • the drain of the first MOS transistor Q1 is connected to a logic processing circuit to provide a feedback voltage signal FB to the logic processing circuit.
  • any one of the first MOS transistor Q1 and the second MOS transistor Q2 may be an NMOS transistor.
  • the feedback voltage signal generating circuit further includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7.
  • the source of the first MOS transistor is connected to the output terminal of the booster circuit through a sixth resistor R6, and the source of the second MOS transistor is connected to the booster circuit through a third resistor R3 and a fourth resistor R4 connected in series
  • the drain of the second MOS transistor is electrically grounded through a seventh resistor R7, one end of the fifth resistor R5 is connected to the source of the second MOS transistor, and the other end of the fifth resistor R5 is electrically grounded.
  • the boosting circuit includes a third MOS transistor Q3, an eighth resistor R8, and an inductor L1, a diode D1, and a capacitor C1 connected in series.
  • a gate of the third MOS transistor is connected to the logic processing circuit to receive a second control signal from the logic processing circuit, a drain of the third MOS transistor is connected between the inductor L1 and the diode D1, and a source of the third MOS transistor passes through Eight resistor R8 is electrically grounded.
  • the non-inverting input of the operational amplifier is connected between one end of the resistor R8 and the source of the third MOS transistor Q3, and the other end of the resistor R8 is connected to the ground.
  • the resistor R8 is configured to detect the current of the boosting circuit and provide a voltage signal to the operational amplifier, and the amplified voltage signal is input to the logic processing circuit by the operational amplifier for logic processing.
  • the signal can feedback the working condition of the current of the boosting circuit in real time, and different operating currents can feed different voltages to the logic processing.
  • the third MOS transistor Q3 may be an NMOS transistor.
  • the logic processing circuit adjusts the gate drive signals G1 and G2 according to the operationally amplified voltage signals, and applies the gate drive signals G1 and G2 to the gates of the first MOS transistor Q1 and the second MOS transistor Q2, respectively.
  • the first MOS transistor Q1 and the second MOS transistor Q2 adjust the feedback voltage signal FB according to the gate drive signals G1 and G2.
  • the logic processing circuit, the operational amplifier, the resistor R8, and the third MOS transistor Q3 are included in an integrated circuit (IC) module.
  • the logic processing circuit controls the on and off of the first MOS transistor Q1 and the second MOS transistor Q2 in accordance with signals of different voltage levels received from the operational amplifier. For example, if the magnitude of the voltage is higher than a certain threshold (ie, the working current is proven to be large), the logic processing circuit passes the gate drive signal G1 and the gate drive signal applied to the gate of the first MOS transistor and the gate of the second MOS transistor, respectively. G2, turning on the second MOS transistor Q2 and turning off the first MOS transistor Q1, can reduce the amplitude of the feedback voltage signal FB and lower the output voltage of the booster circuit.
  • a certain threshold ie, the working current is proven to be large
  • the feedback voltage signal FB is supplied to the logic processing circuit to cause the IC module to compensate for the drop in the output voltage due to the large current and to reduce the ripple.
  • the logic processing circuit turns on the first MOS transistor Q1 and the second MOS transistor Q2 through the gate driving signals G1 and G2.
  • the amplitude of the feedback voltage signal FB can be increased to increase the output voltage of the booster circuit.
  • the feedback voltage signal FB is supplied to the logic processing circuit to cause the IC module to compensate for the recovery of the output voltage due to the small current and to reduce the ripple.
  • the specific threshold can be set according to actual needs.
  • the logic processing circuit detects the feedback voltage signal FB in addition to detecting an output voltage level of the operational amplifier.
  • the logic processing circuit controls the on-duty of the third MOS transistor Q3 by adjusting the duty ratio of the second control signal applied to the gate of the third MOS transistor according to the magnitude of the feedback voltage signal FB, thereby controlling the overall The magnitude of the output voltage for timely compensation. For example, if the amplitude of the detected feedback voltage signal FB is less than another specific threshold, the logic processing circuit increases the conduction duty ratio of the third MOS transistor Q3 by adjusting the duty ratio of the second control signal.
  • the logic processing circuit adjusts the duty ratio of the second control signal The on-duty of the third MOS transistor Q3 is decreased to lower the output voltage of the booster circuit.
  • the other specific threshold may be set according to actual needs. As described above, the voltage stabilizing function of the voltage stabilizing device can be further realized.
  • the logic processing circuit may further include an error amplifier (not shown) for monitoring the feedback voltage signal FB, and comparing the feedback voltage signal FB with a predetermined signal set in advance, so that the logic processing circuit is as described above.
  • the mode adjusts the duty ratio of the second control signal to adjust the magnitude of the on-duty of the third MOS transistor Q3.
  • the voltage stabilizing device when operating under light and heavy load conditions, can effectively feedback the magnitude of the output load in time, and by controlling the feedback, the output is substantially stabilized in a straight line, thereby maintaining the output voltage.
  • the stability can also reduce ripple.
  • the voltage stabilizing device can be applied to various functional circuits (for example, the booster circuit as described above), and can be synchronously extended to other topologies.
  • the voltage stabilizing device can be applied to a driving circuit of a liquid crystal display or the like to achieve voltage stabilization and ripple reduction.
  • the voltage stabilizing device can be implemented as various hardware components and applied to various electronic devices as needed, based on the processing performed by the respective elements defined by the present invention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Dc-Dc Converters (AREA)
  • Amplifiers (AREA)

Abstract

一种稳压装置，所述稳压装置包括信号侦测放大电路、反馈电压信号产生电路、逻辑处理电路；信号侦测放大电路用于侦测功能电路的工作电压，将侦测到的工作电压进行运算放大，并将运算放大后的电压信号输出到逻辑处理电路；逻辑处理电路用于根据运算放大后的电压信号调节第一控制信号，并将调节后的第一控制信号输出到反馈电压信号产生电路；反馈电压信号产生电路用于根据调节后的第一控制信号调节反馈电压信号，并将调节后的反馈电压信号输出到逻辑处理电路；逻辑处理电路还用于根据调节后的反馈电压信号调节第二控制信号，并将调节后的第二控制信号输出到功能电路，从而控制功能电路的输出电压使输出电压稳定。

Description

稳压装置 技术领域
本发明涉及一种轻重载变化下的稳压装置，该稳压装置可应用于液晶显示器的背光及驱动等领域。
背景技术
现在的显示面板的解析度越来越高，所需要的各路电流也越来越大。
然而，由于各路输出电压的抽载变化大，同时在面板驱动中也存在轻重载画面的变化，进而导致在这段时间内，由于各路电流变小而造成输出电压在轻重载变化下会有较大变化，导致输出电压不稳定以及纹波(Ripple)比较大。因此，轻重载变化下的电压控制变得尤其重要。
发明内容
为克服现有技术的不足，本发明的示例性实施例提供一种控制并更改反馈电压的大小的装置，使得在轻重载变化下能更改不同的反馈电压，尽力维持输出电压的稳定性以及减小纹波大小。
根据本发明的示例性实施例，提供一种用于功能电路的稳压装置，所述稳压装置包括：信号侦测放大电路、反馈电压信号产生电路、逻辑处理电路。信号侦测放大电路用于侦测功能电路的工作电压，将侦测到的工作电压进行运算放大，并将运算放大后的电压信号输出到逻辑处理电路。逻辑处理电路用于根据运算放大后的电压信号调节第一控制信号，并将调节后的第一控制信号输出到反馈电压信号产生电路。反馈电压信号产生电路用于根据调节后的第一控制信号调节反馈电压信号，并将调节后的反馈电压信号输出到逻辑处理电路。逻辑处理电路还用于根据调节后的反馈电压信号调节第二控制信号，并将调节后的第二控制信号输出到功能电路，从而控制功能电路的输出电压保持稳定。
可选地，如果运算放大后的电压信号的幅值高于第一阈值，则逻辑处理电 路使反馈电压信号的幅值减小，从而使由第二控制信号控制的功能电路的输出电压下降。
可选地，如果运算放大后的电压信号的幅值低于第一阈值，则逻辑处理电路使反馈电压信号的幅值增大，从而使由第二控制信号控制的功能电路的输出电压上升。
可选地，信号侦测放大电路包括：运算放大器、第一电阻器、第二电阻器。运算放大器的同相输入端用于侦测功能电路的工作电压，运算放大器的反相输入端通过第一电阻器电性接地，运算放大器的输出端连接至逻辑处理电路，第二电阻器连接在运算放大器的反相输入端和输出端之间。
可选地，反馈电压信号产生电路包括：第一MOS晶体管、第二MOS晶体管。第一MOS晶体管的栅极和第二MOS晶体管的栅极连接到逻辑处理电路以用于接收第一控制信号，第一MOS晶体管的源极和第二MOS晶体管的源极均连接到功能电路的输出端以用于接收功能电路的输出电压，第一MOS晶体管的漏极连接到逻辑处理电路以用于将反馈电压信号输出到逻辑处理电路，第二MOS晶体管的漏极电性接地。根据运算放大后的电压信号的幅值，逻辑处理电路通过施加到第一MOS晶体管的栅极和第二MOS晶体管的栅极的第一控制信号而控制第一MOS晶体管和第二MOS晶体管的导通和截止，以调节反馈电压信号的幅值。
可选地，如果运算放大后的电压信号的幅值高于第一阈值，则逻辑处理电路根据第一控制信号使第一MOS晶体管截止并使第二MOS晶体管导通，从而使反馈电压信号的幅值减小；如果运算放大后的电压信号的幅值低于第一阈值，则逻辑处理电路根据第一控制信号使第一MOS晶体管导通并使第二MOS晶体管截止，从而使反馈电压信号的幅值增大。
可选地，反馈电压信号产生电路还包括：第三电阻器、第四电阻器、第五电阻器、第六电阻器、第七电阻器。第一MOS晶体管的源极通过第六电阻器连接到功能电路的输出端，第二MOS晶体管的源极通过串联的第三电阻器和第四电阻器连接到功能电路的输出端，第二MOS晶体管的漏极通过第七电阻器电性接地，第五电阻器的一端连接到第二MOS晶体管的源极，第五电阻器的另一端电性接地。
可选地，所述功能电路是升压电路，所述升压电路包括：第三MOS晶体管以及串联连接的电感器、二极管和电容器。第三MOS晶体管的栅极连接到逻辑处理电路以用于从逻辑处理电路接收第二控制信号，第三MOS晶体管的漏极连接到电感器和二极管之间，第三MOS晶体管的源极电性接地。如果反馈电压信号的幅值低于第二阈值，则逻辑处理电路通过调节第二控制信号的占空比而使第三MOS晶体管的导通占空比增大，从而控制功能电路的输出电压上升；如果反馈电压信号的幅值高于第二阈值，则逻辑处理电路通过调节第二控制信号的占空比而使第三MOS晶体管的导通占空比减小，从而控制功能电路的输出电压下降。
可选地，所述升压电路还包括：第八电阻器。第三MOS晶体管的源极通过第八电阻器电性接地。
根据本发明的示例性实施例，提供一种液晶显示器的驱动电路，所述驱动电路包括根据本发明的实施例中的任何一个所述的稳压装置。
将在接下来的描述中部分阐述本发明另外的方面和/或优点，还有一部分通过描述将是清楚的，或者可以经过本发明的实施而得知。
附图说明
通过下面结合附图进行的对实施例的描述，本发明的上述和/或其它目的和优点将会变得更加清楚，其中：
图1是根据本发明示例性实施例的将稳压装置应用于功能电路的结构框图；
图2是示出根据本发明示例性实施例的用于升压电路的稳压装置的电路示意图。
具体实施方式
现将详细描述本发明的示例性实施例，所述实施例的示例在附图中示出，其中，相同的标号指示相同的部分。以下将通过参照附图来说明所述实施例，以便解释本发明。
图1是根据本发明示例性实施例的将稳压装置应用于功能电路的结构框图。如图1所示，稳压装置包括信号侦测放大电路、反馈电压信号产生电路、逻辑处理电路。信号侦测放大电路用于侦测功能电路的工作电压，将侦测到的工作电压进行运算放大，并将运算放大后的电压信号输出到逻辑处理电路。逻辑处理电路用于根据运算放大后的电压信号调节第一控制信号，并将调节后的第一控制信号输出到反馈电压信号产生电路。反馈电压信号产生电路用于根据调节后的第一控制信号调节反馈电压信号，并将调节后的反馈电压信号输出到逻辑处理电路。此外，反馈电压信号产生电路可以连接到功能电路，以接收功能电路的输出电压信号。
逻辑处理电路还用于根据调节后的反馈电压信号调节第二控制信号，并将调节后的第二控制信号输出到功能电路，从而控制功能电路的输出电压保持稳定。
如果运算放大后的电压信号的幅值高于第一阈值，则逻辑处理电路使反馈电压信号的幅值减小，从而使由第二控制信号控制的功能电路的输出电压下降。或者，如果运算放大后的电压信号的幅值低于第一阈值，则逻辑处理电路使反馈电压信号的幅值增大，从而使由第二控制信号控制的功能电路的输出电压上升。
上述稳压装置可应用或集成到液晶显示器等电子设备的驱动电路中，以实现稳压以及减少纹波的功能。
图2是示出根据本发明示例性实施例的用于升压电路的稳压装置的电路示意图。如图2所示，在此以升压(BOOST)电路作为功能电路的示例，示出一种用于升压电路的稳压装置。所述稳压装置包括信号侦测放大电路、反馈电压信号产生电路、逻辑处理电路。
信号侦测放大电路包括：运算放大器、第一电阻器R1、第二电阻器R2。运算放大器的同相输入端用于侦测升压电路的工作电压，运算放大器的反相输入端通过第一电阻器R1电性接地，运算放大器的输出端连接至逻辑处理电路。第二电阻器R2连接在运算放大器的反相输入端和输出端之间。信号侦测放大电路将侦测到的工作电压进行运算放大，并将运算放大后的电压信号输出到逻辑处理电路。
反馈电压信号产生电路包括第一MOS晶体管Q1和第二MOS晶体管Q2。第一MOS晶体管Q1的栅极和第二MOS晶体管Q2的栅极连接到逻辑处理电路以从逻辑处理电路接收第一控制信号，所述第一控制信号包括由逻辑处理电路分别施加到第一MOS晶体管Q1的栅极和第二MOS晶体管Q2的栅极的栅极驱动信号G1和G2，使得逻辑处理电路可以通过栅极驱动信号G1和G2分别控制第一MOS晶体管Q1和第二MOS晶体管Q2。此外，第一MOS晶体管Q1的漏极连接到逻辑处理电路，从而向逻辑处理电路提供反馈电压信号FB。
可选地，第一MOS晶体管Q1和第二MOS晶体管Q2中的任何一个可以是NMOS晶体管。
反馈电压信号产生电路还包括：第三电阻器R3、第四电阻器R4、第五电阻器R5、第六电阻器R6、第七电阻器R7。第一MOS晶体管的源极通过第六电阻器R6连接到升压电路的输出端，第二MOS晶体管的源极通过串联连接的第三电阻器R3和第四电阻器R4连接到升压电路的输出端，第二MOS晶体管的漏极通过第七电阻器R7电性接地，第五电阻器R5的一端连接到第二MOS晶体管的源极，第五电阻器R5的另一端电性接地。
所述升压电路包括：第三MOS晶体管Q3、第八电阻器R8以及串联连接的电感器L1、二极管D1和电容器C1。第三MOS晶体管的栅极连接到逻辑处理电路以从逻辑处理电路接收第二控制信号，第三MOS晶体管的漏极连接在电感器L1和二极管D1之间，第三MOS晶体管的源极通过第八电阻器R8电性接地。运算放大器的同相输入端连接在电阻器R8的一端与第三MOS晶体管Q3的源极之间，电阻器R8的另一端连接到地。电阻器R8被配置为侦测升压电路的电流，并向运算放大器提供电压信号，通过运算放大器运算放大后的电压信号输入到逻辑处理电路以进行逻辑处理。所述信号可以实时反馈升压电路的电流的工作状况，不同的工作电流可以向逻辑处理反馈不同的电压。
可选地，第三MOS晶体管Q3可以是NMOS晶体管。
逻辑处理电路根据运算放大后的电压信号调节栅极驱动信号G1和G2，并将栅极驱动信号G1和G2分别施加到第一MOS晶体管Q1和第二MOS晶体管Q2的栅极。第一MOS晶体管Q1和第二MOS晶体管Q2根据栅极驱动信号G1和G2调节反馈电压信号FB。
在所述升压电路示例中，逻辑处理电路、运算放大器、电阻器R8和第三MOS晶体管Q3被包含在集成电路(IC)模块中。
逻辑处理电路根据从运算放大器接收的不同电压水平的信号来控制第一MOS晶体管Q1和第二MOS晶体管Q2的导通和截止。例如，若电压的幅值比特定阈值高(即，证明工作电流大)，则逻辑处理电路通过分别施加到第一MOS晶体管的栅极和第二MOS晶体管的栅极的栅极驱动信号G1和G2，使第二MOS晶体管Q2导通并使第一MOS晶体管Q1截止，可以使反馈电压信号FB的幅值减小，使升压电路的输出电压下降。同时，反馈电压信号FB被提供给逻辑处理电路，使所述IC模块对由于大电流导致的输出电压的下降进行补偿并减小纹波。此外，若电压的幅值比特定阈值低(即，证明工作电流小)，则逻辑处理电路通过所述栅极驱动信号G1和G2，使第一MOS晶体管Q1导通并使第二MOS晶体管Q2截止，可以使反馈电压信号FB的幅值增大，使升压电路的输出电压上升。同时，反馈电压信号FB被提供给逻辑处理电路，使所述IC模块对由于小电流导致的输出电压的恢复进行补偿并减小纹波。可根据实际需要来设置所述特定阈值。
可选地，逻辑处理电路除了侦测运算放大器的输出电压水平，还侦测所述反馈电压信号FB。逻辑处理电路根据反馈电压信号FB的幅值，通过调节施加到第三MOS晶体管的栅极的第二控制信号的占空比，来控制第三MOS晶体管Q3的导通占空比，从而控制整体输出电压的大小，以便及时进行补偿。例如，如果侦测到的反馈电压信号FB的幅值小于另一特定阈值，则逻辑处理电路通过调节所述第二控制信号的占空比来使第三MOS晶体管Q3的导通占空比增大，从而使所述升压电路的输出电压上升；如果侦测到的反馈电压信号FB的幅值大于所述另一特定阈值，则逻辑处理电路通过调节所述第二控制信号的占空比来使第三MOS晶体管Q3的导通占空比减小，从而使所述升压电路的输出电压下降。可根据实际需要来设置所述另一特定阈值。如上所述，可以进一步实现稳压装置的稳压功能。
可选地，逻辑处理电路还可以包括误差放大器(未示出)，误差放大器用于监测反馈电压信号FB，将反馈电压信号FB与预先设置的预定信号进行比较，以便逻辑处理电路按照前面描述的方式调节所述第二控制信号的占空比，以便调节第三MOS晶体管Q3的导通占空比的大小。
如上所述，当在轻重载变化的情况下工作时，所述稳压装置可以有效及时地反馈输出负载的大小，并通过控制反馈，将输出基本稳定在一条直线上，从而在保持输出电压的稳定性的同时还可以减小纹波。
应注意，本发明仅示出了部分电子器件，本领域技术人员可以根据需要设置更细分的电阻及补偿电路，可以设置更多的电阻及MOS晶体管，以便实现更稳定的控制。
虽然本发明以上述电路结构为例，但是，所述稳压装置可应用于各种功能电路(例如，如上所述的升压电路)中，还可以同步扩展到其他拓扑架构中。例如，稳压装置可应用于液晶显示器等的驱动电路，以实现稳压以及减少纹波的功能。
此外，基于本发明限定的各个元件所执行的处理，本领域技术人员可以根据需要而将根据本发明的示例性实施例的稳压装置实现为各种硬件组件并应用于各种电子设备。
本发明的以上实施例仅仅是示例性的，而本发明并不受限于此。本领域技术人员应该理解：在不脱离本发明的原理和精神的情况下，可对这些实施例进行改变，其中，本发明的范围在权利要求及其等同物中限定。

Claims (11)

  1. 一种用于功能电路的稳压装置，其中，包括：信号侦测放大电路、反馈电压信号产生电路、逻辑处理电路；
    信号侦测放大电路用于侦测功能电路的工作电压，将侦测到的工作电压进行运算放大，并将运算放大后的电压信号输出到逻辑处理电路；
    逻辑处理电路用于根据运算放大后的电压信号调节第一控制信号，并将调节后的第一控制信号输出到反馈电压信号产生电路；
    反馈电压信号产生电路用于根据调节后的第一控制信号调节反馈电压信号，并将调节后的反馈电压信号输出到逻辑处理电路；
    逻辑处理电路还用于根据调节后的反馈电压信号调节第二控制信号，并将调节后的第二控制信号输出到功能电路，从而控制功能电路的输出电压保持稳定。
  2. 如权利要求1所述的稳压装置，其中，如果运算放大后的电压信号的幅值高于第一阈值，则逻辑处理电路使反馈电压信号的幅值减小，从而使由第二控制信号控制的功能电路的输出电压下降。
  3. 如权利要求1所述的稳压装置，其中，如果运算放大后的电压信号的幅值低于第一阈值，则逻辑处理电路使反馈电压信号的幅值增大，从而使由第二控制信号控制的功能电路的输出电压上升。
  4. 如权利要求1所述的稳压装置，其中，信号侦测放大电路包括：运算放大器、第一电阻器、第二电阻器；
    运算放大器的同相输入端用于侦测功能电路的工作电压，运算放大器的反相输入端通过第一电阻器电性接地，运算放大器的输出端连接至逻辑处理电路，第二电阻器连接在运算放大器的反相输入端和输出端之间。
  5. 如权利要求1所述的稳压装置，其中，反馈电压信号产生电路包括：第一MOS晶体管、第二MOS晶体管；
    第一MOS晶体管的栅极和第二MOS晶体管的栅极连接到逻辑处理电路以用于接收第一控制信号，第一MOS晶体管的源极和第二MOS晶体管的源极均连接到功能电路的输出端以用于接收功能电路的输出电压，第一MOS晶体管的漏极连接到逻辑处理电路以用于将反馈电压信号输出到逻辑处理电路，第二MOS晶体管的漏极电性接地；
    其中，根据运算放大后的电压信号的幅值，逻辑处理电路通过施加到第一MOS晶体管的栅极和第二MOS晶体管的栅极的第一控制信号而控制第一MOS晶体管和第二MOS晶体管的导通和截止，以调节反馈电压信号的幅值。
  6. 如权利要求5所述的稳压装置，其中，如果运算放大后的电压信号的幅值高于第一阈值，则逻辑处理电路根据第一控制信号使第一MOS晶体管截止并使第二MOS晶体管导通，从而使反馈电压信号的幅值减小；如果运算放大后的电压信号的幅值低于第一阈值，则逻辑处理电路根据第一控制信号使第一MOS晶体管导通并使第二MOS晶体管截止，从而使反馈电压信号的幅值增大。
  7. 如权利要求5所述的稳压装置，其中，反馈电压信号产生电路还包括：第三电阻器、第四电阻器、第五电阻器、第六电阻器、第七电阻器；
    第一MOS晶体管的源极通过第六电阻器连接到功能电路的输出端，第二MOS晶体管的源极通过串联的第三电阻器和第四电阻器连接到功能电路的输出端，第二MOS晶体管的漏极通过第七电阻器电性接地，第五电阻器的一端连接到第二MOS晶体管的源极，第五电阻器的另一端电性接地。
  8. 如权利要求6所述的稳压装置，其中，反馈电压信号产生电路还包括：第三电阻器、第四电阻器、第五电阻器、第六电阻器、第七电阻器；
    第一MOS晶体管的源极通过第六电阻器连接到功能电路的输出端，第二MOS晶体管的源极通过串联的第三电阻器和第四电阻器连接到功能电路的输出端，第二MOS晶体管的漏极通过第七电阻器电性接地，第五电阻器的一端连接到第二MOS晶体管的源极，第五电阻器的另一端电性接地。
  9. 如权利要求1所述的稳压装置，其中，所述功能电路是升压电路，所述升压电路包括：第三MOS晶体管以及串联连接的电感器、二极管和电容器；
    第三MOS晶体管的栅极连接到逻辑处理电路以用于从逻辑处理电路接收第二控制信号，第三MOS晶体管的漏极连接到电感器和二极管之间，第三MOS晶体管的源极电性接地；
    如果反馈电压信号的幅值低于第二阈值，则逻辑处理电路通过调节第二控制信号的占空比而使第三MOS晶体管的导通占空比增大，从而控制功能电路的输出电压上升；如果反馈电压信号的幅值高于第二阈值，则逻辑处理电路通过调节第二控制信号的占空比而使第三MOS晶体管的导通占空比减小，从而控制功能电路的输出电压下降。
  10. 如权利要求9所述的稳压装置，其中，所述升压电路还包括：第八电阻器；第三MOS晶体管的源极通过第八电阻器电性接地。
  11. 一种液晶显示器的驱动电路，其中，包括用于功能电路的稳压装置，其中，包括：信号侦测放大电路、反馈电压信号产生电路、逻辑处理电路；
    信号侦测放大电路用于侦测功能电路的工作电压，将侦测到的工作电压进行运算放大，并将运算放大后的电压信号输出到逻辑处理电路；
    逻辑处理电路用于根据运算放大后的电压信号调节第一控制信号，并将调节后的第一控制信号输出到反馈电压信号产生电路；
    反馈电压信号产生电路用于根据调节后的第一控制信号调节反馈电压信号，并将调节后的反馈电压信号输出到逻辑处理电路；
    逻辑处理电路还用于根据调节后的反馈电压信号调节第二控制信号，并将调节后的第二控制信号输出到功能电路，从而控制功能电路的输出电压保持稳定。
PCT/CN2016/086330 2016-05-20 2016-06-18 稳压装置 Ceased WO2017197698A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/118,813 US10062344B2 (en) 2016-05-20 2016-06-18 Voltage stabilizing device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610345442.9 2016-05-20
CN201610345442.9A CN105788559B (zh) 2016-05-20 2016-05-20 稳压装置

Publications (1)

Publication Number Publication Date
WO2017197698A1 true WO2017197698A1 (zh) 2017-11-23

Family

ID=56380391

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/086330 Ceased WO2017197698A1 (zh) 2016-05-20 2016-06-18 稳压装置

Country Status (3)

Country Link
US (1) US10062344B2 (zh)
CN (1) CN105788559B (zh)
WO (1) WO2017197698A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106354075B (zh) * 2016-11-25 2020-01-21 北京意同创科技有限公司 一种具有背光屏的遥控器控制电路
CN110635688B (zh) * 2019-09-24 2020-12-08 福州京东方光电科技有限公司 供电电路和显示装置
CN111179870A (zh) * 2020-01-31 2020-05-19 北京京东方显示技术有限公司 一种电源驱动电路、其驱动方法及显示装置
CN112350575A (zh) * 2020-09-11 2021-02-09 苏州浪潮智能科技有限公司 一种动态调节输出电压的Buck电路及动态调节方法
CN112398214A (zh) * 2020-10-27 2021-02-23 国网山东省电力公司昌邑市供电公司 一种可充电式太阳能外接电源装置、电能表供电系统
CN121605467A (zh) * 2023-02-28 2026-03-03 京东方科技集团股份有限公司 驱动芯片的温控电路和温控方法和时序控制驱动板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080054984A1 (en) * 2006-08-31 2008-03-06 International Rectifier Corporation High voltage gate driver ic with ramp driver
CN103680422A (zh) * 2013-12-06 2014-03-26 深圳市华星光电技术有限公司 一种背光源驱动电路及液晶显示装置和驱动方法
CN103929060A (zh) * 2014-04-17 2014-07-16 卓荣集成电路科技有限公司 降压变换电路
CN104575356A (zh) * 2015-01-19 2015-04-29 京东方科技集团股份有限公司 一种稳压电路、其稳压方法及显示器件

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100599957B1 (ko) * 1999-12-24 2006-07-12 비오이 하이디스 테크놀로지 주식회사 액정표시 장치의 게이트 전압 구동회로
JP2002351417A (ja) * 2001-05-24 2002-12-06 Internatl Business Mach Corp <Ibm> 表示装置に使用されるドライバ回路の駆動電源電圧とそのドライバ回路内で階調電圧生成のために用いられる基準電圧とを生成する駆動電源回路、それら駆動電源電圧と基準電圧を生成するドライバ回路用電圧生成方法およびその駆動電源回路を備えた表示装置
JP4873677B2 (ja) * 2001-09-06 2012-02-08 東北パイオニア株式会社 発光表示パネルの駆動装置
JP2004138958A (ja) * 2002-10-21 2004-05-13 Semiconductor Energy Lab Co Ltd 表示装置
JP2005181951A (ja) * 2003-11-25 2005-07-07 Tohoku Pioneer Corp 自発光表示モジュールおよび同モジュールにおける欠陥状態の検証方法
JP4646187B2 (ja) * 2004-02-12 2011-03-09 東北パイオニア株式会社 発光ディスプレイ装置およびその駆動制御方法
JP2007004420A (ja) * 2005-06-23 2007-01-11 Seiko Epson Corp 電源回路
JP2011050157A (ja) * 2009-08-26 2011-03-10 Canon Inc 電子機器
CN204066687U (zh) * 2014-08-27 2014-12-31 池州信安电子科技有限公司 一种用于lcd液晶显示的led背光源电路
CN204945542U (zh) * 2015-09-11 2016-01-06 深圳市华源显示技术有限公司 液晶显示模组的电压驱动电路、液晶显示模组及显示屏

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080054984A1 (en) * 2006-08-31 2008-03-06 International Rectifier Corporation High voltage gate driver ic with ramp driver
CN103680422A (zh) * 2013-12-06 2014-03-26 深圳市华星光电技术有限公司 一种背光源驱动电路及液晶显示装置和驱动方法
CN103929060A (zh) * 2014-04-17 2014-07-16 卓荣集成电路科技有限公司 降压变换电路
CN104575356A (zh) * 2015-01-19 2015-04-29 京东方科技集团股份有限公司 一种稳压电路、其稳压方法及显示器件

Also Published As

Publication number Publication date
US20180174536A1 (en) 2018-06-21
CN105788559A (zh) 2016-07-20
US10062344B2 (en) 2018-08-28
CN105788559B (zh) 2018-10-30

Similar Documents

Publication Publication Date Title
WO2017197698A1 (zh) 稳压装置
US7443149B2 (en) Regulator circuit capable of detecting variations in voltage
US7764113B2 (en) Output circuit
TWI354195B (en) Voltage regulator
US9146570B2 (en) Load current compesating output buffer feedback, pass, and sense circuits
TWI479780B (zh) 降壓轉換器
JP4833651B2 (ja) レギュレータ回路およびそれを搭載した自動車
TWI480713B (zh) Voltage regulator
US9367074B2 (en) Voltage regulator capable of stabilizing an output voltage even when a power supply fluctuates
WO2017049710A1 (zh) 一种环路补偿电路及开关电源电路
CN101930246A (zh) 输出装置
US11334102B2 (en) Power supply circuitry
US9160230B2 (en) DC/DC converter and electronic apparatus
US7889190B2 (en) Apparatus for supplying power source
TWI535196B (zh) 放大器及其操作方法
US7705578B2 (en) Switching regulator
US10263585B2 (en) Amplifier system and method for controlling amplifier
JP2017068472A (ja) ボルテージレギュレータ
US7495939B2 (en) Ripple filter circuit
JP5666694B2 (ja) 負荷電流検出回路
US8058832B2 (en) Motor driving circuit and method thereof
US10211839B2 (en) System and method of automatic power control system and bias current control circuit
TWI911503B (zh) 低壓降穩壓器
JP6495670B2 (ja) Ｌｅｄ駆動回路
JP2023027545A (ja) 半導体モジュール

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15118813

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16902080

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 16902080

Country of ref document: EP

Kind code of ref document: A1