WO2017196826A1 - Convertisseur de puissance - Google Patents

Convertisseur de puissance Download PDF

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Publication number
WO2017196826A1
WO2017196826A1 PCT/US2017/031726 US2017031726W WO2017196826A1 WO 2017196826 A1 WO2017196826 A1 WO 2017196826A1 US 2017031726 W US2017031726 W US 2017031726W WO 2017196826 A1 WO2017196826 A1 WO 2017196826A1
Authority
WO
WIPO (PCT)
Prior art keywords
die
switches
charge
layer
phase
Prior art date
Application number
PCT/US2017/031726
Other languages
English (en)
Inventor
David Giuliano
Original Assignee
Peregrine Semiconductor Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Peregrine Semiconductor Corporation filed Critical Peregrine Semiconductor Corporation
Priority to CN201780042383.0A priority Critical patent/CN109478845B/zh
Priority to DE112017002374.2T priority patent/DE112017002374T5/de
Publication of WO2017196826A1 publication Critical patent/WO2017196826A1/fr

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1582—Buck-boost converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
    • H02M7/2195—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration the switches being synchronously commutated at the same frequency of the AC input voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0016—Control circuits providing compensation of output voltage deviations using feedforward of disturbance parameters
    • H02M1/0022—Control circuits providing compensation of output voltage deviations using feedforward of disturbance parameters the disturbance parameters being input voltage fluctuations
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0043—Converters switched with a phase shift, i.e. interleaved
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
    • H02M1/007—Plural converter units in cascade
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/072—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps adapted to generate an output voltage whose value is lower than the input voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1584—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
    • H02M3/1586—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel switched with a phase shift, i.e. interleaved
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/06—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode
    • H02M7/10—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode arranged for operation in series, e.g. for multiplication of voltage
    • H02M7/103—Containing passive elements (capacitively coupled) which are ordered in cascade on one source

Definitions

  • This disclosure relates to power supplies, and in particular to power converters.
  • Switch-mode power converters regulate the output voltage or current by switching energy storage elements (i.e. inductors and capacitors) into different electrical configurations using a switch network.
  • Switched-capacitor converters are switch-mode power converters that primarily use capacitors to transfer energy. These converters transfer energy from an input to an output by using switches to cycle a network of capacitors through different topological states.
  • a common converter of this type known as a "charge pump,” is commonly used to produce the high voltages in FLASH memories and other reprogrammable memories. Charge pumps have also been used in connection with overcoming the nuclear strong force to transform one element into another.
  • Switches in the switch network are usually active devices that are implemented with transistors.
  • the switch network may be integrated on a single or on multiple monolithic semiconductor substrates, or formed using discrete devices. Furthermore, since each switch in a power converter normally carries high current, it may be composed of numerous smaller switches connected in parallel.
  • Typical DC-DC converters perform voltage transformation and output regulation. This is usually done in a single-stage converter such as a buck converter. However, it is possible to split these two functions into two specialized stages, namely a transformation stage, such as a switching network, and a separate regulation stage, such as a regulating circuit.
  • the transformation stage transforms one voltage into another, while the regulation stage ensures that the voltage and/or current output of the transformation stage maintains desired characteristics.
  • the transformation stage and the regulating stage are close together, a direct connection is possible.
  • the regulating stage may be far from the transformation stage. Under these circumstances, it is useful to filter the output of the transformation stage to reduce loss.
  • the invention features a transformation stage for transforming a first voltage into a second voltage.
  • a transformation stage includes a switching network, a filter, and a controller.
  • the filter is configured to connect the transformation stage to a regulator, and the controller controls the switching network.
  • the filter includes an LC filter.
  • the filter includes an inductance that, in operation at a particular switching frequency, sustains a peak-to-peak voltage ripple and supports an inductor current that passes into a load, the inductor current defining an average inductor current.
  • the inductance is selected by dividing the peak-to-peak voltage ripple by a product of the average inductor current and the switching frequency multiplied by 13/24.
  • Some embodiments include the regulating circuit.
  • the filter is configured to connect the transformation stage to more than one regulator.
  • Yet other embodiments include plural regulating circuits, wherein the filter connects the transformation stage to all of the regulators.
  • the transformation stage includes plural switching networks.
  • the filter connects to all of the switching networks to a regulating circuit.
  • transformation stage includes a plurality of units in series.
  • Each unit includes a switching network in series with a filter.
  • Typical DC-DC converters perform voltage transformation and output regulation. This is usually done in a single-stage converter such as a buck converter. However, it is possible to split these two functions into two specialized stages, namely a transformation stage, such as a switching network, and a separate regulation stage, such as a regulating circuit.
  • the transformation stage transforms one voltage into another, while the regulation stage ensures that the voltage and/or current output of the transformation stage maintains desired characteristics.
  • the transformation stage and the regulating stage are close together, a direct connection is possible.
  • the regulating stage may be far from the transformation stage. Under these circumstances, it is useful to filter the output of the transformation stage to reduce loss.
  • the invention includes an apparatus having phase and stack switches for operating a switched-capacitor converter.
  • the phase and stack switches are on respective first and second dies.
  • Some embodiments include a first controller that controls the switches on the first die and a second controller that controls switches on the second die.
  • An inter-controller commissure provides a link between the first and second controllers to permit operation of the first switches to depend at least in part on operation of the second switches, and to permit operation of the second switches to depend at least in part on operation of the first switches.
  • the first controller is on the first die
  • the second controller is on the second die
  • the inter-controller commissure extends between the first die and the second die.
  • those that include a third die and a fourth die are those that include a third die and a fourth die. In these embodiments, the first controller is on the third die, the second controller is on the fourth die, and the inter-controller commissure extends between the third die and the fourth die.
  • the switched-capacitor converter is a two-phase converter. Some of these embodiments have third and fourth dies.
  • the stack switches comprise first and second sets, each of which is associated with one of the two phases. The first set of stack switches is on the second die and the second set of stack switches is on the fourth die.
  • phase switches comprise first and second sets of phase switches, each of which is associated with one of the two phases.
  • the first set of phase switches is on the first die and the second set of phase switches is on the third die.
  • the embodiments include charge-transfer capacitors connected to the stack switches and to the phase switches.
  • the charge-transfer capacitors are discrete capacitors that connect to the first and second dies.
  • the first die and the second die are connected via an inter-die commissure having a length that corresponds to a distance between positive and negative terminals of the charge-transfer capacitors.
  • embodiments are those that have an interdie commissure connecting the first and second dies, wherein the first and second dies have first terminals for connection to positive terminals of the charge-transfer capacitors, and second terminals for connection to negative terminals of the charge-transfer capacitors, with the first and second terminals and the second terminals being disposed on opposite ends of the interdie commissure, and with the charge-transfer capacitors being oriented such that positive terminals thereof lie closer to the first terminals than they do to the second terminals and negative terminals thereof lie closer to the second terminals than to the first terminals.
  • interdie commissure has first and second regions such that, during operation, the first region carries more current than the second region. In these embodiments, the first region is wider than the second region.
  • the charge-transfer capacitors have capacitances that are a function of voltage applied across the charge-transfer capacitors. In operation, the charge- transfer capacitors sustain different maximum voltages. The charge-transfer capacitors are selected such that, when at their respective maximum voltages, the charge-transfer capacitors all have the same capacitance.
  • Some embodiments include an interdie commissure connecting the first and second dies. As a result of a fold in the interdie commissure, the first and second dies lie on different planes. Other embodiments feature coplanar first and second dies.
  • Embodiments include those in which the switched-capacitor converter is a multi- phase converter, and the apparatus has a third die.
  • the phase switches comprise a first set of phase switches associated with a first phase and a second set of phase switches associated with a second phase, with the first set being on the first die and the second set on the second die.
  • embodiments that have first and second sets of charge-transfer capacitors, with the first set of charge-transfer capacitors being connected between the first die and the second die, and the second set of charge-transfer capacitors being connected between the third die and the second die.
  • inventions include a substrate and charge-transfer capacitors.
  • the substrate supports the charge-transfer capacitors, the first die, and the second die.
  • the device faces of the first and second dies face the substrate, and conducting bumps between the device face and the substrate provide electrical communication between the dies and the charge-transfer capacitors.
  • embodiments that have a package, with the first and second dies being in the package and oriented so that they are either coplanar or non-coplanar.
  • inventions include a substrate, a package, a third die, and charge-transfer capacitors.
  • the charge-transfer capacitors are integrated into the third die, the substrate supports the package, the package includes the first die, the second die, and the third die, and the first, second, and third dies are distributed among different layers of the package.
  • the package comprises a first layer and a second layer.
  • the first and second dies are in the first layer and the third die is in the second layer.
  • the package comprises a first layer and a second layer.
  • the first and third dies are in the first layer and the second die is in the second layer.
  • the package comprises a first layer, a second layer, and a third layer.
  • each layer contains at most one die.
  • the second layer is between the first and third layers, and the third die is in the second layer.
  • Some embodiments include a substrate that supports a package.
  • the package has an upper layer and a lower layer, with the lower layer being closer to the substrate than the upper layer.
  • the lower layer contains a die and the upper layer contains charge-transfer capacitors.
  • the inductor is on the substrate outside the package. Among these are embodiments in which the die's device face faces the substrate.
  • the apparatus further includes first and second interconnect layers, and electrically conducting bumps.
  • the first interconnect layer connects the charge-transfer capacitors to the die, and the second interconnect layer connects the die to the charge-transfer capacitors and to the electrical bumps.
  • the electrical bumps connect the package with the inductor.
  • a device face of the die faces away from the substrate.
  • These embodiments include a heat sink, thermally-conducting bumps, a first interconnect layer, a second interconnect layer, and electrically-conducting bumps.
  • the first interconnect layer connects the charge-transfer capacitors to the die.
  • the second interconnect layer connects the die to the charge-transfer capacitors and to the electrically-conducting bumps.
  • the electrically-conducting bumps connect the package with the inductor.
  • the heat sink faces the substrate, and the thermally-conducting bumps connect the heat sink to the substrate. These thermally-conducting bumps carry only heat. They are electrically disconnected from the circuit.
  • a first interconnect layer connects charge-transfer capacitors to the die
  • a second interconnect layer connects the die to the charge-transfer capacitors and to electrically conducting pads.
  • the electrically conducting pads connect the package with the inductor.
  • the thermally-conducting pad connects the heat sink, which faces the substrate, to the substrate. This thermally-conducting pad carries only heat. It is electrically isolated from the inductor, the charge-transfer capacitor, and the die.
  • inventions also include a substrate that supports a package having upper and lower layers, with the lower layer being closer to the substrate that the upper layer.
  • the inductor is in the package.
  • the lower layer contains a die and upper layer contains charge- transfer capacitors are in the upper layer.
  • the inductor is disposed in the upper layer.
  • conductive traces around an inductor core in the layer form the inductor.
  • thermally-conducting bumps connect a heat sink to the substrate. These thermally-conducting bumps only carry heat. They are electrically isolated from the die, the charge-transfer capacitors, and the inductor.
  • Yet other embodiments include regulator switches in the first die.
  • FIG. 1 shows a power converter with a separable transformation stage and regulation stage
  • FIG. 2 shows a power converter similar to that shown in FIG. 1 but with an isolated transformation stage
  • FIGS. 3 to 10 show different ways of connecting transformation and regulation stages
  • FIG. 1 1 shows a DC-DC converter with a separate regulating circuit and switching network
  • FIG. 12 shows a power converter with a filter between the switching network and the regulation stage
  • FIG. 13 shows the power converter of FIG. 12 but without the regulation stage
  • FIG. 14 explicitly shows control circuitry associated with a converter as shown in FIG. 11 ;
  • FIG. 15 shows details of the control circuitry shown in FIG. 14;
  • FIG. 16 shows signals present during operation of the control circuitry of FIG. 15;
  • FIG. 17 is a close-up of four signals from FIG. 12 showing the dead-time interval
  • FIG. 18 shows details of switch layout in a converter similar to that shown in FIG. 1 ;
  • FIGS. 19 and 20 show dependence of switching period and peak-to-peak ripple as a function of output load current in two embodiments of the control circuitry as shown in FIG. 14;
  • FIG. 21 shows a multi-phase converter similar to that shown in FIG. 14;
  • FIGS. 22 and 23 show signals present during operation of the control circuitry of FIG. 21 ;
  • FIG. 24 shows another power converter similar to that shown in FIG. 14 but with one regulator and plural switching networks;
  • FIG. 25 shows another power converter similar to that shown in FIG. 14 but with one switching network and plural regulators;
  • FIG. 26 shows a power converter similar to that shown in FIG. 25 but with a filter between the switching network and the regulators;
  • FIG. 27 shows a power converter similar to that shown in FIG. 24 but with a filter between the switching networks and the regulator;
  • FIG. 28 shows a bidirectional version of FIG. 1 1 ; T/US2017/031726
  • FIGS. 29-30 show DC-DC converters with alternate configurations of regulating circuits and switching networks
  • FIG. 31 shows a DC-DC converter like that shown in FIG. 30 with a controller
  • FIG. 32 shows another configuration of a DC-DC converter
  • FIG. 33 shows a particular implementation of the power converter illustrated in FIG. 32;
  • FIG. 34 shows an embodiment with multiple regulating circuits;
  • FIG. 35 shows an RC circuit
  • FIG 36 shows a model of a switched capacitor DC-DC converter
  • FIG. 37 shows an isolated variant of FIG. 36
  • FIG. 38 shows output resistance of a switched-capacitor network as a function of switching frequency
  • FIGS. 39-40 show a series-parallel SC converter operating in charge phase and discharge phase respectively;
  • FIG. 41 shows a series pumped symmetric cascade multiplier with diodes
  • FIG. 42 shows a parallel pumped symmetric cascade multiplier with diodes
  • FIG. 43 shows charge pump signals
  • FIG. 44 shows a two-phase symmetric series pumped cascade multiplier with switches
  • FIG. 45 shows a two-phase symmetric parallel pumped cascade multiplier with switches
  • FIG. 46 shows four cascade multipliers along with corresponding half-wave versions
  • FIG. 47 shows the circuit of FIG. 35 with an auxiliary converter used to reduce loss associated with charging a capacitor
  • FIG. 48 shows an implementation of the circuit of FIG. 47
  • FIG. 49 shows a cascade multiplier with clocked current sources
  • FIG. 50 shows output impedance of a switched-capacitor converter as a function of frequency
  • FIGS. 51 , 52, and 53 show clocked current sources
  • FIG. 54 shows a cascade multiplier with the clocked current source of FIG. 52;
  • FIG. 55 shows an embodiment of the circuit shown in FIG. 54
  • FIG. 56 shows current and voltage at selected locations in the circuit of FIG. 55;
  • FIG. 57 shows a particular implementation of the DC-DC converter illustrated in FIG. 28 with a full-wave adiabatically charged switching network
  • FIG. 58 shows the DC-DC converter illustrated in FIG. 54 during phase A
  • FIG. 59 shows the DC-DC converter illustrated in FIG. 54 during phase B;
  • FIG. 60 shows various waveforms associated with a 4: 1 adiabatically charged converter
  • FIG. 61 shows adiabatic charging of series connected stages
  • FIG. 62 shows a particular implementation of the power converter illustrated in FIG. 61 ;
  • FIG. 63 shows adiabatic charging of series connected stages with filters between each stage;
  • FIG. 64 shows a particular implementation of the power converter illustrated in FIG. 63;
  • FIG. 65 shows an AC-DC power converter architecture;
  • FIG. 66 shows an AC voltage rectified using a reconfigured switched-capacitor stage
  • FIG. 67 shows an embodiment of the AC-DC power converter architecture in FIG. 65, which includes an AC switching network
  • FIG. 68 shows a particular implementation of the AC-DC converter illustrated in FIG. 67;
  • FIGS. 69-70 shows the AC-DC converter in FIG. 68 during the positive and negative portions of the AC cycle respectively;
  • FIG. 71 shows an AC-DC power converter architecture with power-factor correction
  • FIG. 72 shows a converter having an isolated controller
  • FIG. 73 shows an alternative architecture of the converter in FIG. 72 where the switching network is loaded by an LC filter
  • FIG. 74 shows a converter in which a control signal for the regulating circuit is isolated from a control signal for the switching network
  • FIG. 75 shows a configuration of FIG. 29 with an isolated controller as shown in FIG. 74;
  • FIG. 76 shows a configuration of FIG. 32 with an isolated controller as shown in FIG. 74;
  • FIG. 77 shows an implementation of the rectifier shown in FIG. 65;
  • FIG. 78 shows an alternative implementation of the rectifier shown in FIG. 65;
  • FIG. 79 shows an EMI filter from the rectifiers shown in FIGS. 77 and 78;
  • FIG. 80 shows an alternative EMI filter from the rectifiers shown in FIGS. 77 and 78;
  • FIG. 81 shows an AC bridge for use in the embodiments shown in FIGS. 77 and 78;
  • FIG. 82 shows one transformation stage driving two parallel regulation stages
  • FIG. 83 shows a transformation stage providing filtered output to parallel regulating stages
  • FIGS. 84 and 85 show implementations of the DC-DC converter illustrated in FIG. 28;
  • FIGS. 86 and 87 show implementations of the DC-DC converter illustrated in FIG. 30;
  • FIGS. 88 and 89 show implementations of the DC-DC converter illustrated in FIG. 29;
  • FIGS. 90 and 91 show implementations of the DC-DC converter illustrated in FIG. 32;
  • FIG. 92 shows a switching network implemented as a stack of layers
  • FIGS. 93-96 are cross-sections of the stack in FIG. 92 with different orders of passive and active layers;
  • FIGS. 97-100 show different locations of active and passive device faces for the two-layer stack shown in FIG. 93;
  • FIGS. 101-104 show different locations of active and passive device faces for the two-layer stack shown in FIG.94;
  • FIG. 105 shows an implementation of FIG. 93 in which the passive device layer has a planar capacitor
  • FIG. 106 shows an implementation of FIG. 93 in which the passive device layer has a trench capacitor
  • FIG. 107 shows an implementation of FIG. 105 with wafer-to-wafer bonding instead of die- to-die bonding;
  • FIG. 108 shows an implementation of FIG. 107 but with the device face of the active layer being its upper face instead of its lower face;
  • FIG. 109 shows three partitioned current paths of a switching network
  • FIG. 1 10 shows an active layer with eight switches superimposed on eight capacitors on a passive layer below it;
  • FIG. 111 shows one of the switches in FIG. 1 10 that has been partitioned into nine partitions;
  • FIG. 112 shows a divided switching but not partitioned switch and capacitor;
  • FIG. 113 shows a partitioned switch and capacitor
  • FIG. 114 shows a capacitor partitioned in two dimensions
  • FIG. 115 is a functional block diagram of one embodiment of the switching network shown in FIGS. 13 and 12;
  • FIG. 116 shows an exemplary circuit of the switching network shown in FIG. 115;
  • FIG. 117 shows a particular terminal layout for implementation of the switching network shown in FIG. 115;
  • FIG. 118 is a functional block diagram of another embodiment of the switching network shown in FIGS. 13 and 12;
  • FIG. 119 shows an exemplary circuit of the switching network shown in FIG. 118;
  • FIG. 120 shows a particular terminal layout for implementation of the switching network shown in FIG. 1 18;
  • FIG. 121 shows the terminal layout for the phase-die in FIG. 120 with the locations of the phase switches in FIG. 119 explicitly shown therein;
  • FIG. 122 is a functional block diagram of another embodiment of the switching network shown in FIGS. 13 and 12, but the inclusion of switches for a regulator to which the switching network is to be connected;
  • FIG. 123 shows a substrate bearing components for implementing a switching network
  • FIG. 124 shows the phase die and stack die of FIG. 123 within the same package
  • FIG. 125 shows a stacked phase die and stack die
  • FIG. 126 shows the circuit of FIG. 124 but with the charge-transfer capacitors now being on their own capacitor die and included on their own layer in the package.
  • FIG. 127 shows the circuit of FIG. 124 but with the charge-transfer capacitors now being on their own capacitor die, included in the package, and occupying the same layer as the phase die.
  • FIG. 128 shows a package in which the charge-transfer capacitor die is sandwiched between the phase die and the stack die
  • FIGS. 129-133 show embodiments of a circuit that also includes an inductor.
  • Some power converters carry out both regulation and transformation with a limited number of circuit components by comingling these functions into a single stage. As a result, certain components are used both for regulation and transformation.
  • the regulation stage is referred to as a regulating circuit and the transformation stage is referred to as a switching network. As used herein, these terms mean the same thing.
  • FIG. 1 shows a modular multi-stage power converter that separates the converter's transformation and regulation functions. These functions are no longer accomplished together as they would be in a single-stage converter design. As a result, in a multi-stage power converter, as shown in FIG. 1 , it is possible to optimize a transformation stage and a regulation stage for their specific functions.
  • the transformation stage and the regulation stage can be treated as either independent entities or coupled entities.
  • a transformation stage receives an input voltage Vm across its two input terminals and outputs an intermediate voltage V x across its two output terminals at a fixed voltage conversion ratio. Therefore, the intermediate voltage ⁇ changes in response to changes in the input voltage V !N .
  • the transformation stage is thus regarded as “variable” if the voltage conversion ratio can be varied. However, it is not required that a transformation stage be "variable”.
  • FIG. 37 An example of such a transformation stage is shown in FIG. 37 with a voltage conversion ratio of Ni :N 2 .
  • two functional components of a circuit or system are said to be isolated, in a galvanic sense, if no direct conduction path exists between those two components, and yet energy and information can still be communicated between those components. The communication of such energy and information can be carried out in a variety of ways that do not require actual current flow.
  • Electromagnetic waves in this context include waves in the visible range, as well as just outside the visible range.
  • Such communication can also be implemented via static or quasi-static electric or magnetic fields, capacitively, inductively, or by mechanical means.
  • Galvanic isolation is particularly useful for cases in which the two functional components have grounds that are at different potentials. Through galvanic isolation of components, it is possible to essentially foreclose the occurrence of ground loops. It is also possible to reduce the likelihood that current will reach ground through an unintended path, such as through a person's body.
  • the transformation stage efficiently provides an intermediate voltage V x Xhat differs from the input voltage V m and that varies over a much smaller range than the input voltage V/N.
  • the intermediate voltage Vx varies during operation if there are changes at either the input or output of the transformation stage. These variations require correction to achieve the desired output voltage V 0 . It is for this reason that a regulation stage is necessary.
  • a regulation stage receives the intermediate voltage V x across its input terminals and provides a regulated voltage V 0 across its output terminals.
  • the architecture shown in FIG. 1 is flexible enough to permit designs with different requirements. For example, if magnetic isolation is required, a magnetic isolated fly-back converter can be used. Designs that require multiple regulated output voltages can be accomplished by using two separate regulation stages and a single transformation stage.
  • the architecture shown in FIG. 1 in effect creates a modular architecture for power converters in which fundamental building blocks can be mixed and matched in a variety of ways to achieve particular goals.
  • FIGS. 3-10 are block diagrams showing different ways to arrange the transformation stage and the regulation stage relative to a source or a load.
  • the fact that these can even be represented as block diagrams at all stems from the modularity of the architecture.
  • Such modularity is not present in a conventional single-stage converter. In such a converter, the functions of regulation and transformation are so intimately comingled that it is not possible to extract two separate circuits and to say that one carries out regulation and the other carries 1726
  • FIG. 3 shows a generic architecture in which a pair of transformation stages sandwiches a regulation stage.
  • Each transformation stage includes one or more switched- capacitor networks.
  • each regulation stage includes one or more regulating circuits. It is also possible to have more than one source and more than one load.
  • the double-headed arrows in FIG. 3 and in other figures indicate bidirectional power flow.
  • FIG. 4 shows a source-regulating configuration in which power flows from a source to a transformation stage.
  • the transformation stage then provides the power to a regulation stage, which then passes it to a load.
  • the load ultimately receives power from the regulation stage.
  • FIG. 5 shows a load-regulating configuration.
  • a load-regulating configuration power flows from a source to a regulation stage, which then regulates it and passes it to a transformation stage.
  • the load receives power directly from the transformation stage instead of directly from the regulation stage.
  • FIG. 6 shows a reverse source-regulating configuration similar to that shown in FIG. 4, but with power flowing in the opposite direction.
  • FIG. 7 shows a reverse load-regulating configuration similar to that shown FIG. 5, but with power flowing in the other direction.
  • FIGS. 8 and 9 two transformation stages bracket a regulation stage. These are distinguished by direction of current flow.
  • FIG. 8 shows a source/load-regulating configuration in which power flows from the source to the load via a first transformation stage, a regulation stage, and a second transformation stage
  • FIG. 9 shows a reverse source/load-regulating configuration in which power flows from the load to the source via a first transformation stage, a regulation stage, and a second transformation stage.
  • FIG. 10 In another embodiment, shown in FIG. 10, several regulating circuits rely on the same switched-capacitor converter. Note that of the three power paths, a first and second power path are in the load-regulating configuration whereas the third power path is in the source/load-regulating configuration. An embodiment having several regulating circuits is particularly useful since it enables different output voltages to be provided to different loads.
  • FIG. 1 1 shows a power converter 10 assembled by combining two modules using the principles suggested by FIG. 1.
  • the illustrated power converter 10 includes a switching network 12A, a voltage source 14, a regulating circuit 16A, and an inter-module link 11 A that connects an output of the switching network 12A to an input of the regulating circuit 16A.
  • a load 18 A connects to an output of the regulating circuit 16A. Power flows between the voltage source 14 and the load 18A in the direction indicated by the arrows. To simplify representation, the separation of the connection into positive and negative lines has been omitted.
  • the regulating circuit 16A can be at some distance from the switching network 12A. In such cases, it is useful to include a filter at the output of the switching network 12A.
  • FIG. 12 shows a power converter 10 that, like the embodiment shown in FIG. 11, has a voltage source 14 that provides a first voltage V] to a switching network 12A.
  • the switching network 12A provides a second voltage V2 to an inductance Lj .
  • the inductance Li and the capacitance Ci together define an LC filter that outputs a third voltage Vj that ultimately makes its way to the regulating circuit 16A shown in FIG. 1 1.
  • the regulating circuit 16A adjusts the unregulated third voltage V 3 to yield a regulated fourth voltage V 4 , which it then provides to the load 18A.
  • FIG. 13 An alternative embodiment, shown in FIG. 13, connects the third voltage V 3 directly to the load 18A.
  • the filter formed by the combination of the capacitor C) and inductor Li regulates the third voltage V 3 without the need for a regulating circuit 16A.
  • the various configurations shown above have switches that need to be opened and closed at certain times. Thus, they all implicitly require one or more controllers to provide control signals that open and close these switches. The structure and operation of such a controller 20 A is described in connection with FIGS. 14-23.
  • FIG. 14 shows the power converter 10 of FIG. 1 1, but with a controller 20A explicitly shown.
  • the controller 20A features three sensor inputs: an intermediate-voltage input for an intermediate voltage V x , an output-voltage input for the output voltage Vo, and an optional input-voltage input for the input voltage V !N .
  • the controller 20A has two other inputs: a clock input to receive a clock signal CLK and a reference input to receive a reference voltage VREF. Examples of the various signals above, as well as others to be described below, can be seen in FIG. 16.
  • the controller 20A Based on the aforementioned inputs, the controller 20A provides a first control signal ⁇ to control switches in the switched-capacitor element 12A and a second control signal PWM to control switching of the regulating circuit 16A.
  • the first control signal is a two- dimensional vector having first and second complementary phases ⁇ , ⁇ . In some embodiments, the first control signal is a vector having higher dimensionality.
  • the second control signal PWM is a scalar. However, in multi-phase embodiments described below, the second control signal PWM is also a vector.
  • the controller 20A relies on the clock signal CLK and the intermediate voltage V x to set the period of the second control signal PWM for controlling the regulating circuit 16A.
  • a comparison between the reference voltage VREF and the output voltage Vo provides a basis for controlling the output voltage Vo.
  • the controller 20A synchronizes operation of the switching network 12A and the regulating circuit 16A. It does so by synchronizing a ripple on the intermediate voltage Vx with the second control signal PWM. Such synchronization relaxes the requirement of running the regulation circuit 16A at a significantly higher frequency than the switching network 12A in an attempt to achieve effective feed-forward control.
  • the control method described herein also avoids glitches inherent in changing the switching frequency of the switching network 12A. It does so by making use of a regulating circuit 16A that draws discontinuous input current.
  • a regulating circuit 16A is one that uses a buck converter.
  • the controller 20A has a switched-capacitor section 301 and a regulator section 302. These can be on the same die or on different dies.
  • the switched-capacitor section 301 outputs the first control signal ⁇ .
  • the complementary first and second phases ⁇ , ⁇ that make up the first control signal are shown as the last two traces in FIG. 16.
  • the switched-capacitor section 301 has an undershoot limiter 36 that receives the input voltage V IN and the intermediate voltage Vx. Based on these, the undershoot limiter 36 determines a trigger level V X L .
  • the trigger level V X L is shown as a dashed horizontal line superimposed on the sixth trace on FIG. 16.
  • the switched capacitor section 301 ultimately uses this trigger level VX_L to determine when it is time to generate the first control signal ⁇ . The details of how this is done are described below.
  • the undershoot limiter 36 After having generated the trigger level V X L based on the input voltage V !N and the intermediate voltage V x , the undershoot limiter 36 provides it to a first comparator 35.
  • the first comparator 35 then compares the trigger level V X L with the intermediate signal Vx. Based on the comparison, the first comparator 35 provides a first trigger signal to a first control signal generator 34, which ultimately outputs the first control signal ⁇ .
  • the switched capacitor section 301 thus forms a first feedback loop that manipulates the first control signal ⁇ in an effort to control the intermediate voltage Vx based on the combination of the intermediate voltage V x md the input voltage VIM.
  • the first control signal generator 34 does not generate the first control signal ⁇ immediately. Instead, the first control signal generator 34 waits for an opportune moment to do so. The occurrence of this opportune moment depends on what the regulator section 302 is doing.
  • the regulator section 302 While the switched capacitor section 301 is busy providing the first trigger signal to the first control signal generator 34, the regulator section 302 is also busy generating the second control signal PWM.
  • the regulator section 302 begins this process with a voltage compensator 31 that receives a voltage output Vo and a reference voltage VREF- From these, the voltage compensator 31 generates an error voltage VERR.
  • the voltage compensator 31 includes linear voltage-mode control and peak current-mode control. However, other modes are possible. Assuming linear voltage-mode control for the regulation circuit 16A, the voltage compensator 31 compares the output voltage V 0 of the power converter 10 with a reference voltage VREF and provides an error signal VERR to a second comparator 32. This error signal V E RR is shown in FIG. 16 superimposed on a serrated waveform VSAW on the second trace shown in FIG. 16.
  • the regulator section 302 thus forms a second feedback loop that manipulates the second control signal PWM in an effort to control the output voltage V 0 based on the combination of a reference signal VREF and the output voltage V 0 .
  • the switched capacitor section 301 and the regulator section 302 do not operate independently. Instead, the controller 20A synchronizes their operation.
  • the regulator section 302 includes a saw- tooth generator 30.
  • the saw-tooth generator 30 generates the serrated waveform V SAW based on a clock signal CLK and the intermediate voltage V x .
  • This serrated waveform VSAW ultimately provides a way to synchronize the first control signal ⁇ and the second control signal PWM.
  • the second comparator 32 compares the error voltage V E RR with the serrated waveform VSAW and outputs a second trigger signal based on this comparison.
  • the second control signal PWM changes state in response to a change in the sign of the difference between the error voltage V ERR and the serrated waveform VSAW- Since the serrated waveform VSAW is ultimately based on the intermediate voltage V x , this provides a basis for synchronizing the operation of the switched-capacitor section 301 and the regulator section 302.
  • the second control signal generator 33 receives the second trigger signal from the second comparator 32 and uses it as a basis for generating the second control signal PWM.
  • This second control signal PWM ultimately serves as a gate drive to actually drive the gate of a transistor that implements a main switch 152 in a regulating circuit 16A, details of which are seen in FIG. 18.
  • This main switch 152 ultimately controls an inductor voltage V L and an inductor current h across and through an inductor 154 within the regulating circuit 16A, as shown by the fourth and fifth traces in FIG. 16.
  • the switched-capacitor section 301 implements a hysteretic control system in which a controlled variable, namely the intermediate voltage Vx, switches abruptly between two states based upon a hysteresis band.
  • the intermediate voltage Vx is a piecewise linear
  • Synchronization between the regulator section 302 and the switched capacitor section 301 is important to enable the dead-time interval of the switching network 12A to occur when no current is being drawn by the regulating circuit 16A.
  • the first control signal ⁇ will actually cycle through three states, not just two. In the first state, the first control signal ⁇ opens a first set of switches and closes a second set of switches. In the second state, the first control signal ⁇ closes the first set of switches and opens the second set of switches.
  • the first control signal ⁇ cycles through a third state, which lasts for a dead-time interval DT. During this third state, all switches open. This minimizes the unpleasant possibility that a switch in the second set will not have opened by the time the switches in the first set have closed.
  • certain regulating circuits 16A such as buck converters and the like, draw input current discontinuously.
  • such regulating circuits 16A have short intervals during which they are drawing zero current.
  • the controller 20A avoids glitches by synchronizing the operation of the switching network 12A and the regulating circuit 16A such that the regulating circuit 16A draws zero current during the dead-time interval DT.
  • a further benefit of such synchronization is the ability to cause switches in the switching network 12A to change state when there is no current flowing through them. This reduces commutation losses. Causing the dead-time interval DT to occur when the regulating circuit 16A is not drawing current, and causing switches in the switching network 12 A to only change state at the beginning and the end of the dead-time interval 7 " thus ensures zero- current switching, as shown in FIG. 17.
  • the regulator section 302 and the switched capacitor section 301 cooperate to ensure that the length of one cycle of the first control signal ⁇ will be equal to an integral number of cycles of the second control signal PWM.
  • this constraint is met because the one cycle of the first control signal ⁇ is equal to an integral number of cycles of the second control signal PWM.
  • the first control signal generator 34 receives a first trigger signal from the first comparator 35 indicating that the intermediate voltage V x has fallen below the trigger level V X L . However, as alluded to above, the first control signal generator 34 does not act immediately. Instead, it waits until there is an opportune time to make a state change.
  • the intermediate voltage will already have fallen to an undershoot A V d below the trigger level V X _L-
  • the undershoot A V d is small and capped by an undershoot cap of ViAV x , which only occurs when the switching frequency of the regulator section 302 and the switched capacitor section 301 are equal. This undershoot cap depends on load current and input voltage V m .
  • the undershoot limiter 36 selects a suitable trigger level V X L to limit this undershoot ⁇ V d by indirectly controlling the undershoot cap ⁇ ⁇ ⁇ .
  • the undershoot limiter 36 uses the intermediate voltage V x and the input voltage Vm to select an appropriate value of the trigger level V X _ L .
  • FIG. 1 7 shows a close up of selected waveforms in FIG. 16 at a scale that is actually large enough to show a dead-time interval DT between the two phases ⁇ , ⁇ that make up the first control signal ⁇ .
  • FIG. 18 it is useful to consider the circuit shown in FIG. 18, which was introduced earlier in a discussion of the function of the second control signal PWM.
  • FIG. 18 shows a first set of switches 141, 143, 146, 148, which is controlled by the first phase ⁇ , and a second set of switches 142, 144, 145, 147, which is controlled by the second phase ⁇ .
  • FIG. 18 also shows the main switch 152 that connects the regulating circuit 16A to the switching network 12A.
  • the main switch 152 has already been discussed above.
  • the dead-time DT places a limit on the maximum possible duty cycle D max . It is therefore desirable to reduce the dead-time DT as much as possible to increase the range of possible transformation ratios for the regulating circuit 16A.
  • the control strategy as described above and implemented by the controller 20A in FIG. 15 is one of many possible implementations.
  • the switching frequency for switches 141, 143, 146, 148, 142, 144, 145, 147 in the switching network 12A will change in discrete steps as the load current of the power converter 10 varies.
  • FIG. 19 shows how the output current affects both the period with which the switches 141, 143, 146, 148, 142, 144, 145, 147 of the switching network 12A change state and the corresponding A Vx ripple.
  • the ripple magnitude A ⁇ varies as a function of load current.
  • the ripple magnitude ⁇ V x defines a serrated waveform having a peak-to-peak amplitude that decreases with load current. As the load current approaches zero, the peak-to-peak amplitude approaches half of the maximum peak-to-peak amplitude.
  • the A V X ripple it is also possible to get the A V X ripple to approach the maximum peak-to-peak amplitude as the load current approaches zero, as shown in FIG. 20.
  • the switching period for the switches 141, 143, 146, 148, 142, 144, 145, 147 stays the same for a range of output currents.
  • the converter relies on the regulating circuit 16A to make up the difference between the voltage that the switching network 12A provides whatever voltage is required. At some point, the regulating circuit 16A can no longer make the necessary correction. At that point, the period takes a step down.
  • the controller 20A shown in FIG. 14 is a single-phase converter.
  • the first control signal is a two-dimensional vector and the second control signal PWM is a scalar.
  • the first control signal ⁇ is a 2N-dimensional vector and the second control signal PWM is an N-dimensional vector having components PW i, PWM 2 , .... PWM confine that are phase shifted relative to each other.
  • the phase shift between these components is 360/N degrees.
  • FIG. 21 shows an example of an N-phase converter having plural regulation circuits 16A, 16B.
  • Each regulation circuit 16A, 16B has a corresponding switching network 12A, 12B.
  • Each regulation circuit 16A, 16B is also driven by its own control signal, hence the need for an N-dimensional second control signal PWM.
  • Each switching network 12A, 12B is driven by a pair of phases, hence the need for a 2N-dimensional first control signal.
  • An N-phase controller 20A controls the N-phase converter.
  • the N-phase controller 20A is similar to the single-phase controller in FIG. 14 but with additional inputs for the N intermediate voltages V X i, V X 2, .... V ⁇ .
  • FIG. 22 shows waveforms similar to those shown in FIG. 16 but for a three-phase version of the controller shown in FIG. 14.
  • the second control signal PWM consists of second control signal elements PWMi, PWM 2 , PWM 3 that are separated from each other by a delay time that corresponds to a 120° phase shift between them.
  • the three intermediate voltages V X] , V X2 , V x3 are shifted from each other by an integer multiple of this delay time.
  • the integer is unity.
  • other integers are possible.
  • FIG. 23 shows an alternative method of operation similar to that shown in FIG. 22, but with the intermediate voltages V X V x2 , V X3 having been shifted by a larger multiple of the delay time. This results in a more significant phase shift between the intermediate voltages V X1 , V x2 , V X3 , a result of which is a reduced ripple in the output voltage V 0 .
  • a multi-phase controller 20A for controlling the N-phase converter shown in FIG. 21 can be thought of as N single-phase controllers 20A as shown in FIG. 15 operating in parallel but with a specific phase relationship between them.
  • a multi-phase controller 20A would thus look very similar to the one in FIG. 15, but with an additional input and output signals.
  • the intermediate voltages (V X i, V x2 , ... )3 ⁇ 4) and the output voltage Vo are required for proper operation of the controller 20A.
  • FIG. 24 shows a converter similar to that shown in FIG. 21 , but having only one regulation circuit 16A that is connected to plural switching networks 12A, 12B. Since there is only one regulation circuit 16A, only a 1 -dimensional second control signal PWM is required. Each switching network 12A, 12B is driven by a pair of phases, hence the need for a 2N- dimensional first control signal.
  • FIG. 25 shows a converter that is essentially the converse of FIG. 24.
  • the converter has plural regulation circuits 16A, 16B, all of which are coupled to the same switching network 12A.
  • Each regulation circuit 16A, 16B is driven by its own control signal, hence the need for an N-dimensional second control signal PWM.
  • the sole switching network 12A is driven by a pair of phases, hence the need for a 2-dimensional first control signal.
  • FIG. 26 shows a converter similar to that shown in FIG. 25, but with an inductance Li connected to both the output of the switching network 12A and to the inputs of the regulating circuits 16A,16B.
  • a grounded capacitor Q provides a place to store excess charge during operation.
  • the N-phase controller 20A observes both a switching-network's output voltage ⁇ and a regulating circuits' input voltage V x .
  • FIG. 27 shows a converter similar to that shown in FIG. 24 but with an inductance Li..L N connected to the outputs of each of the switching networks 12A, 12B and to the input of the regulating circuit 16A.
  • a grounded capacitor Ci provides a place to store excess charge during operation.
  • the N-phase controller 20A uses the switching-networks' output voltages Vyi ... V m and the regulating circuit's input voltage Vx to generate suitable control signals.
  • a non-capacitive regulating circuit 16A loads down the switching network 12A.
  • This regulating circuit 16A is switched at a high frequency.
  • the components from the high-frequency switching of the regulating circuit 16A are ultimately superimposed on the lower frequency serrated waveform of the intermediate voltage V x , as shown in sixth trace on FIG. 16.
  • the duty cycle of the saw-tooth approximation waveform depends on the topology of the switching network 12A.
  • the frequency of the complementary switching- network control signals varies with changes in response to changes in the slope of the intermediate signal. These changes, in turn, arise as a result of changes in the power converter's operating point.
  • the switching network 12A and the regulating circuit 16A are essentially modular and can be mixed and matched in a variety of different ways. As such, the configuration shown in FIG. 11 represents only one of multiple ways to configure one or more switching networks 12A with one or more regulating circuits 16A to form a multi-stage converter 10.
  • FIG. 28 shows a bidirectional version of FIG.11 in which power can flow either from a voltage source 14 to a load 18A or from the load 18A to the voltage source 14 as indicated by the arrows.
  • switching networks 12A and regulating circuits 16A There are two fundamental elements described in connection with the following embodiments: switching networks 12A and regulating circuits 16A. Assuming series connected elements of the same type are combined, there are a total of four basic building blocks. These are shown FIGS. 28, 29, 30, and 32.
  • the power converters disclosed herein include at least one of the four basic building blocks. More complex converter can be realized by combining the fundamental building blocks.
  • the first building block features a switching network 12A whose output connects to an input of a regulating circuit 16A.
  • the second building block shown in FIG. 29, features a first switching network 12A whose output connects to a regulating circuit 16A via a first intermodule link 11A, an output of which connects to an input of a second switching network 12B via a second intermodule link 11B.
  • an output of a regulating circuit 16A connects to an input of a switching network 12A via an intermodule link 11B.
  • a fourth building block shown in FIG. 33, features a first regulating circuit 300A having an output that connects to an input of a first switching network 200, an output of which connects to an input of a second regulating circuit 300B.
  • Additional embodiments further contemplate the application of object-oriented programming concepts to the design of power converters by enabling switching networks 12A and regulating circuits 16A to be "instantiated" in a variety of different ways so long as their inputs and outputs continue to match in a way that facilitates modular assembly of power converters having various properties.
  • the switching network 12A in many embodiments is instantiated as a switched- capacitor network.
  • switched capacitor topologies are: Ladder, Dickson, Series-Parallel, Fibonacci, and Doubler, all of which can be adiabatically charged and configured into multi-phase networks.
  • a particularly useful switching capacitor network is an adiabatically charged version of a full-wave cascade multiplier. However, diabatically charged versions can also be used.
  • changing the charge on a capacitor "adiabatically” means causing an amount of charge stored in that capacitor to change by passing the charge through a non- papacitive element.
  • a positive adiabatic change in charge on the capacitor is considered adiabatic charging while a negative adiabatic change in charge on the capacitor is considered adiabatic discharging.
  • non-capacitive elements include inductors, magnetic elements, resistors, and combinations thereof.
  • a capacitor can be charged adiabatically for part of the time and diabatically for the rest of the time. Such capacitors are considered to be adiabatically charged. Similarly, in some cases, a capacitor can be discharged adiabatically for part of the time and diabatically for the rest of the time. Such capacitors are considered to be adiabatically discharged.
  • Diabatic charging includes all charging that is not adiabatic and diabatic discharging includes all discharging that is not adiabatic.
  • an "adiabatically charged switching network” is a switching network having at least one capacitor that is both adiabatically charged and adiabatically discharged.
  • a “diabatically charged switching network” is a switching network that is not an adiabatically charged switching network.
  • the regulating circuit 16A can be instantiated as any converter with the ability to regulate the output voltage.
  • a buck converter for example, is an attractive candidate due to its high efficiency and speed.
  • Other suitable regulating circuits 16A include boost converters, buck/boost converters, fly-back converters, forward converters, half-bridge converters, full- bridge converters, Cuk converters, resonant converters, and linear regulators.
  • the fly-back converter can more specifically be a quasi -resonant fly-back converter, or an active-clamp fly-back converter, or an interleaved fly-back converter, or a two-switch fly-back converter.
  • the forward converter can be more specifically a multi-resonant forward converter, or an active-clamp forward converter, or an interleaved forward converter, or a two-switch forward converter.
  • the half-bridge converter can more specifically be an asymmetric half-bridge converter, or a multi-resonant half-bridge converter, or a LLC resonant half- bridge.
  • a source voltage 14 provides an input to a first switching network 12A, which is instantiated as a switching capacitor network.
  • the output of the first switching network 12A is a lower voltage than the input voltage that is provided to a regulating circuit 16A (e.g. a buck, a boost, or a buck/boost converter).
  • This regulating circuit 16A provides a regulated input voltage to a second switching network 12B, such as another switching capacitor network.
  • a high voltage output of this second switching network 12B is then applied to a load 18A.
  • An embodiment such as that shown in FIG. 28 can be configured to regulate the load 18A or to regulate the voltage source 14 depending on the direction of energy flow.
  • a low voltage source 14 connects to an input of a regulating circuit 16A, the output of which is provided to an input of a switching network 12A to be boosted to a higher DC value. The output of the switching network is then provided to a load 18A.
  • An embodiment such as that shown in FIG. 30 can be used to regulate the voltage source 14 or the load 18A depending on the direction of energy flow.
  • FIG. 31 shows the modular DC-DC converter IOC of FIG. 30, but with a controller 20A explicitly shown.
  • the controller 20A is similar to that described in connection with FIG. 15.
  • the controller 20A features three sensor inputs, one for an intermediate voltage V X , one for the output voltage V 0 , and an optional one for the input voltage, V IN .
  • the controller 20A also has two inputs that are not sensor inputs.
  • One non-sensor input receives a clock signal CLK and the other receives a reference voltage V RE F-
  • the clock signal CLK is used to set the period of a second control signal PWM and the reference voltage VREF is used to set the desired output voltage.
  • the controller 20A Based on these inputs, the controller 20A outputs a first control signal having two phases to the switched-capacitor element 12A and a second control signal PWM to control switching of the regulating circuit 16A.
  • This second control signal PWM is a pulse-width modulated signal.
  • FIG. 32 another embodiment of a converter 100 includes a first regulating circuit 300A connected to a converter input 102 and a second regulating circuit 300B connected to a converter output 104. Between the first and second regulating circuits 300A, 300B is a switching network 200 having a switching network input 202 and a switching network output 204.
  • the switching network 200 includes charge storage elements 210 interconnected by switches 212. These charge storage elements 210 are divided into first and second groups 206, 208.
  • the switching network 200 is a bidirectional switching capacitor network such as that shown in FIG. 33.
  • the switching capacitor network in FIG. 33 features a first capacitor 20 and a second capacitor 22 in parallel.
  • a first switch 24 selectively connects one of the first and second capacitors 20, 22 to a first regulating circuit 300A
  • a second switch 26 selectively connects one of the first and second capacitors 20, 22 to the second regulating circuit 300B.
  • Both the first and second switches 24, 26 can be operated at high frequency, thus facilitating the adiabatic charging and discharging of the first and second capacitors 20, 22.
  • FIG. 33 has a two-phase switching network 200.
  • other types of switching networks can be used instead.
  • multiple regulating circuits 16A, 16B, 16C are provided at an output of a first switching network 12A for driving multiple loads 18A-18C.
  • a second switching network 12B is provided between the load 18C and the corresponding regulating circuit 16C thus creating a pathway similar to that shown in FIG. 30.
  • FIG. 34 thus provides an example of how the modular construction of regulating circuits and switching networks facilitates the ability to mix and match
  • a switched-capacitor power converter includes a network of switches and capacitors. By cycling the network through different topological states using these switches, one can transfer energy from an input to an output of the switched-capacitor network.
  • Some converters known as “charge pumps,” can be used to produce high voltages in flash and other reprogrammable memories.
  • FIG. 35 shows a capacitor C initially charged to some value Vc (0).
  • Vc (0) some value
  • the switch S is closed.
  • a brief surge of current flows as the capacitor C charges to its final value of Vi N .
  • v c (t) (0) + [V w - v c (0)]( ⁇ - e-' /RC ) and
  • the energy loss incurred while charging the capacitor can be found by calculating the energy dissipated by resistor R, which is
  • a switched-capacitor converter can be modeled as an ideal transformer, as shown in FIG. 36, with a finite output resistance R 0 that accounts for the power loss incurred in charging or discharging of the energy transfer capacitors, as shown in FIG. 36.
  • the embodiment shown in FIG. 36 is non-isolated because the negative terminals on both sides of the transformer are connected. However, this is by no means required.
  • FIG. 37 shows an embodiment in which the same terminals are not connected, in which case the converter is isolated.
  • transformer shown is only for modeling purpose.
  • a converter of this type would generally not have windings wrapped around an iron core.
  • the power losses associated with charging and discharging are typically dissipated in the ON resistance of the MOSFETs and equivalent series resistance of the capacitors.
  • the output voltage of the switched-capacitor converter is given by
  • R 0 is sensitive to the series resistance of the MOSFETs and capacitors, but is not a function of the operating frequency.
  • R 0 of the converter operating in the fast-switching limit is a function of parasitic resistance and R 0 is given by:
  • the calculations for R S SL and R FS L given above are based on the charge multiplier vector concept.
  • the vector a ] through a" can be obtained by inspection for any standard well posed w-phase converter.
  • the charge multiplier vectors are computed using constraints imposed by Kirchoff's current law in each topological state along with the steady-state constraint that the n charge multiplier quantities must sum to zero on each capacitor.
  • other losses such as switching losses, driver losses, and control losses can be calculated.
  • the switching loss is comparable to conduction loss.
  • W g is the gate capacitance loss
  • W on is the overlap or commutation loss
  • W ds is the output capacitance loss
  • the optimal switching frequency, capacitance, and device sizes must be selected. If the switching frequency is too low, then the conduction losses, P con d, dominate. On the other hand, if the switching frequency is too high, then P sw dominates. Although doing so tends to decrease output ripple, rarely will a switched-capacitor converter operate far above the transitional region between the slow switching limit and fast switching limit. After all, operating above this region tends to increase switching losses without lowering the output resistance to compensate for those increases switching losses. Thus, there is little to gain by operating above that region.
  • FIGS. 41 and 42 Another useful topology is that shown in FIGS. 41 and 42.
  • the source is located at V ⁇ and the load is located at V 2 .
  • packets of charge are pumped along a diode chain as the coupling capacitors are successively charged and discharged.
  • clock signals v clk and with amplitude v pump are 180 degrees out of phase.
  • the coupling capacitors can either be pumped in series or parallel.
  • V 2 for the converters in FIG. 42 is V ⁇ +(n- ⁇ )xv pump in both pumping configurations.
  • the foregoing topologies are suitable for stepping up voltage, they can also be used to step down voltage by switching the location of the source and the load.
  • the diodes can be replaced with controlled switches such as MOSFETs and BJTs.
  • FIGS. 41 and 42 show topologies that transfer charge during only one phase of the clock signal. Such topologies are referred to as "half-wave" topologies because charge transfer only occurs during half of a clock cycle. A disadvantage of a half-wave topology is a discontinuous input current.
  • topologies shown in FIGS. 41 and 42 It is possible to convert the topologies shown in FIGS. 41 and 42 so that they transfer charge during both phases of the clock signal. This can be carried out by connecting two such topologies in parallel and driving them 180 degrees out of phase. Such a topology is referred to herein as a "full-wave" topology because charge transfer occurs in both halves of the clock cycle.
  • FIG. 44 show a topology derived from that shown in FIG. 41 , but modified so that charge transfer occurs in both phases of the clock signal.
  • FIG. 45 show a topology derived from that shown in FIG. 42, but modified so that charge transfer occurs in both phases of the clock signals.
  • the topologies shown in FIGS. 44 and 45 use switches. Unlike diodes, which are inherently unidirectional, the switches shown in FIG. 44 and FIG. 45 are bidirectional. As a result, in the topologies shown in FIGS. 44 and 45, power can flow either from the terminal to the V 2 terminal or vice versa. As such, these topologies can be used to step-up a voltage or step- down a voltage.
  • asymmetric topologies half of the capacitors are used to support a DC voltage and not to transfer energy.
  • these embodiments do not require that each switch endure such a high peak voltage.
  • the peak voltage in the case in which only one switch chain is being pumped is only half of what it would be if both switch chains were actually being pumped.
  • the sole switch chain that is being used to transfer energy can be modified to transfer charge during both phases of the clock signal using principles set forth in connection with FIG. 44.
  • FIG. 46 shows eight exemplary topologies that use the principles set forth in connection with FIGS. 41 -45.
  • the first and second columns show half- wave topologies in both asymmetric and symmetric configurations, whereas the third and fourth columns show full-wave wave topologies in both asymmetric and symmetric configurations.
  • the topologies shown in FIG. 46 can be further modified to combineN phases in parallel and to run them 180 degrees/N out of phase. Doing so reduces output voltage ripple and increases output power handling capability.
  • the basic building blocks in the modular architecture shown FIGS. 28, 29, 30, and 32 can either be connected as independent entities or coupled entities.
  • switching networks and regulating circuits are tightly coupled, it is possible to prevent and/or reduce the systemic energy loss mechanism of the switching networks through adiabatic charging.
  • This generally includes using a regulating circuit to control the charging and discharging of the capacitors in the switching network.
  • the output voltage of the regulating circuit and thus the total converter can be regulated in response to external stimuli.
  • One approach to regulating the output voltage is by controlling the average DC current in the magnetic storage element.
  • the regulating circuit In general, it is desirable for the regulating circuit to operate in a way that limits the root mean square (RMS) current through the capacitors in the switching network.
  • the regulating circuit can do so using either resistive elements or magnetic storage elements. Because resistive elements consume power, magnetic storage elements are generally preferable for this purpose. Therefore, embodiments described herein rely on a combination of switches and a magnetic storage element in the regulating circuit to limit RMS current in the switching network. To limit RMS current, the regulating circuit forces the capacitor current through the magnetic storage element in a regulating circuit that has an average DC current. The switches in the regulating circuit then operate to maintain an average DC current through the magnetic storage element.
  • RMS root mean square
  • the regulating circuit may limit both the RMS charging current and the RMS discharging current of at least one capacitor in the switching network.
  • a single regulating circuit may limit the current into or out of the switching network by sinking and/or sourcing current. Therefore, there are four fundamental configurations, which are shown in FIGS. 28, 29, 30, and 32.
  • the regulating circuit 16A may sink both the charging and discharging current of the switching network 12 A.
  • the regulating circuit 16A may source both the charging and discharging current of the switching network 12B while also sinking both the charging and discharging current of the switching network 12 A. Furthermore, if both the switching networks and the regulating circuits allow power to flow in both directions, then bidirectional power flow is possible.
  • the regulating circuit 16A may source both the charging and discharging current of the switching network 12A.
  • the regulating circuit 300A may source the charging current of switching network 200 and the regulating circuit 300B may sink the discharging current of the same switching network 200 and vice-versa.
  • a fundamental difficulty that afflicts switched-capacitor networks is that the mere act of charging a capacitor incurs energy loss. This energy loss depends a great deal on how much the voltage across the capacitor changes as a result of the charging event.
  • the energy loss EL associated with using a fixed voltage source at a voltage Vto charge a capacitance C from zero to V is 1/2CT 2 . This loss does not depend on the parasitic series resistance R. Since this loss arises whenever voltage changes, every charging interval during operation incurs a loss equal to MICAV 2 , where AW corresponds to the difference between the initial and final value of the capacitor voltage.
  • a converter as described herein overcomes the foregoing disadvantage by providing more efficient use of the capacitors. This means that capacitors can be made smaller and/or that there will be an overall improvement in system efficiency. Although a converter as described herein does not require a reconfigurable switched-capacitor circuit, it may nevertheless take advantage of one as described above.
  • FIG. 47 illustrates a method for improving the charge-up efficiency of the capacitor C shown in FIG. 35 after switch S closes.
  • the regulating circuit 16A adiabatically charges the capacitor C.
  • the regulating circuit 16A is a switch-mode converter that supplies an output.
  • a suitable regulating circuit is a low-voltage magnetic based converter.
  • FIG. 47 thus permits more efficient use of capacitors than that shown in FIG. 35. This enables reduction in the required capacitor size and/or improvement in system efficiency when extended to switched-capacitor converters.
  • FIG. 48 illustrates one implementation of the foregoing embodiment in which a switching network 12A connects to regulating circuit 16A that serves as both a means to adiabatically charge/discharge the capacitors in the switching network 12A and regulate the output voltage V 0 .
  • the regulating circuit 16A need not be at a higher frequency than the switching network to promote adiabatic operation; it can even be at a lower frequency.
  • the regulating circuit 16A is a synchronous buck converter and the switching network 12A is a single-phase series-parallel converter.
  • the switching network 12A features first switches 1 that open and close together, second switches 2 that also open and close together, a first pump capacitor d, and a second pump capacitor c 2 .
  • the regulating circuit 16A includes a filter capacitor C x that serves only as a filter and bypass for the regulating circuit 16A. Consequently, the capacitance of the filter capacitor Cx should be much smaller than that of the first and second pump capacitors Ci and C 2 of the switching network 12A.
  • the switching network 12A alternates between being in a charging state and a discharging state. During the charging state, it charges the first and second pump capacitors Ci, C 2 . Then, during the discharging state, it discharges the first and second pump capacitors Ci, C ⁇ in parallel.
  • the first switches 1 close and the second switches 2 open.
  • the difference between the input voltage Vm, and the sum of the voltages across the first and second pump capacitors Ci, C 2 appears across the input terminal of the regulating circuit 16A.
  • the first and second pump capacitors Ci, C 2 charge with low loss, and at a rate determined by the power drawn from the regulating circuit 16A to control the system output.
  • the second switches 2 close and the first switches 1 open.
  • the switching network 12A then discharge in parallel at a rate based on the power needed to regulate the output.
  • Cascade multipliers are a preferred switching network because of their superior fast-switching limit impedance, ease of scaling up in voltage, their two-phase operation, and low switch stress.
  • the coupling capacitors are typically pumped with a clocked voltage source v clk & ⁇ .
  • the coupling capacitors are pumped with a clocked current source i cik & instead, as shown in FIG. 49, then the RMS charging and discharging current in the coupling capacitor may be limited.
  • the capacitors are at least partially charged adiabatically thus lowering, if not eliminating, the 1/2C A V c 2 loss that is associated with a switched-capacitor converter when operated in the slow-switching limit. This has the effect of lowering the output impedance to the fast-switching limit impedance.
  • the black dotted line in FIG. 50 which depicts adiabatic operation under full adiabatic charging, the output impedance would no longer be a function of switching frequency.
  • an adiabatically charged switched-capacitor converter can operate at a much lower switching frequency than a conventionally charged switched- capacitor converter, but at higher efficiency.
  • an adiabatically charged switched- capacitor converter can operate at the same frequency and with the same efficiency as a conventionally charged switched-capacitor converter, but with much smaller coupling capacitors, for example between four and ten times smaller.
  • Embodiments described herein can operate with two clocked current sources i cik , that operate 180 degrees out of phase, as shown in FIG. 51.
  • One implementation, shown in FIG. 52 uses one current source 72, a first switch pair 1 and a second switch pair 2.
  • the first and second switch pairs 1, 2 are best synchronized with a switch chain.
  • a suitable implementation of the current source in FIG. 52 is an inductance, represented in FIG. 53 by an inductor L.
  • FIG. 54 shows the cascade multiplier of FIG. 49 with the clocked current sources in FIG. 52.
  • FIG. 55 shows the cascade multiplier of FIG. 49 with the clocked current sources in FIG. 53.
  • the current source 72 There are numerous ways of implementing the current source 72. These include buck converters, boost converters, fly-back converter, resonant converters, and linear regulators.
  • a power converter having a constant input current implements the constant current source.
  • a power converter that has a constant input current for a portion of an interval defined by the reciprocal of its switching frequency implements the constant current source.
  • a linear regulator implements the constant current source.
  • the inductor L should limit the RMS current through the coupling capacitors (to provide adiabatic operation) while also providing a relatively constant output voltage Vo.
  • This can be achieved by having a large inductance and/or a capacitance (not shown) in parallel with the load 18A.
  • a large inductance consumes considerable area. And to make matters worse, the windings necessary for a large inductance will cause considerable resistive losses.
  • inductance of L in FIG. 55 it is desirable to choose an inductance that is small enough to avoid consuming excessive area and generating loss, but that is large enough to provide some assurance that the current I x will just graze the zero line without actually becoming negative.
  • a suitable value of inductance can be obtained by dividing the peak-to-peak value of the voltage V x by the product of the average value of the current ⁇ and the switching frequency. The result is then multiplied by a constant.
  • a suitable constant is 13/24.
  • FIG. 57 shows a step-down converter consistent with the architecture shown in FIG. 28.
  • a switching network 12A is adiabatically charged using a regulating circuit 16A.
  • the clocked current sources i clk & are emulated by Four switches and the regulating circuit 16A emulate the clocked current sources i ci fc, T ⁇ .
  • the output capacitor Co has also been removed so as to allow V x to swing.
  • the regulating circuit 16A is a boost converter that behaves as constant source with a small AC ripple. Any power converter that has a non-capacitive input impedance at the frequency of operation would have allowed adiabatic operation.
  • switch-mode power converters are attractive candidates due to their high efficiency, linear regulators are also practical.
  • closing switches labeled “1” charges capacitors C 4 , C 5 , and Ce while discharging capacitors d, C 2 , and C 3 .
  • closing switches "2" has the complementary effect.
  • the first topological state (phase A) is shown in FIG. 57, where all switches labeled “1” are closed and all switches labeled “2” are opened.
  • the second topological state (phase B) is shown in FIG. 58, where all switches labeled "2" are closed and all switches labeled "1” are opened.
  • the regulating circuit 16A limits the RMS charge and discharging current of each capacitor. For example, capacitor C3 is discharged through the filter inductor in the regulating circuit 16A during phase A, while capacitor C 3 is charged through the filter inductor in regulating circuit 16A during phase B, clearly demonstrating the adiabatic concept. Furthermore, all of the active components are implemented with switches so that the converter can process power in both directions.
  • FIG. 60 A few representative node voltages and currents are shown in FIG. 60. There is a slight amount of distortion on the rising and falling edges of the two illustrated currents (I P ⁇ and I P2 ), but for the most part, the currents resemble two clocks 180 degrees out of phase.
  • adiabatic charging occurs in cascade multipliers if at least one end of a switch stack is not loaded with a large capacitance, as is the case in this embodiment, where the V x node is loaded down by regulating circuit 16A.
  • the switches shown in FIG. 57 will transition between states at some switching frequency. It is desirable that, in order to reduce loss, the switching network 12A operate such that the RMS current through the switches is constrained at that switching frequency. One way to ensure that this is the case is to choose the resistances of the switches such that they are so large that the RC time constant of the charge transfer between the capacitors is similar if not longer than the switching frequency. As can be seen in FIG. 50, by controlling the width "W" of the switches and hence their resistance and their size, the switching network 12A can be forced into the fast-switching limit region.
  • the regulating circuit 16A allows us to reduce the resistance of the switches and operate adiabatically. Therefore, the switches can be optimally sized for the highest efficiency without worrying about constraining the RMS current since it is handled by the regulating circuit 16A (or optionally a magnetic filter).
  • the optimal size for each switch is chosen by balancing the resistive and capacitive losses in each switch at a given switching frequency and at a given current.
  • the modular architecture with the basic building blocks shown in FIGS. 11, 29, 30, and 32 may be expanded to cover a wider range of applications, such as high-voltage DC, AC-DC, AC-AC, buck-boost, and multiple output voltages. Each of these applications includes separating the transformation and regulation functions. Extension of the architecture can also incorporate adiabatically charged switched-capacitor converters.
  • Adiabatic charging of a preceding series-connected switching network only occurs if the following switching network controls the charging and discharging current of the preceding stage.
  • FIG. 62 shows a converter with two series-connected switching networks consistent with the architecture shown in FIG. 61.
  • FIG. 64 shows a similar architecture, but with filters between the series-connected switching networks in a manner consistent with the architecture shown in FIG. 63.
  • Both switching networks 12A, 12D are two-phase cascade multipliers.
  • switches labeled “1” and “2” are always in complementary states and switches labeled "7" and “8” are always in complementary states.
  • switches labeled "1” are open and all switches labeled "2" are closed.
  • In a second switched- state all switches labeled "1” are closed and all switches labeled "2" are opened.
  • closing switches 1 charges capacitors Q, Ci, C3, while discharging capacitors C 4 , Cs, C6 and closing switches 2 has the complementary effect.
  • closing switches 7 charges capacitors C 7 , C 8 , C 9 , while discharging capacitors Ci 0 , Cn, C12 and closing switches 8 has the complementary effect.
  • the power converter provides a total step-down of 32: 1 , assuming the regulating circuit 16A is a buck converter with a nominal step-down ratio of 2: 1. Furthermore, if the input voltage is 32 V and the output voltage is 1 V, then the switches in the first switching network 12A will need to block 8 volts while the switches in the second switching network 12D will need to block 2 volts.
  • the modular architecture with the basic building blocks shown in FIGS. 11 , 29, 30, and 32 may be configured to handle an AC input voltage as shown in FIG. 65.
  • An AC rectification stage 19A receives an AC waveform from an AC source 14B and provides an average DC voltage to a converter 10, the output of which is connected to a load 18A.
  • the converter 10 can be isolated or otherwise.
  • switched-capacitor converters One of the main attributes of switched-capacitor converters is their ability to operate efficiency over a large input range by reconfiguring the switched-capacitor network. If the AC wall voltage (i.e. 60 Hz & 120 VRMS) can be thought of as a slow-moving DC voltage, then a front-end AC switching network 13A should be able to unfold the time-varying input voltage into a relatively stable DC voltage.
  • AC wall voltage i.e. 60 Hz & 120 VRMS
  • a front-end AC switching network 13A should be able to unfold the time-varying input voltage into a relatively stable DC voltage.
  • FIG. 66 shows a diagram of a 120 V RMS AC waveform over a single 60 Hz cycle overlaid with the unfolded DC voltage.
  • FIG. 67 shows an AC switching network 13A of the sort that can incorporate the AC rectification stage 19A of FIG. 65.
  • the AC switching network 13A is a front-end switched-capacitor stage (i.e., switching network) in combination with a selective inverting stage (i.e., rectifying stage).
  • the front-end switched-capacitor stage has different configurations ( 1 /3, 1 /2, 1 /1 ) at its disposal.
  • the AC switching network 13A keeps the DC voltage under 60 V.
  • the AC switching network 13A is a special-purpose adiabatic switched- capacitor network.
  • a regulating circuit 16A shown in FIG. 67, produces a final output voltage.
  • another switching network 16A between the AC switching network 13A and the regulating circuit 16A further conditions the voltage. If this is the case, then the caveats for series-connected stages hold true since the AC switching network 13A is a special purpose switching network 12A.
  • Some form of magnetic or electric isolation is also common in AC-DC converters for safety reasons.
  • voltages: V A c, V D c > and V 0 are purposely defined as being agnostic to a common ground.
  • FIG. 68 shows an AC-DC converter corresponding to the architecture shown in FIG. 67.
  • the AC switching network 13A is a synchronous AC bridge rectifier followed by a reconfigurable two-phase step-down cascade multiplier with three distinct conversion ratios (1/3, 1/2, 1 /1 ) while the regulating circuit 16A is a synchronous buck converter.
  • switches labeled 7 and 8 are always in complementary states. During the positive portion of the AC cycle (0 to ⁇ radians) all switches labeled "7" are closed while all switches labeled "8" are opened as shown in FIG. 69. Similarly, during the negative portion of the AC cycle ( ⁇ to 2 ⁇ radians) all switches labeled 8 are closed while all switches labeled "7” are opened as shown in FIG. 70.
  • switches 1A- IE and switches 2A-2E may be selectively opened and closed as shown in Table 1 to provide three distinct conversion ratios of: 1/3, 1/2, and 1.
  • the AC switching network 13A is provided with a digital clock signal CLK.
  • a second signal CLKB is also generated, which may simply be the complement of CLK (i.e. is high when CLK is low and low when CLK is high), or which may be generated as a non- overlapping complement.
  • the AC switching network 13A provides a step-down ratio of one-third (1/3).
  • the AC switching network 13A provides a step-down ratio of one-half (1/2).
  • the AC switching network 13 A provides a step- down ratio of one.
  • FIG. 71 shows an AC-DC converter 8 that controls harmonic current and boosts power factor towards unity.
  • the illustrated AC- DC converter 8 features an AC switching network 13A that receives an AC voltage from an AC source 14B and rectifies it.
  • An output of the AC switching network 13A connects to an input of an active power-factor correction circuit 17A.
  • the AC switching network 13A may also provide voltage transformation via a switched-capacitor circuit.
  • the power-factor correction circuit 21A controls its input current so that it remains, to the greatest extent possible, in-phase with the voltage waveform provided by the AC source 14B. This drives reactive power toward zero.
  • the output of the power-factor correction circuit 17A is then provided to a regulating circuit 16A that operates in the same way as shown in FIG. 67.
  • FIG. 72 shows a particular embodiment of FIG. 65 's modular power converter 10 connected between first and second circuits 51, 52.
  • the first and second circuits 51, 52 can be a source, a load, or another circuit, such as a power converter, a PFC circuit, or an EMI filter.
  • the illustrated power converter 10 includes a regulating circuit 16A, a switching network 12A, and an isolated controller 60.
  • a circuit having an input and an output is considered isolated if the input voltage and the output voltage do not share a common ground. Such isolation can be carried out by having the input voltage correspond to an input voltage of a transformer and having the output voltage corresponds to an output voltage of a transformer.
  • the regulating circuit 16A is isolated.
  • the switching network 12A that is isolated. Although only one of the foregoing is needed to consider the modular DC-DC converter 10 as a whole isolated, there are also embodiments in which both the switching network 12A and the regulating circuit 16A are isolated.
  • the switching network 12A is an unregulated switched- capacitor converter having a fixed voltage-conversion ratio.
  • These embodiments generally include a regulating circuit 16A to regulate the output of the switching network 12 A.
  • Examples of a suitable regulating circuit 16A include a boost converter, a buck converter, a fly-back converter, and a linear regulator.
  • FIG. 73 shows a variation of the converter shown in FIG. 72 in which an LC filter 21A is added between the switching network 12A and the second circuit 252.
  • the purpose of the LC filter is to promote adiabatic charging of the switching network 12A via the method shown in FIG. 53.
  • FIG. 74 shows a particular embodiment of the modular DC-DC converter 10 shown in FIG. 73.
  • the regulating circuit 16A is implemented as a fly-back converter having a switch Si, a diode Di, a capacitor Ci, and a transformer Tj.
  • the regulating circuit 16A transitions between first and second states. In the first state, the switch Si is closed, and the diode Di does not conduct. During this first state, the capacitor Ci acts as a charge reservoir to supply power to the output of the regulator 16A. In the second state, the switch Sj is opened and the diode Di conducts.
  • the isolated controller 60 includes a first control signal CTR1 that controls the switching network 12A, a second control signal CTR2 that controls the regulating circuit 16A, and an isolation barrier 61 between them.
  • the first and second control signals CRTl, CTR2 have different grounds and connect to different sides of the transformer Ti.
  • the isolation barrier 61 can include any one or more of sonic isolation, optical isolation, capacitive isolation, inductive isolation, and mechanical isolation.
  • FIG. 29 can be modified to operate with an AC source 14B, as shown in FIG. 75, which shows a modular DC-DC converter 10 connected between first and second circuits 51, 52.
  • the modular DC-DC converter 10 includes first and second switching networks 12A, 12B and a regulating circuit 16A.
  • the first switching network 12A receives, at its input thereof, a voltage from the first circuit 251.
  • the second switching network 12B provides its output to the second circuit 252.
  • the regulating circuit 16A receives an output from the first switching network 12A and provides its own output to an input of the second switching network 12B.
  • An isolated controller 60 provides a first control signal to the first switching network 12A, a second control signal to the second switching network 12B, and a third control signal to the regulating circuit 16A.
  • FIG. 32 can be modified to operate with an AC source 14B, as shown in FIG. 76, which shows first and second regulating circuits 16A, 16B and a switching network 12A.
  • the first regulating circuit 16A receives, at its input, a voltage from the first circuit 251.
  • the second regulating circuit 16B provides its output to the second circuit 252.
  • the switching network 12A receives an output from the first regulating circuit 16A and provides its own output to an input of the second regulating circuit 126.
  • An isolated controller 60 provides a first control signal to the first regulating circuit 16A, a second control signal to the regulating circuit 16B, and a third control signal to the switching network 12A.
  • FIG. 76 shows first and second regulating circuits 16A, 16B and a switching network 12A.
  • the second regulating circuit 16B can be implemented as an LC filter 21 A.
  • the AC rectification stage 19A shown in FIG. 65 can be implemented in a variety of ways.
  • the rectifier 19A features a fuse 71, a capacitor d, an AC bridge 80, and a first electromagnetic interference filter 70A between the AC bridge 80 and the AC source 14B.
  • a second EMI filter 70B and a power-factor correction circuit 90 replaces the capacitor Ci.
  • the first electromagnetic interference filter 70 A reduces the common-mode and differential-mode noise produced by the AC-DC converter 8 by a desired amount.
  • the extent to which such noise is reduced is typically set by a government body, such as the FCC.
  • the AC bridge 80 accepts an AC voltage and outputs an average DC voltage.
  • a particular implementation of an AC bridge 80 is shown in FIG. 81.
  • the bridge includes first, second, third, and fourth diodes D b D 2 , D 3 , D 4 .
  • the AC bridge 80 transitions between first and second states. In the first state, the first and third diodes Di, D 3 are reverse biased, and the second and fourth diodes are forward biased. In the second state, the second and fourth diodes D 2 , D 4 are forward biased and the first and third diodes Di, D 3 are reverse biased.
  • PMlCs power management integrated circuits
  • one voltage may be required to operate a processor, whereas another voltage may be needed to operate a display.
  • FIG. 82 A solution to this difficulty is that shown in FIG. 82, in which one transformation stage drives two or more regulation stages in parallel. Each regulation stage thus provides a separate output voltage.
  • the regulator stage can be any of those already described, including a linear regulator. As shown in FIG. 83, some
  • embodiments include a filter between the transformation stage and the regulation stages.
  • the majority of the power drawn by the various regulation stages come by way of a constant current (or constrained current). This can be achieved, for example, by synchronizing the regulation stages so that they draw as constant a current as possible, thus avoiding larger resistive losses (i.e., due to higher RMS current) in the switched-capacitor network of the transformation stage.
  • FIGS. 84-80 show specific implementations of modular power converters that conform to the architectural diagrams shown in FIGS. 28, 29, 30, and 32. In each
  • a regulating circuit or multiple regulating circuits may limit both the RMS charging current and the RMS discharging current of at least one capacitor in each switching network so all of these switching networks are adiabatically charged switching networks.
  • decoupling capacitors 9A or 9B are present, then the ability of the regulating circuit to limit the RMS charging and discharging current may be diminished.
  • Capacitors 9A and 9B are optional and to keep the output voltage fairly constant capacitor Co is used. All of the stages share a common ground, however this need not be case. For example, if a regulating circuit is implemented as a fly-back converter than the ground can be separated easily, even a switching network can have separate grounds through capacitive isolation.
  • the switching network in each implementation has a single conversion ratio. However, reconfigurable switching networks that provide power conversion at multiple distinct conversion ratios may be used instead.
  • switches labeled "1" and “2" are always in complementary states. Thus, in a first switched-state, all switches labeled “1” are open and all switches labeled “2” are closed. In a second switched-state, all switches labeled “1” are closed and all switches labeled “2” are opened. Similarly, switches labeled “3” are “4" are in complementary states, switches labeled “5" are “6” are in complementary states, and switches labeled "7” are “8” are in complementary states.
  • the regulating circuits operate at higher switching frequencies than the switching networks. However, there is no requirement on the switching frequencies between and amongst the switching networks and regulating circuits.
  • FIG. 84 shows a step-up converter corresponding to the architecture shown in FIG. 11.
  • the switching network 12A is a two-phase step-up cascade multiplier with a conversion ratio of 1 :3 while the regulating circuit 16A is a two-phase boost converter.
  • closing switches labeled 1 and opening switches 2 charges capacitors C 3 and C 4 while discharging capacitors Ci and C 2 .
  • opening switches 1 and closing switches 2 charges capacitors Ci and C 2 while discharging capacitors C3 and C 4 .
  • FIG. 8 shows bidirectional step-down converter corresponding to the architecture shown in FIG. 28.
  • the switching network 12A is a two-phase step-down cascade multiplier with a conversion ratio of 4: 1 while the regulating circuit 16A is synchronous buck converter.
  • closing switches 1 and opening switches 2 charges capacitors Ci, C 2 , and C3 while discharging capacitors C 4 , C 5 , and Ce.
  • opening switches 1 and closing switches 2 charges capacitors C 4 , C5, and C6 while discharging capacitors Ci, C 2 , and C3. All of the active components are implemented with switches so that the converter can process power in both directions.
  • FIG. 86 shows a step-up converter consistent with the architecture shown in FIG. 30.
  • the regulating circuit 16A is boost converter while the switching network 12A is a two-phase step-up series-parallel switched-capacitor converter with a conversion ratio of 1 :2.
  • closing switches 1 charges capacitor C 2 while discharging capacitor Ci. Closing switches 2 has the complementary effect.
  • FIG. 87 shows a bidirectional up-down converter consistent with the architecture shown in FIG. 30.
  • the regulating circuit 16A is synchronous four switch buck-boost converter while the switching network 12A is a two-phase step-up cascade multiplier with a conversion ratio of 1 :4.
  • closing switches 1 charges capacitors C 4 , C 5 , and C 6 while discharging capacitors Ci, C 2 , and C 3 .
  • Closing switches 2 has the complementary effect. All of the active components are implemented with switches so that the converter can process power in both directions.
  • FIG. 88 shows an inverting up-down converter consistent with the architecture shown in FIG. 2.
  • the first switching network 12A is a step-down series-parallel switched-capacitor converter with a conversion ratio of 2: 1
  • the first regulating circuit 16A is a buck/boost converter
  • the second switching network 12B is a step-up series-parallel switched-capacitor converter with a conversion ratio of 1 :2.
  • closing switches 1 charges capacitor Ci while closing switches 2 discharges capacitor Ci.
  • closing switches 7 discharges capacitor C2 while closing switches 8 charges capacitor C 2 .
  • FIG. 89 shows a bidirectional inverting up-down converter consistent with the architecture shown in FIG. 29.
  • the first switching network 12A is a two- phase step-down series-parallel switched-capacitor converter with a conversion ratio of 2: 1
  • the regulating circuit 16A is a synchronous buck/boost converter
  • the second switching network 12B is a two-phase step-up series-parallel switched-capacitor converter with a conversion ratio of 1 :2.
  • closing switches 1 charges capacitor Ci while discharging capacitor C2.
  • Closing switches 2 has the complementary effect.
  • closing switches 7 charges capacitor C4 while discharging capacitor C3.
  • Closing switches 2 has the complementary effect. All of the active components are implemented with switches so that the converter can process power in both directions.
  • FIG. 90 shows a step-down converter consistent with the block diagram shown in FIG. 32.
  • the first regulating circuit 300A is a boost converter
  • the switching network 200 is a two-phase step-up series-parallel switched-capacitor converter with a conversion ratio of 1 :2
  • the second regulating circuit 300B is a boost converter.
  • closing switches 1 charges capacitors C and C 2 while simultaneously discharging capacitors C 3 and C 4 .
  • Closing switches 2 has the complementary effect.
  • FIG. 80 shows a bidirectional up-down converter consistent with the block diagram shown in FIG. 32.
  • the first regulating circuit 300A is a synchronous boost converter
  • the switching network 200 is a two-phase fractional step-down series-parallel switched-capacitor converter with a conversion ratio of 3:2
  • the second regulating circuit 300B is a synchronous buck converter.
  • closing switches 1 charges capacitors C 3 and C 4 while simultaneously discharging capacitors Ci and C 2 .
  • Closing switches 2 has the complementary effect. All of the active components are implemented with switches so that the converter can process power in both directions.
  • the topology of the regulating circuit can be any type of power converter with the ability to regulate the output voltage, including, but without limitation, synchronous buck, three-level synchronous buck, sepic, soft switched or resonant converters.
  • the switching networks can be realized with a variety of switched- capacitor topologies, depending on desired voltage transformation and permitted switch voltage.
  • the physical implementation of the foregoing switching networks 12A includes four primary components: passive device layers, active device layers, interconnect structures, and thru-vias.
  • the passive device layers have passive devices, such as capacitors.
  • the active device layers have active devices, such as switches.
  • the devices are integrated into a single monolithic substrate. In other embodiments, the devices are integrated into multiple monolithic substrates.
  • the monolithic substrates are typically made of semiconductor material, such as silicon.
  • FIG. 92 shows a circuit block diagram of a modular converter that uses capacitors in a switched-capacitor circuit to transfer energy.
  • the block diagram shows a stack of layers that includes layers for both switches and capacitors.
  • the switches within the stack of layers include first and second switches Si, S2.
  • the capacitors within the stack of layers includes first and second capacitors Cj, C 2 .
  • a discrete inductor Lj is mounted outside the layer stack.
  • FIGS. 93-95 show side views of different ways of stacking layers, and placement of the interconnect structure and vias corresponding to each such configuration of layers.
  • the active device layers also known as switch device layer
  • the passive device layers include capacitors.
  • an active device layer connects to a printed-circuit board via a set of C4 bumps and a passive device layer is stacked above the active device layer.
  • Thru-vias TV provide a connection between the printed-circuit board and an interconnect structure between the two layers.
  • FIG. 95 shows the possibility of stacking multiple passive or active layers.
  • Through vias TV provide a path for connecting the printed-circuit board to interconnect structures between adjacent layers.
  • FIG. 96 shows an embodiment that has at least two device layers, one of which has switches and another of which has capacitors.
  • the C4 bumps are laid out along the printed-circuit board at a first pitch.
  • An interconnect structure includes C5 bumps laid out at a second pitch that is smaller than the first pitch. An example of such C5 bumps can be seen in FIG. 106.
  • Each passive layer has capacitors that occupy a certain footprint on the chip.
  • the capacitors are located such that each one is within a footprint of a switch on an active layer that is above or below the passive layer. Such an arrangement helps reduce energy loss and other parasitic losses in the interconnect structures.
  • a layer is said to "face" the +z direction if a vector that is
  • a layer perpendicular to a plane defined by that layer and that is directed in a direction away from that layer is directed in the +z direction.
  • a layer is said to face in the -z direction if it does not face the +z direction.
  • FIGS. 97-99 show the four possible configurations of device faces when the upper layer is the passive layer, as shown in FIG. 93.
  • FIGS. 101 -104 show the four possible configurations of device faces when the upper layer is the active layer, as shown in FIG. 94.
  • the active layer's device face is its upper face and the passive layer's device face is its lower face. Given that there are only two layers, this means they face each other.
  • FIG. 99 shows a converse case in which the passive layer's device face is its upper face and the active layer's device face is its lower face.
  • both the device faces of both the active and passive layers are on upper faces, whereas in FIG. 100 both are on lower faces.
  • FIGS . 101 - 104 show the converse of FIGS. 97-100 for the case in which the active layer is now the upper layer.
  • the active devices are on a lower face and the passive devices are on an upper face. Since there are only two layers, the active and passive devices face each other as they did in FIG. 97.
  • the active devices and passive devices are on upper faces of their respective layers, whereas in FIG. 104 they are on lower faces of their respective layers.
  • FIG. 103 the active devices are on an upper face and the passive devices are on a lower face.
  • the passive device layer and active device layer can be in any form when attached. Two common choices would be in die or wafer form.
  • FIGS. 104-106 show cross-sections of two die-to-die arrangements in which an interconnect structure connects switches in an active die to capacitors on a passive die.
  • the switches connect to a planar capacitor whereas in FIG. 106 the switches connect to a trench capacitor.
  • the first bumps C4 which provide the electrical connections from the die stack to the printed-circuit board, and through-vias TV are omitted in FIGS. 104-106 but can be seen in FIGS. 107-108.
  • trench capacitors are preferable to planar capacitors because trench capacitors offer greater capacitance per unit of die area than planar capacitors, sometimes by one or two orders of magnitude. Additionally, trench capacitors offer lower equivalent series resistance than planar capacitors. Both of these capacitor attributes are desirable for use in power converters that use capacitive energy transfer because they affect the efficiency of the power converter.
  • an interconnect structure connects the switches on the active die to the capacitors on the passive die.
  • This interconnect structure can be implemented in numerous ways.
  • the interconnect structure is the union of a multilayer interconnect structure on the passive die, a single layer of second bumps C5, and a multilayer interconnect structure on the active die.
  • the only requirements are that the interconnect structure connects the switches on one device layer to the capacitors on the other device layer, that the two device layers are stacked one on top of the other, and that the second bumps C5 have a much finer pitch than the first bumps C4.
  • the pitch of the second bumps C5 is four times greater than the pitch of the first bumps.
  • pitch means the number of bumps per unit length.
  • FIGS. 107-108 show another embodiment implemented by wafer-to-wafer stacking.
  • the active and passive wafers electrically connect to each other using a bonding process.
  • the device face of the active layer is its lower face and in FIG. 108, the device face of the active layer is its upper face. Examples of suitable bonding processes are copper-copper and oxide-oxide bonding.
  • FIGS. 107-108 show the thru-vias and some of the first bumps C4, which were omitted in FIGS. 104- 106.
  • a switched-capacitor power converter of the type discussed herein has a great many switches and capacitors in a switched-capacitor power converter. These all have to be interconnected correctly for the power converter to operate. There are many ways to physically lay out the conducting paths that interconnect these components. However, not all of these ways are equally efficient. Depending on their geometry, some of these conducting paths may introduce noticeable parasitic resistance and/or inductance. Because there are so many interconnections, it can be a daunting challenge to choose a set of interconnections that will both provide acceptable parasitic resistance and inductance for the power converter as a whole.
  • One method that can be used to control these parasitic quantities is to partition the switches and capacitors.
  • FIG. 1 10 An example of this technique is shown in FIG. 1 10, in which eight switches Si-Ss and a controller 20A are disposed on an active layer that is located below a passive layer having two capacitors. Although the switches are not completely visible through the passive layer, their locations are marked by dotted lines on FIG. 110.
  • the figure shows a first capacitor d on top of switches Si, S 2 , S 5 , S6 and a second capacitor C 2 on top of switches S3, S4, S 7 , S».
  • switches in a switching network 12A are usually active devices that are implemented with transistors.
  • the switching network 12A may be integrated on a single monolithic semiconductor substrate or on multiple monolithic semiconductor substrates, or formed using discrete devices. Furthermore, since the device is a power converter, each switch may be expected to 31726
  • a switch that carries a great deal of current is often implemented by numerous current paths connected in parallel to a common terminal.
  • FIG. 109 and FIG. 1 12 shows a transistor on a first layer and a capacitor on a lower layer.
  • the transistor has first, second, and third current paths with the second current path being between the first and third.
  • the three current paths extend between one source terminal and one drain terminal of the transistor.
  • FIG. 112 shows a capacitor that has three separate current paths connected to first and second capacitor terminals. In the course of being charged and discharged, some lateral current is inevitable for reasons discussed in connection with the transistor in the upper layer.
  • One way to reduce this lateral current is to partition the switches and the capacitors into numerous partitions, as shown in FIG. 109 and FIG. 1 13.
  • This partitioning essentially involves converting an rc-terminal device into an (n+m) terminal device where m depends on the number of partitions.
  • the two-terminal capacitor of FIG. 112 is transformed into a six-terminal capacitor in FIG. 113.
  • the source terminal and drain terminal of the transistor in FIG. 1 12 is transformed into three source terminals and three drain terminals in the transistor of FIG. 1 13.
  • FIG. 1 12 shows three current paths connected in parallel, whereas FIG. 113 shows three current paths that are partitioned and therefore isolated from each other.
  • the capacitor represented by the lower layer of FIG. 1 12 is a two-terminal capacitor like any conventional capacitor.
  • Prior art converters use capacitors of this type.
  • a converter as disclosed herein uses a six-terminal capacitor as shown FIG. 113. Although such a capacitor is more complex because it has more terminals that need to be both made and properly aligned, it reduces parasitic effects caused by lateral current.
  • the transistor switch represented by the upper layer of FIG. 112 has one source terminal and one drain terminal. This is the kind of transistor that is used in conventional power converters.
  • the transistor represented by the upper layer of FIG. 113 has three source terminals and three drain terminals. Although such a transistor is more complex because it has more terminals that need to be both made and properly aligned, it reduces parasitic effects caused by lateral current.
  • partitioning is geometry-independent. Its essence is that of turning an ⁇ -terminal device into an (n+m) terminal device in an effort to reduce parasitic effects. There is no requirement that the device be oriented in any particular way. In particular, there is no requirement that the partitioning be carried out in only one dimension as shown in FIG. 113. For example, it is quite possible to partition a component along x and y directions as shown in the nine-partition switch of FIG. 1 11 and the six-partition capacitor shown in FIG. 114.
  • FIG. 1 15 shows a functional block diagram of the switching network 12A of FIGS. 13 and 12.
  • the illustrated switching network 12A is a two-phase cascade multiplier that transforms a first voltage VI into a second voltage V2. It does so by choreographing the flow of charge into and out of charge-transfer capacitors (also known as coupling capacitors) in a first charge-transfer capacitor set 50A.
  • charge-transfer capacitors also known as coupling capacitors
  • each charge-transfer capacitor may have a capacitance that is a function of the voltage across it.
  • the charge-transfer capacitors are selected so that they all have the same capacitance at their respective operating voltages. However, at the same voltage, it may well be that the different charge-transfer capacitors will have different capacitances (e.g., MLCC have a strong capacitance dependence upon dc voltage bias).
  • the switching network 12A includes first and second phase-switch sets 54A, 54B, one for each phase.
  • the switches within each phase-switch set 54A, 54B will be referred to herein as "phase switches.”
  • the switching network 12A includes first and second stack-switch sets 52A, 52B, again, one for each phase.
  • the switches within each stack-switch set 52A, 52B will be referred to herein as "stack switches.”
  • Each of the switches takes up a certain amount of area on semiconductor substrate (e.g., silicon, GaAs, GaN, and SiC).
  • semiconductor substrate e.g., silicon, GaAs, GaN, and SiC.
  • the areas taken up by each switch need not be the same, however. In general, it is useful to have switches that are expected to carry considerable amounts of current be larger than those that carry less current. This permits the overall circuit to be smaller, while avoiding excessive conductive losses.
  • One or more of the switches can be partitioned to discourage lateral flow of current within the area defined by the switch. This can be carried out by having multiple terminals on each end of the switch. With such multiple terminals, current entering through any one terminal will be more likely to flow to a terminal directly opposite, thus reducing the extent of lateral current flow within the switch.
  • the switching network 12A features two separate and distinct controllers: a phase controller 59A to control the phase switches and a stack controller 51 to control the stack switches.
  • the phase controller 59A controls the phase switches based at least in part on a phase- controller input signal I 0 i- It does so through a phase control path 55B that connects the phase controller 59A to the phase switches.
  • the stack controller 51 controls the stack switches based at least in part on a stack-controller input signal Io2- It does so through a stack control path 55A that connects the stack controller 51 to the stack switches.
  • An inter- controller commissure 57 provides communication between the phase controller 59A and the stack controller 51. This permits the phase controller 59A and the stack controller 51 to control the phase switches and stack switches in a coordinated fashion rather than independently.
  • An advantage of the manufacturing procedures used in integrated circuits is the ability to integrate many components on a single die. This makes it easier to manufacture many components at once, and to thus reduce the manufacturing cost per component.
  • One way to manufacture the switching network 12A shown in FIG. 1 15 is to place the first and second stack-switch sets 52A, 52B and the first and second phase-switch sets 54A, 54B on the same die. Since only one die has to be manufactured, the cost of manufacture on a per switch basis would be expected to be reduced.
  • the stack switches and the phase switches have different requirements.
  • the phase switches do not experience such high voltages or currents.
  • the phase switches are relatively simple and inexpensive to manufacture.
  • the stack switches are regularly exposed to fairly high voltage differences across them. Because of these special needs, the stack switches require different manufacturing steps.
  • the more complex procedure used to manufacture stack switches can be used to also manufacture phase switches.
  • the switching network 12A shown in FIG. 1 15 avoids this advantage by having the first and second stack-switch sets 52A, 52B and the first and second phase-switch sets 54A, 54B be on different dies instead of on the same die. As a result, it becomes necessary to use two manufacturing steps instead of a single manufacture step.
  • FIG. 115 shows a first phase-die 58A and a stack-die 56.
  • the first phase- die 58A contains the first and second phase-switch sets 54A, 54B and the phase controller 59A.
  • the stack-die 56 contains the first and second stack-switch sets 52A, 52B and the stack controller 51.
  • phase controller 59A and the stack controller 51 are also on separate controller dies, thus further increasing the number of separate manufacturing operations that must be carried out to construct the switching network 12A.
  • first and second phase-switch sets 54A, 54B are both on the first phase-die 58A and the first and second stack-switch sets 52A, 52B are on a separate stack-die 56.
  • each die is associated with both phases.
  • FIG. 1 16 shows a circuit that transforms a first voltage Vj into a second voltage V 2 , which it provides to the load 18A.
  • the circuit has four separate dies: a first phase- die for the first phase-switch set 54A, a second phase-die for the second phase-switch set 54B, a first stack-die for the first stack-switch set 52A, and a fourth stack-die for the second stack- switch set 52B.
  • the first phase-switch set 54A and the first stack-die are associated with the first phase
  • the second phase-switch set 54B and the second stack- switch set 52B are associated with the second phase.
  • phase controller 59A and the stack controller 51 have been omitted to promote clarity.
  • the switches are also shown schematically instead of as transistors. Had they been shown as transistors, the phase controller 59A and the stack controller 51 would connect to the gate terminals of those transistors.
  • the first phase-switch set 54A in FIG. 1 15 corresponds to first and second phase switches Spi, Sp 2 in FIG. 116.
  • the second phase-switch set 54B in FIG. 1 15 correspond to third and fourth switches Sp3, Sp4 in FIG. 116. These are placed together on the same first phase-die 58A in FIG. 115.
  • the first stack-switch set 52A in FIG. 115 corresponds to the switches S , S 2 A, $3A, S 4 A in FIG. 1 16.
  • the second stack-switches 52B in FIG. 1 15 correspond to the switches SIB, S 2 B, S3B, S 4 B in FIG. 1 16. These are all placed together on the same stack-die 56 in FIG. 115.
  • FIG. 11 7 shows a particular implementation of terminals on the stack-die 56 and terminals on the first phase-die 58A for the embodiment shown in FIG. 115.
  • Charge-transfer capacitors from the first charge-transfer capacitor set 50A extend between the stack-die 56 and the first phase-die 58A.
  • the terminals shown in FIG. 116 have been configured so that those that connect to the positive terminals of the charge-transfer capacitors are all on one side and those that connect to the negative terminals of the charge-transfer capacitors are all on the other side. This reduces path length between the stack switches, the phase switches, and the charge-transfer capacitors.
  • both the stack-die 56 and the first phase-die 58A connect to the output of the switching network 12A.
  • a conducting interdie commissure 63 of length Yl connects the output terminal of the switching network 12A to both the stack-die 56 and the first phase-die 58A.
  • This length Y t is tuned to the length of the capacitors in the first charge-transfer capacitor set 50A.
  • FIG. 117 results in the stack-die 56 being coplanar with the first phase-die 58A.
  • it is possible to further reduce conducting path lengths by having the stack-die 56 and first phase-die 58A on different planes. This can be achieved by folding the layout shown in FIG. 1 17 about a vertical line extending down the middle of the interdie commissure 63.
  • it is possible to have different phases on different levels by folding along a horizontal axis of symmetry.
  • each charge-transfer capacitor Ci A , C 2 A, C3A, C A, CiB, C2B, C3B, C B will at some point be connected to the first phase-switch set 54A and to the second phase-switch set 54B. It is possible, however, to arrange the components to form a switching network 12A that has first and second charge-transfer capacitor sets 50A, 50B, each of which connects to only one of the first and second phase-switch sets 54A, 54B. An example of this topology can be seen in FIG. 1 1 8.
  • FIG. 1 1 8 shows a functional block diagram of a two-phase switching network 12A that transforms a first voltage V / into a second voltage V2. It does so by choreographing the flow of charge into and out of charge-transfer capacitors.
  • the switching network 12A of FIG. 1 1 8 has first and second phase-switch sets 53 A, 53B, one for each phase, and first and second stack-switch sets 52A, 52B, one for each phase.
  • the switching network 12A features three separate and distinct controllers: a first phase-controller 59A to control phase switches in the first phase- switch set 53A, a stack controller 51 to control stack switches in the first and second stack- switch sets 52A, 52B, and a second phase-controller 59B to control phase switches in the second phase-switch set 53B.
  • the first phase-controller 59A controls the operation of the phase switches in the first phase-switch set 53A based in part on a first-phase-controller input signal Ioi- It does so through a first phase-control path 55B that connects the phase controller 59A to the phase switches.
  • the second phase-controller 59B controls the operation of the phase switches in the second phase-switch set 53B based at least in part on a second-phase-controller input signal loi- It does so through a second phase-control path 55C that connects the second phase controller 59B to the second phase-switch set 53B.
  • the stack controller 51 receives a stack-control input signal I02 and uses that to control the operation of the stack switches in the first and second stack-switch sets 52 A, 52B. It does so via a stack control path 55A.
  • the first phase-controller 59A, the second phase- controller 59B, and the stack controller 51 all communicate via an inter-controller commissure 57.
  • FIG. 1 1 9 shows a circuit with four separate dies: a first phase-die for the first phase- switch set 53A, a second phase-die for the second phase-switch set 53B, a first stack-die for the first stack-switch set 52A, and a fourth stack-die for the second stack-switch set 52B.
  • first phase-switch set 54A and the first stack-die are associated with the first phase
  • second phase-switch set 54B and the second stack- switch set 52B are associated with the second phase.
  • the first and second phase-controllers 59A, 59B and the stack controller 51 have been omitted to promote clarity.
  • the switches are also shown schematically instead of as transistors.
  • the circuit shown in FIG. 1 19 includes a voltage source 14 and a load 18A.
  • the voltage source 14 provides the first voltage Vj in FIG. 118.
  • the load 18A connects to the second voltage V2 in FIG. 1 18.
  • the first phase-switch set 53A in FIG. 118 corresponds to first, second, third, and fourth phase switches S P j, Sp2, Sp 3 , Sp 4 in FIG. 119.
  • first and second phase-dies 58 A, 58B in FIG. 118 correspond to fifth, sixth, seventh, and eighth switches Sps, Sps, Sp 7 , S P s in FIG. 1 19. These are placed on first and second phase-dies 58 A, 58B in FIG. 118.
  • the first stack-switch 52A in FIG. 118 corresponds to the first, second, third, fourth, and fifth switches Sj A , S 2 A, S 3 A, S 4A , SSA in FIG. 1 19.
  • the second stack switches 52B in FIG. 1 18 correspond to the sixth, seventh, eighth, ninth, and tenth switches SIB, S2B, S3B, S 4 B, SSB in FIG. 119. These are all placed together on the same stack-die 56 in FIG. 118.
  • FIG. 120 shows a particular implementation of terminals on the stack-die 56
  • the terminals on the second phase-die 58B are laid out in a manner similar to that shown for the first phase-die 58A and have thus been omitted for clarity.
  • the interconnections between the charge-transfer capacitors C ] A , C 2A , C 3A , C 4A and both the stack-die 56 and the first phase-die 58A are similar to those shown in FIG. 120 and are omitted for clarity.
  • an interdie commissure 63 again connects the second phase-switch die 58B to the stack-die 56.
  • the interdie commissure 63 has a bridge section having a length Y 2 that depends on the physical size of the charge-transfer capacitors Ci B , C 2B , C 3 B, C 4B from the second charge-transfer capacitor set 50B.
  • the dimensions of the interdie commissure 63 are enlarged at selected locations to avoid excessive build-up of current density. As a result, the interdie commissure 63 is wider at locations where considerable current is expected to flow, but narrower at locations where smaller currents are expected to flow. This avoids having an excessively large footprint while also avoiding resistive losses.
  • the switching network 12A is to be connected to a regulator (also known as regulating circuit). Under these circumstances, it is useful to include a regulator- switch set 65 within the phase-die 58C as shown in FIG. 122. It is expedient to integrate the first and second phase-switch sets 54A, 54B and the regulator-switch set 65 in the phase-die 58C since the regulator switches and the phase switches have similar performance requirements. Both the phase switches and the regulator switches are intended to sustain essentially the same voltage. As such, the same manufacturing process can be used for both kinds of switch.
  • the regulator that is to be coupled to the regulator-switch set 65 introduces an inductive load, which in turn introduces considerable noise in the substrate of any die that contains the regulator-switch set 65. Since, during operation, the substrate of the phase-die 58C is inherently noisier than the substrate of the stack-die 56, it is advantageous to include the regulator-switch set 65 in the phase-die 58C so that operation of the stack-die 56 can proceed with minimal disturbance due to electrical noise.
  • the phase controller is replaced by a hybrid controller 59C configured to control both the regulator-switch set 65 and the phase-switch set 54A, 54B via a phase control path 55B, which extends from the hybrid controller 59C to the phase-switch set 54A, 54B, and a regulator control path 55D, which extends from the hybrid controller 59C to the regulator-switch set 65.
  • a hybrid controller 59C configured to control both the regulator-switch set 65 and the phase-switch set 54A, 54B via a phase control path 55B, which extends from the hybrid controller 59C to the phase-switch set 54A, 54B, and a regulator control path 55D, which extends from the hybrid controller 59C to the regulator-switch set 65.
  • phase switches and stack switches are placed on separate dies instead of integrating them into the same die. Since this die must undergo a more expensive manufacturing process, and since the manufacturing cost is a function of die area, it is advantageous to reduce the die area. Since only the stack switches actually require the more expensive manufacturing process, it is advantageous to omit the phase switches and to place them on a separate die, which can then be manufactured more inexpensively.
  • FIGS. 123-128 collectively illustrate the flexibility associated with having a separate phase-die 58 and stack-die 56.
  • FIG. 123 shows a substrate 28 supporting charge-transfer capacitors CIA, C 2A , a first die Ui and a second die U 2 .
  • the first die Ul corresponds to the stack-die 56 and the second die U 2 corresponds to the phase-die 58.
  • the first and second dies Ui, U2 are side-by-side with their respective device faces both facing the substrate 28.
  • Electrically-conductive bumps 45 provide electrical communication between the first and second dies Uj, U 2 and the charge-transfer capacitors CIA, C 2 A-
  • FIG. 124 shows a substrate 28 supporting charge-transfer capacitors CI A , C 2 A, a first die Ui, and a second die U 2 .
  • the first and second dies Ui, U 2 are side-by-side inside a package 82 with their respective device faces both facing the substrate 28.
  • a first electrical interconnect layer 43A provides interconnection between the first and second dies Ui, U 2 .
  • Electrically-conductive bumps 45 provide electrical
  • FIG. 125 shows the substrate 28 supporting a package 82 in which the second die U 2 is stacked on top of the first die Ui.
  • a first interconnect layer 43 A connects the first die Ui with the rest of the switching network 12A and a second interconnect layer 43B connects the second die U 2 with the rest of the switching network 12A.
  • Electrically-conductive bumps 45 provide electrical communication between the package 82 and the charge-transfer capacitors CIA, C 2 A-
  • FIG. 126 shows the substrate 28 supporting a package 82 having a passive device layer 41A and an active device layer 42A.
  • the charge-transfer capacitors CI A -C 4 B are integrated into their own capacitor die 81, which is in the passive device layer 41A.
  • the first and second dies Ui, U 2 are in the active device layer 42A.
  • the passive device layer 41A can be viewed as a charge-transfer layer and the active device layer 42A can be viewed as a switching layer.
  • Electrically-conductive bumps 45 provide electrical communication between the package 82 and any external components.
  • FIG. 127 shows the substrate 28 supporting a package 82 having a mixed device layer 40A, which is a hybrid layer that serves as both a switching layer and a charge-transfer layer, and an active device layer 42A, which is only a switching layer.
  • the charge-transfer capacitors CIA-C 4B are integrated into their own capacitor die 81, which is in the mixed device layer 40A, along with the second die U 2 .
  • the first die Ui is in the active device layer 42A, but laterally offset from the second die U 2 . This provides a shorter path length for connections between the first and second dies Ui, U 2 .
  • Yet another advantage of having the various components of a switched-capacitor circuit be on separate dies is that doing so can promote heat dissipation. This is because there will be more surface area available to radiate heat. The ability to efficiently dissipate heat is particularly important for a power converter, since a power converter has a tendency to run hot.
  • An example of how to arrange dies to promote cooling is shown in FIG. 128.
  • FIG. 128 shows the substrate 28 supporting a package 82 having a first active device layer 42 A, a second active device layer 42B, and a passive device layer 41A between the first active device layer 42A and the second active device layer 42B.
  • the charge-transfer capacitors CI A -C 4 B are integrated into their own capacitor die 81, which is in the passive device layer 41A.
  • the second die U2 is in the second active device layer 42B and the first die Ui is in the first active device layer 42 A.
  • the passive device layer 41 A is the charge-transfer layer and the first and second active device layers 42A, 42B are both switching layers.
  • Electrically-conductive bumps 45 provide electrical communication between the package 82 and any external components.
  • An advantage of the embodiment shown in FIG. 128 is that the hottest components of the circuit, namely the active device layers 42A, 42B, are outside, whereas the passive device layer 41A, which stays cooler, is in the inside. This configuration thus promotes cooling.
  • FIG. 129 shows the substrate 28 supporting an inductor L] and a package 82 having a passive device layer 41A and an active device layer 42A.
  • Charge-transfer capacitors C JA , C 2A are disposed in the passive device layer 41 A.
  • the charge -transfer capacitors CJA, C 2 A are discrete elements that, in some embodiments, are surrounded by a matrix 74 to mechanically support them.
  • the first die Ui is in the active device layer 42A with its device face facing electrically conductive bumps 45 that provide electrical communication between the package 82 and external components, including the inductor L t .
  • the passive device layer 41A is the charge-transfer layer and the active device layer 42A is the switching layer.
  • First and second interconnect layers 43A, 43B provide electrical communication between the charge-transfer capacitors Ci A , C 2A and the first die Uj.
  • FIG. 130 shows the substrate 28 supporting an inductor Li and a package 82.
  • the package 82 has a passive device layer 41A and an active device layer 42A.
  • interconnect layer 43A resting on electrically-conductive bumps 45 provides electrical communication between the package 82 and external components, including the inductor Lj.
  • Charge-transfer capacitors Ci A , C 2A are disposed in the passive device layer 41A. These charge-transfer capacitors Cj A , C 2A are discrete elements that, in some embodiments, are surrounded by a matrix 74 to mechanically support them.
  • the first die Ui is in the active device layer 42A with its device face facing a second interconnect layer 43B at the passive device layer 41A.
  • the switching layer thus corresponds to the active device layer 42A and the charge-transfer layer is the passive device layer 41A.
  • the second interconnect layer 43B provides electrical communication between the first die Ui and the charge-transfer capacitors CiA, C2A- A heatsink 76 opposite the device face contacts thermally-conductive bumps 46. Unlike the electrically-conductive bumps 45, which conduct both heat and electricity, the thermally-conductive bumps 46 are dedicated to heat transfer only.
  • FIG. 131 shows the substrate 28 supporting an inductor LI and a package 82.
  • the package 82 has a passive device layer 41 A, which serves as the charge-transfer layer, and an active device layer 42A, which serves as a switching layer.
  • a first interconnect layer 43A rests on an electrically-conductive pad 45B. This first interconnect layer 43A provides electrical communication between the package 82 and external components, including the inductor Li.
  • Charge-transfer capacitors CIA, C 2 A are disposed in the passive device layer 41 A. These charge-transfer capacitors CIA, C 2 A are discrete elements that, in some embodiments, are surrounded by a matrix 74 to mechanically support them.
  • the first die Ui is in the active device layer 42A with its device face facing a second interconnect layer 43B at the passive device layer 41 A.
  • This second interconnect layer 43B provides electrical communication between the first die Ui and the charge-transfer capacitors CIA, C 2 A- A heatsink 76 opposite the device face contacts a thermally-conductive pad 46B.
  • the thermally-conductive pad 46B is dedicated to heat transfer only.
  • FIG. 132 shows the substrate 28 supporting a package 82 having a passive device layer 41A and an active device layer 42A.
  • the pass device layer 41A serves as the charge- transfer layer
  • the active device layer 42A serves as a switching layer.
  • a first interconnect layer 43A resting on electrically-conductive bumps 45 provides electrical communication between the package 82 and external components.
  • An inductor Li and charge-transfer capacitors CIA, C 2 A are disposed in the passive device layer 41A. These are discrete elements that, in some embodiments, are surrounded by a matrix 74 to mechanically support them.
  • the first die Uj is in the active device layer 42A with its device face facing a second interconnect layer 43B at the passive device layer 41 A.
  • This second interconnect layer 43B provides electrical communication between the first die Ui, the charge-transfer capacitors CI , C 2 A, and the inductor Li.
  • FIG. 133 shows the substrate 28 supporting a package 82 having a passive device layer 41A and a mixed device layer 40A.
  • the passive device layer 41A serves as the charge- transfer layer
  • the mixed device layer 40A serves as a switching layer.
  • a first interconnect layer 43A resting on electrically-conductive bumps 45 provides electrical communication between the package 82 and external components.
  • Charge-transfer capacitors Ci A , C2A are disposed in the passive device layer 41A. These are discrete elements that, in some embodiments, are surrounded by a matrix 74 to mechanically support them.
  • An inductor L] and the first die Ui are side-by-side in the mixed device layer 40A.
  • the inductor L] is formed by metallic traces wound around a core in the mixed device layer 40A.
  • the first die Ui has its device face facing a second interconnect layer 43B at the passive device layer 41A.
  • This second interconnect layer 43B provides electrical communication between the first die Uj, the charge-transfer capacitors CIA, C2A, and the inductor Li.
  • a heatsink 76 opposite the device face contacts thermally-conductive bumps 46. Unlike the electrically-conductive bumps 45, which conduct both heat and electricity, the thermally-conductive bumps 46 are dedicated to heat transfer only.
  • Another advantage of using different dies to build a switching network 12A is that come components are not good neighbors on the same die.
  • the stack switches handle considerable amounts of power. As a result, the stack switches do not always make good neighbors on the same die. In particular, when the stack switches and phase switches are on the same die, the phase switch operation can be adversely affected by stack switch operation.
  • the stack controller 51 is integrated into the stack-die. This reduces overall pin count and also avoids the need to fabricate a separate die. However, the very high currents associated with the operation of the stack switches may interfere with operation of the stack controller 51, both because of EMI and because of electrical coupling. Thus, in some embodiments, the stack controller 51 is on a separate die.
  • the arrangements described above avoid the component and pin count penalty, reduce the energy loss in the parasitic interconnect structures, and reduces the total footprint of power converters that use capacitors to transfer energy.
  • a computer accessible storage medium includes a database representative of one or more components of the converter.
  • the database may include data representative of a switching network that has been optimized to promote low- loss operation of a charge pump.
  • a computer accessible storage medium may include any non- transitory storage media accessible by a computer during use to provide instructions and/or data to the computer.
  • a computer accessible storage medium may include storage media such as magnetic or optical disks and semiconductor memories.
  • a database representative of the system may be a database or other data structure that can be read by a program and used, directly or indirectly, to fabricate the hardware comprising the system.
  • the database may be a behavioral-level description or register-transfer level (RTL) description of the hardware functionality in a high level design language (HDL) such as Verilog or VHDL.
  • the description may be read by a synthesis tool that may synthesize the description to produce a netlist comprising a list of gates from a synthesis library.
  • the netlist comprises a set of gates that also represent the functionality of the hardware comprising the system.
  • the netlist may then be placed and routed to produce a data set describing geometric shapes to be applied to masks.
  • the masks may then be used in various semiconductor fabrication steps to produce a semiconductor circuit or circuits corresponding to the system.
  • the database may itself be the netlist (with or without the synthesis library) or the data set.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Dc-Dc Converters (AREA)

Abstract

Un appareil de conversion de puissance comprend un étage de transformation destiné à transformer une première tension en une seconde tension. L'étage de transformation comprend un réseau de commutation, un filtre et un contrôleur. Le filtre est conçu pour connecter l'étage de transformation à un régulateur. Le contrôleur commande le réseau de commutation.
PCT/US2017/031726 2016-05-09 2017-05-09 Convertisseur de puissance WO2017196826A1 (fr)

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US10917007B2 (en) 2011-05-05 2021-02-09 Psemi Corporation Power converter with modular stages connected by floating terminals
US11211861B2 (en) 2011-05-05 2021-12-28 Psemi Corporation DC-DC converter with modular stages
DE112020002215T5 (de) 2019-05-03 2022-01-20 pSemi Corporation Steuerkreis für Schalter, die in einer Ladungspumpe verwendet werden
US11303205B2 (en) 2011-05-05 2022-04-12 Psemi Corporation Power converters with modular stages
US11316424B2 (en) 2011-05-05 2022-04-26 Psemi Corporation Dies with switches for operating a switched-capacitor power converter
DE112020004712T5 (de) 2019-09-30 2022-06-30 Psemi Corporation Unterdrückung von neuausgleichsströmen in einem geschalteten kondensatornetzwerk
EP4277099A1 (fr) * 2022-05-10 2023-11-15 Goodrich Aerospace Services Private Limited Convertisseurs cc-cc haute tension
WO2023220682A1 (fr) * 2022-05-12 2023-11-16 Psemi Corporation Appareil et procédés de fabrication de circuit à condensateurs commutés
WO2023220679A1 (fr) * 2022-05-12 2023-11-16 Psemi Corporation Boîtiers de convertisseurs de puissance, appareil de conversion de puissance et procédés de mise sous boîtier de circuit intégré

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US11791723B2 (en) 2010-12-30 2023-10-17 Psemi Corporation Switched-capacitor converter configurations with phase switches and stack switches
US11316424B2 (en) 2011-05-05 2022-04-26 Psemi Corporation Dies with switches for operating a switched-capacitor power converter
US10917007B2 (en) 2011-05-05 2021-02-09 Psemi Corporation Power converter with modular stages connected by floating terminals
US11211861B2 (en) 2011-05-05 2021-12-28 Psemi Corporation DC-DC converter with modular stages
US11303205B2 (en) 2011-05-05 2022-04-12 Psemi Corporation Power converters with modular stages
US11764670B2 (en) 2011-05-05 2023-09-19 Psemi Corporation DC-DC converter with modular stages
US10193441B2 (en) 2015-03-13 2019-01-29 Psemi Corporation DC-DC transformer with inductor for the facilitation of adiabatic inter-capacitor charge transport
US11646657B2 (en) 2015-03-13 2023-05-09 Psemi Corporation DC-DC transformer with inductor for the facilitation of adiabatic inter-capacitor charge transport
US10715036B2 (en) 2015-03-13 2020-07-14 Psemi Corporation DC-DC transformer with inductor for the facilitation of adiabatic inter-capacitor charge transport
DE112020002215T5 (de) 2019-05-03 2022-01-20 pSemi Corporation Steuerkreis für Schalter, die in einer Ladungspumpe verwendet werden
DE112020004712T5 (de) 2019-09-30 2022-06-30 Psemi Corporation Unterdrückung von neuausgleichsströmen in einem geschalteten kondensatornetzwerk
EP4277099A1 (fr) * 2022-05-10 2023-11-15 Goodrich Aerospace Services Private Limited Convertisseurs cc-cc haute tension
WO2023220682A1 (fr) * 2022-05-12 2023-11-16 Psemi Corporation Appareil et procédés de fabrication de circuit à condensateurs commutés
WO2023220679A1 (fr) * 2022-05-12 2023-11-16 Psemi Corporation Boîtiers de convertisseurs de puissance, appareil de conversion de puissance et procédés de mise sous boîtier de circuit intégré

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