WO2017179104A1 - Semiconductor element bonding structure, image pickup module, and endoscope device - Google Patents

Semiconductor element bonding structure, image pickup module, and endoscope device Download PDF

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Publication number
WO2017179104A1
WO2017179104A1 PCT/JP2016/061711 JP2016061711W WO2017179104A1 WO 2017179104 A1 WO2017179104 A1 WO 2017179104A1 JP 2016061711 W JP2016061711 W JP 2016061711W WO 2017179104 A1 WO2017179104 A1 WO 2017179104A1
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Prior art keywords
silicon wafer
semiconductor element
metal
bonding structure
element bonding
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PCT/JP2016/061711
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French (fr)
Japanese (ja)
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中山　高志
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オリンパス株式会社
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Priority to PCT/JP2016/061711 priority Critical patent/WO2017179104A1/en
Publication of WO2017179104A1 publication Critical patent/WO2017179104A1/en

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    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B1/00—Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopes; Illuminating arrangements therefor
    • A61B1/04—Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopes; Illuminating arrangements therefor combined with photographic or television appliances
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof

Definitions

  • the present invention relates to an imaging device and an endoscope apparatus including the imaging module, for example, a semiconductor element junction structure employed in an integrated circuit used in the imaging module.
  • An electronic device equipped with an imaging module for capturing an optical image that can be introduced from the outside of the living body or structure in order to observe difficult places such as the inside of the living body or the inside of the structure.
  • Endoscopes are used, for example, in the medical field or the industrial field.
  • the imaging unit of the electronic endoscope includes an objective lens that forms a subject image and an image sensor disposed on the imaging surface of the objective lens.
  • a silicon through electrode (TSV) and a bump electrode are formed on an upper wafer, and after another wafer is laminated, a seed layer for bump formation is formed. Techniques for removal are disclosed.
  • TSV formation a through groove is formed in a Si substrate, an insulating film is coated on a side wall, and then a conductor is embedded.
  • TSV formation has a complicated process, and bumps for laminating a plurality of wafers must be separately formed. is there.
  • the present invention has been made in view of the above-described problems, and an object of the present invention is to reduce the number of man-hours at the time of manufacture and to manufacture a semiconductor element junction structure, an imaging module, and an endoscope that can be manufactured at low cost. Is to provide a device.
  • a first silicon wafer in which a through-hole portion is formed and an electrode is formed around the through-hole portion in a surface layer portion, and the first silicon wafer are stacked.
  • a second silicon wafer formed with a metal pillar portion to be fitted into the through-hole portion, and the metal pillar portion is a base metal provided on a surface layer portion of the second silicon wafer;
  • the imaging module of one embodiment of the present invention includes a first silicon wafer in which a through-hole portion is formed and an electrode is formed around the through-hole portion in a surface layer portion, and the first silicon wafer is laminated, A second silicon wafer formed with a metal pillar portion to be inserted into the through-hole portion, the metal pillar portion being a base metal provided on a surface layer portion of the second silicon wafer, and the base metal And a low melting point metal having a melting point lower than that of the pedestal metal, and is formed from a semiconductor element bonding structure.
  • Integrated circuit Integrated circuit.
  • a first silicon wafer in which a through-hole portion is formed and an electrode is formed around the through-hole portion in a surface layer portion, and the first silicon wafer are stacked.
  • a semiconductor element bonding structure comprising: a low melting point metal that is laminated on a base metal and is melted and electrically bonded to the electrode of the first silicon wafer, and has a melting point lower than that of the base metal
  • An imaging module having an integrated circuit formed from
  • the figure which shows the structure of the endoscope system which concerns on 1 aspect of this invention The perspective view which shows the structure of an imaging device similarly Sectional drawing which shows the semiconductor element junction structure before two wafers are laminated
  • FIG. 1 is a diagram illustrating a configuration of an endoscope system according to one embodiment of the present invention
  • FIG. 2 is a perspective view illustrating a configuration of an imaging device
  • FIG. 3 is a semiconductor element bonding before two wafers are stacked.
  • FIG. 4 is a cross-sectional view showing a semiconductor element bonding structure after two wafers are stacked
  • FIG. 5 is a cross-sectional view showing a semiconductor element bonding structure in which two wafers are electrically bonded. .
  • An endoscope apparatus (hereinafter abbreviated as an endoscope) 101 according to the present embodiment has a configuration that can be introduced into a subject such as a human body and optically images a predetermined observation site in the subject. ing.
  • the subject into which the endoscope 101 is introduced is not limited to a human body, and may be another living body or an artificial object such as a machine or a building.
  • the endoscope 101 includes an insertion portion 102 introduced into the subject, an operation portion 103 located at the proximal end of the insertion portion 102, and a universal cord 104 extending from a side portion of the operation portion 103. It is mainly composed.
  • the insertion portion 102 includes a distal end portion 110 disposed at the distal end, a bendable bending portion 109 disposed on the proximal end side of the distal end portion 110, and an operation portion 103 disposed on the proximal end side of the bending portion 109.
  • a flexible tube portion 108 having flexibility is connected to the tip end side of the tube.
  • the endoscope 101 may have a form called a so-called rigid endoscope that does not include a flexible portion in the insertion portion 102.
  • An imaging device 1 having an imaging module 10 described later is provided at the distal end portion 110.
  • the operation unit 103 is provided with an angle operation knob 106 for operating the bending of the bending unit 109.
  • an endoscope connector 105 connected to the external device 120 is provided.
  • the external device 120 to which the endoscope connector 105 is connected is connected to an image display unit 121 such as a monitor via a cable.
  • the endoscope 101 includes an optical fiber bundle (not shown) that transmits illumination light from the universal cord 104, the operation unit 103, the composite cable 115 inserted into the insertion unit 102, and the light source unit provided in the external device 120. )have.
  • the composite cable 115 is configured to electrically connect the endoscope connector 105 and the imaging device 1. By connecting the endoscope connector 105 to the external device 120, the imaging device 1 is electrically connected to the external device 120 through the composite cable 115.
  • the power supply from the external device 120 to the imaging device 1 and the communication between the external device 120 and the imaging device 1 are performed via the composite cable 115.
  • the external device 120 is provided with an image processing unit 120a.
  • the image processing unit 120 a generates a video signal based on the image sensor output signal output from the imaging device 1 and outputs the video signal to the image display unit 121. That is, in the present embodiment, an optical image (endoscopic image) captured by the imaging device 1 is displayed on the image display unit 121 as a video.
  • the endoscope 101 is not limited to the configuration connected to the external device 120 or the image display unit 121, and may be configured to include a part or all of the image processing unit or the monitor, for example.
  • the optical fiber bundle is configured to transmit light emitted from the light source unit of the external device 120 to the illumination window as the illumination light emitting unit of the tip part 110.
  • the light source unit may be arranged on the operation unit 103 or the distal end portion 110 of the endoscope 101.
  • the configuration of the imaging module 10 provided in the imaging device 1 provided in the tip portion 110 will be described.
  • the object side direction (left side in each figure) from the imaging module 10 toward the subject may be referred to as the front end or the front, and the opposite image side direction may be referred to as the base end or the rear. .
  • the imaging apparatus 1 includes a CSP (Chip) in which a cover glass 12 is provided on the front side and an integrated circuit (IC chip) such as an image sensor chip and a driving circuit chip is stacked.
  • IC chip integrated circuit
  • a reinforcing resin that is connected to the base end side of the imaging module 10 and is formed of an adhesive or the like so as to cover the plurality of wirings 16 of the composite cable 115 extending rearward. Part 15.
  • the image sensor chip of the imaging module 10 is provided with a light receiving unit 11 that receives light of a subject image having a photographing optical axis O on the front side.
  • the image sensor chip is an image sensor chip such as a CCD or CMOS, and the above-described cover glass 12 is disposed on the front surface portion where the light receiving unit 11 is provided.
  • IC chip integrated circuit
  • driving circuit chip provided in the imaging module 10
  • the semiconductor element bonding structure 30 includes a first silicon wafer 31 and a second silicon wafer 41 as shown in FIGS.
  • the insulating film 32 is formed on the surface of the first silicon wafer 31 by thermal oxidation or the like, and here, a plurality of through-hole portions 33 shown in the figure are formed.
  • the plurality of through-hole portions 33 have a narrow pitch, they are formed by dry etching such as inductive coupling (ICP), and the insulating film 32 is formed on the inner peripheral surface by thermal oxidation or the like.
  • ICP inductive coupling
  • the first silicon wafer 31 is provided with a wiring electrode portion 34 formed by patterning with copper or the like around the plurality of through-hole portions 33 on the surface layer on the upper surface side.
  • the insulating film 42 is formed on the surface of the second silicon wafer 41 by thermal oxidation or the like, and a plurality of electrode posts 45 as metal pillars, two of which are shown here, are arranged on the surface layer portion on the upper surface side. It is installed.
  • the plurality of electrode posts 45 include a conductive metal portion 43 that is a pedestal metal formed from a conductive metal such as copper, nickel, and aluminum by electrolytic plating or the like on the surface layer portion of the second silicon wafer 41, and solder.
  • a molten metal portion 44 that is a low melting point metal formed from a molten metal having a low melting point temperature is sequentially laminated.
  • the conductive metal part 43 should just be a conductive metal whose melting
  • the plurality of electrode posts 45 are formed in a columnar shape, for example.
  • the plurality of electrode posts 45 may not have a cylindrical shape but may have a quadrangular prism shape, a triangular prism shape, or the like.
  • the through-hole portion 33 may be formed in a hole shape such as a columnar shape, a quadrangular prism, or a triangular prism in accordance with the shape of the electrode post 45.
  • the conductive metal portion 43 is formed with a height d2 lower than the thickness d1 of the first silicon wafer 31. Further, as shown in FIG. 4, the molten metal portion 44 has a predetermined length from the surface layer portion of the first silicon wafer 31 in a state where the first silicon wafer 31 and the second silicon wafer 41 are laminated. It is formed so as to have a height d3 that protrudes only.
  • the molten metal portion 44 protrudes from the surface layer portion of the first silicon wafer 31 in a state where the thickness d1 of the wafer 31 is longer and the first silicon wafer 31 and the second silicon wafer 41 are laminated.
  • the dimensions are set.
  • the plurality of electrode posts 45 are inserted into the plurality of through-hole portions 33 of the corresponding first silicon wafer 31 when the first silicon wafer 31 and the second silicon wafer 41 are stacked. It is formed at the position of the surface layer portion of the second silicon wafer 41.
  • a first silicon wafer 31 is laminated on a second silicon wafer 41 as shown in FIG.
  • the plurality of electrode posts 45 are inserted in alignment with the plurality of through-hole portions 33 of the corresponding first silicon wafer 31.
  • the base material on which the first silicon wafer 31 and the second silicon wafer 41 are laminated is heated to the melting temperature of the molten metal portions 44 of the plurality of electrode posts 45.
  • the molten metal portion 44 is melted at the portion protruding from the surface layer portion of the first silicon wafer 31, so that the plurality of through-hole portions 33 in the surface layer portion of the first silicon wafer 31 are melted.
  • a weld portion 44a is formed by welding to the wiring electrode portion 34 formed in the periphery.
  • the plurality of wiring electrode portions 34 of the first silicon wafer 31 and the plurality of electrode posts 45 of the second silicon wafer 41 are electrically connected.
  • the semiconductor element bonding structure 30 does not require a separate bump electrode as in the conventional method of manufacturing a semiconductor element that forms a through silicon via (TSV). Since electrical bonding can be performed simply by heating at the time of bonding a plurality of wafers, the number of manufacturing steps can be reduced as compared with the conventional method, and the manufacturing cost can be reduced.
  • TSV through silicon via
  • the semiconductor element bonding structure 30 can be manufactured at a low cost by reducing the number of manufacturing steps, and accordingly, the imaging module 10 and the endoscope having an integrated circuit (IC chip) using the semiconductor element bonding structure 30.
  • the manufacturing cost of 101 can also be reduced.
  • FIG. 6 is a cross-sectional view showing the semiconductor element bonding structure before the two wafers of the first modification are stacked
  • FIG. 7 is the semiconductor element bonding structure after the two wafers of the first modification are stacked
  • FIG. 8 is a cross-sectional view showing a semiconductor element bonding structure in which two wafers of a first modification are electrically bonded.
  • the second silicon wafer 41 is formed in the surface layer portion on the upper surface side.
  • the conductive metal portions 43 of the plurality of electrode posts 45 shown in the figure are convex in cross section.
  • the conductive metal portion 43 is inserted into the through-hole portion 33 integrally formed with the insertion metal portion 43a inserted into the through-hole portion 33 of the first silicon wafer 31 and the insertion metal portion 43a. And a base metal portion 43b as a spacer having a large outer diameter so as not to be formed.
  • the insertion metal part 43a of the conductive metal part 43 is formed with a height d2 lower than the thickness d1 of the first silicon wafer 31.
  • the base metal portion 43b of the conductive metal portion 43 is formed to have a predetermined height d5 of about several tens of micrometers.
  • the insertion metal part 43a has a base metal part 43b formed on the surface layer part of the second silicon wafer 41 by patterning a conductive metal such as copper by electrolytic plating, and the insertion metal part on the base metal part 43b. 43a is formed by patterning.
  • the insertion metal part 43a and the base metal part 43b are formed in a cylindrical shape, a quadrangular prism, a triangular prism, or a combination thereof.
  • the other components of the semiconductor element bonding structure 30 are the same as those in the above-described embodiment.
  • the plurality of electrode posts 45 are aligned with the plurality of through-hole portions 33 of the corresponding first silicon wafer 31, respectively.
  • a first silicon wafer 31 is stacked on the second silicon wafer 41.
  • the base material on which the first silicon wafer 31 and the second silicon wafer 41 are laminated is heated to the melting temperature of the molten metal portions 44 of the plurality of electrode posts 45.
  • the molten metal portion 44 is melted at a portion protruding from the surface layer portion of the first silicon wafer 31, so that the plurality of through-hole portions 33 in the surface layer portion of the first silicon wafer 31 are melted.
  • a weld portion 44a is formed by welding to the wiring electrode portion 34 formed in the periphery.
  • a gap serving as a spacer is formed between the first silicon wafer 31 and the second silicon wafer 41 by the height d5 of the base metal portion 43b of the conductive metal portion 43.
  • a gap of a predetermined distance (d5) is formed between the first silicon wafer 31 and the second silicon wafer 41, and the two wafers can be separated by a predetermined distance.
  • the surface area of the integrated circuit (IC chip) to be mounted is increased, and a heat dissipation effect can be expected.
  • the semiconductor element bonding structure 30 of the present modification is configured so that there is a gap between the first silicon wafer 31 and the second silicon wafer 41 and a predetermined distance (d5) can be maintained.
  • Other devices such as sensors such as MEMS can be provided on the surface layer of the wafer 41.
  • the semiconductor element bonding structure 30 of the present modification can improve the heat dissipation effect in addition to the above-described effects, and can also provide other devices on the second silicon wafer 41. It becomes the structure which can be done.
  • the plurality of electrode posts 45 can form a gap between the first silicon wafer 31 and the second silicon wafer 41 with no problem in strength, all the conductive metal portions 43 have a convex cross section. It does not have to be.
  • FIG. 9 is a cross-sectional view showing a semiconductor element bonding structure in which a heat radiating gel is disposed between two wafers of a second modification.
  • the semiconductor element bonding structure 30 of this modification example is further cooled in the gap between the first silicon wafer 31 and the second silicon wafer 41 as shown in FIG.
  • a heat radiating gel 46 which is a heat radiating member made of insulating resin, is provided to enhance the effect.
  • the heat radiating gel 46 may be formed on the surface layer of the second silicon wafer 41 at the wafer level by spinning, or filled at the integrated circuit (IC chip) level after the semiconductor element bonding structure 30 is separated. May be.
  • the semiconductor element bonding structure 30 can be further expected to have a heat radiation effect by the heat radiation gel 46.
  • FIG. 10 is a cross-sectional view showing a semiconductor element bonding structure before two wafers of the third modification are stacked
  • FIG. 11 is a semiconductor element bonding structure after two wafers of the third modification are stacked
  • FIG. 12 is a cross-sectional view showing a semiconductor element bonding structure in which two wafers of a third modification are electrically bonded.
  • the second silicon wafer 41 here is formed on the surface layer portion on the upper surface side, as in the first modification, and a plurality of electrode posts 45 shown here are convex in cross section. Yes.
  • the electrode post 45 is formed by patterning a base metal portion 47 as a base metal with a conductive metal such as copper, nickel, or aluminum on the surface layer portion of the second silicon wafer 41, The molten metal portion 44 to be inserted into the through hole portion 33 of the first silicon wafer 31 is patterned on the base metal portion 47 serving as a spacer.
  • the molten metal portion 44 is longer than the thickness d1 of the first silicon wafer 31, and the first silicon wafer 31 is in a state where the first silicon wafer 31 and the second silicon wafer 41 are laminated. It is formed so as to have a height d3 protruding from the surface layer portion by a predetermined length.
  • the base metal portion 47 is formed with a large outer diameter so as not to be inserted into the through-hole portion 33 and having a predetermined height d5 of about several tens of micrometers.
  • the other components of the semiconductor element bonding structure 30 are the same as those in the above-described embodiment.
  • a first silicon wafer 31 is stacked on the second silicon wafer 41.
  • the base material on which the first silicon wafer 31 and the second silicon wafer 41 are laminated is heated to the melting temperature of the molten metal portions 44 of the plurality of electrode posts 45.
  • the molten metal portion 44 is melted at a portion protruding from the surface layer portion of the first silicon wafer 31, so A weld portion 44a is formed by welding to the wiring electrode portion 34 formed in the periphery.
  • a gap can be formed between the first silicon wafer 31 and the second silicon wafer 41 by the height d5 of the base metal part 47, It can be set as the structure which has the effect similar to a 1st modification.
  • the third modification instead of sequentially forming the base metal part 43b and the insertion metal part 43a having different outer dimensions like the insertion metal part 43 of the first modification by patterning by electrolytic plating, Since the base metal part 47 may be formed, the number of manufacturing steps can be further reduced and the manufacturing cost can be reduced.
  • FIG. 13 is a cross-sectional view showing a semiconductor element bonding structure in which a heat radiating gel is disposed between two wafers of a fourth modification.
  • the semiconductor element bonding structure 30 includes a first silicon wafer 31 and a second silicon wafer 41 as shown in FIG. 13 as described in the second modification in the configuration of the third modification.
  • a heat radiating gel 46 which is a heat radiating member made of an insulating resin that enhances the cooling effect, may be provided in the gap between the radiating member and the gap.
  • the imaging module 10 It is effective for an integrated circuit (IC chip) on which an amplifier, a driver, etc., which generate a large amount of heat, such as an image sensor chip and a driving circuit chip provided in the circuit board, are mounted.
  • IC chip integrated circuit
  • the described requirements can be deleted if the stated problem can be solved and the stated effect can be obtained.
  • the configuration can be extracted as an invention.

Abstract

A semiconductor element bonding structure 30 is provided with: a first silicon wafer 31, on which an electrode 34 is formed around a through hole 33; and a second silicon wafer 41, on which the first silicon wafer 31 is laminated, and a metal column section 45 inserted and fitted in the through hole 33 is formed. The metal column section 41 is provided with: a pedestal metal 43 that is provided on the second silicon wafer 41; and a low-melting-point metal 44, which is configured such that the low-melting-point metal melts and is electrically connected to the electrode 34 of the first silicon wafer 31 by being laminated on the pedestal metal 43, said low-melting-point metal having a melting point temperature that is lower than that of the pedestal metal 43.

Description

半導体素子接合構造、撮像モジュールおよび内視鏡装置Semiconductor element junction structure, imaging module, and endoscope apparatus
　本発明は、例えば、撮像モジュールに用いられる集積回路に採用される半導体素子接合構造であって、撮像モジュールおよび撮像モジュールを備えた内視鏡装置に関する。 The present invention relates to an imaging device and an endoscope apparatus including the imaging module, for example, a semiconductor element junction structure employed in an integrated circuit used in the imaging module.
　生体の体内や構造物の内部などの観察が困難な箇所を観察するために、生体や構造物の外部から内部に導入可能であって、光学像を撮像するための撮像モジュールなどを具備した電子内視鏡が、例えば医療分野または工業分野において利用されている。 An electronic device equipped with an imaging module for capturing an optical image that can be introduced from the outside of the living body or structure in order to observe difficult places such as the inside of the living body or the inside of the structure. Endoscopes are used, for example, in the medical field or the industrial field.
　電子内視鏡の撮像ユニットは、被写体像を結像する対物レンズと、対物レンズの結像面に配設されたイメージセンサを具備している。 The imaging unit of the electronic endoscope includes an objective lens that forms a subject image and an image sensor disposed on the imaging surface of the objective lens.
　このようなイメージセンサには、例えば、特開２０１４－８６４９８号公報に開示されるような半導体素子が搭載されている。 In such an image sensor, for example, a semiconductor element as disclosed in Japanese Patent Application Laid-Open No. 2014-86498 is mounted.
　特開２０１４－８６４９８号公報に開示された半導体素子の製造方法では、上部ウエハにシリコン貫通電極（ＴＳＶ）およびバンプ電極を形成し、他のウエハを積層した後に、バンプ形成のためのシード層を除去する技術が開示されている。なお、ＴＳＶ形成は、Ｓｉ基板に貫通溝を形成し、側壁に絶縁膜を被覆した後、導電体を埋め込むとされている。 In the method for manufacturing a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2014-86498, a silicon through electrode (TSV) and a bump electrode are formed on an upper wafer, and after another wafer is laminated, a seed layer for bump formation is formed. Techniques for removal are disclosed. In TSV formation, a through groove is formed in a Si substrate, an insulating film is coated on a side wall, and then a conductor is embedded.
　しかしながら、従来の半導体素子の製造方法において、ＴＳＶ形成は工程が複雑であると共に、複数のウエハ積層のためのバンプを別途形成しなければならず製造時の工数が掛かりコスト高になるという課題がある。 However, in the conventional semiconductor device manufacturing method, TSV formation has a complicated process, and bumps for laminating a plurality of wafers must be separately formed. is there.
　そこで、本発明は、上述した課題に鑑みてなされたものであって、その目的とするところは、製造時の工数を低減して、安価に製造できる半導体素子接合構造、撮像モジュールおよび内視鏡装置を提供することである。 Accordingly, the present invention has been made in view of the above-described problems, and an object of the present invention is to reduce the number of man-hours at the time of manufacture and to manufacture a semiconductor element junction structure, an imaging module, and an endoscope that can be manufactured at low cost. Is to provide a device.
　本発明の一態様の半導体素子接合構造は、貫通孔部が形成され、表層部の前記貫通孔部の周囲に電極が形成された第１のシリコンウエハと、前記第１のシリコンウエハが積層され、前記貫通孔部に挿嵌する金属柱部が形成された第２のシリコンウエハと、を備え、前記金属柱部は、前記第２のシリコンウエハの表層部に設けられた台座金属と、前記台座金属に積層されて前記第１のシリコンウエハの前記電極に溶融して電気的に接合するように構成され、前記台座金属よりも融点温度の低い低融点金属と、を具備する。 In the semiconductor element bonding structure of one embodiment of the present invention, a first silicon wafer in which a through-hole portion is formed and an electrode is formed around the through-hole portion in a surface layer portion, and the first silicon wafer are stacked. A second silicon wafer formed with a metal pillar portion to be fitted into the through-hole portion, and the metal pillar portion is a base metal provided on a surface layer portion of the second silicon wafer; A low melting point metal that is laminated on a base metal and is melted and electrically joined to the electrode of the first silicon wafer and has a melting point lower than that of the base metal.
　本発明の一態様の撮像モジュールは、貫通孔部が形成され、表層部の前記貫通孔部の周囲に電極が形成された第１のシリコンウエハと、前記第１のシリコンウエハが積層され、前記貫通孔部に挿嵌する金属柱部が形成された第２のシリコンウエハと、を備え、前記金属柱部は、前記第２のシリコンウエハの表層部に設けられた台座金属と、前記台座金属に積層されて前記第１のシリコンウエハの前記電極に溶融して電気的に接合するように構成され、前記台座金属よりも融点温度の低い低融点金属と、を具備する半導体素子接合構造から形成された集積回路を有する。 The imaging module of one embodiment of the present invention includes a first silicon wafer in which a through-hole portion is formed and an electrode is formed around the through-hole portion in a surface layer portion, and the first silicon wafer is laminated, A second silicon wafer formed with a metal pillar portion to be inserted into the through-hole portion, the metal pillar portion being a base metal provided on a surface layer portion of the second silicon wafer, and the base metal And a low melting point metal having a melting point lower than that of the pedestal metal, and is formed from a semiconductor element bonding structure. Integrated circuit.
　本発明の一態様の内視鏡装置は、貫通孔部が形成され、表層部の前記貫通孔部の周囲に電極が形成された第１のシリコンウエハと、前記第１のシリコンウエハが積層され、前記貫通孔部に挿嵌する金属柱部が形成された第２のシリコンウエハと、を備え、前記金属柱部は、前記第２のシリコンウエハの表層部に設けられた台座金属と、前記台座金属に積層されて前記第１のシリコンウエハの前記電極に溶融して電気的に接合するように構成され、前記台座金属よりも融点温度の低い低融点金属と、を具備する半導体素子接合構造から形成された集積回路を有する撮像モジュールを具備する。 In an endoscope apparatus according to an aspect of the present invention, a first silicon wafer in which a through-hole portion is formed and an electrode is formed around the through-hole portion in a surface layer portion, and the first silicon wafer are stacked. A second silicon wafer formed with a metal pillar portion to be fitted into the through-hole portion, and the metal pillar portion is a base metal provided on a surface layer portion of the second silicon wafer; A semiconductor element bonding structure comprising: a low melting point metal that is laminated on a base metal and is melted and electrically bonded to the electrode of the first silicon wafer, and has a melting point lower than that of the base metal An imaging module having an integrated circuit formed from
　以上に記載の本発明によれば、製造時の工数を低減して、安価に製造できる半導体素子接合構造、撮像モジュールおよび内視鏡装置を実現可能である。 According to the present invention described above, it is possible to realize a semiconductor element junction structure, an imaging module, and an endoscope apparatus that can be manufactured at low cost by reducing the number of manufacturing steps.
本発明の一態様に係る内視鏡システムの構成を示す図The figure which shows the structure of the endoscope system which concerns on 1 aspect of this invention. 同、撮像装置の構成を示す斜視図The perspective view which shows the structure of an imaging device similarly 同、２つのウエハが積層される前の半導体素子接合構造を示す断面図Sectional drawing which shows the semiconductor element junction structure before two wafers are laminated | stacked the same 同、２つのウエハが積層された後の半導体素子接合構造を示す断面図Sectional drawing which shows the semiconductor element junction structure after two wafers were laminated | stacked the same 同、２つのウエハが電気的に接合された半導体素子接合構造を示す断面図Sectional drawing which shows the semiconductor element joining structure where the two wafers were electrically joined similarly 同、第１の変形例の２つのウエハが積層される前の半導体素子接合構造を示す断面図Sectional drawing which shows the semiconductor element junction structure before two wafers of a 1st modification are laminated | stacked equally 同、第１の変形例の２つのウエハが積層された後の半導体素子接合構造を示す断面図Sectional drawing which shows the semiconductor element junction structure after two wafers of a 1st modification were laminated | stacked equally 同、第１の変形例の２つのウエハが電気的に接合された半導体素子接合構造を示す断面図Sectional drawing which shows the semiconductor element junction structure where the two wafers of the 1st modification were electrically joined similarly 同、第２の変形例の２つのウエハ間に放熱ジェルが配設された半導体素子接合構造を示す断面図Sectional drawing which shows the semiconductor element junction structure by which the thermal radiation gel was arrange | positioned between the two wafers of the 2nd modification similarly 同、第３の変形例の２つのウエハが積層される前の半導体素子接合構造を示す断面図Sectional drawing which shows the semiconductor element junction structure before the two wafers of a 3rd modification are laminated | stacked similarly 同、第３の変形例の２つのウエハが積層された後の半導体素子接合構造を示す断面図Sectional drawing which shows the semiconductor element junction structure after two wafers of a 3rd modification were laminated | stacked similarly 同、第３の変形例の２つのウエハが電気的に接合された半導体素子接合構造を示す断面図Sectional drawing which shows the semiconductor element joining structure where the two wafers of the 3rd modification were electrically joined similarly 同、第４の変形例の２つのウエハ間に放熱ジェルが配設された半導体素子接合構造を示す断面図Sectional drawing which shows the semiconductor element junction structure by which the thermal radiation gel was arrange | positioned between the two wafers of the 4th modification similarly
　以下に、本発明の好ましい形態について図面を参照して説明する。なお、以下の説明に用いる各図においては、各構成要素を図面上で認識可能な程度の大きさとするため、構成要素毎に縮尺を異ならせてあるものであり、本発明は、これらの図に記載された構成要素の数量、構成要素の形状、構成要素の大きさの比率、および各構成要素の相対的な位置関係のみに限定されるものではない。また、以下の説明においては、図の紙面に向かって見た上下方向を構成要素の上部および下部として説明している場合がある。　
　先ず、本発明の一態様の半導体素子接合構造を用いた撮像モジュールを有する撮像装置１を具備する内視鏡装置について、図面に基づいて、以下に説明する。 Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the drawings used for the following description, the scale of each component is made different in order to make each component recognizable on the drawing. It is not limited only to the quantity of the component described in (1), the shape of the component, the ratio of the size of the component, and the relative positional relationship of each component. Moreover, in the following description, the up-down direction seen toward the paper surface of the figure may be described as the upper part and the lower part of the component.
First, an endoscope apparatus including an imaging device 1 having an imaging module using the semiconductor element bonding structure of one embodiment of the present invention will be described with reference to the drawings.
　なお、図１は、本発明の一態様に係る内視鏡システムの構成を示す図、図２は撮像装置の構成を示す斜視図、図３は２つのウエハが積層される前の半導体素子接合構造を示す断面図、図４は２つのウエハが積層された後の半導体素子接合構造を示す断面図、図５は２つのウエハが電気的に接合された半導体素子接合構造を示す断面図である。 1 is a diagram illustrating a configuration of an endoscope system according to one embodiment of the present invention, FIG. 2 is a perspective view illustrating a configuration of an imaging device, and FIG. 3 is a semiconductor element bonding before two wafers are stacked. FIG. 4 is a cross-sectional view showing a semiconductor element bonding structure after two wafers are stacked, and FIG. 5 is a cross-sectional view showing a semiconductor element bonding structure in which two wafers are electrically bonded. .
　先ず、図１を参照して、本発明に係る半導体素子接合構造を用いた撮像モジュールを有する撮像装置１を具備する内視鏡装置の構成の一例を説明する。 First, an example of the configuration of an endoscope apparatus including an imaging apparatus 1 having an imaging module using a semiconductor element junction structure according to the present invention will be described with reference to FIG.
　本実施形態の内視鏡装置（以下、内視鏡と略記）１０１は、人体などの被検体内に導入可能であって被検体内の所定の観察部位を光学的に撮像する構成を有している。 An endoscope apparatus (hereinafter abbreviated as an endoscope) 101 according to the present embodiment has a configuration that can be introduced into a subject such as a human body and optically images a predetermined observation site in the subject. ing.
　なお、内視鏡１０１が導入される被検体は、人体に限らず、他の生体であっても良いし、機械、建造物などの人工物であっても良い。 Note that the subject into which the endoscope 101 is introduced is not limited to a human body, and may be another living body or an artificial object such as a machine or a building.
　内視鏡１０１は、被検体の内部に導入される挿入部１０２と、この挿入部１０２の基端に位置する操作部１０３と、この操作部１０３の側部から延出するユニバーサルコード１０４とで主に構成されている。 The endoscope 101 includes an insertion portion 102 introduced into the subject, an operation portion 103 located at the proximal end of the insertion portion 102, and a universal cord 104 extending from a side portion of the operation portion 103. It is mainly composed.
　挿入部１０２は、先端に配設される先端部１１０、この先端部１１０の基端側に配設される湾曲自在な湾曲部１０９およびこの湾曲部１０９の基端側に配設され操作部１０３の先端側に接続される可撓性を有する可撓管部１０８が連設されて構成されている。 The insertion portion 102 includes a distal end portion 110 disposed at the distal end, a bendable bending portion 109 disposed on the proximal end side of the distal end portion 110, and an operation portion 103 disposed on the proximal end side of the bending portion 109. A flexible tube portion 108 having flexibility is connected to the tip end side of the tube.
　なお、内視鏡１０１は、挿入部１０２に可撓性を有する部位を具備しない、所謂硬性鏡と称される形態のものであってもよい。 The endoscope 101 may have a form called a so-called rigid endoscope that does not include a flexible portion in the insertion portion 102.
　先端部１１０には、後述の撮像モジュール１０を有する撮像装置１が設けられている。また、操作部１０３には、湾曲部１０９の湾曲を操作するためのアングル操作ノブ１０６が設けられている。 An imaging device 1 having an imaging module 10 described later is provided at the distal end portion 110. In addition, the operation unit 103 is provided with an angle operation knob 106 for operating the bending of the bending unit 109.
　ユニバーサルコード１０４の基端部には、外部装置１２０に接続される内視鏡コネクタ１０５が設けられている。内視鏡コネクタ１０５が接続される外部装置１２０は、モニタなどの画像表示部１２１にケーブルを介して接続されている。 At the proximal end of the universal cord 104, an endoscope connector 105 connected to the external device 120 is provided. The external device 120 to which the endoscope connector 105 is connected is connected to an image display unit 121 such as a monitor via a cable.
　また、内視鏡１０１は、ユニバーサルコード１０４、操作部１０３および挿入部１０２内に挿通された複合ケーブル１１５および外部装置１２０に設けられた光源部からの照明光を伝送する光ファイバ束（不図示）を有している。 The endoscope 101 includes an optical fiber bundle (not shown) that transmits illumination light from the universal cord 104, the operation unit 103, the composite cable 115 inserted into the insertion unit 102, and the light source unit provided in the external device 120. )have.
　複合ケーブル１１５は、内視鏡コネクタ１０５と撮像装置１とを電気的に接続するように構成されている。内視鏡コネクタ１０５が外部装置１２０に接続されることによって、撮像装置１は、複合ケーブル１１５を介して外部装置１２０に電気的に接続される。 The composite cable 115 is configured to electrically connect the endoscope connector 105 and the imaging device 1. By connecting the endoscope connector 105 to the external device 120, the imaging device 1 is electrically connected to the external device 120 through the composite cable 115.
　この複合ケーブル１１５を介して、外部装置１２０から撮像装置１への電力の供給および外部装置１２０と撮像装置１との間の通信が行われる。 The power supply from the external device 120 to the imaging device 1 and the communication between the external device 120 and the imaging device 1 are performed via the composite cable 115.
　外部装置１２０には、画像処理部１２０ａが設けられている。この画像処理部１２０ａは、撮像装置１から出力された撮像素子出力信号に基づいて映像信号を生成し、画像表示部１２１に出力する。即ち、本実施形態では、撮像装置１により撮像された光学像（内視鏡像）が、映像として画像表示部１２１に表示される。 The external device 120 is provided with an image processing unit 120a. The image processing unit 120 a generates a video signal based on the image sensor output signal output from the imaging device 1 and outputs the video signal to the image display unit 121. That is, in the present embodiment, an optical image (endoscopic image) captured by the imaging device 1 is displayed on the image display unit 121 as a video.
　なお、内視鏡１０１は、外部装置１２０または画像表示部１２１に接続する構成に限定されず、例えば、画像処理部またはモニタの一部または全部を有する構成であっても良い。 Note that the endoscope 101 is not limited to the configuration connected to the external device 120 or the image display unit 121, and may be configured to include a part or all of the image processing unit or the monitor, for example.
　また、光ファイバ束は、外部装置１２０の光源部から発せられた光を、先端部１１０の照明光出射部としての照明窓まで伝送するように構成されている。さらに、光源部は、内視鏡１０１の操作部１０３または先端部１１０に配設される構成であってもよい。 Also, the optical fiber bundle is configured to transmit light emitted from the light source unit of the external device 120 to the illumination window as the illumination light emitting unit of the tip part 110. Further, the light source unit may be arranged on the operation unit 103 or the distal end portion 110 of the endoscope 101.
　次に、先端部１１０に設けられる撮像装置１に設けられる撮像モジュール１０の構成を説明する。なお、以下の説明においては、撮像モジュール１０から被写体へ向かう物体側の方向（各図において左方）を先端または前方と称し、その反対の像側の方向を基端または後方と称する場合がある。 Next, the configuration of the imaging module 10 provided in the imaging device 1 provided in the tip portion 110 will be described. In the following description, the object side direction (left side in each figure) from the imaging module 10 toward the subject may be referred to as the front end or the front, and the opposite image side direction may be referred to as the base end or the rear. .
　図２に示すように、本実施の形態の撮像装置１は、前方側にカバーガラス１２が設けられ、イメージセンサチップ、駆動用回路チップなどの集積回路（ＩＣチップ）が積層されたＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋaｇｅ）の撮像モジュール１０を備え、この撮像モジュール１０の基端側に接続されて、後方に延出する複合ケーブル１１５の複数の配線１６を覆うように接着剤などによって形成された補強用樹脂部１５を有している。 As shown in FIG. 2, the imaging apparatus 1 according to the present embodiment includes a CSP (Chip) in which a cover glass 12 is provided on the front side and an integrated circuit (IC chip) such as an image sensor chip and a driving circuit chip is stacked. A reinforcing resin that is connected to the base end side of the imaging module 10 and is formed of an adhesive or the like so as to cover the plurality of wirings 16 of the composite cable 115 extending rearward. Part 15.
　なお、撮像モジュール１０のイメージセンサチップには、前面側に撮影光軸Ｏを有する被写体像の光を受光する受光部１１が配設されている。このイメージセンサチップは、ＣＣＤ、ＣＭＯＳなどの撮像素子チップであって、受光部１１が設けられた先面部に上述のカバーガラス１２が配設されている。 Note that the image sensor chip of the imaging module 10 is provided with a light receiving unit 11 that receives light of a subject image having a photographing optical axis O on the front side. The image sensor chip is an image sensor chip such as a CCD or CMOS, and the above-described cover glass 12 is disposed on the front surface portion where the light receiving unit 11 is provided.
　次に、撮像モジュール１０に設けられるイメージセンサチップ、駆動用回路チップなどの集積回路（ＩＣチップ）を製造する際に、積層する複数のウエハを電気的に接合する半導体素子接合構造について、以下に詳しく説明する。なお、これら集積回路（ＩＣチップ）は、半導体素子接合構造である積層した複数のウエハをダイシングして個片化することで製造したものでも良いことは言うまでもない。 Next, a semiconductor element bonding structure for electrically bonding a plurality of stacked wafers when manufacturing an integrated circuit (IC chip) such as an image sensor chip and a driving circuit chip provided in the imaging module 10 will be described below. explain in detail. Needless to say, these integrated circuits (IC chips) may be manufactured by dicing a plurality of stacked wafers having a semiconductor element bonding structure into individual pieces.
　本実施の形態の半導体素子接合構造３０は、図３から図５に示すように、第１のシリコンウエハ３１と、第２のシリコンウエハ４１と、を有している。 The semiconductor element bonding structure 30 according to the present embodiment includes a first silicon wafer 31 and a second silicon wafer 41 as shown in FIGS.
　第１のシリコンウエハ３１は、熱酸化などにより絶縁膜３２が表面に形成されており、ここでは２つが図示されている複数の貫通孔部３３が形成されている。 The insulating film 32 is formed on the surface of the first silicon wafer 31 by thermal oxidation or the like, and here, a plurality of through-hole portions 33 shown in the figure are formed.
　なお、複数の貫通孔部３３は、挟ピッチであるため、誘導結合方式（ＩＣＰ）などのドライエッチングにより形成され、内周面に熱酸化などによって上述の絶縁膜３２が形成されている。なお、複数の貫通孔部３３は、挟ピッチでない場合には、誘導結合方式（ＩＣＰ）などのドライエッチングでなくとも、如何なる穿孔工法を採用してもよい。 Since the plurality of through-hole portions 33 have a narrow pitch, they are formed by dry etching such as inductive coupling (ICP), and the insulating film 32 is formed on the inner peripheral surface by thermal oxidation or the like. In addition, as long as the through-hole part 33 is not pinching pitch, what kind of perforation construction method may be employ | adopted even if it is not dry etching, such as an inductive coupling method (ICP).
　第１のシリコンウエハ３１は、上面側の表層に、複数の貫通孔部３３の周辺に銅などによりパターニング形成された配線電極部３４が設けられている。 The first silicon wafer 31 is provided with a wiring electrode portion 34 formed by patterning with copper or the like around the plurality of through-hole portions 33 on the surface layer on the upper surface side.
　第２のシリコンウエハ４１は、熱酸化などにより絶縁膜４２が表面に形成されており、上面側の表層部に、ここでは２つが図示されている金属柱部としての複数の電極ポスト４５が配設されている。 The insulating film 42 is formed on the surface of the second silicon wafer 41 by thermal oxidation or the like, and a plurality of electrode posts 45 as metal pillars, two of which are shown here, are arranged on the surface layer portion on the upper surface side. It is installed.
　これら複数の電極ポスト４５は、第２のシリコンウエハ４１の表層部に電解メッキなどによって銅、ニッケル、アルミなどの導電性金属から形成された台座金属となる導電性金属部４３と、はんだなどの低融点温度を有する溶融金属から形成された低融点金属となる溶融金属部４４が順に積層されている。なお、導電性金属部４３は、溶融金属部４４よりも融点温度が高い導電性金属であればよい。 The plurality of electrode posts 45 include a conductive metal portion 43 that is a pedestal metal formed from a conductive metal such as copper, nickel, and aluminum by electrolytic plating or the like on the surface layer portion of the second silicon wafer 41, and solder. A molten metal portion 44 that is a low melting point metal formed from a molten metal having a low melting point temperature is sequentially laminated. In addition, the conductive metal part 43 should just be a conductive metal whose melting | fusing point temperature is higher than the molten metal part 44. FIG.
　複数の電極ポスト４５は、例えば円柱状に形成されている。なお、複数の電極ポスト４５は、円柱状でなくとも四角柱、三角柱などの形状としてもよい。また、貫通孔部３３は、電極ポスト４５の形状に合わせて、円柱状、四角柱、三角柱などの孔形状にすればよい。 The plurality of electrode posts 45 are formed in a columnar shape, for example. The plurality of electrode posts 45 may not have a cylindrical shape but may have a quadrangular prism shape, a triangular prism shape, or the like. Further, the through-hole portion 33 may be formed in a hole shape such as a columnar shape, a quadrangular prism, or a triangular prism in accordance with the shape of the electrode post 45.
　導電性金属部４３は、第１のシリコンウエハ３１の厚さｄ１よりも高さｄ２が低く形成される。また、溶融金属部４４は、図４に示すように、第１のシリコンウエハ３１と第２のシリコンウエハ４１とが積層された状態において、第１のシリコンウエハ３１の表層部から所定の長さだけ突出する高さｄ３を有するように形成される。 The conductive metal portion 43 is formed with a height d2 lower than the thickness d1 of the first silicon wafer 31. Further, as shown in FIG. 4, the molten metal portion 44 has a predetermined length from the surface layer portion of the first silicon wafer 31 in a state where the first silicon wafer 31 and the second silicon wafer 41 are laminated. It is formed so as to have a height d3 that protrudes only.
　即ち、複数の電極ポスト４５は、その高さｄ４が導電性金属部４３の高さｄ２と溶融金属部４４の高さｄ３との和（ｄ４＝ｄ２+ｄ３）であって、第１のシリコンウエハ３１の厚さｄ１よりも長く、第１のシリコンウエハ３１と第２のシリコンウエハ４１とが積層された状態において、溶融金属部４４が第１のシリコンウエハ３１の表層部から突出するように寸法が設定されている。 That is, the plurality of electrode posts 45 has a height d4 that is the sum of the height d2 of the conductive metal portion 43 and the height d3 of the molten metal portion 44 (d4 = d2 + d3), and the first silicon The molten metal portion 44 protrudes from the surface layer portion of the first silicon wafer 31 in a state where the thickness d1 of the wafer 31 is longer and the first silicon wafer 31 and the second silicon wafer 41 are laminated. The dimensions are set.
　なお、複数の電極ポスト４５は、第１のシリコンウエハ３１と第２のシリコンウエハ４１とを積層する際に、それぞれ対応する第１のシリコンウエハ３１の複数の貫通孔部３３に挿嵌される第２のシリコンウエハ４１の表層部の位置に形成されている。 The plurality of electrode posts 45 are inserted into the plurality of through-hole portions 33 of the corresponding first silicon wafer 31 when the first silicon wafer 31 and the second silicon wafer 41 are stacked. It is formed at the position of the surface layer portion of the second silicon wafer 41.
　以上のように構成された半導体素子接合構造３０は、図４に示すように、第２のシリコンウエハ４１上に第１のシリコンウエハ３１が積層される。 In the semiconductor element bonding structure 30 configured as described above, a first silicon wafer 31 is laminated on a second silicon wafer 41 as shown in FIG.
　このとき、複数の電極ポスト４５は、それぞれ対応する第１のシリコンウエハ３１の複数の貫通孔部３３に位置合わせされて挿嵌される。 At this time, the plurality of electrode posts 45 are inserted in alignment with the plurality of through-hole portions 33 of the corresponding first silicon wafer 31.
　そして、第１のシリコンウエハ３１と第２のシリコンウエハ４１とが積層された基材を複数の電極ポスト４５の溶融金属部４４の溶融温度まで加熱させる。 Then, the base material on which the first silicon wafer 31 and the second silicon wafer 41 are laminated is heated to the melting temperature of the molten metal portions 44 of the plurality of electrode posts 45.
　これにより、溶融金属部４４は、図５に示すように、第１のシリコンウエハ３１の表層部から突出した部分が溶融して第１のシリコンウエハ３１の表層部の複数の貫通孔部３３の周辺に形成された配線電極部３４に溶着して溶着部４４ａが形成される。 As a result, as shown in FIG. 5, the molten metal portion 44 is melted at the portion protruding from the surface layer portion of the first silicon wafer 31, so that the plurality of through-hole portions 33 in the surface layer portion of the first silicon wafer 31 are melted. A weld portion 44a is formed by welding to the wiring electrode portion 34 formed in the periphery.
　したがって、第１のシリコンウエハ３１の複数の配線電極部３４と第２のシリコンウエハ４１の複数の電極ポスト４５が電気的に接続される。 Therefore, the plurality of wiring electrode portions 34 of the first silicon wafer 31 and the plurality of electrode posts 45 of the second silicon wafer 41 are electrically connected.
　以上に説明したように、本実施の形態の半導体素子接合構造３０は、従来のようなシリコン貫通電極（ＴＳＶ）を形成する半導体素子の製造方法のように別途バンプ電極を形成する必要が無く、複数のウエハの接合時に加熱するだけで電気的な接合が行えるため、従来に比して製造工数が低減し、製造コストを低減することができる。 As described above, the semiconductor element bonding structure 30 according to the present embodiment does not require a separate bump electrode as in the conventional method of manufacturing a semiconductor element that forms a through silicon via (TSV). Since electrical bonding can be performed simply by heating at the time of bonding a plurality of wafers, the number of manufacturing steps can be reduced as compared with the conventional method, and the manufacturing cost can be reduced.
　したがって、半導体素子接合構造３０は、製造時の工数を低減して、安価に製造でき、それに伴い、この半導体素子接合構造３０を用いた集積回路（ＩＣチップ）を有する撮像モジュール１０および内視鏡１０１の製造コストも低減することができる。 Therefore, the semiconductor element bonding structure 30 can be manufactured at a low cost by reducing the number of manufacturing steps, and accordingly, the imaging module 10 and the endoscope having an integrated circuit (IC chip) using the semiconductor element bonding structure 30. The manufacturing cost of 101 can also be reduced.
（第１の変形例）
　次に、撮像モジュール１０に設けられるイメージセンサチップ、駆動用回路チップなどを製造する際に、積層する複数のウエハを電気的に接合する半導体素子接合構造３０の第１の変形例について、以下に詳しく説明する。 (First modification)
Next, a first modification of the semiconductor element bonding structure 30 that electrically bonds a plurality of stacked wafers when manufacturing an image sensor chip, a driving circuit chip, and the like provided in the imaging module 10 will be described below. explain in detail.
　図６は、第１の変形例の２つのウエハが積層される前の半導体素子接合構造を示す断面図、図７は第１の変形例の２つのウエハが積層された後の半導体素子接合構造を示す断面図、図８は第１の変形例の２つのウエハが電気的に接合された半導体素子接合構造を示す断面図である。 FIG. 6 is a cross-sectional view showing the semiconductor element bonding structure before the two wafers of the first modification are stacked, and FIG. 7 is the semiconductor element bonding structure after the two wafers of the first modification are stacked. FIG. 8 is a cross-sectional view showing a semiconductor element bonding structure in which two wafers of a first modification are electrically bonded.
　ここでの第２のシリコンウエハ４１は、上面側の表層部に形成される、ここでは２つが図示されている複数の電極ポスト４５の導電性金属部４３が断面凸形状となっている。 Here, the second silicon wafer 41 is formed in the surface layer portion on the upper surface side. Here, the conductive metal portions 43 of the plurality of electrode posts 45 shown in the figure are convex in cross section.
　具体的には、導電性金属部４３は、第１のシリコンウエハ３１の貫通孔部３３に挿嵌される挿通金属部４３ａと、この挿通金属部４３ａに一体形成されて貫通孔部３３に挿通しないように外径寸法が大きく形成されたスペーサとしての土台金属部４３ｂと、を有している。 Specifically, the conductive metal portion 43 is inserted into the through-hole portion 33 integrally formed with the insertion metal portion 43a inserted into the through-hole portion 33 of the first silicon wafer 31 and the insertion metal portion 43a. And a base metal portion 43b as a spacer having a large outer diameter so as not to be formed.
　そして、導電性金属部４３の挿通金属部４３ａは、第１のシリコンウエハ３１の厚さｄ１よりも高さｄ２が低く形成される。また、導電性金属部４３の土台金属部４３ｂは、およそ数十マイクロメートルの所定の高さｄ５を有して形成される。 The insertion metal part 43a of the conductive metal part 43 is formed with a height d2 lower than the thickness d1 of the first silicon wafer 31. The base metal portion 43b of the conductive metal portion 43 is formed to have a predetermined height d5 of about several tens of micrometers.
　挿通金属部４３ａは、銅などの導電性金属を電解メッキによるパターンニングによって、先に土台金属部４３ｂが第２のシリコンウエハ４１の表層部に形成し、この土台金属部４３ｂ上に挿通金属部４３ａがパターンニングによって形成される。 The insertion metal part 43a has a base metal part 43b formed on the surface layer part of the second silicon wafer 41 by patterning a conductive metal such as copper by electrolytic plating, and the insertion metal part on the base metal part 43b. 43a is formed by patterning.
　ここでも、挿通金属部４３ａおよび土台金属部４３ｂは、円柱状、四角柱、三角柱などの形状、またはそれらを組み合わせた形状に形成されている。なお、その他の半導体素子接合構造３０の構成要素は、上述の実施の形態と同じである。 Also here, the insertion metal part 43a and the base metal part 43b are formed in a cylindrical shape, a quadrangular prism, a triangular prism, or a combination thereof. The other components of the semiconductor element bonding structure 30 are the same as those in the above-described embodiment.
　本変形例の半導体素子接合構造３０は、図６から図７に示すように、複数の電極ポスト４５が、それぞれ対応する第１のシリコンウエハ３１の複数の貫通孔部３３に位置合わせされて、第２のシリコンウエハ４１上に第１のシリコンウエハ３１が積層される。 As shown in FIGS. 6 to 7, in the semiconductor element bonding structure 30 of this modification, the plurality of electrode posts 45 are aligned with the plurality of through-hole portions 33 of the corresponding first silicon wafer 31, respectively. A first silicon wafer 31 is stacked on the second silicon wafer 41.
　そして、第１のシリコンウエハ３１と第２のシリコンウエハ４１とが積層された基材を複数の電極ポスト４５の溶融金属部４４の溶融温度まで加熱させる。 Then, the base material on which the first silicon wafer 31 and the second silicon wafer 41 are laminated is heated to the melting temperature of the molten metal portions 44 of the plurality of electrode posts 45.
　これにより、溶融金属部４４は、図８に示すように、第１のシリコンウエハ３１の表層部から突出した部分が溶融して第１のシリコンウエハ３１の表層部の複数の貫通孔部３３の周辺に形成された配線電極部３４に溶着して溶着部４４ａが形成される。 As a result, as shown in FIG. 8, the molten metal portion 44 is melted at a portion protruding from the surface layer portion of the first silicon wafer 31, so that the plurality of through-hole portions 33 in the surface layer portion of the first silicon wafer 31 are melted. A weld portion 44a is formed by welding to the wiring electrode portion 34 formed in the periphery.
　ここでの半導体素子接合構造３０では、第１のシリコンウエハ３１と第２のシリコンウエハ４１との間に導電性金属部４３の土台金属部４３ｂの高さｄ５だけスペーサとなる隙間ができる。 In the semiconductor element bonding structure 30 here, a gap serving as a spacer is formed between the first silicon wafer 31 and the second silicon wafer 41 by the height d5 of the base metal portion 43b of the conductive metal portion 43.
　このように、第１のシリコンウエハ３１と第２のシリコンウエハ４１との間に所定の距離（ｄ５）の隙間ができ２つのウエハを所定の距離だけ離間させることができるため、撮像モジュール１０に実装される集積回路（ＩＣチップ）の表面積が増え、放熱効果が期待できる。 As described above, a gap of a predetermined distance (d5) is formed between the first silicon wafer 31 and the second silicon wafer 41, and the two wafers can be separated by a predetermined distance. The surface area of the integrated circuit (IC chip) to be mounted is increased, and a heat dissipation effect can be expected.
　さらに、本変形例の半導体素子接合構造３０は、第１のシリコンウエハ３１と第２のシリコンウエハ４１との間に隙間があり所定の距離（ｄ５）を保てる構成であるため、第２のシリコンウエハ４１の表層上に他のデバイス、例えばＭＥＭＳなどのセンサを設けることができる。 Further, the semiconductor element bonding structure 30 of the present modification is configured so that there is a gap between the first silicon wafer 31 and the second silicon wafer 41 and a predetermined distance (d5) can be maintained. Other devices such as sensors such as MEMS can be provided on the surface layer of the wafer 41.
　以上に説明したように、本変形例の半導体素子接合構造３０は、上述した作用効果に加え、放熱効果を向上させることができるほか、第２のシリコンウエハ４１上に他のデバイスを設けることもできる構成となる。 As described above, the semiconductor element bonding structure 30 of the present modification can improve the heat dissipation effect in addition to the above-described effects, and can also provide other devices on the second silicon wafer 41. It becomes the structure which can be done.
　なお、複数の電極ポスト４５は、第１のシリコンウエハ３１と第２のシリコンウエハ４１との間に、強度的に問題がなく隙間が形成できれば、全ての導電性金属部４３が断面凸形状でなくてもよい。 If the plurality of electrode posts 45 can form a gap between the first silicon wafer 31 and the second silicon wafer 41 with no problem in strength, all the conductive metal portions 43 have a convex cross section. It does not have to be.
（第２の変形例）
　次に、撮像モジュール１０に設けられるイメージセンサチップ、駆動用回路チップなどを製造する際に、積層する複数のウエハを電気的に接合する半導体素子接合構造３０の第２の変形例について説明する。 (Second modification)
Next, a second modification of the semiconductor element bonding structure 30 that electrically bonds a plurality of wafers to be stacked when manufacturing an image sensor chip, a driving circuit chip, and the like provided in the imaging module 10 will be described.
　図９は、第２の変形例の２つのウエハ間に放熱ジェルが配設された半導体素子接合構造を示す断面図である。 FIG. 9 is a cross-sectional view showing a semiconductor element bonding structure in which a heat radiating gel is disposed between two wafers of a second modification.
　本変形例の半導体素子接合構造３０は、第１の変形例の構成に加え、さらに、図９に示すように、第１のシリコンウエハ３１と第２のシリコンウエハ４１との間の隙間に冷却効果を高める絶縁樹脂製の放熱部材である放熱ジェル４６が設けられている。 In addition to the configuration of the first modification example, the semiconductor element bonding structure 30 of this modification example is further cooled in the gap between the first silicon wafer 31 and the second silicon wafer 41 as shown in FIG. A heat radiating gel 46, which is a heat radiating member made of insulating resin, is provided to enhance the effect.
　この放熱ジェル４６は、第２のシリコンウエハ４１の表層上にスピニングによりウエハレベルで形成してもよいし、半導体素子接合構造３０を個片化した後の集積回路（ＩＣチップ）レベルで充填形成してもよい。 The heat radiating gel 46 may be formed on the surface layer of the second silicon wafer 41 at the wafer level by spinning, or filled at the integrated circuit (IC chip) level after the semiconductor element bonding structure 30 is separated. May be.
　このような構成とすることで、半導体素子接合構造３０は、放熱ジェル４６により、さらに放熱効果が期待できる。 By adopting such a configuration, the semiconductor element bonding structure 30 can be further expected to have a heat radiation effect by the heat radiation gel 46.
（第３の変形例）
　次に、撮像モジュール１０に設けられるイメージセンサチップ、駆動用回路チップなどを製造する際に、積層する複数のウエハを電気的に接合する半導体素子接合構造３０の第３の変形例について説明する。 (Third Modification)
Next, a third modified example of the semiconductor element bonding structure 30 that electrically bonds a plurality of stacked wafers when manufacturing an image sensor chip, a driving circuit chip, and the like provided in the imaging module 10 will be described.
　図１０は、第３の変形例の２つのウエハが積層される前の半導体素子接合構造を示す断面図、図１１は第３の変形例の２つのウエハが積層された後の半導体素子接合構造を示す断面図、図１２は第３の変形例の２つのウエハが電気的に接合された半導体素子接合構造を示す断面図である。 FIG. 10 is a cross-sectional view showing a semiconductor element bonding structure before two wafers of the third modification are stacked, and FIG. 11 is a semiconductor element bonding structure after two wafers of the third modification are stacked. FIG. 12 is a cross-sectional view showing a semiconductor element bonding structure in which two wafers of a third modification are electrically bonded.
　ここでの第２のシリコンウエハ４１は、第１の変形例と同様に、上面側の表層部に形成される、ここでは２つが図示されている複数の電極ポスト４５が断面凸形状となっている。 The second silicon wafer 41 here is formed on the surface layer portion on the upper surface side, as in the first modification, and a plurality of electrode posts 45 shown here are convex in cross section. Yes.
　具体的には、電極ポスト４５は、第２のシリコンウエハ４１の表層部に例えば、銅、ニッケル、アルミなどの導電性金属によって台座金属としての土台金属部４７をパターンニング形成し、ここでのスペーサとなる土台金属部４７上に第１のシリコンウエハ３１の貫通孔部３３に挿嵌される溶融金属部４４をパターンニング形成した構成となっている。 Specifically, the electrode post 45 is formed by patterning a base metal portion 47 as a base metal with a conductive metal such as copper, nickel, or aluminum on the surface layer portion of the second silicon wafer 41, The molten metal portion 44 to be inserted into the through hole portion 33 of the first silicon wafer 31 is patterned on the base metal portion 47 serving as a spacer.
　ここでの溶融金属部４４は、第１のシリコンウエハ３１の厚さｄ１よりも長く、第１のシリコンウエハ３１と第２のシリコンウエハ４１とが積層された状態において、第１のシリコンウエハ３１の表層部から所定の長さだけ突出する高さｄ３を有するように形成される。 Here, the molten metal portion 44 is longer than the thickness d1 of the first silicon wafer 31, and the first silicon wafer 31 is in a state where the first silicon wafer 31 and the second silicon wafer 41 are laminated. It is formed so as to have a height d3 protruding from the surface layer portion by a predetermined length.
　そして、ここでも、土台金属部４７は、貫通孔部３３に挿通しないように外径寸法が大きく、およそ数十マイクロメートルの所定の高さｄ５を有して形成される。なお、その他の半導体素子接合構造３０の構成要素は、上述の実施の形態と同じである。 Also here, the base metal portion 47 is formed with a large outer diameter so as not to be inserted into the through-hole portion 33 and having a predetermined height d5 of about several tens of micrometers. The other components of the semiconductor element bonding structure 30 are the same as those in the above-described embodiment.
　本変形例の半導体素子接合構造３０は、図１０から図１１に示すように、複数の電極ポスト４５が、それぞれ対応する第１のシリコンウエハ３１の複数の貫通孔部３３に位置合わせされて、第２のシリコンウエハ４１上に第１のシリコンウエハ３１が積層される。 As shown in FIG. 10 to FIG. A first silicon wafer 31 is stacked on the second silicon wafer 41.
　そして、第１のシリコンウエハ３１と第２のシリコンウエハ４１とが積層された基材を複数の電極ポスト４５の溶融金属部４４の溶融温度まで加熱させる。 Then, the base material on which the first silicon wafer 31 and the second silicon wafer 41 are laminated is heated to the melting temperature of the molten metal portions 44 of the plurality of electrode posts 45.
　これにより、溶融金属部４４は、図１２に示すように、第１のシリコンウエハ３１の表層部から突出した部分が溶融して第１のシリコンウエハ３１の表層部の複数の貫通孔部３３の周辺に形成された配線電極部３４に溶着して溶着部４４ａが形成される。 As a result, as shown in FIG. 12, the molten metal portion 44 is melted at a portion protruding from the surface layer portion of the first silicon wafer 31, so A weld portion 44a is formed by welding to the wiring electrode portion 34 formed in the periphery.
　このような構成としても、第１の変形例と同様に、第１のシリコンウエハ３１と第２のシリコンウエハ４１との間に土台金属部４７の高さｄ５だけ隙間を形成することができ、第１の変形例と同様の作用効果を有する構成とすることができる。 Even with such a configuration, as in the first modification, a gap can be formed between the first silicon wafer 31 and the second silicon wafer 41 by the height d5 of the base metal part 47, It can be set as the structure which has the effect similar to a 1st modification.
　さらに、第３の変形例では、第１の変形例の挿通金属部４３のように外形寸法の異なる土台金属部４３ｂおよび挿通金属部４３ａを電解メッキによるパターンニングによって順次形成するかわりに、１つの土台金属部４７を形成すれば良いので、より製造工数が低減し、製造コストを低減することができる。 Further, in the third modification, instead of sequentially forming the base metal part 43b and the insertion metal part 43a having different outer dimensions like the insertion metal part 43 of the first modification by patterning by electrolytic plating, Since the base metal part 47 may be formed, the number of manufacturing steps can be further reduced and the manufacturing cost can be reduced.
（第４の変形例）
　図１３は、第４の変形例の２つのウエハ間に放熱ジェルが配設された半導体素子接合構造を示す断面図である。 (Fourth modification)
FIG. 13 is a cross-sectional view showing a semiconductor element bonding structure in which a heat radiating gel is disposed between two wafers of a fourth modification.
　なお、半導体素子接合構造３０は、第３の変形例の構成に第２の変形例に記載したように、さらに、図１３に示すように、第１のシリコンウエハ３１と第２のシリコンウエハ４１との間の隙間に冷却効果を高める絶縁樹脂製の放熱部材である放熱ジェル４６を設けてもよい。 The semiconductor element bonding structure 30 includes a first silicon wafer 31 and a second silicon wafer 41 as shown in FIG. 13 as described in the second modification in the configuration of the third modification. A heat radiating gel 46, which is a heat radiating member made of an insulating resin that enhances the cooling effect, may be provided in the gap between the radiating member and the gap.
　以上に記載の第１～第４の変形例に記載したような第１のシリコンウエハ３１と第２のシリコンウエハ４１との間の隙間を設けることで冷却効果を高めた構成では、撮像モジュール１０に設けられるイメージセンサチップ、駆動用回路チップなどの特に発熱量の多いアンプ、ドライバなどを搭載した集積回路（ＩＣチップ）に有効となる。 In the configuration in which the cooling effect is enhanced by providing a gap between the first silicon wafer 31 and the second silicon wafer 41 as described in the first to fourth modifications described above, the imaging module 10 It is effective for an integrated circuit (IC chip) on which an amplifier, a driver, etc., which generate a large amount of heat, such as an image sensor chip and a driving circuit chip provided in the circuit board, are mounted.
　以上に記載した実施の形態および各変形例は、それぞれの構成を組み合わせてもよい。即ち、上述の実施の形態に記載した発明は、その実施の形態および変形例に限ることなく、その他、実施段階ではその要旨を逸脱しない範囲で種々の変形を実施し得ることが可能である。　
　また、上記実施の形態は、シリコンウエハを用いて説明したが、これに限ることなく、その他の半導体ウエハ、例えばＳｉＯ（シリコンカーバイド）ウエハ等の化合物半導体ウエハでも実施することは可能である。 The embodiment and each modification described above may be combined with each other. That is, the invention described in the above-described embodiment is not limited to the embodiment and modification examples, and various modifications can be made without departing from the scope of the invention in the implementation stage.
Although the above embodiment has been described using a silicon wafer, the present invention is not limited to this, and the present invention can also be implemented with other semiconductor wafers such as a compound semiconductor wafer such as a SiO (silicon carbide) wafer.
　さらに、上記実施の形態には、種々の段階の発明が含まれており、開示される複数の構成要件における適宜な組合せにより種々の発明が抽出され得るものである。 Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements.
　例えば、実施の形態に示される全構成要件から幾つかの構成要件が削除されても、述べられている課題が解決でき、述べられている効果が得られる場合には、この構成要件が削除された構成が発明として抽出され得るものである。 For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the described requirements can be deleted if the stated problem can be solved and the stated effect can be obtained. The configuration can be extracted as an invention.

Claims (6)

  1. 　貫通孔部が形成され、表層部の前記貫通孔部の周囲に電極が形成された第１のシリコンウエハと、
    　前記第１のシリコンウエハが積層され、前記貫通孔部に挿嵌する金属柱部が形成された第２のシリコンウエハと、
    　を備え、
    　前記金属柱部は、前記第２のシリコンのウエハの表層部に設けられた台座金属と、前記台座金属に積層されて前記第１のシリコンウエハの前記電極に溶融して電気的に接合されており、前記台座金属よりも融点温度の低い低融点金属と、を具備することを特徴とする半導体素子接合構造。     A first silicon wafer in which a through-hole portion is formed and an electrode is formed around the through-hole portion in the surface layer portion;
    A second silicon wafer in which the first silicon wafer is laminated and a metal pillar portion to be inserted into the through-hole portion is formed;
    With
    The metal column portion is a base metal provided on a surface layer portion of the second silicon wafer, and is laminated on the base metal and melted and electrically joined to the electrode of the first silicon wafer. And a low melting point metal having a melting point lower than that of the base metal.
  2. 　前記台座金属は、前記第１のシリコンウエハの厚さよりも低い高さを有していることを特徴とする請求項１に記載の半導体素子接合構造。 2. The semiconductor element bonding structure according to claim 1, wherein the base metal has a height lower than a thickness of the first silicon wafer.
  3. 　前記低融点金属は、前記第１のシリコンウエハの表層部から突出する高さを有していることを特徴とする請求項１または請求項２に記載の半導体素子接合構造。 3. The semiconductor element bonding structure according to claim 1, wherein the low melting point metal has a height protruding from a surface layer portion of the first silicon wafer.
  4. 　前記台座金属は、前記第１のシリコンウエハと前記第２のシリコンウエハとの間に所定の距離の隙間を形成し、前記貫通孔部よりも外形が大きく形成されたスペーサを有していることを特徴とする請求項１から請求項３のいずれか１項に記載の半導体素子接合構造。 The base metal has a spacer that forms a gap of a predetermined distance between the first silicon wafer and the second silicon wafer, and has an outer shape larger than the through-hole portion. The semiconductor element junction structure according to any one of claims 1 to 3, wherein:
  5. 　請求項１から請求項４のいずれか１項に記載の半導体素子接合構造によって形成された集積回路を備えたことを特徴とする撮像モジュール。 An imaging module comprising an integrated circuit formed by the semiconductor element junction structure according to any one of claims 1 to 4.
  6. 　請求項５に記載の撮像モジュールを備えたことを特徴とする内視鏡装置。 An endoscope apparatus comprising the imaging module according to claim 5.
PCT/JP2016/061711 2016-04-11 2016-04-11 Semiconductor element bonding structure, image pickup module, and endoscope device WO2017179104A1 (en)

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