WO2017173613A1 - Tsv structure planarization process and apparatus - Google Patents

Tsv structure planarization process and apparatus Download PDF

Info

Publication number
WO2017173613A1
WO2017173613A1 PCT/CN2016/078656 CN2016078656W WO2017173613A1 WO 2017173613 A1 WO2017173613 A1 WO 2017173613A1 CN 2016078656 W CN2016078656 W CN 2016078656W WO 2017173613 A1 WO2017173613 A1 WO 2017173613A1
Authority
WO
WIPO (PCT)
Prior art keywords
metal layer
substrate
barrier layer
tsv structure
wet etch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/078656
Other languages
French (fr)
Inventor
Yinuo JIN
Yingwei DAI
Guipu YANG
Jian Wang
Hui Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ACM Research Shanghai Inc
Original Assignee
ACM Research Shanghai Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ACM Research Shanghai Inc filed Critical ACM Research Shanghai Inc
Priority to PCT/CN2016/078656 priority Critical patent/WO2017173613A1/en
Priority to SG11201808636TA priority patent/SG11201808636TA/en
Priority to KR1020187031089A priority patent/KR102599825B1/en
Priority to CN201680084216.8A priority patent/CN108886016B/en
Priority to TW105133926A priority patent/TWI774645B/en
Publication of WO2017173613A1 publication Critical patent/WO2017173613A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/66—Wet etching of conductive or resistive materials
    • H10P50/663—Wet etching of conductive or resistive materials by chemical means only
    • H10P50/667—Wet etching of conductive or resistive materials by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/04—Planarisation of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/062—Manufacture or treatment of conductive parts of the interconnections by smoothing of conductive parts, e.g. by planarisation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers

Definitions

  • the present invention generally relates to semiconductor device manufacture, and more particularly to a TSV (through-silicon-via) structure planarization process and apparatus.
  • a copper metal layer deposition and planarization process includes following steps: PVD (physical vapor deposition) , ECP (electro-chemical plating) , annealing, CMP (chemical-mechanical-planarization) .
  • Vias in TSV or interposer are commonly with high aspect ratio.
  • a thick overburden copper layer will be deposited on a surface of a substrate by plating process.
  • huge amount of copper layer needs to remove by CMP, which causes the CMP process costs the most in 3D TSV and 2.5D interposer package integration. For example, in a via-middle process, the CMP process occupies 35%of total cost.
  • the huge CTE (coefficient of thermal expansion) mismatch between Cu and Si causes stress which is shown as wafer level warpage.
  • the stress further induces micro-crack in Si layer, carrier’s mobility change and device defect. It’s proved that higher annealing temperature and thicker overburden copper layer result in higher wafer level warpage.
  • the substrate will be flattened by CMP head’s down press. The external mechanical pressure will conflict with the substrate internal stress and induce the substrate cracking or defect.
  • the present invention provides a TSV structure planarization process.
  • the TSV structure includes a substrate, vias formed in the substrate, an oxide layer formed on the substrate, a barrier layer formed on the oxide layer, bottom and sidewall of the vias, a metal layer formed in the vias and on the barrier layer.
  • the TSV structure planarization process comprises: removing all metal layer formed on a non-recessed area of the substrate by a stress-free polishing process; and removing metal layer residual and the barrier layer on the non-recessed area by a chemical wet etch process.
  • the present invention provides a TSV structure planarization process.
  • the TSV structure includes a substrate, vias formed in the substrate, an oxide layer formed on the substrate, a barrier layer formed on the oxide layer, bottom and sidewall of the vias, a metal layer formed in the vias and on the barrier layer.
  • the TSV structure planarization process comprises: removing a large proportion of metal layer on a non-recessed area of the substrate by a stress-free polishing process and remaining a certain thickness of the metal layer on the non- recessed area; removing the remained metal layer on the non-recessed area by a metal layer chemical wet etch process; and removing metal layer residual and the barrier layer on the non-recessed area by a barrier layer chemical wet etch process.
  • the present invention provides a TSV structure planarization process.
  • the TSV structure includes a substrate, vias formed in the substrate, an oxide layer formed on the substrate, a barrier layer formed on the oxide layer, bottom and sidewall of the vias, a metal layer formed in the vias and on the barrier layer.
  • the TSV structure planarization process comprises: removing all metal layer formed on a non-recessed area of the substrate by a stress-free polishing process; removing metal layer residual on the non-recessed area by a chemical-mechanical-planarization process; and removing the barrier layer on the non-recessed area by a barrier layer chemical wet etch process.
  • the present invention provides a TSV structure planarization process.
  • the TSV structure includes a substrate, vias formed in the substrate, an oxide layer formed on the substrate, a barrier layer formed on the oxide layer, bottom and sidewall of the vias, a metal layer formed in the vias and on the barrier layer.
  • the TSV structure planarization process comprises: removing a large proportion of metal layer on a non-recessed area of the substrate and remaining a certain thickness of the metal layer on the non-recessed area; removing the remained metal layer on the non-recessed area by a chemical-mechanical-planarization process; and removing metal layer residual and the barrier layer on the non-recessed area by a barrier layer chemical wet etch process.
  • the present invention provides a TSV structure planarization apparatus.
  • the TSV structure includes a substrate, vias formed in the substrate, an oxide layer formed on the substrate, a barrier layer formed on the oxide layer, bottom and sidewall of the vias, a metal layer formed in the vias and on the barrier layer.
  • the TSV structure planarization apparatus comprises at least one SFP module, a CMP module and a wet etch module.
  • the at least one SFP module is used for applying a stress-free polishing process to the substrate to remove the metal layer on a non-recessed area of the substrate.
  • the CMP module is used for applying a chemical-mechanical-planarization process to the substrate to remove the metal layer on the non-recessed area.
  • the wet etch module is used for applying a chemical wet etch process to the substrate to remove the metal layer and/or the barrier layer on the non-recessed area.
  • the present invention compares to a conventional TSV structure planarization process, which uses the CMP process to remove the metal layer and the barrier layer on the non-recessed area, the present invention utilizes the stress-free polishing process and the chemical wet etch process to stress-free remove the metal layer and the barrier layer on the non-recessed area, just retaining the metal layer and the barrier layer in the vias, which improves the metal layer dishing uniformity, reduces stress during the planarization process, minimizes the opportunity of the substrate micro-crack, and shortens the CMP process duration, finally reduces the planarization process cost and reduces waste chemical drain.
  • FIG. 1 is a cross-sectional view showing an exemplary TSV structure before carrying out planarization process.
  • FIG. 2 is a cross-sectional view showing the TSV structure which has been flattened.
  • FIG. 3 is a flow chart showing a TSV structure planarization process according to an embodiment of the present invention.
  • FIG. 4 is a flow chart showing a TSV structure planarization process according to another embodiment of the present invention.
  • FIG. 5 is a flow chart showing a TSV structure planarization process according to another embodiment of the present invention.
  • FIG. 6 is a flow chart showing a TSV structure planarization process according to another embodiment of the present invention.
  • FIG. 7 is a flow chart showing a TSV structure planarization process according to another embodiment of the present invention.
  • FIG. 8 is a flow chart showing a TSV structure planarization process according to another embodiment of the present invention.
  • FIG. 9 shows an exemplary wet etch pulse mode recipe.
  • FIG. 10 is a block diagram showing a TSV structure planarization apparatus according to the present invention.
  • FIG. 11 is a block diagram showing a substrate transferring sequence.
  • FIG. 12 is a block diagram showing another substrate transferring sequence.
  • a process sequence of forming a TSV structure generally includes the following steps: forming vias 102 in a substrate 101 by etching, wherein the material of the substrate 101 can select silicon; depositing an oxide layer 103 on the substrate 101 by plasma enhanced chemical vapor deposition (PECVD) , wherein the material of the oxide layer 103 can select silicon dioxide (SiO 2 ) ; depositing a barrier layer 104 on the oxide layer 103, the bottom and the sidewall of the vias 102 by physical vapor deposition (PVD) , wherein the material of the barrier layer 104 can select titanium (Ti) ; depositing a metal layer 105 in the vias 102 by electrochemical plating, wherein the material of the metal layer 105 can select copper.
  • PECVD plasma enhanced chemical vapor deposition
  • PVD physical vapor deposition
  • a thick overburden metal layer 105 is deposited on the barrier layer 104 by electrochemical plating.
  • FIG. 1 an exemplary TSV structure before carrying out planarization process is illustrated.
  • the thickness of the metal layer 105 deposited on a non-recessed area is about 2um-4um.
  • FIG. 3 is a flow chart showing a TSV structure planarization process for removing the metal layer 105 and the barrier layer 104 formed on the non-recessed area according to an embodiment of the present invention.
  • the TSV structure planarization process includes the following steps:
  • Step 301 removing all metal layer 105 deposited on the non-recessed area by a stress-free polishing (SFP) process.
  • SFP stress-free polishing
  • a metal layer dishing in the via 102 is controlled by SFP over polish.
  • the SFP process is a chemical-electrical process.
  • the metal layer 105 on the substrate 101 is as anode and an electrolyte nozzle is as cathode.
  • the metal layer 105 is dissolved and polished by the contacted electrolyte when a positive voltage is applied between the anode and the cathode.
  • U.S. patent application Ser. No. 10/590,460 entitled “Controlling removal rate uniformity of an electropolishing process in integrated circuit fabrication” , filed on February 23, 2005, the entire content of which is incorporated herein by reference.
  • Step 303 removing metal layer residual on the non-recessed area by a metal layer chemical wet etch process.
  • the metal layer chemical wet etch process is applied to remove the metal layer residual.
  • the material of the metal layer 105 preferably selects copper, and correspondingly, the etchant for removing copper residual mainly contains hydrogen peroxide (H 2 O 2 ) , additive and hydrofluoric acid, and the concentration of the hydrofluoric acid is in the range of 2%to 10%.
  • the etchant will be ejected to the surface of the substrate in pulse mode, as shown in FIG. 9.
  • One pulse mode step is combined with a step of etchant and a step of DIW, for example, firstly 10 sec chemical wet etch is applied to the substrate, after that, a 5 sec DIW is applied to the substrate.
  • a plurality of periodical steps form a wet etch process recipe.
  • the periodical wet etch process will optimize the recessed area copper dishing.
  • the DIW will fill in the recessed area and reduce the etch rate of this area.
  • the substrate is fixed on a chuck, and is rotated with the chuck.
  • the favor substrate spin speed for the wet etch process is from 200RPM to 600RPM.
  • the removal profile is related to the spin speed.
  • the higher spin speed induces the higher substrate edge removal rate and lower substrate center removal rate; and conversely, the lower spin speed induces the lower substrate edge removal rate and higher substrate center removal rate.
  • the etchant nozzle is movable during the process.
  • the etch rate is influenced by the nozzle scan speed and scan area.
  • the optimal scan speed is in range of 40mm/sec to 100mm/sec.
  • Step 305 removing the barrier layer 104 on the non-recessed area by a barrier layer chemical wet etch process.
  • the thickness of the barrier layer 104 on the non-recessed area is about 0.2um-0.5um, which is depended on process request.
  • the material of the barrier layer 104 contains Ti, and correspondingly, the chemical for the barrier layer chemical wet etch process mainly contains hydrofluoric acid (HF) and additive, and the concentration of the hydrofluoric acid is in the range of 0.1%to 1%.
  • the etchant will be ejected to the surface of the substrate in pulse mode. As shown in FIG.
  • one pulse mode step is combined with a step of etchant and a step of DIW, for example, firstly 10 sec chemical wet etch is applied to substrate, after that, a 5 sec DIW is applied to the substrate.
  • a plurality of periodical steps form a wet etch process recipe.
  • the periodical wet etch process will optimize the barrier layer on the side wall of the recessed area over etch.
  • the DIW will fill in the recessed area and reduce the etch rate of this area.
  • the substrate is fixed on a chuck, and is rotated with the chuck.
  • the favor substrate spin speed for the wet etch process is from 200RPM to 600RPM.
  • the removal profile is related to the spin speed.
  • the higher spin speed induces the higher substrate edge removal rate and lower substrate center removal rate; and conversely, the lower spin speed induces the lower substrate edge removal rate and higher substrate center removal rate.
  • the etchant nozzle is movable during the process.
  • the etch rate is influenced by the nozzle scan speed and scan area.
  • the optimal scan speed is in range of 40mm/sec to 100mm/sec.
  • the oxide layer 103 under the barrier layer 104 is exposed.
  • the material of the oxide layer 103 is SiO 2 , and the thickness of the oxide layer 103 is about 2um.
  • a CMP process is applied to remove a part of the oxide layer 103. Normally, the removal thickness of the oxide layer 103 is 0.2um.
  • the CMP process has a high selectivity between the oxide layer 103 and the copper metal layer 105, such as 100: 1. The CMP process can recover the roughness of the copper metal layer 105 in the via 102.
  • FIG. 4 is a flow chart showing a TSV structure planarization process for removing the metal layer 105 and the barrier layer 104 formed on the non-recessed area according to another embodiment of the present invention.
  • the TSV structure planarization process includes the following steps:
  • Step 401 removing all metal layer 105 deposited on the non-recessed area by a stress-free polishing (SFP) process.
  • SFP stress-free polishing
  • a metal layer dishing in the via 102 is controlled by SFP over polish.
  • the SFP process is a chemical-electrical process.
  • the metal layer 105 on the substrate 101 is as anode and an electrolyte nozzle is as cathode.
  • the metal layer 105 is dissolved and polished by the contacted electrolyte when a positive voltage is applied between the anode and the cathode.
  • U.S. patent application Ser. No. 10/590,460 entitled “Controlling removal rate uniformity of an electropolishing process in integrated circuit fabrication” , filed on February 23, 2005, the entire content of which is incorporated herein by reference.
  • Step 403 removing metal layer residual and the barrier layer 104 on the non-recessed area by a barrier layer chemical wet etch process.
  • the material of the metal layer 105 is copper and the material of the barrier layer 104 contains Ti.
  • the chemical for the barrier layer chemical wet etch process mainly contains hydrofluoric acid (HF) and additive, and the concentration of the hydrofluoric acid is in the range of 0.1%to 1%.
  • the etchant will be ejected to the surface of the substrate in pulse mode. As shown in FIG.
  • one pulse mode step is combined with a step of etchant and a step of DIW, for example, firstly 10 sec chemical wet etch is applied to substrate, after that, a 5 sec DIW is applied to the substrate.
  • a plurality of periodical steps form a wet etch process recipe.
  • the periodical wet etch process will optimize the barrier layer on the side wall of the recessed area over etch.
  • the DIW will fill in the recessed area and reduce the etch rate of this area.
  • the substrate is fixed on a chuck, and is rotated with the chuck.
  • the favor substrate spin speed for the wet etch process is from 200RPM to 600RPM.
  • the removal profile is related to the spin speed.
  • the higher spin speed induces the higher substrate edge removal rate and lower substrate center removal rate; and conversely, the lower spin speed induces the lower substrate edge removal rate and higher substrate center removal rate.
  • the etchant nozzle is movable during the process.
  • the etch rate is influenced by the nozzle scan speed and scan area.
  • the optimal scan speed is in range of 40mm/sec to 100mm/sec.
  • the oxide layer 103 under the barrier layer 104 is exposed.
  • the material of the oxide layer 103 is SiO 2 , and the thickness of the oxide layer 103 is about 2um.
  • a CMP process is applied to remove a part of the oxide layer 103. Normally, the removal thickness of the oxide layer 103 is 0.2um.
  • the CMP process has a high selectivity between the oxide layer 103 and the copper metal layer 105, such as 100: 1. The CMP process can recover the roughness of the copper metal layer 105 in the via 102.
  • FIG. 5 is a flow chart showing a TSV structure planarization process for removing the metal layer 105 and the barrier layer 104 formed on the non-recessed area according to another embodiment of the present invention.
  • the TSV structure planarization process includes the following steps:
  • Step 501 removing a large proportion of metal layer 105 on the non-recessed area by a SFP process and remaining about 0.2um-0.5um metal layer 105 on the non-recessed area.
  • the SFP process is a chemical-electrical process.
  • the metal layer 105 on the substrate 101 is as anode and an electrolyte nozzle is as cathode.
  • the metal layer 105 is dissolved and polished by the contacted electrolyte when a positive voltage is applied between the anode and the cathode.
  • U.S. patent application Ser. No. 10/590,460 entitled “Controlling removal rate uniformity of an electropolishing process in integrated circuit fabrication” , filed on February 23, 2005, the entire content of which is incorporated herein by reference.
  • Step 503 removing the remained metal layer 105 on the non-recessed area by a metal layer chemical wet etch process.
  • a metal layer dishing in the via 102 is controlled by the over etch time length of the metal layer chemical wet etch process.
  • the material of the metal layer 105 is copper.
  • the chemical for the copper layer chemical wet etch process mainly contains hydrogen peroxide (H 2 O 2 ) , additive and hydrofluoric acid, and the concentration of the hydrofluoric acid is in the range of 2%to 10%.
  • the etchant will be ejected to the surface of the substrate in pulse mode, as shown in FIG. 9.
  • One pulse mode step is combined with a step of etchant and a step of DIW, for example, firstly 10 sec chemical wet etch is applied to the substrate, after that, a 5 sec DIW is applied to the substrate.
  • a plurality of periodical steps form a wet etch process recipe.
  • the periodical wet etch process will optimize the copper dishing in the recessed area.
  • the DIW will fill in the recessed area and reduce the etch rate of this area.
  • the substrate is fixed on a chuck, and is rotated with the chuck.
  • the favor substrate spin speed for the wet etch process is from 200RPM to 600RPM.
  • the removal profile is related to the spin speed.
  • the higher spin speed induces the higher substrate edge removal rate and lower substrate center removal rate; and conversely, the lower spin speed induces the lower substrate edge removal rate and higher substrate center removal rate.
  • the etchant nozzle is movable during the process.
  • the etch rate is influenced by the nozzle scan speed and scan area.
  • the optimal scan speed is in range of 40mm/sec to 100mm/sec.
  • Step 505 removing metal layer residual and the barrier layer 104 on the non-recessed area by a barrier layer chemical wet etch process.
  • the material of the barrier layer 104 contains Ti.
  • the chemical for the barrier layer chemical wet etch process mainly contains hydrofluoric acid (HF) and additive, and the concentration of the hydrofluoric acid is in the range of 0.1%to 1%.
  • the etchant will be ejected to the surface of the substrate in pulse mode. As shown in FIG. 9, one pulse mode step is combined with a step of etchant and a step of DIW, for example, firstly 10 sec chemical wet etch is applied to substrate, after that, a 5 sec DIW is applied to the substrate.
  • a plurality of periodical steps form a wet etch process recipe.
  • the periodical wet etch process will optimize the barrier layer on the side wall of the recessed area over etch.
  • the DIW will fill in the recessed area and reduce the etch rate of this area.
  • the substrate is fixed on a chuck, and is rotated with the chuck.
  • the favor substrate spin speed for the wet etch process is from 200RPM to 600RPM.
  • the removal profile is related to the spin speed.
  • the higher spin speed induces the higher substrate edge removal rate and lower substrate center removal rate; and conversely, the lower spin speed induces the lower substrate edge removal rate and higher substrate center removal rate.
  • the etchant nozzle is movable during the process.
  • the etch rate is influenced by the nozzle scan speed and scan area.
  • the optimal scan speed is in range of 40mm/sec to 100mm/sec.
  • the oxide layer 103 under the barrier layer 104 is exposed.
  • the material of the oxide layer 103 is SiO 2 , and the thickness of the oxide layer 103 is about 2um.
  • a CMP process is applied to remove a part of the oxide layer 103. Normally, the removal thickness of the oxide layer 103 is 0.2um.
  • the CMP process has a high selectivity between the oxide layer 103 and the copper metal layer 105, such as 100: 1. The CMP process can recover the roughness of the copper metal layer 105 in the via 102.
  • FIG. 6 is a flow chart showing a TSV structure planarization process for removing the metal layer 105 and the barrier layer 104 formed on the non-recessed area according to another embodiment of the present invention.
  • the TSV structure planarization process includes the following steps:
  • Step 601 removing all metal layer 105 deposited on the non-recessed area by a stress-free polishing (SFP) process.
  • SFP stress-free polishing
  • a metal layer dishing in the via 102 is controlled by SFP over polish.
  • the SFP process is a chemical-electrical process.
  • the metal layer 105 on the substrate 101 is as anode and an electrolyte nozzle is as cathode.
  • the metal layer 105 is dissolved and polished by the contacted electrolyte when a positive voltage is applied between the anode and the cathode.
  • U.S. patent application Ser. No. 10/590,460 entitled “Controlling removal rate uniformity of an electropolishing process in integrated circuit fabrication” , filed on February 23, 2005, the entire content of which is incorporated herein by reference.
  • Step 603 removing metal layer residual on the non-recessed area by a chemical-mechanical-planarization (CMP) process.
  • CMP chemical-mechanical-planarization
  • the chemical-mechanical-planarization process is applied to the substrate 101 to remove the metal layer residual. Since almost all metal layer on the non-recessed area is removed by the SFP process, therefore, the process time of the CMP process is short, which saves cost and avoids damage to the substrate.
  • Step 605 removing the barrier layer 104 on the non-recessed area by a barrier layer chemical wet etch process.
  • the thickness of the barrier layer 104 on the non-recessed area is about 0.2um-0.5um.
  • the thickness of the barrier layer 104 on the non-recessed area is depended on process request.
  • the material of the barrier layer 104 contains Ti, and correspondingly, the chemical for the barrier layer chemical wet etch process mainly contains hydrofluoric acid (HF) and additive, and the concentration of the hydrofluoric acid is in the range of 0.1%to 1%.
  • the etchant will be ejected to the surface of the substrate in pulse mode. As shown in FIG.
  • one pulse mode step is combined with a step of etchant and a step of DIW, for example, firstly 10 sec chemical wet etch is applied to substrate, after that, a 5 sec DIW is applied to the substrate.
  • a plurality of periodical steps form a wet etch process recipe.
  • the periodical wet etch process will optimize the barrier layer on the side wall of the recessed area over etch.
  • the DIW will fill in the recessed area and reduce the etch rate of this area.
  • the substrate is fixed on a chuck, and is rotated with the chuck.
  • the favor substrate spin speed for the wet etch process is from 200RPM to 600RPM.
  • the removal profile is related to the spin speed.
  • the higher spin speed induces the higher substrate edge removal rate and lower substrate center removal rate; and conversely, the lower spin speed induces the lower substrate edge removal rate and higher substrate center removal rate.
  • the etchant nozzle is movable during the process.
  • the etch rate is influenced by the nozzle scan speed and scan area.
  • the optimal scan speed is in range of 40mm/sec to 100mm/sec.
  • the oxide layer 103 under the barrier layer 104 is exposed.
  • the material of the oxide layer 103 is SiO 2 , and the thickness of the oxide layer 103 is about 2um.
  • a CMP process is applied to remove a part of the oxide layer 103. Normally, the removal thickness of the oxide layer 103 is 0.2um.
  • the CMP process has a high selectivity between the oxide layer 103 and the copper metal layer 105, such as 100: 1. The CMP process can recover the roughness of the copper metal layer 105 in the via 102.
  • FIG. 7 is a flow chart showing a TSV structure planarization process for removing the metal layer 105 and the barrier layer 104 formed on the non-recessed area according to another embodiment of the present invention.
  • the TSV structure planarization process includes the following steps:
  • Step 701 removing a large proportion of metal layer 105 on the non-recessed area by a SFP process and remaining about 0.2um-0.5um metal layer 105 on the non-recessed area.
  • the SFP process is a chemical-electrical process.
  • the metal layer 105 on the substrate 101 is as anode and an electrolyte nozzle is as cathode.
  • the metal layer 105 is dissolved and polished by the contacted electrolyte when a positive voltage is applied between the anode and the cathode.
  • U.S. patent application Ser. No. 10/590,460 entitled “Controlling removal rate uniformity of an electropolishing process in integrated circuit fabrication” , filed on February 23, 2005, the entire content of which is incorporated herein by reference.
  • Step 703 removing the remained metal layer 105 on the non-recessed area by a chemical-mechanical-planarization process.
  • a metal layer dishing in the via 102 is controlled by the over polish time length of the chemical-mechanical-planarization process.
  • the material of the metal layer 105 is copper.
  • Step 705 removing metal layer residual and the barrier layer 104 on the non-recessed area by a barrier layer chemical wet etch process.
  • the material of the barrier layer 104 contains Ti.
  • the chemical for the barrier layer chemical wet etch process mainly contains hydrofluoric acid (HF) and additive, and the concentration of the hydrofluoric acid is in the range of 0.1%to 1%.
  • the etchant will be ejected to the surface of the substrate in pulse mode. As shown in FIG. 9, one pulse mode step is combined with a step of etchant and a step of DIW, for example, firstly 10 sec chemical wet etch is applied to substrate, after that, a 5 sec DIW is applied to the substrate.
  • a plurality of periodical steps form a wet etch process recipe.
  • the periodical wet etch process will optimize the barrier layer on the side wall of the recessed area over etch.
  • the DIW will fill in the recessed area and reduce the etch rate of this area.
  • the substrate is fixed on a chuck, and is rotated with the chuck.
  • the favor substrate spin speed for the wet etch process is from 200RPM to 600RPM.
  • the removal profile is related to the spin speed.
  • the higher spin speed induces the higher substrate edge removal rate and lower substrate center removal rate; and conversely, the lower spin speed induces the lower substrate edge removal rate and higher substrate center removal rate.
  • the etchant nozzle is movable during the process.
  • the etch rate is influenced by the nozzle scan speed and scan area.
  • the optimal scan speed is in range of 40mm/sec to 100mm/sec.
  • the oxide layer 103 under the barrier layer 104 is exposed.
  • the material of the oxide layer 103 is SiO 2 , and the thickness of the oxide layer 103 is about 2um.
  • a CMP process is applied to remove a part of the oxide layer 103. Normally, the removal thickness of the oxide layer 103 is 0.2um.
  • the CMP process has a high selectivity between the oxide layer 103 and the copper metal layer 105, such as 100: 1. The CMP process can recover the roughness of the copper metal layer 105 in the via 102.
  • FIG. 8 is a flow chart showing a TSV structure planarization process for removing the metal layer 105 and the barrier layer 104 formed on the non-recessed area according to another embodiment of the present invention.
  • the TSV structure planarization process includes the following steps:
  • Step 801 removing a large proportion of metal layer 105 on the non-recessed area by a metal layer chemical wet etch process and remaining about 0.2um-0.5um metal layer 105 on the non-recessed area.
  • the material of the metal layer 105 preferably selects copper, and correspondingly, the chemical for copper chemical wet etch process mainly contains hydrogen peroxide (H 2 O 2 ) , additive and hydrofluoric acid, and the concentration of the hydrofluoric acid is in the range of 2%to 10%.
  • Step 803 removing the remained metal layer 105 on the non-recessed area by a chemical-mechanical-planarization process.
  • a metal layer dishing in the via 102 is controlled by the over polish time length of the chemical-mechanical-planarization process.
  • Step 805 removing metal layer residual and the barrier layer 104 on the non-recessed area by a barrier layer chemical wet etch process.
  • the material of the barrier layer 104 contains Ti.
  • the chemical for the barrier layer chemical wet etch process mainly contains hydrofluoric acid (HF) and additive, and the concentration of the hydrofluoric acid is in the range of 0.1%to 1%.
  • the oxide layer 103 under the barrier layer 104 is exposed.
  • the material of the oxide layer 103 is SiO 2 , and the thickness of the oxide layer 103 is about 2um.
  • a CMP process is applied to remove a part of the oxide layer 103. Normally, the removal thickness of the oxide layer 103 is 0.2um.
  • the CMP process has a high selectivity between the oxide layer 103 and the copper metal layer 105, such as 100: 1. The CMP process can recover the roughness of the copper metal layer 105 in the via 102.
  • FIG. 10 is a block diagram showing a TSV structure planarization apparatus according to the present invention.
  • the apparatus includes an EFEM (Equipment Front End Module) 1001, a buffer station 1003, a process robot 1005, two SFP modules 1007 which are stacked, a CMP module 1009, a metrology module 1011, a brush clean module 1013, a wet etch module 1015 and a clean module 1017.
  • the metrology module 1011 and the brush clean module 1013 are stacked.
  • the wet etch module 1015 and the clean module 1017 are stacked.
  • the apparatus also includes an electrical module, a gas module and a plumbing module.
  • the SFP module 1007 is used for applying a stress-free polishing process to the substrate to remove the metal layer on the non-recessed area of the substrate.
  • the CMP module 1009 is used for applying a chemical-mechanical-planarization process to the substrate to remove the metal layer on the non-recessed area.
  • the wet etch module 1015 is used for applying a chemical wet etch process to the substrate to remove the metal layer and/or the barrier layer on the non-recessed area.
  • the chemical wet etch process includes a metal layer chemical wet etch process and/or a barrier layer chemical wet etch process.
  • the wet etch process takes a pulse mode and each pulse mode step is combined with a step of etchant and a step of DIW.
  • FIG. 11 is a block diagram showing an exemplary substrate transferring sequence.
  • An EFEM robot takes an unprocessed substrate from a load port and transfers the substrate to the buffer station 1003.
  • the process robot 1005 takes the substrate from the buffer station 1003 and transfers the substrate to the metrology module 1011 for measuring the thickness of the metal layer.
  • the process robot 1005 takes the substrate from the metrology module 1011 and transfers the substrate to one of the SFP modules 1007.
  • a SFP process is applied to the substrate to remove all metal layer on the non-recessed area.
  • the process robot 1005 takes the substrate from the SFP module 1007 and transfers the substrate to the clean module 1017 for cleaning the substrate. Then the process robot 1005 takes the substrate from the clean module 1017 and transfers the substrate to the CMP module 1009. In the CMP module 1009, a CMP process is applied to the substrate to remove metal layer residual on the non-recessed area. After the CMP process is completed, the process robot 1005 takes the substrate from the CMP module 1009 and transfers the substrate to the brush clean module 1013 for cleaning the substrate. Then the process robot 1005 takes the substrate from the brush clean module 1013 and transfers the substrate to the wet etch module 1015.
  • a barrier layer chemical wet etch process is applied to the substrate to remove the barrier layer on the non-recessed area.
  • the process robot 1005 takes the substrate from the wet etch module 1015 and transfers the substrate to the clean module 1017 for cleaning the substrate. Then the process robot 1005 takes the substrate from the clean module 1017 and transfers the substrate to the buffer station 1003. At last, the EFEM robot takes the substrate from the buffer station 1003 and transfers the substrate to the substrate load port.
  • the substrate should be transferred to the metrology module 1011 to measure the post SFP metal layer thickness, as shown in FIG. 12.
  • the present invention utilizes the SFP process, the metal layer chemical wet etch process and the barrier layer chemical wet etch process to stress-free remove the metal layer 105 and the barrier layer 104 on the non-recessed area, just retaining the metal layer 105 and the barrier layer 104 in the vias 102, as shown in FIG. 2, which improves the TSV structure metal layer dishing uniformity, reduces stress during the planarization process, minimizes the opportunity of the substrate micro-crack, and shortens the CMP process duration, finally reduces the planarization process cost and reduces waste chemical drain.

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Medicinal Preparation (AREA)
  • Weting (AREA)
  • Supporting Of Heads In Record-Carrier Devices (AREA)
  • Shaping Of Tube Ends By Bending Or Straightening (AREA)

Abstract

A TSV structure planarization process and apparatus. The TSV structure includes a substrate (101), vias (102) formed in the substrate (101), an oxide layer (103) formed on the substrate (101), a barrier layer (104) formed on the oxide layer (103), bottom and sidewall of the vias (102), a metal layer (105) formed in the vias (102) and on the barrier layer (104).The TSV structure planarization process comprises: removing all metal layer formed on a non-recessed area of the substrate by a stress-free polishing process (301); and removing metal layer residual and the barrier layer on the non-recessed area by a chemical wet etch process (303) (305).

Description

TSV STRUCTURE PLANARIZATION PROCESS AND APPARATUS BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor device manufacture, and more particularly to a TSV (through-silicon-via) structure planarization process and apparatus.
2. The Related Art
With the rapid development of electronic industry, the demand on mini-size, low power consumption and high reliability becomes inevitable to electronic products. Based on Moore’s law, decreasing the feature size of integrated circuits is approaching a bottleneck. In recent years, wafer-level vertical miniaturization 3D through-silicon-via (TSV) and 2.5D interposer package integration are becoming an alternative solution to break through the bottleneck of Moore’s law by down scaling in design, process and cost. Correspondingly, due to copper’s higher conductivity, better electromigration resistance, the copper is widely used to fill vias when making TSV or interposer.
Conventionally, a copper metal layer deposition and planarization process includes following steps: PVD (physical vapor deposition) , ECP (electro-chemical plating) , annealing, CMP (chemical-mechanical-planarization) . Vias in TSV or interposer are commonly with high aspect ratio. In order to void-free fill the deep vias, a thick overburden copper layer will be deposited on a surface of a substrate by plating process. Hence, huge amount of copper layer needs to remove by CMP, which causes the CMP process costs the most in 3D TSV and 2.5D interposer package integration. For example, in a via-middle process, the CMP process occupies 35％of total cost. On the other hand, the huge CTE (coefficient of thermal expansion)  mismatch between Cu and Si causes stress which is shown as wafer level warpage. The stress further induces micro-crack in Si layer, carrier’s mobility change and device defect. It’s proved that higher annealing temperature and thicker overburden copper layer result in higher wafer level warpage. During the CMP process, the substrate will be flattened by CMP head’s down press. The external mechanical pressure will conflict with the substrate internal stress and induce the substrate cracking or defect. Although the conventional process route is optimized and the copper overburden thickness is minimized before anneal, which can successfully release the stress and minimize the substrate warpage before CMP, however, whether 3D TSV or 2.5D interposer can be rapid industrialization, depends on the solution to reduce the cost and stress.
SUMMARY
In an embodiment, the present invention provides a TSV structure planarization process. The TSV structure includes a substrate, vias formed in the substrate, an oxide layer formed on the substrate, a barrier layer formed on the oxide layer, bottom and sidewall of the vias, a metal layer formed in the vias and on the barrier layer. The TSV structure planarization process comprises: removing all metal layer formed on a non-recessed area of the substrate by a stress-free polishing process； and removing metal layer residual and the barrier layer on the non-recessed area by a chemical wet etch process.
In another embodiment, the present invention provides a TSV structure planarization process. The TSV structure includes a substrate, vias formed in the substrate, an oxide layer formed on the substrate, a barrier layer formed on the oxide layer, bottom and sidewall of the vias, a metal layer formed in the vias and on the barrier layer. The TSV structure planarization process comprises: removing a large proportion of metal layer on a non-recessed area of the substrate by a stress-free polishing process and remaining a certain thickness of the metal layer on the non- recessed area； removing the remained metal layer on the non-recessed area by a metal layer chemical wet etch process； and removing metal layer residual and the barrier layer on the non-recessed area by a barrier layer chemical wet etch process.
In another embodiment, the present invention provides a TSV structure planarization process. The TSV structure includes a substrate, vias formed in the substrate, an oxide layer formed on the substrate, a barrier layer formed on the oxide layer, bottom and sidewall of the vias, a metal layer formed in the vias and on the barrier layer. The TSV structure planarization process comprises: removing all metal layer formed on a non-recessed area of the substrate by a stress-free polishing process； removing metal layer residual on the non-recessed area by a chemical-mechanical-planarization process； and removing the barrier layer on the non-recessed area by a barrier layer chemical wet etch process.
In another embodiment, the present invention provides a TSV structure planarization process. The TSV structure includes a substrate, vias formed in the substrate, an oxide layer formed on the substrate, a barrier layer formed on the oxide layer, bottom and sidewall of the vias, a metal layer formed in the vias and on the barrier layer. The TSV structure planarization process comprises: removing a large proportion of metal layer on a non-recessed area of the substrate and remaining a certain thickness of the metal layer on the non-recessed area； removing the remained metal layer on the non-recessed area by a chemical-mechanical-planarization process； and removing metal layer residual and the barrier layer on the non-recessed area by a barrier layer chemical wet etch process.
In an embodiment, the present invention provides a TSV structure planarization apparatus. The TSV structure includes a substrate, vias formed in the substrate, an oxide layer formed on the substrate, a barrier layer formed on the oxide layer, bottom and sidewall of the vias, a metal layer formed in the vias and on the barrier layer. The TSV structure planarization apparatus comprises at least one SFP module, a CMP module and a wet etch module. The at least one SFP module is used  for applying a stress-free polishing process to the substrate to remove the metal layer on a non-recessed area of the substrate. The CMP module is used for applying a chemical-mechanical-planarization process to the substrate to remove the metal layer on the non-recessed area. The wet etch module is used for applying a chemical wet etch process to the substrate to remove the metal layer and/or the barrier layer on the non-recessed area.
Comparing to a conventional TSV structure planarization process, which uses the CMP process to remove the metal layer and the barrier layer on the non-recessed area, the present invention utilizes the stress-free polishing process and the chemical wet etch process to stress-free remove the metal layer and the barrier layer on the non-recessed area, just retaining the metal layer and the barrier layer in the vias, which improves the metal layer dishing uniformity, reduces stress during the planarization process, minimizes the opportunity of the substrate micro-crack, and shortens the CMP process duration, finally reduces the planarization process cost and reduces waste chemical drain.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional view showing an exemplary TSV structure before carrying out planarization process.
FIG. 2 is a cross-sectional view showing the TSV structure which has been flattened.
FIG. 3 is a flow chart showing a TSV structure planarization process according to an embodiment of the present invention.
FIG. 4 is a flow chart showing a TSV structure planarization process according to another embodiment of the present invention.
FIG. 5 is a flow chart showing a TSV structure planarization process according to another embodiment of the present invention.
FIG. 6 is a flow chart showing a TSV structure planarization process according to another embodiment of the present invention.
FIG. 7 is a flow chart showing a TSV structure planarization process according to another embodiment of the present invention.
FIG. 8 is a flow chart showing a TSV structure planarization process according to another embodiment of the present invention.
FIG. 9 shows an exemplary wet etch pulse mode recipe.
FIG. 10 is a block diagram showing a TSV structure planarization apparatus according to the present invention.
FIG. 11 is a block diagram showing a substrate transferring sequence.
FIG. 12 is a block diagram showing another substrate transferring sequence.
DETAILED DESCRIPTION OF EMBODIMENTS
A process sequence of forming a TSV structure generally includes the following steps: forming vias 102 in a substrate 101 by etching, wherein the material of the substrate 101 can select silicon； depositing an oxide layer 103 on the substrate 101 by plasma enhanced chemical vapor deposition (PECVD) , wherein the material of the oxide layer 103 can select silicon dioxide (SiO2) ； depositing a barrier layer 104 on the oxide layer 103, the bottom and the sidewall of the vias 102 by physical vapor deposition (PVD) , wherein the material of the barrier layer 104 can select titanium (Ti) ； depositing a metal layer 105 in the vias 102 by electrochemical plating, wherein the material of the metal layer 105 can select copper.
Because the vias 102 of the TSV structure normally have high aspect ratio, therefore, in order to void-free deposit the metal layer 105 in the vias 102, a thick overburden metal layer 105 is deposited on the barrier layer 104 by electrochemical plating. As shown in FIG. 1, an exemplary TSV structure before  carrying out planarization process is illustrated. The thickness of the metal layer 105 deposited on a non-recessed area is about 2um-4um. After depositing the metal layer 105 in the vias 102 and on the non-recessed area, a subsequent step is to remove the metal layer 105 and the barrier layer 104 deposited on the non-recessed area.
Referring to FIG. 3, FIG. 3 is a flow chart showing a TSV structure planarization process for removing the metal layer 105 and the barrier layer 104 formed on the non-recessed area according to an embodiment of the present invention. The TSV structure planarization process includes the following steps:
Step 301: removing all metal layer 105 deposited on the non-recessed area by a stress-free polishing (SFP) process. A metal layer dishing in the via 102 is controlled by SFP over polish. The SFP process is a chemical-electrical process. The metal layer 105 on the substrate 101 is as anode and an electrolyte nozzle is as cathode. The metal layer 105 is dissolved and polished by the contacted electrolyte when a positive voltage is applied between the anode and the cathode. For more detailed description of the SFP process, see U.S. patent application Ser. No. 10/590,460, entitled “Controlling removal rate uniformity of an electropolishing process in integrated circuit fabrication” , filed on February 23, 2005, the entire content of which is incorporated herein by reference.
Step 303: removing metal layer residual on the non-recessed area by a metal layer chemical wet etch process. After the SFP process, there maybe some metal layer residual is remained on the barrier layer 104 on the non-recessed area. In order to remove the metal layer residual remaining on the barrier layer 104 on the non-recessed area, the metal layer chemical wet etch process is applied to remove the metal layer residual. The material of the metal layer 105 preferably selects copper, and correspondingly, the etchant for removing copper residual mainly contains hydrogen peroxide (H2O2) , additive and hydrofluoric acid, and the concentration of the hydrofluoric acid is in the range of 2％to 10％. In the wet etch process, the etchant will be ejected to the surface of the substrate in pulse mode, as shown in FIG. 9. One  pulse mode step is combined with a step of etchant and a step of DIW, for example, firstly 10 sec chemical wet etch is applied to the substrate, after that, a 5 sec DIW is applied to the substrate. A plurality of periodical steps form a wet etch process recipe. The periodical wet etch process will optimize the recessed area copper dishing. The DIW will fill in the recessed area and reduce the etch rate of this area. The substrate is fixed on a chuck, and is rotated with the chuck. The favor substrate spin speed for the wet etch process is from 200RPM to 600RPM. The removal profile is related to the spin speed. The higher spin speed induces the higher substrate edge removal rate and lower substrate center removal rate； and conversely, the lower spin speed induces the lower substrate edge removal rate and higher substrate center removal rate. Furthermore, the etchant nozzle is movable during the process. The etch rate is influenced by the nozzle scan speed and scan area. The optimal scan speed is in range of 40mm/sec to 100mm/sec.
Step 305: removing the barrier layer 104 on the non-recessed area by a barrier layer chemical wet etch process. The thickness of the barrier layer 104 on the non-recessed area is about 0.2um-0.5um, which is depended on process request. The material of the barrier layer 104 contains Ti, and correspondingly, the chemical for the barrier layer chemical wet etch process mainly contains hydrofluoric acid (HF) and additive, and the concentration of the hydrofluoric acid is in the range of 0.1％to 1％. As similar with the copper wet etch process, in the barrier layer wet etch process, the etchant will be ejected to the surface of the substrate in pulse mode. As shown in FIG. 9, one pulse mode step is combined with a step of etchant and a step of DIW, for example, firstly 10 sec chemical wet etch is applied to substrate, after that, a 5 sec DIW is applied to the substrate. A plurality of periodical steps form a wet etch process recipe. The periodical wet etch process will optimize the barrier layer on the side wall of the recessed area over etch. The DIW will fill in the recessed area and reduce the etch rate of this area. The substrate is fixed on a chuck, and is rotated with the chuck. The favor substrate spin speed for the wet etch process is from 200RPM to 600RPM. The removal profile is related to the spin speed. The higher spin speed induces the  higher substrate edge removal rate and lower substrate center removal rate； and conversely, the lower spin speed induces the lower substrate edge removal rate and higher substrate center removal rate. Furthermore, the etchant nozzle is movable during the process. The etch rate is influenced by the nozzle scan speed and scan area. The optimal scan speed is in range of 40mm/sec to 100mm/sec.
After the barrier layer 104 on the non-recessed area is removed by the barrier layer chemical wet etch process, the oxide layer 103 under the barrier layer 104 is exposed. The material of the oxide layer 103 is SiO2, and the thickness of the oxide layer 103 is about 2um. In order to achieve a flat top surface, preferably, a CMP process is applied to remove a part of the oxide layer 103. Normally, the removal thickness of the oxide layer 103 is 0.2um. The CMP process has a high selectivity between the oxide layer 103 and the copper metal layer 105, such as 100: 1. The CMP process can recover the roughness of the copper metal layer 105 in the via 102.
Referring to FIG. 4, FIG. 4 is a flow chart showing a TSV structure planarization process for removing the metal layer 105 and the barrier layer 104 formed on the non-recessed area according to another embodiment of the present invention. The TSV structure planarization process includes the following steps:
Step 401: removing all metal layer 105 deposited on the non-recessed area by a stress-free polishing (SFP) process. A metal layer dishing in the via 102 is controlled by SFP over polish. The SFP process is a chemical-electrical process. The metal layer 105 on the substrate 101 is as anode and an electrolyte nozzle is as cathode. The metal layer 105 is dissolved and polished by the contacted electrolyte when a positive voltage is applied between the anode and the cathode. For more detailed description of the SFP process, see U.S. patent application Ser. No. 10/590,460, entitled “Controlling removal rate uniformity of an electropolishing process in integrated circuit fabrication” , filed on February 23, 2005, the entire content of which is incorporated herein by reference.
Step 403: removing metal layer residual and the barrier layer 104 on the non-recessed area by a barrier layer chemical wet etch process. In an embodiment, the material of the metal layer 105 is copper and the material of the barrier layer 104 contains Ti. The chemical for the barrier layer chemical wet etch process mainly contains hydrofluoric acid (HF) and additive, and the concentration of the hydrofluoric acid is in the range of 0.1％to 1％. In the barrier layer wet etch process, the etchant will be ejected to the surface of the substrate in pulse mode. As shown in FIG. 9, one pulse mode step is combined with a step of etchant and a step of DIW, for example, firstly 10 sec chemical wet etch is applied to substrate, after that, a 5 sec DIW is applied to the substrate. A plurality of periodical steps form a wet etch process recipe. The periodical wet etch process will optimize the barrier layer on the side wall of the recessed area over etch. The DIW will fill in the recessed area and reduce the etch rate of this area. The substrate is fixed on a chuck, and is rotated with the chuck. The favor substrate spin speed for the wet etch process is from 200RPM to 600RPM. The removal profile is related to the spin speed. The higher spin speed induces the higher substrate edge removal rate and lower substrate center removal rate； and conversely, the lower spin speed induces the lower substrate edge removal rate and higher substrate center removal rate. Furthermore, the etchant nozzle is movable during the process. The etch rate is influenced by the nozzle scan speed and scan area. The optimal scan speed is in range of 40mm/sec to 100mm/sec.
After the metal layer residual and the barrier layer 104 on the non-recessed area are removed by the barrier layer chemical wet etch process, the oxide layer 103 under the barrier layer 104 is exposed. The material of the oxide layer 103 is SiO2, and the thickness of the oxide layer 103 is about 2um. In order to achieve a flat top surface, preferably, a CMP process is applied to remove a part of the oxide layer 103. Normally, the removal thickness of the oxide layer 103 is 0.2um. The CMP process has a high selectivity between the oxide layer 103 and the copper metal layer 105, such as 100: 1. The CMP process can recover the roughness of the copper metal layer 105 in the via 102.
Referring to FIG. 5, FIG. 5 is a flow chart showing a TSV structure planarization process for removing the metal layer 105 and the barrier layer 104 formed on the non-recessed area according to another embodiment of the present invention. The TSV structure planarization process includes the following steps:
Step 501: removing a large proportion of metal layer 105 on the non-recessed area by a SFP process and remaining about 0.2um-0.5um metal layer 105 on the non-recessed area. The SFP process is a chemical-electrical process. The metal layer 105 on the substrate 101 is as anode and an electrolyte nozzle is as cathode. The metal layer 105 is dissolved and polished by the contacted electrolyte when a positive voltage is applied between the anode and the cathode. For more detailed description of the SFP process, see U.S. patent application Ser. No. 10/590,460, entitled “Controlling removal rate uniformity of an electropolishing process in integrated circuit fabrication” , filed on February 23, 2005, the entire content of which is incorporated herein by reference.
Step 503: removing the remained metal layer 105 on the non-recessed area by a metal layer chemical wet etch process. A metal layer dishing in the via 102 is controlled by the over etch time length of the metal layer chemical wet etch process. The material of the metal layer 105 is copper. The chemical for the copper layer chemical wet etch process mainly contains hydrogen peroxide (H2O2) , additive and hydrofluoric acid, and the concentration of the hydrofluoric acid is in the range of 2％to 10％. In the wet etch process, the etchant will be ejected to the surface of the substrate in pulse mode, as shown in FIG. 9. One pulse mode step is combined with a step of etchant and a step of DIW, for example, firstly 10 sec chemical wet etch is applied to the substrate, after that, a 5 sec DIW is applied to the substrate. A plurality of periodical steps form a wet etch process recipe. The periodical wet etch process will optimize the copper dishing in the recessed area. The DIW will fill in the recessed area and reduce the etch rate of this area. The substrate is fixed on a chuck, and is rotated with the chuck. The favor substrate spin speed for the wet etch process is from 200RPM to 600RPM. The removal profile is related to the spin speed. The higher spin  speed induces the higher substrate edge removal rate and lower substrate center removal rate； and conversely, the lower spin speed induces the lower substrate edge removal rate and higher substrate center removal rate. Furthermore, the etchant nozzle is movable during the process. The etch rate is influenced by the nozzle scan speed and scan area. The optimal scan speed is in range of 40mm/sec to 100mm/sec.
Step 505: removing metal layer residual and the barrier layer 104 on the non-recessed area by a barrier layer chemical wet etch process. The material of the barrier layer 104 contains Ti. The chemical for the barrier layer chemical wet etch process mainly contains hydrofluoric acid (HF) and additive, and the concentration of the hydrofluoric acid is in the range of 0.1％to 1％. In the barrier layer wet etch process, the etchant will be ejected to the surface of the substrate in pulse mode. As shown in FIG. 9, one pulse mode step is combined with a step of etchant and a step of DIW, for example, firstly 10 sec chemical wet etch is applied to substrate, after that, a 5 sec DIW is applied to the substrate. A plurality of periodical steps form a wet etch process recipe. The periodical wet etch process will optimize the barrier layer on the side wall of the recessed area over etch. The DIW will fill in the recessed area and reduce the etch rate of this area. The substrate is fixed on a chuck, and is rotated with the chuck. The favor substrate spin speed for the wet etch process is from 200RPM to 600RPM. The removal profile is related to the spin speed. The higher spin speed induces the higher substrate edge removal rate and lower substrate center removal rate； and conversely, the lower spin speed induces the lower substrate edge removal rate and higher substrate center removal rate. Furthermore, the etchant nozzle is movable during the process. The etch rate is influenced by the nozzle scan speed and scan area. The optimal scan speed is in range of 40mm/sec to 100mm/sec.
After the metal layer residual and the barrier layer 104 on the non-recessed area are removed by the barrier layer chemical wet etch process, the oxide layer 103 under the barrier layer 104 is exposed. The material of the oxide layer 103 is SiO2, and the thickness of the oxide layer 103 is about 2um. In order to achieve a flat top surface, preferably, a CMP process is applied to remove a part of the oxide layer  103. Normally, the removal thickness of the oxide layer 103 is 0.2um. The CMP process has a high selectivity between the oxide layer 103 and the copper metal layer 105, such as 100: 1. The CMP process can recover the roughness of the copper metal layer 105 in the via 102.
Referring to FIG. 6, FIG. 6 is a flow chart showing a TSV structure planarization process for removing the metal layer 105 and the barrier layer 104 formed on the non-recessed area according to another embodiment of the present invention. The TSV structure planarization process includes the following steps:
Step 601: removing all metal layer 105 deposited on the non-recessed area by a stress-free polishing (SFP) process. A metal layer dishing in the via 102 is controlled by SFP over polish. The SFP process is a chemical-electrical process. The metal layer 105 on the substrate 101 is as anode and an electrolyte nozzle is as cathode. The metal layer 105 is dissolved and polished by the contacted electrolyte when a positive voltage is applied between the anode and the cathode. For more detailed description of the SFP process, see U.S. patent application Ser. No. 10/590,460, entitled “Controlling removal rate uniformity of an electropolishing process in integrated circuit fabrication” , filed on February 23, 2005, the entire content of which is incorporated herein by reference.
Step 603: removing metal layer residual on the non-recessed area by a chemical-mechanical-planarization (CMP) process. After the SFP process, there maybe some metal layer residual is remained on the barrier layer 104 on the non-recessed area. In order to remove the metal layer residual, the chemical-mechanical-planarization process is applied to the substrate 101 to remove the metal layer residual. Since almost all metal layer on the non-recessed area is removed by the SFP process, therefore, the process time of the CMP process is short, which saves cost and avoids damage to the substrate.
Step 605: removing the barrier layer 104 on the non-recessed area by a barrier layer chemical wet etch process. The thickness of the barrier layer 104 on the  non-recessed area is about 0.2um-0.5um. The thickness of the barrier layer 104 on the non-recessed area is depended on process request. The material of the barrier layer 104 contains Ti, and correspondingly, the chemical for the barrier layer chemical wet etch process mainly contains hydrofluoric acid (HF) and additive, and the concentration of the hydrofluoric acid is in the range of 0.1％to 1％. In the barrier layer wet etch process, the etchant will be ejected to the surface of the substrate in pulse mode. As shown in FIG. 9, one pulse mode step is combined with a step of etchant and a step of DIW, for example, firstly 10 sec chemical wet etch is applied to substrate, after that, a 5 sec DIW is applied to the substrate. A plurality of periodical steps form a wet etch process recipe. The periodical wet etch process will optimize the barrier layer on the side wall of the recessed area over etch. The DIW will fill in the recessed area and reduce the etch rate of this area. The substrate is fixed on a chuck, and is rotated with the chuck. The favor substrate spin speed for the wet etch process is from 200RPM to 600RPM. The removal profile is related to the spin speed. The higher spin speed induces the higher substrate edge removal rate and lower substrate center removal rate； and conversely, the lower spin speed induces the lower substrate edge removal rate and higher substrate center removal rate. Furthermore, the etchant nozzle is movable during the process. The etch rate is influenced by the nozzle scan speed and scan area. The optimal scan speed is in range of 40mm/sec to 100mm/sec.
After the barrier layer 104 on the non-recessed area is removed by the barrier layer chemical wet etch process, the oxide layer 103 under the barrier layer 104 is exposed. The material of the oxide layer 103 is SiO2, and the thickness of the oxide layer 103 is about 2um. In order to achieve a flat top surface, preferably, a CMP process is applied to remove a part of the oxide layer 103. Normally, the removal thickness of the oxide layer 103 is 0.2um. The CMP process has a high selectivity between the oxide layer 103 and the copper metal layer 105, such as 100: 1. The CMP process can recover the roughness of the copper metal layer 105 in the via 102.
Referring to FIG. 7, FIG. 7 is a flow chart showing a TSV structure planarization process for removing the metal layer 105 and the barrier layer 104  formed on the non-recessed area according to another embodiment of the present invention. The TSV structure planarization process includes the following steps:
Step 701: removing a large proportion of metal layer 105 on the non-recessed area by a SFP process and remaining about 0.2um-0.5um metal layer 105 on the non-recessed area. The SFP process is a chemical-electrical process. The metal layer 105 on the substrate 101 is as anode and an electrolyte nozzle is as cathode. The metal layer 105 is dissolved and polished by the contacted electrolyte when a positive voltage is applied between the anode and the cathode. For more detailed description of the SFP process, see U.S. patent application Ser. No. 10/590,460, entitled “Controlling removal rate uniformity of an electropolishing process in integrated circuit fabrication” , filed on February 23, 2005, the entire content of which is incorporated herein by reference.
Step 703: removing the remained metal layer 105 on the non-recessed area by a chemical-mechanical-planarization process. A metal layer dishing in the via 102 is controlled by the over polish time length of the chemical-mechanical-planarization process. The material of the metal layer 105 is copper.
Step 705: removing metal layer residual and the barrier layer 104 on the non-recessed area by a barrier layer chemical wet etch process. The material of the barrier layer 104 contains Ti. The chemical for the barrier layer chemical wet etch process mainly contains hydrofluoric acid (HF) and additive, and the concentration of the hydrofluoric acid is in the range of 0.1％to 1％. In the barrier layer wet etch process, the etchant will be ejected to the surface of the substrate in pulse mode. As shown in FIG. 9, one pulse mode step is combined with a step of etchant and a step of DIW, for example, firstly 10 sec chemical wet etch is applied to substrate, after that, a 5 sec DIW is applied to the substrate. A plurality of periodical steps form a wet etch process recipe. The periodical wet etch process will optimize the barrier layer on the side wall of the recessed area over etch. The DIW will fill in the recessed area and reduce the etch rate of this area. The substrate is fixed on a chuck, and is rotated with  the chuck. The favor substrate spin speed for the wet etch process is from 200RPM to 600RPM. The removal profile is related to the spin speed. The higher spin speed induces the higher substrate edge removal rate and lower substrate center removal rate； and conversely, the lower spin speed induces the lower substrate edge removal rate and higher substrate center removal rate. Furthermore, the etchant nozzle is movable during the process. The etch rate is influenced by the nozzle scan speed and scan area. The optimal scan speed is in range of 40mm/sec to 100mm/sec.
After the metal layer residual and the barrier layer 104 on the non-recessed area are removed by the barrier layer chemical wet etch process, the oxide layer 103 under the barrier layer 104 is exposed. The material of the oxide layer 103 is SiO2, and the thickness of the oxide layer 103 is about 2um. In order to achieve a flat top surface, preferably, a CMP process is applied to remove a part of the oxide layer 103. Normally, the removal thickness of the oxide layer 103 is 0.2um. The CMP process has a high selectivity between the oxide layer 103 and the copper metal layer 105, such as 100: 1. The CMP process can recover the roughness of the copper metal layer 105 in the via 102.
Referring to FIG. 8, FIG. 8 is a flow chart showing a TSV structure planarization process for removing the metal layer 105 and the barrier layer 104 formed on the non-recessed area according to another embodiment of the present invention. The TSV structure planarization process includes the following steps:
Step 801: removing a large proportion of metal layer 105 on the non-recessed area by a metal layer chemical wet etch process and remaining about 0.2um-0.5um metal layer 105 on the non-recessed area. The material of the metal layer 105 preferably selects copper, and correspondingly, the chemical for copper chemical wet etch process mainly contains hydrogen peroxide (H2O2) , additive and hydrofluoric acid, and the concentration of the hydrofluoric acid is in the range of 2％to 10％.
Step 803: removing the remained metal layer 105 on the non-recessed area by a chemical-mechanical-planarization process. A metal layer dishing in the via  102 is controlled by the over polish time length of the chemical-mechanical-planarization process.
Step 805: removing metal layer residual and the barrier layer 104 on the non-recessed area by a barrier layer chemical wet etch process. The material of the barrier layer 104 contains Ti. The chemical for the barrier layer chemical wet etch process mainly contains hydrofluoric acid (HF) and additive, and the concentration of the hydrofluoric acid is in the range of 0.1％to 1％.
After the metal layer residual and the barrier layer 104 on the non-recessed area are removed by the barrier layer chemical wet etch process, the oxide layer 103 under the barrier layer 104 is exposed. The material of the oxide layer 103 is SiO2, and the thickness of the oxide layer 103 is about 2um. In order to achieve a flat top surface, preferably, a CMP process is applied to remove a part of the oxide layer 103. Normally, the removal thickness of the oxide layer 103 is 0.2um. The CMP process has a high selectivity between the oxide layer 103 and the copper metal layer 105, such as 100: 1. The CMP process can recover the roughness of the copper metal layer 105 in the via 102.
Referring to FIG. 10, FIG. 10 is a block diagram showing a TSV structure planarization apparatus according to the present invention. The apparatus includes an EFEM (Equipment Front End Module) 1001, a buffer station 1003, a process robot 1005, two SFP modules 1007 which are stacked, a CMP module 1009, a metrology module 1011, a brush clean module 1013, a wet etch module 1015 and a clean module 1017. The metrology module 1011 and the brush clean module 1013 are stacked. The wet etch module 1015 and the clean module 1017 are stacked. The apparatus also includes an electrical module, a gas module and a plumbing module. The SFP module 1007 is used for applying a stress-free polishing process to the substrate to remove the metal layer on the non-recessed area of the substrate. The CMP module 1009 is used for applying a chemical-mechanical-planarization process to the substrate to remove the metal layer on the non-recessed area. The wet etch  module 1015 is used for applying a chemical wet etch process to the substrate to remove the metal layer and/or the barrier layer on the non-recessed area. The chemical wet etch process includes a metal layer chemical wet etch process and/or a barrier layer chemical wet etch process. The wet etch process takes a pulse mode and each pulse mode step is combined with a step of etchant and a step of DIW.
Referring to FIG. 11, FIG. 11 is a block diagram showing an exemplary substrate transferring sequence. An EFEM robot takes an unprocessed substrate from a load port and transfers the substrate to the buffer station 1003. The process robot 1005 takes the substrate from the buffer station 1003 and transfers the substrate to the metrology module 1011 for measuring the thickness of the metal layer. After the metrology module 1011 measuring the thickness of the metal layer, the process robot 1005 takes the substrate from the metrology module 1011 and transfers the substrate to one of the SFP modules 1007. In the SFP module 1007, a SFP process is applied to the substrate to remove all metal layer on the non-recessed area. After the SFP process is completed, the process robot 1005 takes the substrate from the SFP module 1007 and transfers the substrate to the clean module 1017 for cleaning the substrate. Then the process robot 1005 takes the substrate from the clean module 1017 and transfers the substrate to the CMP module 1009. In the CMP module 1009, a CMP process is applied to the substrate to remove metal layer residual on the non-recessed area. After the CMP process is completed, the process robot 1005 takes the substrate from the CMP module 1009 and transfers the substrate to the brush clean module 1013 for cleaning the substrate. Then the process robot 1005 takes the substrate from the brush clean module 1013 and transfers the substrate to the wet etch module 1015. In the wet etch module 1015, a barrier layer chemical wet etch process is applied to the substrate to remove the barrier layer on the non-recessed area. After the barrier layer chemical wet etch process is completed, the process robot 1005 takes the substrate from the wet etch module 1015 and transfers the substrate to the clean module 1017 for cleaning the substrate. Then the process robot 1005 takes the substrate from the clean module 1017 and transfers the substrate to the buffer station 1003. At last, the EFEM robot takes the  substrate from the buffer station 1003 and transfers the substrate to the substrate load port.
If the CMP module 1009 has no function of measuring the thickness of the metal layer, before applying the CMP process to the substrate, the substrate should be transferred to the metrology module 1011 to measure the post SFP metal layer thickness, as shown in FIG. 12.
Besides the above substrate transferring sequences, other substrate transferring sequences can be carried out according to different process demands by using the apparatus.
As described above, comparing to a conventional TSV structure planarization process, which uses the CMP process to remove the metal layer and the barrier layer on the non-recessed area, and a part of the oxide layer, the present invention utilizes the SFP process, the metal layer chemical wet etch process and the barrier layer chemical wet etch process to stress-free remove the metal layer 105 and the barrier layer 104 on the non-recessed area, just retaining the metal layer 105 and the barrier layer 104 in the vias 102, as shown in FIG. 2, which improves the TSV structure metal layer dishing uniformity, reduces stress during the planarization process, minimizes the opportunity of the substrate micro-crack, and shortens the CMP process duration, finally reduces the planarization process cost and reduces waste chemical drain.
The foregoing description of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. Such modifications and variations that may be apparent to those skilled in the art are intended to be included within the scope of this invention as defined by the accompanying claims.

Claims (34)

  1. A TSV structure planarization process, wherein the TSV structure includes a substrate, vias formed in the substrate, an oxide layer formed on the substrate, a barrier layer formed on the oxide layer, bottom and sidewall of the vias, a metal layer formed in the vias and on the barrier layer, wherein the TSV structure planarization process comprises:
    removing all metal layer formed on the non-recessed area of the substrate by a stress-free polishing process； and
    removing metal layer residual and the barrier layer on the non-recessed area by a chemical wet etch process.
  2. The TSV structure planarization process as claimed in claim 1, wherein the chemical wet etch process includes a barrier layer chemical wet etch process.
  3. The TSV structure planarization process as claimed in claim 2, wherein the material of the metal layer is copper and the material of the barrier layer contains Ti, the chemical for the barrier layer chemical wet etch process contains hydrofluoric acid and additive.
  4. The TSV structure planarization process as claimed in claim 1, wherein the step of removing metal layer residual and the barrier layer on the non-recessed area by a chemical wet etch process further comprises:
    removing metal layer residual on the non-recessed area of the substrate by a metal layer chemical wet etch process； and
    removing the barrier layer on the non-recessed area by a barrier layer chemical wet etch process.
  5. The TSV structure planarization process as claimed in claim 4, wherein the material of the metal layer is copper, the chemical for the metal layer chemical wet etch process contains hydrogen peroxide, additive and hydrofluoric acid.
  6. The TSV structure planarization process as claimed in claim 4, wherein the material of the barrier layer contains Ti, the chemical for the barrier layer chemical wet etch process contains hydrofluoric acid and additive.
  7. The TSV structure planarization process as claimed in claim 1, wherein the chemical wet etch process takes a pulse mode.
  8. The TSV structure planarization process as claimed in claim 7, wherein each pulse mode step is combined with a step of etchant and a step of DIW.
  9. The TSV structure planarization process as claimed in claim 1, wherein after the metal layer residual and the barrier layer on the non-recessed area are removed by the chemical wet etch process, the oxide layer under the barrier layer is exposed, and a part of the oxide layer is removed by a CMP process.
  10. The TSV structure planarization process as claimed in claim 1, wherein the oxide layer is SiO2.
  11. A TSV structure planarization process, wherein the TSV structure includes a substrate, vias formed in the substrate, an oxide layer formed on the substrate, a barrier layer formed on the oxide layer, bottom and sidewall of the vias, a metal layer formed in the vias and on the barrier layer, wherein the TSV structure planarization process comprises:
    removing a large proportion of metal layer on a non-recessed area of the substrate by a stress-free polishing process and remaining a certain thickness of the metal layer on the non-recessed area；
    removing the remained metal layer on the non-recessed area by a metal layer chemical wet etch process； and
    removing metal layer residual and the barrier layer on the non-recessed area by a barrier layer chemical wet etch process.
  12. The TSV structure planarization process as claimed in claim 11, wherein the thickness of the remained metal layer on the non-recessed area after the stress-free polishing process is 0.2um-0.5um.
  13. The TSV structure planarization process as claimed in claim 11, wherein the material of the metal layer is copper, the chemical for the metal layer chemical wet etch process contains hydrogen peroxide, additive and hydrofluoric acid.
  14. The TSV structure planarization process as claimed in claim 11, wherein the material of the barrier layer contains Ti, the chemical for the barrier layer chemical wet etch process contains hydrofluoric acid and additive.
  15. The TSV structure planarization process as claimed in claim 11, wherein the metal layer chemical wet etch process takes a pulse mode, and each pulse mode step is combined with a step of etchant and a step of DIW.
  16. The TSV structure planarization process as claimed in claim 11, wherein the barrier layer chemical wet etch process takes a pulse mode, and each pulse mode step is combined with a step of etchant and a step of DIW.
  17. The TSV structure planarization process as claimed in claim 11, wherein after the metal layer residual and the barrier layer on the non-recessed area are removed, the oxide layer under the barrier layer is exposed and a part of the oxide layer is removed by a CMP process.
  18. A TSV structure planarization process, wherein the TSV structure includes a substrate, vias formed in the substrate, an oxide layer formed on the substrate, a barrier layer formed on the oxide layer, bottom and sidewall of the vias, a metal layer formed in the vias and on the barrier layer, wherein the TSV structure planarization process comprises:
    removing all metal layer formed on a non-recessed area of the substrate by a stress-free polishing process；
    removing metal layer residual on the non-recessed area by a chemical-mechanical-planarization process； and
    removing the barrier layer on the non-recessed area by a barrier layer chemical wet etch process.
  19. The TSV structure planarization process as claimed in claim 18, wherein the material of the barrier layer contains Ti, the chemical for the barrier layer chemical wet etch process contains hydrofluoric acid and additive.
  20. The TSV structure planarization process as claimed in claim 18, wherein the barrier layer chemical wet etch process takes a pulse mode and each pulse mode step is combined with a step of etchant and a step of DIW.
  21. The TSV structure planarization process as claimed in claim 18, wherein after the barrier layer on the non-recessed area is removed, the oxide layer under the barrier layer is exposed, and a part of the oxide layer is removed by a CMP process.
  22. A TSV structure planarization process, wherein the TSV structure includes a substrate, vias formed in the substrate, an oxide layer formed on the substrate, a barrier layer formed on the oxide layer, bottom and sidewall of the vias, a metal layer formed in the vias and on the barrier layer, wherein the TSV structure planarization process comprises:
    removing a large proportion of metal layer on a non-recessed area of the substrate and remaining a certain thickness of the metal layer on the non-recessed area；
    removing the remained metal layer on the non-recessed area by a chemical-mechanical-planarization process； and
    removing metal layer residual and the barrier layer on the non-recessed area by a barrier layer chemical wet etch process.
  23. The TSV structure planarization process as claimed in claim 22, wherein the large proportion of metal layer on the non-recessed area of the substrate is removed by a stress-free polishing process.
  24. The TSV structure planarization process as claimed in claim 22, wherein the large proportion of metal layer on the non-recessed area of the substrate is removed by a metal layer chemical wet etch process.
  25. The TSV structure planarization process as claimed in claim 24, wherein the material of the metal layer is copper, the chemical for the metal layer chemical wet etch process contains hydrogen peroxide, additive and hydrofluoric acid.
  26. The TSV structure planarization process as claimed in claim 24, wherein the metal layer chemical wet etch process takes a pulse mode, and each pulse mode step is combined with a step of etchant and a step of DIW.
  27. The TSV structure planarization process as claimed in claim 22, wherein the material of the barrier layer contains Ti, the chemical for the barrier layer chemical wet etch process contains hydrofluoric acid and additive.
  28. The TSV structure planarization process as claimed in claim 22, wherein the barrier layer chemical wet etch process takes a pulse mode and each pulse mode step is combined with a step of etchant and a step of DIW.
  29. The TSV structure planarization process as claimed in claim 22, wherein the thickness of the remained metal layer on the non-recessed area is 0.2um-0.5um.
  30. The TSV structure planarization process as claimed in claim 22, wherein after the metal layer residual and the barrier layer on the non-recessed area are removed, the oxide layer under the barrier layer is exposed, and a part of the oxide layer is removed by a CMP process.
  31. A TSV structure planarization apparatus, wherein the TSV structure includes a substrate, vias formed in the substrate, an oxide layer formed on the substrate, a barrier layer formed on the oxide layer, bottom and sidewall of the vias, a metal layer formed in the vias and on the barrier layer, wherein the TSV structure planarization apparatus comprises:
    at least one SFP module for applying a stress-free polishing process to the substrate to remove the metal layer on a non-recessed area of the substrate；
    a CMP module for applying a chemical-mechanical-planarization process to the substrate to remove the metal layer on the non-recessed area； and
    a wet etch module for applying a chemical wet etch process to the substrate to remove the metal layer and/or the barrier layer on the non-recessed area.
  32. The TSV structure planarization apparatus as claimed in claim 31, wherein the chemical wet etch process includes a metal layer chemical wet etch process and/or a barrier layer chemical wet etch process.
  33. The TSV structure planarization apparatus as claimed in claim 31, wherein the wet etch process takes a pulse mode and each pulse mode step is combined with a step of etchant and a step of DIW.
  34. The TSV structure planarization apparatus as claimed in claim 31, further comprising:
    a metrology module for measuring the thickness of the metal layer；
    a brush clean module for cleaning the substrate after the chemical-mechanical-planarization process； and
    a clean module for cleaning the substrate after the stress-free polishing process or the chemical wet etch process.
PCT/CN2016/078656 2016-04-07 2016-04-07 Tsv structure planarization process and apparatus Ceased WO2017173613A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
PCT/CN2016/078656 WO2017173613A1 (en) 2016-04-07 2016-04-07 Tsv structure planarization process and apparatus
SG11201808636TA SG11201808636TA (en) 2016-04-07 2016-04-07 Tsv structure planarization process and apparatus
KR1020187031089A KR102599825B1 (en) 2016-04-07 2016-04-07 Planarization process and device for TSV structures
CN201680084216.8A CN108886016B (en) 2016-04-07 2016-04-07 Planarization process and device of TSV structure
TW105133926A TWI774645B (en) 2016-04-07 2016-10-20 Planarization device for TSV structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/078656 WO2017173613A1 (en) 2016-04-07 2016-04-07 Tsv structure planarization process and apparatus

Publications (1)

Publication Number Publication Date
WO2017173613A1 true WO2017173613A1 (en) 2017-10-12

Family

ID=60000123

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/078656 Ceased WO2017173613A1 (en) 2016-04-07 2016-04-07 Tsv structure planarization process and apparatus

Country Status (5)

Country Link
KR (1) KR102599825B1 (en)
CN (1) CN108886016B (en)
SG (1) SG11201808636TA (en)
TW (1) TWI774645B (en)
WO (1) WO2017173613A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114156231A (en) * 2021-11-04 2022-03-08 上海至临半导体技术有限公司 Method for improving wafer bridging wire structure

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113035727A (en) * 2019-12-09 2021-06-25 盛美半导体设备(上海)股份有限公司 Semiconductor packaging structure and packaging method
CN113059405A (en) * 2019-12-30 2021-07-02 盛美半导体设备(上海)股份有限公司 Processing method and cleaning device for semiconductor structure
WO2025136046A1 (en) * 2023-12-19 2025-06-26 솔브레인 주식회사 Method for planarizing structure of hybrid bonding and device for planarizing structure of hybrid bonding

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103474395A (en) * 2013-09-13 2013-12-25 华进半导体封装先导技术研发中心有限公司 TSV planarization method
US20140004698A1 (en) * 2012-06-29 2014-01-02 Micron Technology, Inc. Devices, systems, and methods related to planarizing semiconductor devices after forming openings
CN105144363A (en) * 2012-11-27 2015-12-09 盛美半导体设备（上海）有限公司 Method for forming interconnection structures
CN105336672A (en) * 2014-07-24 2016-02-17 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and formation method therefor

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020192941A1 (en) * 2001-06-19 2002-12-19 Chia-Lin Hsu Method for reducing dishing in copper chemical mechanical polishing process
US8372757B2 (en) * 2003-10-20 2013-02-12 Novellus Systems, Inc. Wet etching methods for copper removal and planarization in semiconductor processing
WO2010020092A1 (en) * 2008-08-20 2010-02-25 Acm Research (Shanghai) Inc. Barrier layer removal method and apparatus
US8415254B2 (en) * 2008-11-20 2013-04-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method for removing dummy poly in a gate last process
CN101882595B (en) * 2009-05-08 2014-07-09 盛美半导体设备（上海）有限公司 Method and device for removing barrier layer
US9305865B2 (en) * 2013-10-31 2016-04-05 Micron Technology, Inc. Devices, systems and methods for manufacturing through-substrate vias and front-side structures
SG11201508467SA (en) * 2013-04-22 2015-11-27 Acm Research Shanghai Inc Method and apparatus for through-silicon vias reveal
CN103474394B (en) * 2013-09-11 2015-07-08 华进半导体封装先导技术研发中心有限公司 TSV process method without metal CMP
CN105390384B (en) * 2015-10-29 2018-05-01 上海集成电路研发中心有限公司 A kind of method that silica is removed during unstressed electrochemical polish copper

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140004698A1 (en) * 2012-06-29 2014-01-02 Micron Technology, Inc. Devices, systems, and methods related to planarizing semiconductor devices after forming openings
CN105144363A (en) * 2012-11-27 2015-12-09 盛美半导体设备（上海）有限公司 Method for forming interconnection structures
CN103474395A (en) * 2013-09-13 2013-12-25 华进半导体封装先导技术研发中心有限公司 TSV planarization method
CN105336672A (en) * 2014-07-24 2016-02-17 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and formation method therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114156231A (en) * 2021-11-04 2022-03-08 上海至临半导体技术有限公司 Method for improving wafer bridging wire structure

Also Published As

Publication number Publication date
TW201737417A (en) 2017-10-16
CN108886016A (en) 2018-11-23
TWI774645B (en) 2022-08-21
CN108886016B (en) 2023-03-10
KR102599825B1 (en) 2023-11-08
KR20180133433A (en) 2018-12-14
SG11201808636TA (en) 2018-10-30

Similar Documents

Publication Publication Date Title
US20180182665A1 (en) Processed Substrate
JP5220398B2 (en) Electronic structure manufacturing method
US10037940B2 (en) Reliable packaging and interconnect structures
US9466501B2 (en) Method and apparatus for improving CMP planarity
CN100419963C (en) Formation of semiconductor structures using a combination of planarization methods and electropolishing
Kumar et al. Robust TSV via-middle and via-reveal process integration accomplished through characterization and management of sources of variation
WO2017173613A1 (en) Tsv structure planarization process and apparatus
CN102054748B (en) Formation method of copper interconnection and processing method of dielectric layer
US10008391B2 (en) Method of forming copper interconnects
US20150206801A1 (en) Devices, systems, and methods related to planarizing semiconductor devices after forming openings
US20040253809A1 (en) Forming a semiconductor structure using a combination of planarizing methods and electropolishing
TWI601185B (en) A semiconductor wafer cleaning tank and a method of manufacturing a bonded wafer
US6924234B2 (en) Method and apparatus for polishing a copper layer and method for forming a wiring structure using copper
JP2007511095A (en) Integrated circuit interconnect fabrication system and method
JP2023171260A (en) Method for forming a semiconductor device and substrate processing system for forming a semiconductor device
US11887888B2 (en) Multi-pass plating process with intermediate rinse and dry
US20150017798A1 (en) Method of manufacturing through-silicon-via
CN104835748B (en) A method of improving semiconductor devices bonding reliability
US9768064B1 (en) Formation method of semiconductor device structure
Balan et al. CMP process optimization for bonding applications
CN104821279B (en) The forming method of semiconductor devices
WO2016058174A1 (en) Barrier layer removal method and semiconductor structure forming method
CN106558530A (en) A kind of manufacture method of semiconductor device
US20070151860A1 (en) Method for forming a copper metal interconnection of a semiconductor device
KR20070034782A (en) Chemical mechanical polishing method of polysilicon film, recess gate forming method and landing plug poly forming method using same

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 11201808636T

Country of ref document: SG

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20187031089

Country of ref document: KR

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16897548

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 16897548

Country of ref document: EP

Kind code of ref document: A1