CN114156231A - Method for improving wafer bridging wire structure - Google Patents

Method for improving wafer bridging wire structure Download PDF

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Publication number
CN114156231A
CN114156231A CN202111302507.9A CN202111302507A CN114156231A CN 114156231 A CN114156231 A CN 114156231A CN 202111302507 A CN202111302507 A CN 202111302507A CN 114156231 A CN114156231 A CN 114156231A
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CN
China
Prior art keywords
silicon
wafer
wet cleaning
holes
wire structure
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Pending
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CN202111302507.9A
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Chinese (zh)
Inventor
陈新来
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Shanghai Zhilin Semiconductor Technology Co ltd
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Shanghai Zhilin Semiconductor Technology Co ltd
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Priority to CN202111302507.9A priority Critical patent/CN114156231A/en
Publication of CN114156231A publication Critical patent/CN114156231A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers

Abstract

The invention discloses a method for improving a wafer bridging wire structure, which comprises the following steps: step S10, etching through silicon vias on a plurality of wafers respectively; step S20, performing first wet cleaning on the silicon through holes respectively; step S30, forming first barrier layers on the inner walls of the silicon through holes respectively; step S40, performing second wet cleaning on the plurality of silicon through holes respectively; step S50, a plurality of through silicon vias are embedded with a lead structure; step S60, carrying out wet cleaning for the third time on the silicon through holes respectively; and step S90, sequentially overlapping and fixing a plurality of wafers from bottom to top. By applying the method, the wafer bridging wire structure with higher stability and better flatness can be prepared, the influence of pollutants and other particles is eliminated while the flatness of the wire structure in the installation process is improved, the occurrence of a charge concentration phenomenon is reduced, and the quality of corresponding chip products is guaranteed.

Description

Method for improving wafer bridging wire structure
Technical Field
The invention relates to the technical field of wafer interconnection structures, in particular to a method for improving a wafer bridging wire structure.
Background
In the process of wafer production, especially in the process of complex chip assembly, the chips are often required to be connected in series, and it is common that an interconnection structure with a high aspect ratio is established on the surface of the wafer by using a Through Silicon Via (TSV) process, and the requirement of the complex chips for connection in series is met by forming an interconnected bridging wire structure in the TSV. However, while the micro-structures on the chip are more and more nano-scaled, the integration of the transistors is gradually increased from tens of thousands to hundreds of millions in the past under the same unit area and volume, and thus, the size and precision of the bridge wire structure are more strictly required. Under the prior art, no matter in the process of arranging the through silicon via or installing the wire structure, once an abnormal recess or protrusion is generated, a charge concentration phenomenon can be generated at a corresponding position when current passes through the corresponding position, and the concentration phenomenon can easily cause the rapid movement of charges so as to cause the occurrence of a short circuit phenomenon, so that the quality of the bridging wire structure is greatly influenced.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a method for improving a wafer bridge wire structure, comprising:
step S10, etching through silicon vias on a plurality of wafers respectively;
step S20, performing first wet cleaning on the silicon through holes respectively;
step S30, forming first barrier layers on the inner walls of the silicon through holes respectively;
step S40, performing second wet cleaning on the plurality of silicon through holes respectively;
step S50, a plurality of through silicon vias are embedded with a lead structure;
step S60, carrying out wet cleaning for the third time on the silicon through holes respectively;
and step S90, sequentially overlapping and fixing a plurality of wafers from bottom to top.
In another preferred embodiment, the method further comprises:
step S70, forming a second barrier layer at the end of the wire;
and step S80, performing a fourth wet cleaning on the plurality of second barrier layers.
In another preferred embodiment, the plurality of wafers includes: an upper layer wafer, a middle layer wafer and a lower layer wafer;
in another preferred embodiment, the step S10 includes:
step S11, etching a plurality of first through silicon holes on the upper layer wafer;
step S12, etching a plurality of second through silicon holes on the middle layer wafer;
step S13, etching a plurality of third through silicon holes on the lower layer wafer;
in another preferred embodiment, each of the first through-silicon vias is disposed opposite to one of the second through-silicon vias, and each of the second through-silicon vias is disposed opposite to one of the third through-silicon vias.
In another preferred embodiment, the inner diameter of the first through-silicon-via is larger than the inner diameter of the second through-silicon-via, and the inner diameter of the second through-silicon-via is larger than the inner diameter of the third through-silicon-via.
In another preferred embodiment, the inner diameter of the first through-silicon-via is 50nm to 100nm, the inner diameter of the second through-silicon-via is equal to or less than 20nm, and the inner diameter of the third through-silicon-via is equal to or less than 10 nm.
In another preferred embodiment, the upper layer wafer, the middle layer wafer and the lower layer wafer are sequentially arranged from top to bottom, and each of the wire structures sequentially passes through the first through silicon via, the second through silicon via and the third through silicon via.
In another preferred embodiment, the first wet cleaning, the second wet cleaning, the third wet cleaning, and the fourth wet cleaning each include:
step S21, cleaning the through silicon via;
and step S22, drying the through silicon via.
In another preferred embodiment, the cleaning process comprises:
s21.1, washing the through silicon via by using a hydrofluoric acid solution;
s21.2, washing the through silicon holes by using an APM solution;
s21.3, washing the through silicon holes by using an SPM solution;
and step S21.4, rinsing the through silicon holes by using ultrapure water.
In another preferred embodiment, the wire structure is made of copper.
In another preferred embodiment, the first barrier layer and the second barrier layer are made of titanium or tungsten.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following positive effects: by applying the method, the wafer bridging wire structure with higher stability and better flatness can be prepared, the influence of pollutants and other particles is eliminated while the flatness of the wire structure in the installation process is improved, the occurrence of a charge concentration phenomenon is reduced, and the quality of corresponding chip products is guaranteed.
Drawings
FIG. 1 is a schematic view of a wafer bridge wire structure according to an improved method of the present invention;
FIG. 2 is a partially enlarged view of a wafer bridge wire structure according to the method for improving the wafer bridge wire structure of the present invention.
In the drawings:
1. an upper layer wafer; 2. a middle layer wafer; 3. a lower layer wafer; 11. a first through-silicon-via; 21. a second through-silicon-via; 31. a third through-silicon-via; 4. a first barrier layer; 5. a second barrier layer; 6. an uneven portion; 7. and a wire structure.
Detailed Description
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
As shown in fig. 1 and 2, a method for improving a wafer bridge wire structure 7 according to a preferred embodiment includes:
step S10, etching through silicon vias on a plurality of wafers respectively;
step S20, performing first wet cleaning on the silicon through holes respectively;
step S30, forming first barrier layers 4 on the inner walls of the plurality of through silicon vias respectively;
step S40, performing second wet cleaning on the silicon through holes respectively;
step S50, inserting a lead structure 7 into the through-silicon via;
step S60, respectively carrying out a third wet cleaning on the plurality of silicon through holes
In step S90, a plurality of wafers are sequentially stacked and fixed from bottom to top.
Further, as a preferred embodiment, in the step S10, the uneven portion 6 is easily generated during the etching of the through silicon via, i.e. the position where the charge is easily concentrated, i.e. the position indicated by the arrow in fig. 2, the uneven portion 6 is generated at the through silicon via, an oxide layer with uneven growth is generated due to the oxidation of the silicon-based material at the through silicon via, or new contaminants or particles such as micro-dust and some metal particles may be introduced during the processes of etching the through silicon via, forming the first blocking layer 4, forming the second blocking layer 5 and inserting the wire structure 7, and the uneven portion 6 is also generated due to the used materials or corresponding devices during the corresponding processes; furthermore, the unevenness 6 is thus eliminated or weakened or the degree of charge concentration is further reduced, respectively, with one wet cleaning.
Further, as a preferred embodiment, the method further comprises:
step S70, forming a second barrier layer 5 on the end of the wire;
in step S80, a fourth wet cleaning is performed on the plurality of second barrier layers 5.
Further, as a preferred embodiment, the plurality of wafers includes: an upper layer wafer 1, a middle layer wafer 2 and a lower layer wafer 3;
further, as a preferred embodiment, the step S10 includes:
step S11, etching a plurality of first through silicon vias 11 on the upper layer wafer 1;
step S12, etching a plurality of second through silicon vias 21 on the middle-layer wafer 2;
in step S13, a plurality of third through-silicon vias 31 are etched in the lower layer wafer 3.
Further, as a preferred embodiment, each first through-silicon-via 11 is disposed opposite to a second through-silicon-via 21, and each second through-silicon-via 21 is disposed opposite to a third through-silicon-via 31.
Further, as a preferred embodiment, the inner diameter of the first through-silicon-via 11 is larger than the inner diameter of the second through-silicon-via 21, and the inner diameter of the second through-silicon-via 21 is larger than the inner diameter of the third through-silicon-via 31.
Further, as a preferred embodiment, the inner diameter of the first through silicon via 11 is 50nm to 100 nm.
Further, as a preferred embodiment, the inner diameter of the second through-silicon-via 21 is less than or equal to 20 nm.
Further, as a preferred embodiment, the inner diameter of the third through silicon via 31 is less than or equal to 10 nm.
Further, as a preferred embodiment, the upper layer wafer 1, the middle layer wafer 2 and the lower layer wafer 3 are sequentially disposed from top to bottom, and each of the wire structures 7 is sequentially disposed through the first through silicon via 11, the second through silicon via 21 and the third through silicon via 31.
Further, as a preferred embodiment, the first wet cleaning, the second wet cleaning, the third wet cleaning, and the fourth wet cleaning all include:
step S21, cleaning the through silicon via;
and step S22, drying the through silicon via.
Further, as a preferred embodiment, the cleaning process includes:
s21.1, washing the through silicon via by using a hydrofluoric acid solution; further, DHF solution, BOE solution, or the like may be mixed into the hydrofluoric acid solution to clean and remove the uneven portion 6 formed of silicon oxide.
S21.2, washing the through silicon holes by using an APM solution; further, a smooth oxide layer is generated at the corresponding cleaning position by the APM solution and static electricity is removed, so that other contaminants or particles and the like are not easily adhered to the surface thereof.
S21.3, washing the through silicon holes by using an SPM solution; further, the corresponding organic substance such as photoresist or the unevenness 6 of the metal, alloy can be removed by the SPM solution.
And step S21.4, rinsing the through silicon holes by using ultrapure water. Further, the chemical solution and the remaining contaminants are thoroughly removed by the ultrapure water.
Further, as a preferred embodiment, the lead structure 7 is made of copper.
Further, as a preferred embodiment, the first barrier layer 4 and the second barrier layer 5 are made of titanium or tungsten.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope and the implementation manner of the present invention.
The present invention also has the following embodiments in addition to the above:
in a further embodiment of the invention, the drying process comprises:
step S22.1, covering isopropanol on the surface of the wafer;
and S22.2, covering the surface of the wafer with supercritical fluid.
In a further embodiment of the present invention, the supercritical fluid is supercritical carbon dioxide.
In a further embodiment of the invention, water molecules are separated from the surface of the wafer through isopropanol, and then the isopropanol and the water molecules are relatively separated from the surface of the wafer together through supercritical fluid.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims (10)

1. A method for improving a wafer bridge wire structure, comprising:
step S10, etching through silicon vias on a plurality of wafers respectively;
step S20, performing first wet cleaning on the silicon through holes respectively;
step S30, forming first barrier layers on the inner walls of the silicon through holes respectively;
step S40, performing second wet cleaning on the plurality of silicon through holes respectively;
step S50, a plurality of through silicon vias are embedded with a lead structure;
step S60, carrying out wet cleaning for the third time on the silicon through holes respectively;
and step S90, sequentially overlapping and fixing a plurality of wafers from bottom to top.
2. The method as claimed in claim 1, further comprising:
step S70, forming a second barrier layer at the end of the wire;
and step S80, performing a fourth wet cleaning on the plurality of second barrier layers.
3. The method as claimed in claim 1, wherein the step of forming the bridge wire structure is further performed,
the plurality of wafers includes: an upper layer wafer, a middle layer wafer and a lower layer wafer;
the step S10 includes:
step S11, etching a plurality of first through silicon holes on the upper layer wafer;
step S12, etching a plurality of second through silicon holes on the middle layer wafer;
step S13, etching a plurality of third through silicon holes on the lower layer wafer;
each first through silicon via is arranged opposite to one second through silicon via, and each second through silicon via is arranged opposite to one third through silicon via.
4. The method as claimed in claim 3, wherein the first through-silicon-via has an inner diameter larger than that of the second through-silicon-via, and the second through-silicon-via has an inner diameter larger than that of the third through-silicon-via.
5. The method as claimed in claim 4, wherein the first through-silicon-via has an inner diameter of 50nm to 100nm, the second through-silicon-via has an inner diameter of 20nm or less, and the third through-silicon-via has an inner diameter of 10nm or less.
6. The method as claimed in claim 4, wherein the upper wafer, the middle wafer and the lower wafer are sequentially disposed from top to bottom, and each of the conductive wire structures is sequentially disposed through the first through-silicon-via, the second through-silicon-via and the third through-silicon-via.
7. The method for improving a wafer bridge wire structure according to claim 2, wherein the first wet cleaning, the second wet cleaning, the third wet cleaning and the fourth wet cleaning each comprise:
step S21, cleaning the through silicon via;
and step S22, drying the through silicon via.
8. The method as claimed in claim 4, wherein the cleaning process comprises:
s21.1, washing the through silicon via by using a hydrofluoric acid solution;
s21.2, washing the through silicon holes by using an APM solution;
s21.3, washing the through silicon holes by using an SPM solution;
and step S21.4, rinsing the through silicon holes by using ultrapure water.
9. The method as claimed in claim 1, wherein the conductive wire structure is made of copper.
10. The method as claimed in claim 2, wherein the first barrier layer and the second barrier layer are made of titanium or tungsten.
CN202111302507.9A 2021-11-04 2021-11-04 Method for improving wafer bridging wire structure Pending CN114156231A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111302507.9A CN114156231A (en) 2021-11-04 2021-11-04 Method for improving wafer bridging wire structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111302507.9A CN114156231A (en) 2021-11-04 2021-11-04 Method for improving wafer bridging wire structure

Publications (1)

Publication Number Publication Date
CN114156231A true CN114156231A (en) 2022-03-08

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111302507.9A Pending CN114156231A (en) 2021-11-04 2021-11-04 Method for improving wafer bridging wire structure

Country Status (1)

Country Link
CN (1) CN114156231A (en)

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