WO2017172987A1

WO2017172987A1 - Power consumption measurement for system-on-chip devices

Info

Publication number: WO2017172987A1
Application number: PCT/US2017/024850
Authority: WO
Inventors: Souvik K. CHAKRAVARTY; Sukumar GHORAI
Original assignee: Intel Corporation
Priority date: 2016-04-01
Filing date: 2017-03-29
Publication date: 2017-10-05

Abstract

A power consumption monitoring system for a SoC is disclosed. In particular, a system to measure power consumption of a SoC, even when the SoC is in a low power state, is disclosed. The system comprises a SoC, a microcontroller and a memory buffer. The microcontroller determines a current on the power rails of the SoC and adds an information element including indication of the current to the memory buffer.

Description

POWER CONSUMPTION MEASUREMENT FOR SYSTEM-ON-CHIP DEVICES

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of and priority to previously filed India Patent

Application Serial Number 201611011597, filed April 1, 2016, the subject matter of which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

Examples described herein are generally related to power consumption measurement and more particularly to power consumption measurement for mobile and System-on-Chip devices.

BACKGROUND

Power consumption for mobile devices is a primary concern due to the restrictions on power consumption imposed by battery sizes. Said differently, mobile devices power consumption is restricted by the battery size of the mobile device. Optimization of power consumption of mobile devices typically requires a complex and intrusive analysis of power consumption on a per power rail basis. This often requires analysis using various data acquisition instruments. Setup and usage of such data acquisition instruments requires an additional hardware rework (in some case) and require a significant capital investment and is often platform dependent. Furthermore, optimizing power consumption on some devices may not be entirely possible as all the power rails may not be exposed. More specifically, some System-on-Chips (SoCs) do not have all their power rails exposed. Thus, power consumption analysis using data acquisition instruments may not be possible.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a first example system.

FIG. 2 illustrates a second example system.

FIG. 3 illustrates a third example system.

FIG. 4 illustrates a fourth example system.

FIG. 5 illustrates a fifth example system.

FIG. 6 illustrates an example information element.

FIG. 7 illustrates a first example logic flow.

FIG. 8 illustrates a second example logic flow.

FIG. 9 illustrates an example of a storage medium.

FIG. 10 illustrates an example device.

DETAILED DESCRIPTION

The present disclosure provides to measure power consumption (e.g., current consumption, voltage consumption, or the like) of a System-on-Chip (SoC). In particular, the present disclosure provides to measure power consumption on a per power rail basis for SoCs, during both active and low power modes.

In some examples, the present disclosure provides a SoC including power consumption monitoring elements on the power rails and/or power regulators. In some examples, the monitoring elements can be implemented in a power management integrated circuit (PMIC) component of the SoC. The SoC additionally, includes a power consumption component including a memory buffer to store power consumption values measured at the monitoring elements. During operation, the PMIC can measure power consumption on each of the power rails. For example, the PMIC can measure power consumption via the monitoring elements. Additionally, the PMIC can add the values of power consumption of each of the power rails to the memory buffer.

Subsequently, a processing component of the SoC can access the power consumption values from the memory buffer to determine power consumption for the SoC. Of note, the PMIC can repeatedly add power consumption values to the memory buffer, even when the SoC is in a low power or inactive state. Furthermore, collection and caching of the current consumption values may not affect power consumption of the SoC. Said differently, as collection and monitoring of power consumption on the power rails does not involve the processing component portions of the SoC, consumption values may not be falsely inflated due to the power consumption collection efforts.

FIG. 1 illustrates an example power consumption measurement system 100. The system 100 includes an SoC 110, a power management integrated circuit (PMIC) 120 coupled to the SoC 110, and a rail data buffer 130. Additionally, the system 100 includes a rail data microcontroller 140. The rail data microcontroller 140 is coupled to the buffer 130 via a communication interface 152 while the SoC 110 is coupled to the buffer 130 via a

communication interface 154. In general, the system 100 is configured to measure power consumption of the SoC 110. More specifically, the system 100 is configured to measure power consumption (e.g., on a per power rail basis) of the SoC 110 during both active and low power modes.

The SoC 110 can be any of a variety of SoCs. For example, the SoC 110 can be an SoC for mobile computing applications, desktop computing applications, communications applications, or Internet-of-Things (IoT) applications. In particular, the SoC 110 can be any integrated circuit including multiple electronic components integrated into a single "chip" package. The SoC 110 may include one or more of a processing component (e.g., microcontroller, microprocessor, digital signal processor (DSP), processing core, multiple processing cores, or the like), a memory component (e.g., read only memory (ROM), random access memory (RAM), electronically erasable programmable read only memory (EEPROM), flash memory, or the like), a timing component (e.g., oscillators, phase-locked loops, or the like), a peripheral component (e.g., counter-timers, real-time timers, power-on res et generators, or the like), external interfaces (e.g.,. universal serial bus (USB), Fire Wire, Ethernet, Bluetooth, or the like), analog interfaces (e.g., analog to digital converter (ADC), digital to analog converter (DAC), or the like). As an example only, the SoC 110 is depicted including a first component 112 and a second component 114. It is worthy to note, that the number of components of the SoC 110 is depicted at a quantity to facilitate understanding and not to be limiting. For example, the SoC 110 can include one, two, three, four, or more components.

The PMIC 120 can include power components (e.g., voltage regulators, power supply, energy storage device, power management circuits, or the like). The PMIC 120 is coupled to the first component 112, the second component 114, the third component 116, and the fourth component 118 via power rails 122. The PMIC 120 also includes consumption monitors 124 coupled to the power rails 122. In some examples, the consumption monitors 124 can be current sense circuits (e.g., current sense amplifiers, current sense resistors, or the like) and/or voltage sense circuits (e.g., voltage splitters, or the like), or a combination of current and voltage sense circuits.

During operation, the rail data microcontroller 140 can receive power consumption values 132 (e.g., current measurement values and/or voltage measurement values) from the

consumption monitors 124. In particular, the rail data microcontroller 140 can receive power consumption values 132 and store the power consumption values 132 to the rail data buffer 130 via the interface 152. Accordingly, the rail data microcontroller 140 receives current and/or voltage measurement values fro the consumption monitors 124 and writes these values to the rail data buffer 130. In some examples, the rail data buffer 130 is a register or set of registers, in some examples, the rail data buffer 130 is static-random access memory (SRAM) or an always on dynamic random access memory (DRAM). In some examples, the interface 152 can be a high speed interface (e.g., capable of sustained transfer rates of between 50 and 900 kilobits per second.

The microcontroller 140 may repeatedly (e.g., periodically, at set intervals, upon trigger by an interrupt, or the like) sample the power consumption of the power rails 122 from consumption monitors 124 and write the consumption values 132 to the buffer 130. In particular, the microcontroller 140 can sample the power consumption values 132 during periods when the SoC 110 is inactive (e.g., when the first component and/or the second component 114 are asleep, in a low power state, or the like). Furthermore, as the sampling of the power consumption values 132 does not take processing resources (e.g., compute cycles, or the like) from the SoC 110 (and particularly a main processing component (not shown) of the SoC 110), the power consumption values 132 may not be inflated due to the power consumption measurement itself. For example, the values 132 can be sampled without waking processing resources (e.g., the first component 112 and/or the second component 114). Subsequently, the values 132 can be retrieved and/or accessed by an application executing on the SoC 110. In particular, the values 132 can be retrieved via the interface 154. In some examples, the interface 154 can be a memory bus for the SoC 110.

FIG. 2 illustrates an example power consumption measurement system 200. It is noted, the system 200 includes the same elements as the system 100 described with respect to FIG. 1, although in a different configuration. In particular, the system 200 includes SoC 110, PMIC 120 coupled to the SoC 110, and rail data buffer 130. However, the rail data microcontroller 140 is depicted implemented within the SoC 110 as opposed to within the PMIC 120. In particular, the rail data microcontroller 140 can be an always-on-microcontroller of the SoC 110 coupled to the PMIC 120 and the buffer 130 via interface 152.

During operation, the rail data microcontroller 140 can receive power consumption values 132 (e.g., current measurement values and/or voltage measurement values) from the consumption monitors 124. In particular, the rail data microcontroller 140 can receive power consumption values 132 and store the power consumption values 132 to the rail data buffer 130 via the interface 152. The microcontroller 140 may repeatedly (e.g., periodically, at set intervals, upon trigger by an interrupt, or the like) sample the power consumption of the power rails 122 from consumption monitors 124 and write the consumption values 132 to the buffer 130. In particular, the microcontroller 140 can sample the power consumption values 132 during periods when the SoC 110 is inactive (e.g., when the first component and/or the second component 114 are asleep, in a low power state, or the like). Furthermore, as the sampling of the power consumption values 132 does not take processing resources (e.g., compute cycles, or the like) from main processing components the SoC 110, the power consumption values 132 may not be inflated due to the power consumption measurement itself. For example, the values 132 can be sampled without waking processing resources (e.g., the first component 112 and/or the second component 114).

FIG. 3 illustrates an example power consumption measurement system 300. It is noted, the system 300 includes the same elements as the system 100 described with respect to FIG. 1, although in a different configuration. In particular, the system 300 includes SoC 110 and PMIC 120. However, the PMIC 120 is implemented within the SoC 110. The system 300 further includes rail data buffer 130.

During operation, the rail data microcontroller 140 can receive power consumption values 132 (e.g., current measurement values and/or voltage measurement values) from the consumption monitors 124. In particular, the rail data microcontroller 140 can receive power consumption values 132 and store the power consumption values 132 to the rail data buffer 130 via the interface 152. The microcontroller 140 may repeatedly (e.g., periodically, at set intervals, upon trigger by an interrupt, or the like) sample the power consumption of the power rails 122 from consumption monitors 124 and write the consumption values 132 to the buffer 130. In particular, the microcontroller 140 can sample the power consumption values 132 during periods when the SoC 110 is inactive (e.g., when the first component and/or the second component 114 are asleep, in a low power state, or the like). Furthermore, as the sampling of the power consumption values 132 does not take processing resources (e.g., compute cycles, or the like) from the main processing components of the SoC 110, the power consumption values 132 may not be inflated due to the power consumption measurement itself. For example, the values 132 can be sampled without waking processing resources (e.g., the first component 112 and/or the second component 114).

FIG. 4 illustrates an example power consumption measurement system 400. It is noted, the system 400 includes the same elements as the system 100 described with respect to FIG. 1, although in a different configuration. In particular, the system 400 includes SoC 110 and PMIC 120. However, the PMIC 120 is implemented within the SoC 110. Furthermore, the SoC 110 includes a third component 116, which can be a memory storage component. For example, the component 116 can be a DRAM, SRAM, or other memory storage element. The rail data buffer 130 can be implemented within a portion (e.g., partition, or the like) of the storage component 116.

During operation, the rail data microcontroller 140 can receive power consumption values 132 (e.g., current measurement values and/or voltage measurement values) from the consumption monitors 124. In particular, the rail data microcontroller 140 can receive power consumption values 132 and store the power consumption values 132 to the rail data buffer 130 via the interface 152. The microcontroller 140 may repeatedly (e.g., periodically, at set intervals, upon trigger by an interrupt, or the like) sample the power consumption of the power rails 122 from consumption monitors 124 and write the consumption values 132 to the buffer 130. In particular, the microcontroller 140 can sample the power consumption values 132 during periods when the SoC 110 is inactive (e.g., when the first component and/or the second component 114 are asleep, in a low power state, or the like). Furthermore, as the sampling of the power consumption values 132 does not take processing resources (e.g., compute cycles, or the like) from the main processing resources of the SoC 110, the power consumption values 132 may not be inflated due to the power consumption measurement itself. For example, the values 132 can be sampled without waking processing resources (e.g., the first component 112 and/or the second component 114).

It is worthy to note, that the size of the buffer 130 may depend upon the SoC 110, the number of power rails 122, and the amount of data desired to be stored within the buffer 130. However, for a practical application, the buffer 130 may be less than 24 megabytes. In particular, a buffer 130 of approximately 24 megabytes may store indications of power consumption measurements for up to 25 power rails 122 from a 1 KHz sampling frequency over a 15 -minute period. Examples are not limited in this context.

FIG. 5 illustrates an example power consumption measurement system 500. It is noted, the system 500 includes the same elements as the system 100 described with respect to FIG. 1, although in a different configuration. In particular, the system 500 includes SoC 110, rail data buffer 130, and rail data microcontroller 140. It is noted, the rail data microcontroller 140 is depicted implemented outside the SoC 110 as opposed to within the PMIC 120 (e.g., FIG. 1) or within the SoC (e.g., FIGS. 2-4). In particular, the rail data microcontroller 140 can be a microcontroller coupled to the consumption monitors 124 and the buffer 130.

During operation, the rail data microcontroller 140 can receive power consumption values 132 (e.g., current measurement values and/or voltage measurement values) from the consumption monitors 124. In particular, the rail data microcontroller 140 can receive power consumption values 132 and store the power consumption values 132 to the rail data buffer 130 via the interface 152. The microcontroller 140 may repeatedly (e.g., periodically, at set intervals, upon trigger by an interrupt, or the like) sample the power consumption of the power rails 122 from consumption monitors 124 and write the consumption values 132 to the buffer 130. In particular, the microcontroller 140 can sample the power consumption values 132 during periods when the SoC 110 is inactive (e.g., when the first component and/or the second component 114 are asleep, in a low power state, or the like). Furthermore, as the sampling of the power consumption values 132 does not take processing resources (e.g., compute cycles, or the like) from main processing components the SoC 110, the power consumption values 132 may not be inflated due to the power consumption measurement itself. For example, the values 132 can be sampled without waking processing resources (e.g., the first component 112 and/or the second component 114). FIG. 6 illustrates an example of a rail data frame 600 including indications of power consumption measurement (e.g., current, or the like) values 132 for the power rails 122. It is noted, the frame 600 includes a header field 610 and a payload field 620. The header field 610 includes an indication of the number of power rails 122 for which measurement values are sampled or indicated in the consumption values 132. Additionally, the header field 610 can include an indication of the number of power consumption measurement samples (e.g., for each power rail 122, or the like) are indicated in the payload field 620. In some examples, the header field 610 can include an indication (e.g., in the first byte, the first two bytes, the first four bytes, or the like) of the number of power rails to which samples correspond and an indication (e.g., in the next byte, the next two bytes, the next four bytes, or the like) of the number of samples indicated in the payload field 620.

In general, the payload field 620 includes indications of the power consumption values measured by the consumption elements 124. In some examples, the payload field 620 can include indications of the values for each sample consecutively while in some examples, the payload field 620 can include indications of the values for each rail consecutively. For example, for purposes of clarity of presentation only, a payload field 620 could include indications of a first sample of power consumption values for a number of power rails 122, followed by indications of a second sample of power consumption values for the number of power rails 122, followed by indications of a third sample of power consumption values for the number of power rails, etc. As another example, a payload field 620 could include indications of a first, second, third, etc. sample of power consumption values for a first one of the power rails 122, followed by indications of the first, second third, etc. sample of power consumption values for a second one of the power rails 122, followed by indications of the first, second third, etc. sample of power consumption values for a third one of the power rails 122, etc. Examples are not limited in this context.

In some examples, the layout of the rail data frame can follow that depicted in FIG. 6. In particular, the header field 610 can include an indication of the number of power rails (r) in the first four bytes of the frame 600 (e.g., byte offset X) and an indication of the number of samples (n) in the second four bytes of the frame (e.g., byte offset X + 4). The payload field can include an indication of the power consumption values for each rail and sample as follows: Sample 1: value for rail 1 - byte offset X + 8 ... value for rail r - byte offset X + 8 + (r-1)) and Sample n: value for rail 1 - byte offset X + 8 + r * (n-1) ... value for rail r - byte offset X + 8 +( r*n-l)).

FIGS. 7-8 illustrate block diagrams of example logic flows 700 and 800, respectively. The logic flows 700 and 800 can be implemented by the rail data microcontroller 140 to generate the power consumption values 132. Said differently, the rail data microcontroller 140 can implement the logic flows 700 and 800 to generate a rail data frame 600 including indications of power consumption values and add the frame to the buffer 130.

Turning more specifically to FIG. 7 and the logic flow 700. The logic flow 700 can begin at block 710. At block 710 "determine a current on at least one among a number of power rails of a System-on-Chip (SoC) over a period," the rail data microcontroller 140 can determine an amount of current on the power rails 122. For example, the rail data microcontroller 140 can determine an amount of current on the power rails 122 based on the power consumption monitors 124.

Continuing to block 720 "add an information element to a memory buffer, the information element to include an indication of the current," the rail data microcontroller 140 can add an information element (e.g., the rail data frame 600, or the like) including indication of the power consumption values 132 to the rail data buffer 130.

Turning more specifically to FIG. 8 and the logic flow 800. The logic flow 800 can begin at block 810. As block 810 "determine a current on a number of power rails of a System-on-Chip (SoC) over a period," the rail data microcontroller 140 can determine an amount of current on the power rails 122. For example, the rail data microcontroller 140 can determine an amount of current on the power rails 122 based on the power consumption monitors 124.

Continuing to block 820 "add an information element to a memory buffer, the information element to include an indication of the current," the rail data microcontroller 140 can add an information element (e.g., the rail data frame 600, or the like) including indication of the power consumption values 132 to the rail data buffer 130.

Continuing to decision block 830 "SoC asleep?" the rail data microcontroller 140 can determine whether the SoC 110 is asleep. From the decision block 830, the logic flow 800 can continue to block 840 or return to block 810. In particular, the logic flow 800 can continue to block 840 based on a determination that the SoC 110 is asleep (e.g., in a low power state, or the like). Alternatively, the logic flow 800 can return to block 810 based on a determination that the SoC 110 is not asleep.

At block 840 "determine a current on the number of power rails for a set sampling period," the rail data microcontroller 140 can determine an amount of current on the power rails 122 over a sampling period. For example, the rail data microcontroller 140 can determine an amount of current on the power rails 122 based on the power consumption monitors 124. In particular, the rail data microcontroller 140 can determine the current on the power rails 122 at a number of intervals over a sampling period. In some examples, the sampling period can be based on the size of the rail data buffer 130.

Continuing to block 850 "add an indication of the current during the sampling period to the information element," the rail data microcontroller 140 can add an indication of the current during the sampling period to the information element (e.g., the rail data frame 600, or the like) including indication of the power consumption values 132 to the rail data buffer 130.

FIG. 9 illustrates an example storage medium 900. As shown in FIG. 9, the storage medium includes a storage medium 800. The storage medium 900 may comprise an article of manufacture. In some examples, storage medium 900 may include any non-transitory computer readable medium or machine readable medium, such as an optical, magnetic or semiconductor storage. Storage medium 900 may store various types of computer executable instructions, such as instructions to implement logic flow 700 and/or logic flow 800. Examples of a computer readable or machine readable storage medium may include any tangible media capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. Examples of computer executable instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, object-oriented code, visual code, and the like. The examples are not limited in this context.

FIG. 10 illustrates an example device 1000. In some examples, as shown in FIG. 10, computing platform 1000 may include a processing component 1010, other components 1080, or a communications interface 1090.

According to some examples, processing component 1010 may execute processing operations or logic for system 100, system 200, system 300, system 400, 500 and/or storage medium 800. Processing component 1010 may include various hardware elements, software elements, or a combination of both. Examples of hardware elements may include devices, logic devices, components, processors, microprocessors, circuits, processor circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, application specific integrated circuits (ASIC), programmable logic devices (PLD), digital signal processors (DSP), field programmable gate array (FPGA), memory units, logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. Examples of software elements may include software components, programs, applications, computer programs, application programs, device drivers, system programs, software development programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces (API), instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an example is implemented using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints, as desired for a given example.

In some examples, other components 1080 may include common computing elements or circuitry, such as one or more processors, multi-core processors, co-processors, memory units, interfaces, oscillators, timing devices, and so forth. Examples of memory units may include without limitation various types of computer readable and machine readable storage media in the form of one or more higher speed memory units, such as read-only memory (ROM), random- access memory (RAM), dynamic RAM (DRAM), Double-Data-Rate DRAM (DDR AM), synchronous DRAM (SDRAM), static RAM (SRAM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory or any other type of storage media suitable for storing information.

In some examples, communications interface 1090 may include logic and/or features to support a communication interface. For these examples, communications interface 1090 may include one or more communication interfaces that operate according to various communication protocols or standards to communicate over communication links or channels. Communications may occur via use of communication protocols or standards described in one or more industry standards (including progenies and variants) such as those associated with the PCI Express, SATA, SAS (Serial Attached SCSI) standard or specifications.

The components and features of device 1000 may be implemented using any combination of discrete circuitry, application specific integrated circuits (ASICs), logic gates and/or single chip architectures. Further, the features may be implemented using microcontrollers, programmable logic arrays and/or microprocessors or any combination of the foregoing where suitably appropriate. It is noted that hardware, firmware and/or software elements may be collectively or individually referred to herein as "logic" or "circuit."

It should be appreciated that the example device 1000 shown in the block diagram of this figure may represent one functionally descriptive example of many potential implementations. Accordingly, division, omission or inclusion of block functions depicted in the accompanying figures does not infer that the hardware components, circuits, software and/or elements for implementing these functions would necessarily be divided, omitted, or included in

embodiments. One or more aspects of at least one example may be implemented by representative instructions stored on at least one machine-readable medium which represents various logic within the processor, which when read by a machine, computing device or system causes the machine, computing device or system to fabricate logic to perform the techniques described herein. Such representations may be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor.

Various examples may be implemented using hardware elements, software elements, or a combination of both. In some examples, hardware elements may include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, ASICs, PLDs, DSPs, FPGAs, memory units, logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. In some examples, software elements may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an example is implemented using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints, as desired for a given implementation.

Some examples may include an article of manufacture or at least one computer-readable medium. A computer-readable medium may include a non-transitory storage medium to store logic. In some examples, the non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile memory or non- volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. In some examples, the logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, API, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. According to some examples, a computer-readable medium may include a non-transitory storage medium to store or maintain instructions that when executed by a machine, computing device or system, cause the machine, computing device or system to perform methods and/or operations in accordance with the described examples. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. The instructions may be implemented according to a predefined computer language, manner or syntax, for instructing a machine, computing device or system to perform a certain function. The instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language.

Some examples may be described using the expression "in one example" or "an example" along with their derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one example. The appearances of the phrase "in one example" in various places in the specification are not necessarily all referring to the same example.

Some examples may be described using the expression "coupled" and "connected" along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, descriptions using the terms "connected" and/or "coupled" may indicate that two or more elements are in direct physical or electrical contact with each other. The term "coupled," however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

It is emphasized that the Abstract of the Disclosure is provided to comply with 37 C.F.R. Section 1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single example for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed examples require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed example. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate example. In the appended claims, the terms "including" and "in which" are used as the plain-English equivalents of the respective terms "comprising" and "wherein," respectively. Moreover, the terms "first," "second," "third," and so forth, are used merely as labels, and are not intended to impose numerical requirements on their objects.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims. The following examples of the present disclosure are provided.

Example 1. A System-on-Chip (SoC) comprising: a plurality of System-on-Chip (SoC) components; a plurality of power rails to operably couple the plurality of SoC components to a power source; a plurality of power consumption monitors, each of the plurality of power consumption monitors operably coupled to a one of the plurality of power rails to determine an amount of power consumed via the one of the plurality of power rails; a memory buffer; and a rail data microcontroller operably coupled to the plurality of power consumption monitors and the memory buffer, the rail data microcontroller to add a rail data information element to the memory buffer, the rail data information element to include an indication of the amount of power consumed via the plurality of power rails.

Example 2. The SoC of example 1, comprising a power management integrated circuit (PMIC), the PMIC operably coupled to the SoC to manage a flow of current on the plurality of power rails.

Example 3. The SoC of example 2, wherein the rail data microcontroller is implemented as a microcontroller in the PMIC.

Example 4. The SoC of example 2, wherein the rail data microcontroller is implemented as a microcontroller in the SoC.

Example 5. The SoC of example 1, comprising a memory storage component, the memory buffer a partition of the memory storage component.

Example 6. The SoC of example 5, wherein the memory storage component is a dynamic random access memory (DRAM) component or a static-random access memory (SRAM) component.

Example 7. The SoC of example 1, comprising an interface to operably couple the rail data microcontroller to the memory buffer, the rail data microcontroller to add the rail data information element to the memory buffer via the interface.

Example 8. The SoC of example 1, the rail data microcontroller to determine an amount of power consumed via the plurality of power rails at a plurality of intervals, the rail data information element to include indications of the amount of power consumed via the plurality of power rails at each of the plurality of intervals.

Example 9. The SoC of example 8, the rail data information element to include a header field, the header field to include an indication of a quantity of the plurality of power rails and an indication of the quantity of the plurality of intervals.

Example 10. The SoC of example 9, the rail data information element to include a payload field, the payload field to include, for each of the plurality of intervals, an indication of the amount of power consumed via each of the plurality of power rails.

Example 11. The SoC of example 1, the plurality of SoC components comprising at least one of a processor, a graphics processing unit, a memory, a signal processor, a timer, a peripheral, an external interface, or an analog component.

Example 12. The SoC of example 1, wherein the plurality of power consumption monitors comprise at least one of a current sense amplifier, a current sense resistor, or a voltage splitter.

Example 13. An apparatus comprising: a System-on-Chip (SoC) comprising: a plurality of System-on-Chip (SoC) components; a plurality of power rails to operably couple the plurality of SoC components to a power source; and a plurality of power consumption monitors, each of the plurality of power consumption monitors operably coupled to a one of the plurality of power rails to determine an amount of power consumed via the one of the plurality of power rails; a memory buffer; and a rail data microcontroller operably coupled to the plurality of power consumption monitors and the memory buffer, the rail data microcontroller to add a rail data information element to the memory buffer, the rail data information element to include an indication of the amount of power consumed via the plurality of power rails.

Example 14. The apparatus of example 13, comprising a power management integrated circuit (PMIC), the PMIC operably coupled to the SoC to manage a flow of current on the plurality of power rails.

Example 15. The apparatus of example 14, wherein the rail data microcontroller is implemented as a microcontroller in the PMIC.

Example 16. The apparatus of any one of examples 13 to 14, wherein the rail data microcontroller is implemented as a microcontroller in the SoC.

Example 17. The apparatus of any one of examples 13 to 14, comprising a memory storage component, the memory buffer a partition of the memory storage component.

Example 18. The apparatus of example 17, wherein the memory storage component is a dynamic random access memory (DRAM) component or a static -random access memory (SRAM) component. Example 19. The apparatus of example 17, comprising a first interface to operably couple the rail data microcontroller to the memory storage component, the rail data microcontroller to add the rail data information element to the memory buffer via the interface.

Example 20. The apparatus of example 19, comprising a second interface to operably couple the SoC to the memory storage component.

Example 21. The apparatus of any one of examples 13 to 14, the rail data microcontroller to determine an amount of power consumed via the plurality of power rails at a plurality of intervals, the rail data information element to include indications of the amount of power consumed via the plurality of power rails at each of the plurality of intervals.

Example 22. The apparatus of example 21, the rail data information element to include a header field, the header field to include an indication of a quantity of the plurality of power rails and an indication of the quantity of the plurality of intervals.

Example 23. The apparatus of example 22, the rail data information element to include a payload field, the payload field to include, for each of the plurality of intervals, an indication of the amount of power consumed via each of the plurality of power rails.

Example 24. The apparatus of any one of examples 13 to 13, the plurality of SoC components comprising at least one of a processor, a graphics processing unit, a memory, a signal processor, a timer, a peripheral, an external interface, or an analog component.

Example 25. The apparatus of any one of examples 13 to 14, wherein the plurality of power consumption monitors comprise at least one of a current sense amplifier, a current sense resistor, or a voltage splitter.

Example 26. The apparatus of example 14, comprising a power source operably coupled to the PMIC, the power source to provide current to the plurality of power rails.

Example 27. The apparatus of example 26, wherein the power source is a battery, a super capacitor, or a fuel cell.

Example 28. The apparatus of example 27, wherein the apparatus is implemented in a mobile device.

Example 29. A method comprising: determining, at a first instance, a current on at least one of a plurality of power rails of a System-on-Chip (SoC); and adding an information element to a memory buffer, the memory buffer to include an indication of the current on the at least one of the plurality of power rails at the first instance.

Example 30. The method of example 29, comprising: determining, at a second instance, a current on the at least one of the plurality of power rails of the SoC; and adding an indication of the current on the at least one of the plurality of power rails at the second instance to the information element.

Example 31. The method of example 30, wherein the SoC is in a low power state during at least one of the first instance or the second instance.

Example 32. The method of example 31, wherein the memory buffer is a partition within a memory storage component.

Example 33. An apparatus comprising a SoC means, a memory buffer means, and a microcontroller means to perform the method of any one of examples 30 to 32.

Example 34. At least one machine-readable storage medium comprising instructions that when executed by a microcontroller, cause the microcontroller to: determine, at a first instance, a current on at least one of a plurality of power rails of a System-on-Chip (SoC); and add an information element to a memory buffer, the memory buffer to include an indication of the current on the at least one of the plurality of power rails at the first instance.

Example 35. The at least one machine-readable storage medium of example 34, comprising instructions that when executed by the microcontroller, cause the microcontroller to: determine, at a second instance, a current on the at least one of the plurality of power rails of the SoC; and add an indication of the current on the at least one of the plurality of power rails at the second instance to the information element.

Example 36. The at least one machine -readable storage medium of example 35, wherein the SoC is in a low power state during at least one of the first instance or the second instance.

Example 37. The at least one machine -readable storage medium of example 36, wherein the memory buffer is a partition within a memory storage component.

Claims

CLAIMS: What is claimed is:

1. A System-on-Chip (SoC) comprising:

a plurality of System-on-Chip (SoC) components;

a plurality of power rails to operably couple the plurality of SoC components to a power source;

a plurality of power consumption monitors, each of the plurality of power consumption monitors operably coupled to a one of the plurality of power rails to determine an amount of power consumed via the one of the plurality of power rails;

a memory buffer; and

a rail data microcontroller operably coupled to the plurality of power consumption monitors and the memory buffer, the rail data microcontroller to add a rail data information element to the memory buffer, the rail data information element to include an indication of the amount of power consumed via the plurality of power rails.

2. The SoC of claim 1, comprising a power management integrated circuit (PMIC), the PMIC operably coupled to the SoC to manage a flow of current on the plurality of power rails.

3. The SoC of claim 1, comprising an interface to operably couple the rail data microcontroller to the memory buffer, the rail data microcontroller to add the rail data information element to the memory buffer via the interface.

4. The SoC of claim 1 , the rail data microcontroller to determine an amount of power consumed via the plurality of power rails at a plurality of intervals, the rail data information element to include indications of the amount of power consumed via the plurality of power rails at each of the plurality of intervals.

5. The SoC of claim 4, the rail data information element to include a header field, the header field to include an indication of a quantity of the plurality of power rails and an indication of the quantity of the plurality of intervals.

6. The SoC of claim 5, the rail data information element to include a payload field, the payload field to include, for each of the plurality of intervals, an indication of the amount of power consumed via each of the plurality of power rails.

7. The SoC of claim 1, the plurality of SoC components comprising at least one of a processor, a graphics processing unit, a memory, a signal processor, a timer, a peripheral, an external interface, or an analog component.

8. The SoC of claim 1, wherein the plurality of power consumption monitors comprise at least one of a current sense amplifier, a current sense resistor, or a voltage splitter.

9. An apparatus comprising:

a System-on-Chip (SoC) comprising:

a plurality of System-on-Chip (SoC) components;

a plurality of power rails to operably couple the plurality of SoC components to a power source; and

a plurality of power consumption monitors, each of the plurality of power consumption monitors operably coupled to a one of the plurality of power rails to determine an amount of power consumed via the one of the plurality of power rails; a memory buffer; and

10. The apparatus of claim 9, comprising a power management integrated circuit (PMIC), the PMIC operably coupled to the SoC to manage a flow of current on the plurality of power rails.

11. The apparatus of claim 10, wherein the rail data microcontroller is implemented as a microcontroller in the PMIC.

12. The apparatus of claim 10, wherein the rail data microcontroller is implemented as a microcontroller in the SoC.

13. The apparatus of claim 10, comprising a memory storage component, the memory buffer a partition of the memory storage component.

14. The apparatus of claim 13, wherein the memory storage component is a dynamic random access memory (DRAM) component or a static -random access memory (SRAM) component.

15. The apparatus of claim 13, comprising a first interface to operably couple the rail data microcontroller to the memory storage component, the rail data microcontroller to add the rail data information element to the memory buffer via the interface.

16. The apparatus of claim 15, comprising a second interface to operably couple the SoC to the memory storage component.

17. The apparatus of claim 10, the rail data microcontroller to determine an amount of power consumed via the plurality of power rails at a plurality of intervals, the rail data information element to include indications of the amount of power consumed via the plurality of power rails at each of the plurality of intervals.

18. The apparatus of claim 17, the rail data information element to include a header field, the header field to include an indication of a quantity of the plurality of power rails and an indication of the quantity of the plurality of intervals.

19. The apparatus of claim 18, the rail data information element to include a payload field, the payload field to include, for each of the plurality of intervals, an indication of the amount of power consumed via each of the plurality of power rails.

20. The apparatus of claim 14, the plurality of SoC components comprising at least one of a processor, a graphics processing unit, a memory, a signal processor, a timer, a peripheral, an external interface, or an analog component.

21. The apparatus of claim 14, wherein the plurality of power consumption monitors comprise at least one of a current sense amplifier, a current sense resistor, or a voltage splitter.

22. The apparatus of claim 14, comprising a power source operably coupled to the PMIC, the power source to provide current to the plurality of power rails.

23. The apparatus of claim 26, wherein the power source is a battery, a super capacitor, or a fuel cell.

24. The apparatus of claim 23, wherein the apparatus is implemented in a mobile device.

25. A method comprising:

determining, at a first instance, a current on at least one of a plurality of power rails of a System-on-Chip (SoC); and

adding an information element to a memory buffer, the memory buffer to include an indication of the current on the at least one of the plurality of power rails at the first instance.

26. The method of claim 25, comprising:

determining, at a second instance, a current on the at least one of the plurality of power rails of the SoC; and

adding an indication of the current on the at least one of the plurality of power rails at the second instance to the information element.

27. The method of claim 26, wherein the SoC is in a low power state during at least one of the first instance or the second instance.