US20140223214A1 - Dynamic power mode switching per rail - Google Patents

Dynamic power mode switching per rail Download PDF

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Publication number
US20140223214A1
US20140223214A1 US13/950,776 US201313950776A US2014223214A1 US 20140223214 A1 US20140223214 A1 US 20140223214A1 US 201313950776 A US201313950776 A US 201313950776A US 2014223214 A1 US2014223214 A1 US 2014223214A1
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power
amount
current
rails
threshold
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US13/950,776
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Walid Nabhane
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Avago Technologies General IP Singapore Pte Ltd
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Broadcom Corp
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Priority to US201361836327P priority
Priority to US201361836306P priority
Priority to US201361836895P priority
Priority to US201361836903P priority
Priority to US201361836886P priority
Priority to US13/950,776 priority patent/US20140223214A1/en
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Publication of US20140223214A1 publication Critical patent/US20140223214A1/en
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of power-saving mode
    • G06F1/3206Monitoring of events, devices or parameters that trigger a change in power modality
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/3287Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/3058Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
    • G06F11/3062Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations where the monitored property is the power consumption
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/3089Monitoring arrangements determined by the means or processing involved in sensing the monitored data, e.g. interfaces, connectors, sensors, probes, agents
    • G06F11/3093Configuration details thereof, e.g. installation, enabling, spatial arrangement of the probes
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/12Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106Data output latches
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/003Measuring mean values of current or voltage during a given time interval
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/40Testing power supplies
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/3003Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3031Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a motherboard or an expansion card
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/3058Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
    • Y02D10/171

Abstract

Aspects of dynamic power mode switching per rail based on power profiling are described. In one embodiment, an amount of current supplied by at least one of a plurality of power rails is sensed with a current sense circuit. The amount of current is profiled over a period of time and a profile of power consumed is generated and maintained. With reference to the power profile, one or more power-related decisions may be made in a system. One or more power rails may be powered off or placed into low power mode based on various factors, such as the amount of current being consumed per rail, the temperature of certain system components, or an unexpected ongoing consumption of power in the system.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application claims the benefit of:
  • U.S. Provisional Application No. 61/759,470, filed Feb. 1, 2013;
  • U.S. Provisional Application No. 61/833,598, filed Jun. 11, 2013;
  • U.S. Provisional Application No. 61/834,513, filed Jun. 13, 2013;
  • U.S. Provisional Application No. 61/836,327, filed Jun. 18, 2013;
  • U.S. Provisional Application No. 61/836,306, filed Jun. 18, 2013;
  • U.S. Provisional Application No. 61/836,895, filed Jun. 19, 2013;
  • U.S. Provisional Application No. 61/836,886, filed Jun. 19, 2013; and
  • U.S. Provisional Application No. 61/836,903, filed Jun. 19, 2013, the entire contents of each of which are hereby incorporated herein by reference.
  • This application also makes reference to:
  • U.S. patent application Ser. No. ______ (Attorney Docket #50229-4880), titled “Clock Domain Crossing Serial Interface, Direct Latching, and Response Codes” and filed on even date herewith;
  • U.S. patent application Ser. No. ______ (Attorney Docket #50229-4890), titled “Power and System Management Information Visibility” and filed on even date herewith;
  • U.S. patent application Ser. No. ______ (Attorney Docket #50229-4900), titled “Power Mode Register Reduction and Power Rail Bring Up Enhancement” and filed on even date herewith;
  • U.S. patent application Ser. No. ______ (Attorney Docket #50229-4910), titled “Dynamic Power Profiling” and filed on even date herewith;
  • U.S. patent application Ser. No. ______ (Attorney Docket #50229-4920), titled “Charger Detection and Optimization Prior to Host Control” and filed on even date herewith; and
  • U.S. patent application Ser. No. ______ (Attorney Docket #50229-4940), titled “Enhanced Recovery Mechanism” and filed on even date herewith.
  • BACKGROUND
  • Battery-powered computing systems and devices have been adopted for use in many aspects of daily life. As these systems and devices are more widely adopted and used in place of other computing systems and devices, they are designed to be more flexible and powerful, but are also more complex. With advances in the design of battery-powered computing devices, the availability of sufficient power for the devices continues to be an ongoing concern. For example, each new feature in a battery-powered computing device may require the provision of circuitry that supports a supply of power for the feature.
  • In the context of system power management, some battery-powered computing systems include power management processing circuitry that manages the supply of power in the system. Over time, this power management processing circuitry may need to adapt to certain needs in battery-operated systems.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, with emphasis instead being placed upon clearly illustrating the principles of the disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.
  • FIG. 1 illustrates a system for dynamic power mode switching according to an example embodiment.
  • FIG. 2 illustrates a process flow diagram for a process of dynamic power mode switching performed by the system of FIG. 1 according to an example embodiment.
  • FIG. 3 further illustrates the process flow diagram for the process of dynamic power mode switching performed by the system of FIG. 1 according to an example embodiment.
  • FIG. 4 illustrates a power profile maintained by the system of FIG. 1 and the process of FIGS. 2 and 3 for dynamic power mode switching according to an example embodiment.
  • FIG. 5 illustrates a display of a power profile for dynamic power mode switching according to an example embodiment.
  • DETAILED DESCRIPTION
  • In the context of system power management, some battery-powered computing systems include power management processing circuitry that manages the supply of power in the system. Over time, this power management processing circuitry may need to adapt to certain needs in battery-operated systems, such as the need for measurement and profiling of power consumed by various subsystems per power rail.
  • Additionally, the need for power management processing circuitry to identify, profile, and evaluate the consumption of per-rail power is now more important, especially as the number of power rails continues to grow and integrated semiconductor circuitry continues to shrink in size. For example, without the ability to identify the consumption of per-rail power, it might not be possible to identify whether a certain subsystem is operating outside its nominal or expected operating parameters. Further, as semiconductor circuitry continues to shrink in size, current leakage, which is variable in part based on temperature, has become a greater problem.
  • Although an amount of current leakage may be expected and semiconductor circuitry may be characterized to determine an expected amount of current leakage, it has become more difficult in new systems to rely upon an assumed or expected amount of current leakage. Similarly, it has become more difficult in new systems to rely upon an assumed or expected amount of current consumption for subsystems. When accurate power usage measurements and statistics are unavailable, poor overall power management may result.
  • In this context, aspects of dynamic power mode switching per rail based on power profiling are described. In one embodiment, an amount of current supplied by at least one of a plurality of power rails is sensed with a current sense circuit. The amount of current is profiled over a period of time and a profile of power consumed is generated and maintained. With reference to the power profile, one or more power-related decisions may be made in a system. One or more power rails may be powered off or placed into low power mode based on various factors, such as the amount of current being consumed per rail, the temperature of certain system components, or an unexpected ongoing consumption of power in the system.
  • Turning now to the drawings, an introduction and general description of exemplary embodiments of a system is provided, followed by a description of the operation of the same.
  • I. System Introduction
  • FIG. 1 illustrates a system 10 for dynamic power mode switching according to an example embodiment. The system 10 may embody a computing device that includes a number of general and/or specific purpose circuits, processing circuits, processors, registers, memories, sensors, displays, etc. In one embodiment, the system 10 may embody a handheld or portable computing device which is powered from charge stored in a battery. In various embodiments, the system 10 may be embodied as part of a cellular telephone, tablet computing device, laptop computer, or other computing device. Alternatively, because the embodiments described herein are not limited to use in handheld or portable computing devices, the system 10 may be embodied as part of a desktop or set top computing device, for example. Although not illustrated in FIG. 1, it should be appreciated that the system 10 may include one or more displays, microphones, speakers, buttons, indicator lights, haptic feedback elements, memory card readers, etc.
  • Among other elements, the system 10 includes a power management unit (PMU) 100, a host system-on-chip (SOC) 130, a system battery 182, and a system memory 184. The system 10 also includes certain subsystems such as a bluetooth / wireless local area network (WLAN) subsystem 170, a global positioning system (GPS) subsystem 171, a camera subsystem 172, and a sensor subsystem 173. The subsystems 170-173 are representative subsystems which may be included as elements of the system 10, and other subsystems are within the scope and spirit of the embodiments described herein. It is noted that, just as the host SOC 130 requires power for operation, each of the subsystems 170-173, the system memory 184, and other elements and circuits of the system 10 depend on power for operation. As discussed below, this power may be supplied by and under the control of the PMU 100.
  • The system battery 182 may be embodied as any rechargeable battery suitable for the application, such as a lithium-ion, nickel-metal-hydride, or other battery variant, without limitation. The system memory 184 may be embodied as a volatile and/or non-volatile random access memory or combination thereof. The system memory 184 may store computer-readable instructions thereon that, when executed by one or more of the processors 140-142 of the host SOC 130, for example, direct the processors 140-142 to execute various aspects of the embodiments described herein.
  • In general, the PMU 100 controls and/or facilitates control of the distribution of power from the system battery 182 to the elements of the system 10, such as the host SOC 130, the subsystems 170-173, and the system memory 184, for example. As further described below, depending upon the operating state of the system 10 and/or other factors, the PMU 100 may control the distribution of power to one or more elements of the system 10, or the PMU 100 may receive instructions to control the distribution of power to one or more elements of the system 10.
  • Among other elements, the PMU 100 includes a PMU controller 101, a serial interface slave 102, a PMU register bank 103, a current (/) sense circuit 107, a number 0-N of analog-to-digital (ADC) circuits 110-112, and a number of power rail circuits 120-124. It is noted that FIG. 1 illustrates a representative example of elements of the PMU 100, and it should be appreciated that the PMU 100 may include other elements in various embodiments. For example, the PMU 100 may include several additional power rails in addition to those illustrated in FIG. 1, to provide power to each element in the system 10, as needed.
  • In general, each of the power rails 120-124 includes a low dropout regulator (LDO) or switching type of power rail. An LDO power rail includes a linear voltage regulator that operates suitably even with a relatively low differential input vs. output voltage. A switching power rail includes an active switching circuit that charges and/or discharges reactive circuit elements to boost voltage or current, for example. It should be appreciated that an LDO or switching power rail is selected for each of the power rails 120-124 depending upon certain factors such as output voltage, input/output differential voltage, sourced current, power dissipation, cost, etc.
  • Among other elements, the host SOC 130 includes general and/or application specific processors. In FIG. 1, the host SOC 130 includes a power manager 131, an application processor 140, a modem 141, and a graphics processor 142. In various embodiments, the host SOC 130 may omit one or more of the processors 140-142 or include processors in addition to the processors 140-142. The host SOC 130 also includes a subsystem interface 162 and memory interface 163. The subsystem interface 162 and the memory interface 163 electrically and communicatively couple the subsystems 170-173 and the system memory 184 to the host SOC 130 and, particularly, to one or more of the processors 140-142.
  • The application processor 140 may be embodied as a general purpose processor for executing various applications. For example, the application processor 140 may execute an underlying operating system along with applications such as e-mail, short message service (SMS), telephone, camera, web-browser, and other applications, without limitation. As compared to the PMU 100 and/or the power manager 131, the application processor 140 may consume relatively more power during operation. The modem 141 may include a cellular-based (or similar) communications processor for the communication of data wirelessly in connection with radio-frequency front end circuitry, and the graphics processor 142 may include a processor for driving a display of the system 10.
  • The power manager 131 includes a power or system power control processor 132, a memory 133, and a serial interface master 134. The power processor 132 may be embodied as a relatively small and low power processor or processing circuit for interfacing with the PMU 100 via a serial interface 128. In one embodiment, the serial interface master 134 of the power manager 131 controls the serial interface 128, although the PMU 100 may control the serial interface 128 in other embodiments. The memory 133 stores computer-readable instructions for execution by the power processor 132.
  • II. System Operation
  • With reference to the elements of the system 10 introduced above, aspects of the operation of the system 10 are described below.
  • A. PMU Operation
  • The PMU 100 may be designed, adapted, and configured to perform operations that support the host SOC 130, the subsystems 170-173, the system memory 184, and other elements of the system 10. As one operational aspect of the PMU 100, the PMU 100 supplies power from the system battery 182 to other elements of the system 10 via the power rails 120-124. Further, when the system 10 is coupled to charging power via the system bus 180, the PMU 100 may charge the system battery 182. In certain aspects, the PMU 100 may monitor the voltage VBat of the system battery 182 and store a value of the voltage in the PMU register bank 103.
  • In other operational aspects of the PMU 100, the PMU controller 101 coordinates and controls the operations of the PMU 100. The PMU controller 101 may be embodied as a general or specific purpose circuit, processing circuit, processor, state machine, etc. The PMU controller 101 interfaces with the serial interface slave 102 to communicate with the host SOC 130 over the serial interface 128, interfaces with the power rail circuits 120-124 to control and sense power that is supplied to the system 10, and interfaces with the PMU register bank 103 to store and access data associated with the status of the PMU 100 and the system 10.
  • The serial interface slave 102 comprises one end of the serial interface 128 that facilitates communication between the PMU 100 and the host SOC 130. Among various modes and states of operation of the system 10, the serial interface 128 is relied upon to communicate data between the PMU 100 and the host SOC 130.
  • The current sense circuit 107 may be relied upon by the PMU 100 to determine an amount of current or power being supplied by at least one of a plurality of power rails 120-124. In certain embodiments, current sense circuit 107 may determine an amount of current being supplied by each of the power rails 120-124. Data on the amount of current supplied by one or more of the power rails 120-124 is relied upon as power profile data by the system 10. This power profile data may be gathered by the current sense circuit 107, as further described below, at the direction of the PMU controller 101 (and/or the power manager 131) and stored in the PMU register bank 103. The power profile data may also be communicated by the PMU 100 to the power manager 131 and/or the application processor 140 of host SOC 130 for further evaluation and processing.
  • The ADCs 110-112 may be relied upon to determine the voltage VBat of the system battery 182, the temperature of components in the system 10, etc. Particularly, the ADCs 110-112 may convert analog values of the VBat voltage, and voltages representative of the temperature of components in the system 10, into digital values for processing and/or storage by the PMU 100. These digital values include examples of power and management system status data that may be relied upon by the power manager 131 when determining whether to power on or power off certain power rails, as described below.
  • In one aspect, the current sense circuit 107 relies upon representative-scale replica power rail circuits to sense an amount of current being supplied by each of the power rails 120-124. By configuring the current sense circuit 107, the amount of current may be sensed from time to time or over a period of time as directed by the PMU controller 101 and/or the power manager 131. In general, the power profile data may be representative of operational aspects of the system 10.
  • B. Host SOC Operation
  • The host SOC 130 may be generally embodied as a full system-on-chip semiconductor device. In this sense, the host SOC 130 integrates various general and/or application specific processors and processing circuits into a single integrated circuit package, reducing space. Overall, the power manager 131 of the host SOC 130 supports the host SOC 130 and the power requirements of the host SOC 130.
  • In the context of power usage by the host SOC 130, it is noted that each of the power manager 131, the application processor 140, the modem 141, and the graphics processor 142 may be powered by a respective power rail of the PMU 100 in the system 10. For example, in the embodiment illustrated in FIG. 1, the power manager 131 may be powered by the power rail 1 120, and the application processor 140 may be powered by the power rail 2 121. Other elements and/or subsystems in the system 10 and within the host SOC may also be powered, respectively, by one or more power rails of the PMU 100. Each of the power rails 120-124 (and others) may be electrically coupled from the PMU 100 to the host SOC 130 and to other subsystems in the system 10 by respective power traces in the system 10 and power pins or pads of the PMU 100 and the host SOC 130.
  • According to aspects of the embodiments described herein, power manager or power manager circuit 131 of the host SOC 130 may request and retrieve power profile data stored by the PMU 100. The power manager circuit 131 may further evaluate the power profile data stored in the PMU 100, while coordinating power consumption by the host SOC 130 and/or the subsystems 170-173 in connection with control of the power rails 120-124 of the PMU 100.
  • The power manger 131 may retrieve and evaluate the data on the amount of current or power sourced by each of the power rails 120-124 over time. Additionally, the power manger 131 may retrieve and evaluate voltages output by each of the power rails 120-124 over time. Using the current and voltage data, the power manger 131 may calculate the amount of power sourced by each of the power rails 120-124.
  • In this context, the power manager 131 may evaluate the amount of current, voltage, or power sourced by one or more of the power rails 120-124 over a period of time and maintain a power profile of power consumed by one or more system elements in the system. In connection with other system status data from the PMU 100, the power manger 131 may also identify one or more system elements as a source of heat in the system 10 based on the power profile. In response, the power manger 131 may change an output voltage of or power down a power rail associated with the system element which is the source of heat.
  • In another aspect, the power manager 131 may identify an unexpected ongoing processing status or state of a processor or other system element in the system 10 based on an amount of current identified in the power profile over a certain period of time. In certain cases, the identification of the unexpected ongoing processing status or state may be helpful to diagnose a system problem or troubleshoot hardware or software problems. Additionally, as further described below, the power manager 131 may also set the operating mode of one or more power rails over time based on whether an amount of current or power sourced by the one or more power rails is less than or approaches a threshold of current.
  • In connection with the evaluation and review of power profile data, the power manager 131 may operate with the PMU 100 to power up and power down power rails in the system 10 in one or more groups or individually, as needed, over time. It is noted that, in certain embodiments, the host SOC 130 (including the power manager 131) and the PMU 100 may be combined in an integrated circuit. In this case, the serial interface 128 may be omitted and/or the power manager 131 and the PMU controller 101 may be combined.
  • Turning to FIGS. 2 and 3, process flow diagrams illustrating example processes performed by the system 10 for dynamic power mode switching per rail are illustrated. While the process flow diagrams are generally described as being performed by the PMU 100 and/or the power management processor 131 in the system 10 of FIG. 1, it is noted that other systems may perform the illustrated processes. That is, in various embodiments, systems similar to the system 10 may perform the processes illustrated in FIGS. 2 and 3.
  • In certain aspects, the flowcharts of FIGS. 2 and 3 may be considered to depict example steps performed by the system 10 according to one or more embodiments. Although the process diagrams of FIGS. 2 and 3 illustrate an order, it should be understood that the order may differ from that which is depicted. For example, an order of two or more elements in the process may be scrambled relative to that shown, performed concurrently, or performed with partial concurrence. Further, in some embodiments, one or more of the elements may be skipped or omitted within the scope and spirit of the embodiments described herein.
  • FIG. 2 illustrates a process flow diagram for a process 200 of dynamic power mode switching performed by the system 10 of FIG. 1 according to an example embodiment. Starting at reference numeral 202, the process 200 includes sensing an amount of current or power supplied by at least one of a plurality of power rails. For example, the current sense circuit 107 in the PMU 100 (FIG. 1) may sense the amount of current supplied by one of more of the power rails 120-124 from time to time or periodically over time. In one embodiment, the current sense circuit 107 may sense the amount of current supplied by each of the power rails 120-124 from time to time or periodically over time. The sensed current values are converted to digital values and stored by the PMU 100 in the PMU register bank 103. Thus, the amount of current sourced by the power rails 120-124 (and any others) is available as power profile data, for retrieval, reference, and evaluation by the PMU controller 101 and/or the power manager 131.
  • Continuing to reference numeral 204, the process 200 includes profiling and/or evaluating the amount of power or current supplied by the power rails 120-124 over a period of time. It is noted that the period of time for the evaluation may vary among embodiments. For example, the period of time may range from substantially no time (e.g., instantaneous) to microseconds, milliseconds, seconds, minutes, hours, etc., without limitation. In certain aspects, the profiling may include retrieving power profile data stored in the PMU register bank 103 from time to time as it is updated by the PMU 100. The power profile data retrieved from the PMU register bank 103 may include an amount of current supplied over time by each of the power rails 120-124, a voltage output over time by each of the power rails 120-124, system temperature data taken over time, and other system parameters such as the voltage VBat of the system battery 182. The profiling at reference numeral 204 may also include aggregating and organizing the retrieved data. In one embodiment, the data may be aggregated and organized by the power processor and stored, at least in part, in the memory 133 of the power manager 131.
  • At reference numeral 206, the process 200 includes generating and/or maintaining a power profile of power consumed by one or more of a plurality of system elements in the system 10 based on the profiling performed at reference numeral 204. As further described below, the power profile may be maintained for one or more system elements in the system 10, in association with one or more corresponding ones of the power rails 120-124 that supply power to the system elements.
  • With reference to FIG. 4, further details on a maintaining a power profile are described. FIG. 4 illustrates a power profile 410 maintained by the system 10 of FIG. 1 according to an example embodiment. FIG. 4 generally illustrates current sourced or power consumed in the system 10 with reference to example power rails 1-8, individually, and is representative of power consumed by elements or subsystems of the system 10. Power consumed or current sourced by the power rails 120-124 in the system 10 may be represented among the data plotted for one or more of the power rails 1-8 in FIG. 4. The y-axis in FIG. 4 may be representative of current, volts, or power, for example, in mA, mV, or mW, for example, and the x-axis in FIG. 4 may be representative of time.
  • Referring back to FIG. 2, at reference numeral 208, the process 200 includes reviewing the power profile generated and/or maintained at reference numeral 206. In various aspects, the reviewing at reference numeral 208 includes comparing power sourced by one or more power rails to one or more thresholds, identifying correlations between power consumption and heat, and/or identifying unexpected ongoing processes, for example, among other processes. That is, at reference numeral 208, a further review and analysis of the power profile is performed. Further details regarding reviewing the power profile at reference numeral 208 are described below with reference to FIG. 3.
  • At reference numeral 210, the process 200 includes dynamically switching one or more power rails based on the review of the power profile at reference numeral 208. For example, the power manager 131 may set one or more of the power rails 120-124 into low power mode at reference numeral 210, as necessary. Additionally or alternatively, the power manger 131 may power off or power on one or more of the power rails 120-124, etc. In this context, it is noted that the operating parameters for any one of the power rails 120-124 (and any others) may be set, modified, and updated individually, based on the review performed at reference numeral 208. In other scenarios, operating settings for an entire group of the power rails 120-124 may be quickly modified to low power mode, normal mode, etc., by one command to the PMU 100. Thus, the dynamic switching at reference numeral 210 may be performed in a manner which is flexible, with reference to power data for each individual power rail in the system 10. It is noted that the process 200 may return to reference numeral 202 as an iterative process of dynamic power mode switching.
  • In other aspects, at reference numeral 212, the process 200 may include displaying a power profile as an amount of power consumed by one or more system elements of the system 10 over time. In this context, FIG. 5 illustrates display 500 that may be displayed as representative of amount of power consumed by one or more system elements of the system 10 over time. The display 500 may be rendered on a physical display of the system 10, at the request of a user. In FIG. 5, the x-axis may be representative of mA or mW hours or minutes, for example. FIG. 5 generally illustrates power consumed in the system 10 with reference to example power rails 1-8, individually. In practice, the each of the power rails on the display 500 may be identified by system element or subsystem. As opposed to other displays of power information that may be estimated by battery-powered systems, the display 500 may be generated by the system 10 based on actual data sensed by the current sense circuit 107 for current sourced by individual power rails. The display 500 may also be generated using a combination of current and voltage data for respective power rails over time. Thus, the display 500 may provide an accurate real-time display of power usage in battery-powered systems.
  • Turning to FIG. 3, further aspects of reviewing, as performed at reference numeral 208 of the process 200 of FIG. 2, are described. At reference numeral 302, reviewing at reference numeral 208 may include identifying a system element as a source of heat in the system 10. For example, referring to FIG. 4, the power manager 131 may correlate the relatively increased power consumption 402 for the power rail 5 as being associated with an increase in temperature 403 (dashed line) measured by the PMU 100, based on the overlapped or coincident timing of the increased temperature 403 with the increased power consumption 402. By system design, because the power manager 131 and/or the PMU 100 identifies the power rail 5 as being associated with a certain element or subsystem of the system 10, the power manager 131 and/or the PMU 100 may correlate the element or subsystem associated with the power rail 5 (e.g., the BT/WLAN subsystem 170, etc.) as being the cause of the increase in temperature. In this manner, the cause or root of increased temperatures in the system 10 may be more accurately identified. Further, if necessary, the power rail 5 may be powered off, set to an alternative voltage, etc., by the power manager 131 to prevent damage to the system 10, for example.
  • Referencing FIG. 3 again, at reference numeral 304, the reviewing at reference numeral 208 includes identifying an unexpected ongoing processing status or state of an element in the system 10 based on the amount of current. Referring again to FIG. 4, the increased and ongoing power consumptions 404 and 406 may be identified at reference numeral 208 by the power manager 131 as unexpected states of power consumption under certain circumstances. For troubleshooting software and/or hardware, for example, abnormal or unexpected power consumption, such as the power consumptions 404 and 406, may be identified and addressed by the power manager 131. The system or subsystem element associated with the power consumption 404 and the power rail 6, for example, may be reset or powered down, as necessary, to address the problem as illustrated in FIG. 4.
  • At reference numeral 306 of FIG. 3, the reviewing at reference numeral 208 includes comparing an amount of current or power to a threshold. In FIG. 4, for example, the amount of current sourced by the power rail 1 is compared to a current threshold. As one example, the current sourced by the power rail 1 may be compared to a 20 mA threshold by the power manager 131, although use of any current or power threshold values suitable for the application are within the scope and spirit of the embodiments described herein. In turn, when the amount of current sourced by the power rail 1 is less than the 20 mA threshold (e.g., at reference 408 in FIG. 4), the settings of the power rail 1 may be dynamically switched to place the power rail 1 into a low power mode of operation at reference numeral 210 of FIG. 2. Here, it is noted that switching the power rail 1 into the low power mode of operation may help conserve power for the system 10. Particularly, because the power rail 1 is sourcing such a low amount of current, at least part of the circuitry that supports the power rail 1 may be turned off until more current is demanded.
  • In other systems, certain power rails are placed into low power mode depending upon the state of the system, without actual knowledge of measured current consumption. According to aspects of the embodiments described herein, however, power rails may be set into low power mode whenever they are not needed for high current sourcing, based on the power profile 410 maintained by the power manager 131.
  • As another example of comparing current or power to a threshold at reference numeral 306, when the amount of current sourced by the power rail 1 approaches the 20 mA threshold (e.g., at reference 409 in FIG. 4), the settings of the power rail 1 may be dynamically switched at reference numeral 210 of FIG. 2, to place the power rail 1 bank into a normal mode of operation. Thus, the power rail 1 may be dynamically switched between low power and normal modes of operation based on actual power demands in the system 10. In certain aspects, the power rail 1 may be dynamically switched back to a normal power mode of operation by the power manager 131 at some time before the power rail 1 is expected to need to source more than 20 mA of current, for example, or as it “approaches” the 20 mA threshold.
  • Other manners and/or means of review of the power profile at reference numeral 208 are within the scope and spirit of the embodiments described herein. Generally, by relying upon the concepts for dynamic power mode switching per rail described above, power rails may be set to appropriate operating parameters based on actual real time power consumption rather than on semiconductor characterizations of expected consumption and processing state assumptions. Using accurate power measurements and statistics, the overall power management in battery-powered systems may be improved.
  • With regard to aspects of the structure or architecture of the system 10, in various embodiments, each of the PMU controller 101, the power processor 132, and or other processors or processing circuits of the system 10 may comprise general purpose arithmetic processors, state machines, or Application Specific Integrated Circuits (“ASICs”), for example. Each such processor or processing circuit may be configured to execute one or more computer-readable software instruction modules. In certain embodiments, each processor or processing circuit may comprise a state machine or ASIC, and the processes described in FIGS. 5 and 6 may be implemented or executed by the state machine or ASIC according to the computer-readable instructions.
  • The memories and/or registers described herein may comprise any suitable memory devices that store computer-readable instructions to be executed by processors or processing circuits. These memories and/or registers store computer-readable instructions thereon that, when executed by the processors or processing circuits, direct the processors or processing circuits to execute various aspects of the embodiments described herein.
  • As a non-limiting example group, the memories and/or registers may include one or more of an optical disc, a magnetic disc, a semiconductor memory (i.e., a semiconductor, floating gate, or similar flash based memory), a magnetic tape memory, a removable memory, combinations thereof, or any other known memory means for storing computer-readable instructions.
  • In certain aspects, the processors or processing circuits are configured to retrieve computer-readable instructions and/or data stored on the memories and/or registers for execution. The processors or processing circuits are further configured to execute the computer-readable instructions to implement various aspects and features of the embodiments described herein.
  • Although embodiments have been described herein in detail, the descriptions are by way of example. The features of the embodiments described herein are representative and, in alternative embodiments, certain features and elements may be added or omitted. Additionally, modifications to aspects of the embodiments described herein may be made by those skilled in the art without departing from the spirit and scope of the present invention defined in the following claims, the scope of which are to be accorded the broadest interpretation so as to encompass modifications and equivalent structures.

Claims (20)

1. A method, comprising:
sensing, with a current sense circuit in a system, an amount of current supplied by at least one of a plurality of power rails;
profiling the amount of current over a period of time; and
based on the profiling, maintaining a power profile of power consumed by at least one of a plurality of system elements in the system.
2. The method according to claim 1, further comprising:
based on the power profile, identifying a system element as a source of heat in the system; and
changing an output voltage of or powering down a power rail associated with the system element.
3. The method according to claim 1, further comprising identifying an unexpected ongoing processing status or state of an element in the system based on the amount of current.
4. The method according to claim 1, further comprising:
comparing the amount of current to a threshold; and
when the amount of current is less than the threshold, setting at least one of the plurality of power rails into a low power mode of operation.
5. The method according to claim 1, further comprising:
comparing the amount of current to a threshold; and
when the amount of current approaches the threshold, setting at least one of the plurality of power rails into a normal power mode of operation.
6. The method according to claim 1, wherein:
sensing the amount of current comprises sensing an amount of current supplied by each of the plurality of power rails; and
profiling the amount of current comprises profiling the amount of current supplied by each of the plurality of power rails over the period of time.
7. The method according to claim 6, further comprising, based on the profiling, maintaining a power profile for the plurality of system elements in the system
8. The method according to claim 6, further comprising displaying the power profile as an amount of power consumed by the plurality of system elements over time.
9. The method according to claim 1, wherein maintaining the power profile comprises maintaining the power profile based on the amount of current and a voltage of at least one of the plurality of system elements in the system.
10. A system, comprising:
a current sense circuit that senses an amount of current supplied by at least one of a plurality of power rails; and
a power manager circuit that:
evaluates the amount of current over a period of time; and
maintains a power profile of power consumed by at least one of a plurality of system elements in the system.
11. The system according to claim 10, wherein the power manager circuit further:
identifies a system element as a source of heat in the system based on the power profile; and
changes an output voltage of or powers down a power rail associated with the system element.
12. The system according to claim 10, wherein the power manager circuit further identifies an unexpected ongoing processing status or state of an element in the system based on the amount of current.
13. The system according to claim 10, wherein the power manager circuit further:
compares the amount of current to a threshold; and
sets at least one of the plurality of power rails into a low power mode of operation when the amount of current is less than the threshold.
14. The system according to claim 10, wherein the power manager circuit further:
compares the amount of current to a threshold; and
sets at least one of the plurality of power rails into a normal power mode of operation when the amount of current approaches the threshold.
15. The system according to claim 10, wherein:
the current sense circuit senses an amount of current supplied by each of the plurality of power rails; and
the power manager circuit profiles the amount of current supplied by each of the plurality of power rails over the period of time.
16. A method, comprising:
sensing, with a current sense circuit in a system, an amount of power supplied by a plurality of power rails;
profiling the amount of power; and
based on the profiling, maintaining a power profile of power consumed by a plurality of system elements in the system.
17. The method according to claim 16, further comprising:
based on the power profile, identifying a system element as a source of heat in the system; and
changing an output voltage of or powering down a power rail associated with the system element.
18. The method according to claim 16, further comprising identifying an unexpected ongoing processing status or state of an element in the system based on the amount of power.
19. The method according to claim 16, further comprising:
comparing the amount of power to a threshold;
when the amount of power is less than the threshold, setting at least one of the plurality of power rails into a low power mode of operation; and
when the amount of power approaches the threshold, setting at least one of the plurality of power rails into a normal power mode of operation.
20. The method according to claim 16, wherein
sensing the amount of power comprises sensing an amount of current supplied by each of the plurality of power rails; and
profiling the amount of power comprises profiling the amount of current supplied by each of the plurality of power rails over the period of time.
US13/950,776 2013-02-01 2013-07-25 Dynamic power mode switching per rail Abandoned US20140223214A1 (en)

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US201361759470P true 2013-02-01 2013-02-01
US201361833598P true 2013-06-11 2013-06-11
US201361834513P true 2013-06-13 2013-06-13
US201361836327P true 2013-06-18 2013-06-18
US201361836306P true 2013-06-18 2013-06-18
US201361836895P true 2013-06-19 2013-06-19
US201361836903P true 2013-06-19 2013-06-19
US201361836886P true 2013-06-19 2013-06-19
US13/950,776 US20140223214A1 (en) 2013-02-01 2013-07-25 Dynamic power mode switching per rail

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US13/950,725 Abandoned US20140223217A1 (en) 2013-02-01 2013-07-25 Power and system management information visibility
US13/950,762 Active 2034-07-11 US9424127B2 (en) 2013-02-01 2013-07-25 Charger detection and optimization prior to host control
US13/950,776 Abandoned US20140223214A1 (en) 2013-02-01 2013-07-25 Dynamic power mode switching per rail
US13/950,769 Active 2034-11-28 US9542267B2 (en) 2013-02-01 2013-07-25 Enhanced recovery mechanisms
US13/950,713 Active US8996736B2 (en) 2013-02-01 2013-07-25 Clock domain crossing serial interface, direct latching, and response codes
US13/950,750 Active 2033-12-06 US9342400B2 (en) 2013-02-01 2013-07-25 Dynamic power profiling
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US13/950,750 Active 2033-12-06 US9342400B2 (en) 2013-02-01 2013-07-25 Dynamic power profiling
US14/631,709 Active US9448878B2 (en) 2013-02-01 2015-02-25 Clock domain crossing serial interface

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US20140223200A1 (en) 2014-08-07
US20140218011A1 (en) 2014-08-07
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US20140218078A1 (en) 2014-08-07
US20140223217A1 (en) 2014-08-07
US9430323B2 (en) 2016-08-30
US20140223031A1 (en) 2014-08-07
US9448878B2 (en) 2016-09-20
US20140223153A1 (en) 2014-08-07
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US9542267B2 (en) 2017-01-10
US9342400B2 (en) 2016-05-17

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