WO2017172119A1 - Integrated circuit package having integrated emi shield - Google Patents
Integrated circuit package having integrated emi shield Download PDFInfo
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- WO2017172119A1 WO2017172119A1 PCT/US2017/018879 US2017018879W WO2017172119A1 WO 2017172119 A1 WO2017172119 A1 WO 2017172119A1 US 2017018879 W US2017018879 W US 2017018879W WO 2017172119 A1 WO2017172119 A1 WO 2017172119A1
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- Prior art keywords
- integrated circuit
- conductive
- substrate
- fence
- circuit package
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Definitions
- the disclosure herein relates generally to integrated circuit packages and more particularly to electromagnetic interference (EMI) shields for such structures.
- EMI electromagnetic interference
- FIGS. 1 A and IB illustrate generally an example of at least a portion of an integrated circuit package that includes an integrated EMI shield or EMI fence.
- FIG. 2A-2E illustrates generally a graphical flow associated with a method of forming a through-mold EMI shield for an integrated circuit die.
- FIGS. 3A-3C illustrate generally a device including a substrate integrated EMI shield according to an example of the present subject matter.
- FIG. 3D illustrates generally a cross-section of stacked vias having a different stacking pattern than the device of FIG. 3C .
- FIG. 4 illustrates generally a device 400 including an EMI shield according to an example of the present subject matter.
- FIG. 5 illustrates generally a flowchart of a method for providing an EMI shielded integrated circuit.
- an EMI shield can be integrated within over mold material surrounding an integrated circuit with an integrated circuit package, in some examples, an EMI shield can be integrated with a substrate and can be positioned about a cavity of the substrate that houses an integrated circuit. In some examples, an EMI shield can be built up about an integrated circuit housed in a cavity of a substrate.
- standard package fabrication methods including, but not limited to, formation of through mold interconnections, package via formation, cavity package construction, etc. Such methods can typically offer lower cost and short processing times to provide an EMI shield.
- FIGS. 1A and IB illustrate generally an example of at least a portion of an integrated circuit package 100 that includes an integrated EMI shield.
- the integrated circuit package 100 can include a substrate 1 1, an integrated circuit die 102, external solder balls 103, ground pads 104, substrate traces 105, over-mold mold material 106, sidewall EMI shields 107, and a top-side EMI shield 108.
- the integrated circuit die 102 is mounted to terminations (not shown) of the substrate 101, for example via terminals on the underside or bottom of the integrated circuit die 102.
- the substrate 101 can include wire traces 105 and routing structures to connect the appropriate termination of the integrated circuit die 102 to the external solder balls 103 of the substrate 101.
- the top surface of the substrate can include ground pads 104 that surround the integrated circuit die 102 when the integrated circuit die 102 is mounted to the substrate 101.
- the ground pads 104 are electrically coupled to each other using conductive traces 105 of the substrate 101
- the ground pads 1 4 are electrically coupled to each other using conductive traces of the mold material.
- additional conductive material can optionally be coupled to the grounding pads prior to adding the mold material 106. Such additional conductive material can include, but is not limited to, solder balls 109.
- holes 1 10 can be bored through the mold material 106 to each ground pad 104 or corresponding solder ball 109.
- the holes 1 10 can be filled with conductive material to form the sidewall EMI shields 107 or sidewall EMI fence.
- the over-mold mold material 106 can encapsulate the integrated circuit 102 about the side surfaces and the top surface and can house the conductive fence or side wall EMI shields 107.
- a foil, film or sheet 108 of conductive material can be attached to the upper surface of the mold material 106 and the sheet 1 8 of conductive material can be electrically coupled to the conductive material that forms the sidewali EMI shields 107.
- the sheet 108 can be coextensive with the footprint defined by the sidewali EMI shields 107.
- the substrate 101 can have multiple layers and one of tlie layers of the substrate 101 can optionally include a mesh of conductive material.
- the mesh can serve as a lower-side EMI shield of the integrated circuit die 102 and can be electrically coupled to the sidewali shields. Electrical connections between the integrated circuit die 102 and the solder balls 103 on the lower side of the substrate 101 can be routed through openings of the mesh.
- FIG. 1A illustrates generally a cross-section of an integrated circuit package 100 that includes sidewa.13 EMI shields 107 and a top-side EMI shield 108.
- FIG. IB illustrates generally a top-view cross-section of the integrated circuit package 100 of FIG . 1A that includes conductive traces 105 between the ground pads (not shown) and corresponding solder balls 109 of the sidewali EMI shields 107 that surround the integrated circuit die 102.
- FIG. 2A-2E illustrates generally a graphical flow associated with a method of forming a through-moid EMI shield for an integrated circuit die
- FIG 2A shows the integrated circuit die 202 attached to a substrate 201 and solder balls 209 or conductive paste attached to ground pads 104 on the surface of the substrate 201.
- the substrate 201 can include routing structures (not shown) to appropriately connect terminations of the integrated circuit die 202 with terminations on the lower side of the substrate 201.
- a molding compound 206 is added to encapsulate the integrated circuit die and the upper surface of the su bstrate surrounding the integrated circuit die 202.
- holes 210 can be created or bored through the molding compound 206 to extend to and expose the solder balls 209 or conductive paste associated with the grounding pads 204.
- the holes 209 can be bored to expose a portion of each grounding pad 204. In certain examples, the holes 209 can be bored using laser ablation or other boring methods. At FIG. 2D, the holes 209 can be filled with electrically conductive material 211. At FIG. 2E, an electrically conducti ve sheet 208 can be applied to the top surface of the molding compound 206 and can be connected to the conductive material 21 1 filling the holes 210 to complete the through-mold EMI shield of the integrated circuit die 202. In certain examples, external solder balls 203 or external terminations can be added to the substrate 201.
- FIGS. 3A-3D illustrate generally a device 300 including a substrate integrated EMI shield according to an example of the present subject matter.
- the device 300 includes a substrate 301, and an integrated circuit die 302.
- the integrated circuit die 302 can be mounted to the substrate 301 within a cavity 312 of the substrate 301.
- underfill material 313 can be used to secure fill voids between the interior surfaces of the substrate cavity 312 and the integrated circuit die 302.
- the underfill material 313 can isolated and protect the electrical connections between the integrated circuit die 302 and the substrate 301.
- the substrate 301 can include routing structures (not shown) to electrically connect terminations of the integrated circuit die 302 with external terminations 303 of the substrate 301 such as, but not limited to, solder balls located on an underside of the substrate.
- the substrate 301 can include a series of closely stacked vias 314 that surround the cavity 312.
- the substrate 301 can include multiple layers and the stacked vias can include alternating layers of conductive pads 316 and conductive vias, The vias and conductive pads 316 can be coupled directly together and integrated with each of the multiple layers of the substrate 301 to form the stacked vias 314.
- the stacked vias 314 can be coupled to an optional grounding plane or a ground terminal of the substrate 301.
- the stacked vias 314 can include a conductive material or paste 318 located at a top surface of the substrate.
- a conductive sheet 308 or foil can span the top of the cavity 312 and can be electrically coupled to the stacked vias 314 for example, via the conductive paste 318.
- the conductive sheet 308 and stacked vias 314 can form an EMI shield about the integrated circuit die 302.
- the substrate 301 can optionally include a lower conductive mesh 315 to provide EMI shielding underneath the integrated circuit die 302. Openings in the underlying conductive mesh 315 can be used to route electrical connections between the integrated circuit die 302 and external connections 303 on the underside of the substrate 301.
- FIG. 3B illustrates a top-down cross- section of the device 300 and shows that traces 305 can be used to electrically connect the stacked vias 314.
- the traces 305 can be located on one or more of the substrate layers.
- FIG. 3C illustrates a cross-section of the stacked vias 314.
- the stacked vias 314 can be electrically coupled together using a conductive trace or a conductive mesh 315 of the substrate 301.
- FIG. 3D illustrates generally a cross-section of stacked vias 317 having a different stacking pattern than the device 300 of FIG. 3C.
- the stacking pattern of the stacked vias 317 of FIG . 3C uses lateral! offset vias as opposed to the vertically aligned vias of the device of FIG. 3C.
- FIG. 4 illustrates generally a device 400 including an EMI shield according to an example of the present subject matter.
- the device 400 includes a substrate 401, and an integrated circuit die 402.
- the integrated circuit die 402 can be mounted to the substrate within a cavity 412 of the substrate 401.
- underfill material 413 can be used to fill voids between the lower interior surface of the substrate cavity 432 and the integrated circuit die 402.
- the underfill material 413 can isolated and protect the eiectricai connections 420 between the integrated circuit die 402 and the substrate 40 i .
- the remaining voids about the sidewails of the cavity 412 and the sidewails of the integrated circuit die 402 can be filled with conductive material 419 such as a conductive paste to create an EMI shield about the sidewails.
- the substrate 401 can include grounding terminals 421 on one or more layers of the substrate 401.
- the grounding terminals 421 can be exposed at the sidewails of the cavity 412 and can electrically couple the conductiv e material 419 of the EMI shield with ground or other reference voltage level.
- a sheet of conductive material 408 can be placed over the cavity 412 and over the integrated circuit die 402.
- the sheet 408 can be electrically coupled to the conductive material 419 of the EMI shield about the sidewalis or to a grounding terminal 421 exposed at the upper surface of the substrate 401.
- FIG. 5 illustrates generally a flowchart of a method for providing a EMI shielded integrated circuit.
- an integrated circuit can be mounted to and electrically couple with a substrate.
- the integrated circuit die can be mounted on a top surface of the substrate.
- a plurality of solder bails can be electrically coupled to a plurality of pads located about a perimeter of the integrated circuit die.
- the integrated circuit die and the solder balls can be encapsulated within a non -conductive material.
- a plurality of vias can be created in the non-conductive compound via a surface of the non-conductive compound opposite the substrate. Each via can extend to a corresponding solder ball.
- the vias can be filled or lined with conductive material .
- a conductive sheet can cover the upper surface of the nonconductive material and can be electrically coupled with the conductive material filling or lining the vias.
- the pads of the substrate can be electrically coupled together such as by traces of the substrate.
- one or more of the pads can be coupled to an external termination of the substrate such as an external solder ball of the substrate.
- an integrated circuit package can include an integrated circuit mounted to a substrate via connections on a first major surface (e.g., bottom) of the integrated circuit, a conductive fence surrounding side surfaces of the integrated circuit, and a conductive film coupled to the conductive fence, the film located above a second major surface (e.g., top) of the integrated circuit and coextensive with a footprint defined by the conductive fence, the second major surface of the integrated circuit opposite the first major surface of the integrated circuit.
- a first major surface e.g., bottom
- a conductive fence surrounding side surfaces of the integrated circuit
- a conductive film coupled to the conductive fence, the film located above a second major surface (e.g., top) of the integrated circuit and coextensive with a footprint defined by the conductive fence, the second major surface of the integrated circuit opposite the first major surface of the integrated circuit.
- Example 2 the integrated circuit package of Example 1 optionally includes an over-mold configured to encapsulate the integrated circuit about the side surfaces and the second major surface and to house the conductive fence.
- Example 3 the conductive fence of any one or more of
- Examples 1 -2 optionally includes a plurality of solder balls coupled to a plurality of ground pads on a first major surface of the substrate.
- Examples 1-3 optionally is positioned within a cavity of the substrate.
- Example 5 the substrate of any one or more of Examples 1-4 optionally includes the conductive fence surrounding the side surfaces of the integrated circuit and a second conductive fence underlying the integrated circuit.
- Example 6 the second conductive fence of any one or more of
- Examples 1-5 optionally is configured to allow electrically isolated vertical connections between the integrated circuit and external connections exposed on a second major surface of the substrate, the second major surface of the substrate opposite the first major surface of the substrate.
- Example 7 the conductive fence of any one or more of
- Examples 1 -6 optionally includes a plurality of conductive traces and a plurality of conductive vias alternately stacked within the substrate.
- Example 8 the plurality of vias of any one or more of
- Examples 1-7 optionally includes a first via and a second via, wherein the first via and the second via are directly coupled by a conductive trace of the plurality of conductive traces, wherein the first via and the second are positioned in different vertical layers of the substrate, and wherein the first via is laterally offset from the second via.
- Example 9 the plurality of vias of any one or more of
- Examples 1-3 optionally includes a first via and a second via, wherein the first via and the second via are directly coupled by a conductive trace of the plurality of conductive traces, wherein the first via and the second are positioned in different vertical layers of the substrate, and wherein the first via is vertically aligned with the second via.
- Examples 1-9 optionally includes conductive paste configured to fill at least a portion of the cavity about the integrated circuit not filled by the integrated circuit.
- Example 11 the integrated circuit package of any one or more of Examples 1-10 optionally includes underfill configured to isolate the connections on the first major surface of the integrated circuit from the conductive paste.
- Example 12 the substrate of any one or more of Examples 1- 11 optionally includes a plurality of traces configured to electrically couple with the conductive paste.
- Example 13 a first conductive trace of the plurality of conductive traces of any one or more of Examples 1-12 optionally is configured to couple the conductive film to the conductive fence.
- Example 14 a first conductive trace of the pluralit 7 of conductive traces of any one or more of Examples 1-13 optionally is configured to couple the conductive fence to terminal on the second major surface of the substrate.
- a method for providing EMI shielding for in integrated circuit package can include electrically coupling and mounting an integrated circuit to terminations on a top surface of a substrate, electrically coupling a plurality of solder balls to a plurality of pads of the substrate, the plurality of pads located about a perimeter of the integrated circuit, encapsulating the integrated circuit and the solder bails with a non-conductive compound, creating a plurality of vias in the non-conductive compound through a surface opposite the substrate, each via of the plurality of vias extending to a solder ball of the plurality of solder balls, filling each via with a conductive material, covering the surface with a conductive sheet, and coupling the conductive sheet with the conductive material .
- Example 16 the creating a plurality of vias of any one or more of Examples 1-15 optionally includes laser ablating the non-conductive compound.
- Example 17 the method of any one or more of Examples 1-9 optionally includes electrically coupling the plurality of solder balls together to each other.
- Example 18 the method of any one or more of Examples 1 -9 optionally includes electrically coupling the plurality of solder balls to a termination on a bottom side of the substrate.
- a method for providing EMI shielding for in integrated circuit package can include creating a first conductive fence about a cavity of the substrate, electrically coupling and mounting an integrated circuit to tenninations of the substrate within the cavity of the substrate, covering the cavity with a conductive sheet, and coupling the conductive sheet with the conductive fence.
- the creating the conductive fence of any one or more of Examples 1 -19 optionally includes fabricating an opening in a first layer of the substrate, the opening configured to form a portion of a sidewall of the cavity, fabricating a plurality of traces of the first layer, the plurality of traces positioned about the opening, and fabricating a plurality of conductive vias, each via coupled to a corresponding trace of the plurality of traces.
- Example 21 the creating the conductive fence of any one or more of Examples 1-20 optionally includes fabricating a second conductive fence within a second layer of the substrate, the second conductive fence configured to underlie the cavity,
- Example 22 the method of any one or more of Examples 1-9 optionally includes coupling the second conductive fence with the first con ductive fence .
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- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
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Abstract
Apparatus and methods are provided for an integrated circuit package that includes an integrated EMI shield. In an example, an integrated circuit package can include an integrated circuit mounted to a substrate via connections on the bottom surface of the integrated circuit, a conductive fence surrounding side surfaces of the integrated circuit, a conductive film coupled to the conductive fence, the film located above a top surface of the integrated circuit and coextensive with a footprint defined by the conductive fence.
Description
INTEGRATED CIRCUIT PACKAGE HAVING INTEGRATE;
[0001] This application claims the benefit of priority to U.S. Patent
Application Serial No. 15/088,857, filed April 1, 2016, which is incorporated herein by refernce in its entirety.
Technical Field
[0002] The disclosure herein relates generally to integrated circuit packages and more particularly to electromagnetic interference (EMI) shields for such structures.
Background
[0003] Current EMI shielding for molded system in package (SiP) use a physical vapor deposition (PVD) sputtering process to coat the mold surface with a conductive material. The sputtering process has many disadvantages including high cost of the sputtering equipment, long through put time to increase conductive material thickness, complex process for uniform material coverage on package sidewalls, mold surface pre-clean to improve adhesion etc. In the case of EMI shielding between components, laser trenches are made between components and filled with a conductive material. The expensive laser ablation tool and long process for laser trenching can negatively impact cost and throughput time in high volume ma facturing.
Brief Description of the Drawings
[0004] In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar
components. Some embodiments are illustrated by way of example, and not limitation, in the figures of the accompanying drawings in which:
[0005] FIGS. 1 A and IB illustrate generally an example of at least a portion of an integrated circuit package that includes an integrated EMI shield or EMI fence.
[0006J FIG. 2A-2E illustrates generally a graphical flow associated with a method of forming a through-mold EMI shield for an integrated circuit die.
[0007] FIGS. 3A-3C illustrate generally a device including a substrate integrated EMI shield according to an example of the present subject matter.
[0008] FIG. 3D illustrates generally a cross-section of stacked vias having a different stacking pattern than the device of FIG. 3C .
[0009] FIG. 4 illustrates generally a device 400 including an EMI shield according to an example of the present subject matter.
[0010] FIG. 5 illustrates generally a flowchart of a method for providing an EMI shielded integrated circuit.
Detailed Description
[0011] The following description and the drawings sufficiently illustrate specific embodiments to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Embodiments set forth in the claims encompass all available equivalents of those claims.
[0012] The present inventors have recognized apparatus and techniques for providing EMI shielding of integrated circuits assembled within integrated packages. In certain examples, an EMI shield can be integrated within over mold material surrounding an integrated circuit with an integrated circuit package, in some examples, an EMI shield can be integrated with a substrate and can be positioned about a cavity of the substrate that houses an integrated circuit. In some examples, an EMI shield can be built up about an integrated circuit housed in a cavity of a substrate. Each of the above examples, can use standard package fabrication methods including, but not limited to, formation of
through mold interconnections, package via formation, cavity package construction, etc. Such methods can typically offer lower cost and short processing times to provide an EMI shield. In each case, the high cost of the sputtering equipment, long through put time to increase conductive material thickness and complex process for uniform material coverage on package sidewails can be avoided. In addition, the package form factor and thiclaiess are not increased by the above EMI shielding solutions.
[0013] FIGS. 1A and IB illustrate generally an example of at least a portion of an integrated circuit package 100 that includes an integrated EMI shield. In certain examples, the integrated circuit package 100 can include a substrate 1 1, an integrated circuit die 102, external solder balls 103, ground pads 104, substrate traces 105, over-mold mold material 106, sidewall EMI shields 107, and a top-side EMI shield 108. In certain examples, the integrated circuit die 102 is mounted to terminations (not shown) of the substrate 101, for example via terminals on the underside or bottom of the integrated circuit die 102. The substrate 101 can include wire traces 105 and routing structures to connect the appropriate termination of the integrated circuit die 102 to the external solder balls 103 of the substrate 101. The top surface of the substrate can include ground pads 104 that surround the integrated circuit die 102 when the integrated circuit die 102 is mounted to the substrate 101. In some examples, the ground pads 104 are electrically coupled to each other using conductive traces 105 of the substrate 101, In some examples, the ground pads 1 4 are electrically coupled to each other using conductive traces of the mold material. In some examples, additional conductive material can optionally be coupled to the grounding pads prior to adding the mold material 106. Such additional conductive material can include, but is not limited to, solder balls 109. After the mold material 1 6 is over molded around the integrated circuit die 102 and around the surrounding substrate surfaces, including the ground pads 104, holes 1 10 can be bored through the mold material 106 to each ground pad 104 or corresponding solder ball 109. The holes 1 10 can be filled with conductive material to form the sidewall EMI shields 107 or sidewall EMI fence. In certain examples, the over-mold mold material 106 can encapsulate the integrated
circuit 102 about the side surfaces and the top surface and can house the conductive fence or side wall EMI shields 107. In certain examples, a foil, film or sheet 108 of conductive material can be attached to the upper surface of the mold material 106 and the sheet 1 8 of conductive material can be electrically coupled to the conductive material that forms the sidewali EMI shields 107. The sheet 108 can be coextensive with the footprint defined by the sidewali EMI shields 107. In some examples, the substrate 101 can have multiple layers and one of tlie layers of the substrate 101 can optionally include a mesh of conductive material. The mesh can serve as a lower-side EMI shield of the integrated circuit die 102 and can be electrically coupled to the sidewali shields. Electrical connections between the integrated circuit die 102 and the solder balls 103 on the lower side of the substrate 101 can be routed through openings of the mesh. FIG. 1A illustrates generally a cross-section of an integrated circuit package 100 that includes sidewa.13 EMI shields 107 and a top-side EMI shield 108. FIG. IB illustrates generally a top-view cross-section of the integrated circuit package 100 of FIG . 1A that includes conductive traces 105 between the ground pads (not shown) and corresponding solder balls 109 of the sidewali EMI shields 107 that surround the integrated circuit die 102.
[0014] FIG. 2A-2E illustrates generally a graphical flow associated with a method of forming a through-moid EMI shield for an integrated circuit die
202. FIG 2A shows the integrated circuit die 202 attached to a substrate 201 and solder balls 209 or conductive paste attached to ground pads 104 on the surface of the substrate 201. The substrate 201 can include routing structures (not shown) to appropriately connect terminations of the integrated circuit die 202 with terminations on the lower side of the substrate 201. At FIG. 2B, a molding compound 206 is added to encapsulate the integrated circuit die and the upper surface of the su bstrate surrounding the integrated circuit die 202. At FIG. 2C, holes 210 can be created or bored through the molding compound 206 to extend to and expose the solder balls 209 or conductive paste associated with the grounding pads 204. In some examples, the holes 209 can be bored to expose a portion of each grounding pad 204. In certain examples, the holes 209 can be bored using laser ablation or other boring methods. At FIG. 2D, the holes 209
can be filled with electrically conductive material 211. At FIG. 2E, an electrically conducti ve sheet 208 can be applied to the top surface of the molding compound 206 and can be connected to the conductive material 21 1 filling the holes 210 to complete the through-mold EMI shield of the integrated circuit die 202. In certain examples, external solder balls 203 or external terminations can be added to the substrate 201.
[0015] FIGS. 3A-3D illustrate generally a device 300 including a substrate integrated EMI shield according to an example of the present subject matter. In certain examples, the device 300 includes a substrate 301, and an integrated circuit die 302. The integrated circuit die 302 can be mounted to the substrate 301 within a cavity 312 of the substrate 301. Upon mounting the integrated circuit die 302 in the cavity, underfill material 313 can be used to secure fill voids between the interior surfaces of the substrate cavity 312 and the integrated circuit die 302. In addition to assisting secure and immobilize the die, the underfill material 313 can isolated and protect the electrical connections between the integrated circuit die 302 and the substrate 301.
[0016] In certain examples, the substrate 301 can include routing structures (not shown) to electrically connect terminations of the integrated circuit die 302 with external terminations 303 of the substrate 301 such as, but not limited to, solder balls located on an underside of the substrate. In certain examples, the substrate 301 can include a series of closely stacked vias 314 that surround the cavity 312. In certain examples, the substrate 301 can include multiple layers and the stacked vias can include alternating layers of conductive pads 316 and conductive vias, The vias and conductive pads 316 can be coupled directly together and integrated with each of the multiple layers of the substrate 301 to form the stacked vias 314. The stacked vias 314 can be coupled to an optional grounding plane or a ground terminal of the substrate 301. In certain examples, the stacked vias 314 can include a conductive material or paste 318 located at a top surface of the substrate. A conductive sheet 308 or foil can span the top of the cavity 312 and can be electrically coupled to the stacked vias 314 for example, via the conductive paste 318. The conductive sheet 308 and stacked vias 314 can form an EMI shield about the integrated circuit die 302. In
certain examples, the substrate 301 can optionally include a lower conductive mesh 315 to provide EMI shielding underneath the integrated circuit die 302. Openings in the underlying conductive mesh 315 can be used to route electrical connections between the integrated circuit die 302 and external connections 303 on the underside of the substrate 301. FIG. 3B illustrates a top-down cross- section of the device 300 and shows that traces 305 can be used to electrically connect the stacked vias 314. In some examples, the traces 305 can be located on one or more of the substrate layers.
[0017] FIG. 3C illustrates a cross-section of the stacked vias 314. In certain examples, the stacked vias 314 can be electrically coupled together using a conductive trace or a conductive mesh 315 of the substrate 301. FIG. 3D illustrates generally a cross-section of stacked vias 317 having a different stacking pattern than the device 300 of FIG. 3C. The stacking pattern of the stacked vias 317 of FIG . 3C uses lateral! offset vias as opposed to the vertically aligned vias of the device of FIG. 3C.
[0018] FIG. 4 illustrates generally a device 400 including an EMI shield according to an example of the present subject matter. In certain examples, the device 400 includes a substrate 401, and an integrated circuit die 402. The integrated circuit die 402 can be mounted to the substrate within a cavity 412 of the substrate 401. Upon mounting the integrated circuit die 402 in the cavity 412, underfill material 413 can be used to fill voids between the lower interior surface of the substrate cavity 432 and the integrated circuit die 402. In addition to assisting secure and immobilize the integrated circuit die 402, the underfill material 413 can isolated and protect the eiectricai connections 420 between the integrated circuit die 402 and the substrate 40 i , The remaining voids about the sidewails of the cavity 412 and the sidewails of the integrated circuit die 402 can be filled with conductive material 419 such as a conductive paste to create an EMI shield about the sidewails. In certain examples, the substrate 401 can include grounding terminals 421 on one or more layers of the substrate 401. In certain examples, the grounding terminals 421 can be exposed at the sidewails of the cavity 412 and can electrically couple the conductiv e material 419 of the EMI shield with ground or other reference voltage level. In certain examples, a
sheet of conductive material 408 can be placed over the cavity 412 and over the integrated circuit die 402. The sheet 408 can be electrically coupled to the conductive material 419 of the EMI shield about the sidewalis or to a grounding terminal 421 exposed at the upper surface of the substrate 401.
[0019] FIG. 5 illustrates generally a flowchart of a method for providing a EMI shielded integrated circuit. At 501, an integrated circuit can be mounted to and electrically couple with a substrate. In certain examples, the integrated circuit die can be mounted on a top surface of the substrate. At 502, a plurality of solder bails can be electrically coupled to a plurality of pads located about a perimeter of the integrated circuit die. At 503, the integrated circuit die and the solder balls can be encapsulated within a non -conductive material. At 504, a plurality of vias can be created in the non-conductive compound via a surface of the non-conductive compound opposite the substrate. Each via can extend to a corresponding solder ball. At 505, the vias can be filled or lined with conductive material . At 506, a conductive sheet can cover the upper surface of the nonconductive material and can be electrically coupled with the conductive material filling or lining the vias. In some examples, the pads of the substrate can be electrically coupled together such as by traces of the substrate. In some examples, one or more of the pads can be coupled to an external termination of the substrate such as an external solder ball of the substrate.
Additional Examples and Notes
[0020] In Example 1, an integrated circuit package can include an integrated circuit mounted to a substrate via connections on a first major surface (e.g., bottom) of the integrated circuit, a conductive fence surrounding side surfaces of the integrated circuit, and a conductive film coupled to the conductive fence, the film located above a second major surface (e.g., top) of the integrated circuit and coextensive with a footprint defined by the conductive fence, the second major surface of the integrated circuit opposite the first major surface of the integrated circuit.
[0021] In Example 2, the integrated circuit package of Example 1 optionally includes an over-mold configured to encapsulate the integrated circuit
about the side surfaces and the second major surface and to house the conductive fence.
[0022] In Example 3, the conductive fence of any one or more of
Examples 1 -2 optionally includes a plurality of solder balls coupled to a plurality of ground pads on a first major surface of the substrate.
[0023 J In Example 4, the integrated circuit of any one or more of
Examples 1-3 optionally is positioned within a cavity of the substrate.
[0024] In Example 5, the substrate of any one or more of Examples 1-4 optionally includes the conductive fence surrounding the side surfaces of the integrated circuit and a second conductive fence underlying the integrated circuit.
[0025] In Example 6, the second conductive fence of any one or more of
Examples 1-5 optionally is configured to allow electrically isolated vertical connections between the integrated circuit and external connections exposed on a second major surface of the substrate, the second major surface of the substrate opposite the first major surface of the substrate..
[0026] In Example 7, the conductive fence of any one or more of
Examples 1 -6 optionally includes a plurality of conductive traces and a plurality of conductive vias alternately stacked within the substrate.
[0027] In Example 8, the plurality of vias of any one or more of
Examples 1-7 optionally includes a first via and a second via, wherein the first via and the second via are directly coupled by a conductive trace of the plurality of conductive traces, wherein the first via and the second are positioned in different vertical layers of the substrate, and wherein the first via is laterally offset from the second via.
[0028] In Example 9, the plurality of vias of any one or more of
Examples 1-3 optionally includes a first via and a second via, wherein the first via and the second via are directly coupled by a conductive trace of the plurality of conductive traces, wherein the first via and the second are positioned in different vertical layers of the substrate, and wherein the first via is vertically aligned with the second via.
[0029] In Example 10, the conductive fence of any one or more of
Examples 1-9 optionally includes conductive paste configured to fill at least a portion of the cavity about the integrated circuit not filled by the integrated circuit.
[0030] In Example 11, the integrated circuit package of any one or more of Examples 1-10 optionally includes underfill configured to isolate the connections on the first major surface of the integrated circuit from the conductive paste.
[0031] In Example 12, the substrate of any one or more of Examples 1- 11 optionally includes a plurality of traces configured to electrically couple with the conductive paste.
[0032] In Example 13, a first conductive trace of the plurality of conductive traces of any one or more of Examples 1-12 optionally is configured to couple the conductive film to the conductive fence.
[0033] In Example 14, a first conductive trace of the pluralit 7 of conductive traces of any one or more of Examples 1-13 optionally is configured to couple the conductive fence to terminal on the second major surface of the substrate.
[0034] In Example 15, a method for providing EMI shielding for in integrated circuit package can include electrically coupling and mounting an integrated circuit to terminations on a top surface of a substrate, electrically coupling a plurality of solder balls to a plurality of pads of the substrate, the plurality of pads located about a perimeter of the integrated circuit, encapsulating the integrated circuit and the solder bails with a non-conductive compound, creating a plurality of vias in the non-conductive compound through a surface opposite the substrate, each via of the plurality of vias extending to a solder ball of the plurality of solder balls, filling each via with a conductive material, covering the surface with a conductive sheet, and coupling the conductive sheet with the conductive material .
[0035] In Example 16, the creating a plurality of vias of any one or more of Examples 1-15 optionally includes laser ablating the non-conductive compound.
[0036] In Example 17, the method of any one or more of Examples 1-9 optionally includes electrically coupling the plurality of solder balls together to each other.
Θ037] In Example 18, the method of any one or more of Examples 1 -9 optionally includes electrically coupling the plurality of solder balls to a termination on a bottom side of the substrate.
[0038] In Example 19, a method for providing EMI shielding for in integrated circuit package can include creating a first conductive fence about a cavity of the substrate, electrically coupling and mounting an integrated circuit to tenninations of the substrate within the cavity of the substrate, covering the cavity with a conductive sheet, and coupling the conductive sheet with the conductive fence.
[0039J In Example 20, the creating the conductive fence of any one or more of Examples 1 -19 optionally includes fabricating an opening in a first layer of the substrate, the opening configured to form a portion of a sidewall of the cavity, fabricating a plurality of traces of the first layer, the plurality of traces positioned about the opening, and fabricating a plurality of conductive vias, each via coupled to a corresponding trace of the plurality of traces.
[0040] In Example 21, the creating the conductive fence of any one or more of Examples 1-20 optionally includes fabricating a second conductive fence within a second layer of the substrate, the second conductive fence configured to underlie the cavity,
[0041] In Example 22, the method of any one or more of Examples 1-9 optionally includes coupling the second conductive fence with the first con ductive fence .
[0042] Each of these non-limiting examples can stand on its own, or can be combined with one or more of the other examples in any permutation or combination.
[0043] The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as
"examples." Such examples can include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.
[0044] In this document, the terms "a" or "an" are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of "at least one" or "one or more." In this document, the term "or" is used to refer to a nonexclusive or, such that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise indicated. In this document, the terms "including" and "in which" are used as the plain-English equivalents of the respective terms "comprising" and "wherein." Also, in the following claims, the terms "including" and "comprising" are open-ended, that is, a system, device, article, composition, formulation, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.
[0045] The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. § 1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby
incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments can be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are legally entitled.
Claims
What is claimed is: . An integrated circuit package comprising:
an integrated circuit mounted to a substrate via connections on a first major surface of the integrated circuit;
a conductive fence surrounding side surfaces of the integrated circuit; and
a conductive film coupled to the conductive fence, the film located above a second major surface of the integrated circuit and coextensive with a footprint defined by the conductive fence, the second major surface of the integrated circuit opposite the first major surface of the integrated circuit.
2. The integrated circuit package of claim 1 , including an over-mold configured to encapsulate the integrated circuit about the side surfaces and the second major surface and to house the conductive fence.
3. The integrated circuit package of claim 2, wherein the conductive fence includes a plurality of solder balls coupled to a plurality of ground pads on a first major surface of the substrate.
4. The integrated circuit package of claim 1 , wherein the integrated circuit is positioned within a cavity of the subsiraie.
5. The integrated circuit package of claim 4, wherein the substrate includes: the conductive fence surrounding the side surfaces of the integrated circuit; and
a second conductive fence underlying the integrated circuit.
6. The integrated circuit package of claim 5, wherein the second conductive fence is configured to allow electrically isolated vertical connections between the integrated circuit and external connections exposed on a second major
surface of the substrate, the second major surface of the substrate opposite the first major surface of the substrate.
7. The integrated circuit package of claim 4, wherein the conductive fence includes a plurality of conductive traces and a plurality of conductive vias alternately stacked within the substrate.
8. The integrated circuit package of claim 7, wherein the plurality of vias includes a first via and a second via;
wherein the first via and the second via are directly coupled by a conductive trace of the plurality of conductive traces;
wherein the first via and the second are positioned in different vertical layers of the substrate; and
wherein the first via is laterally offset from the second via.
9. The integrated circuit package of claim 7, wherein the plurality of vias includes a first via and a second via;
wherein the first via and the second via are directly coupled by a conductive trace of the plurality of conductive traces;
wherein the first via and the second are positioned in different vertical layers of the substrate; and
wherein the first via is vertically aligned with the second via.
10. The integrated circuit package of claim 4, wherein the conductive fence includes conductive paste configured to fill at least a portion of the cavity about the integrated circuit not filled by the integrated circuit.
11. The integrated circuit package of claim 10, including underfill configured to isolate the connections on the first major surface of the integrated circuit from the conductive paste.
12. The integrated circuit package of claim 10, wherein the substrate includes a plurality of traces configured to electrically couple with the conductive paste.
13. The integrated circuit package of claim 12, wherein a first conductive trace of the plurality of conductive traces is confi gured to couple the conductive film to the conductive fence,
14. The integrated circuit package of claim 12, wherein a first conductive trace of the plurality of conductive traces is configured to couple the conductive fence to terminal on the second major surface of the substrate.
15. A method for providing EMI shielding for in integrated circuit package, the method comprising;
electrically coupling and mounting an integrated circuit to terminations on a top surface of a substrate;
electrically coupling a plurality of solder balls to a plurality of pads of the substrate, the plurality of pads located about a perimeter of the integrated circuit; encapsulating the integrated circuit and the solder balls with a non- conductive compound;
creating a plurality of vias in the non-conductive compound through a surface opposite the substrate, each via of the plurality of vias extending to a solder ball of the plurality of solder balls;
filling each via with a conductive material;
covering the surface with a conductive sheet; and
coupling the conductive sheet with the conductive material.
16. The method of claim 15, wherein the creating a plurality of vias includes laser ablating the non-conductive compound.
17. The method of claim. 15, including electrically coupling the plurality of solder balls together to each other.
18. The method of claim 17, including electrically coupling the plurality of solder balls to a termination on a bottom side of the substrate.
19. A method for providing EMI shielding for in integrated circuit package, the method comprising;
creating a first conductive fence about a cavity of the substrate;
electrically coupling and mounting an integrated circuit to terminations of the substrate within the cavity of the substrate;
covering the cavity with a conductive sheet; and
coupling the conductive sheet with the conductive fence.
20. The method of claim 19, wherein creating the conductive fence includes:
fabricating an opening in a first layer of the substrate, the opening configured to form a portion of a sidewaii of the cavity; fabricating a plurality of traces of the first layer, the plurality of traces positioned about the opening; and fabricating a plurality of conductive vias, each via coupled to a corresponding trace of the plurality of traces.
21. The method of claim 20, wherein creating the conductive fence includes fabricating a second conductive fence within a second layer of the substrate, the second conductive fence configured to underlie the cavity.
22. The method of claim 21, including coupling the second conductive fence with the first conductive fence.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US15/088,857 | 2016-04-01 | ||
US15/088,857 US20170287847A1 (en) | 2016-04-01 | 2016-04-01 | Integrated circuit package having integrated emi shield |
Publications (1)
Publication Number | Publication Date |
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WO2017172119A1 true WO2017172119A1 (en) | 2017-10-05 |
Family
ID=59961233
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/US2017/018879 WO2017172119A1 (en) | 2016-04-01 | 2017-02-22 | Integrated circuit package having integrated emi shield |
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US (1) | US20170287847A1 (en) |
TW (1) | TWI757267B (en) |
WO (1) | WO2017172119A1 (en) |
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JP6648626B2 (en) * | 2016-04-27 | 2020-02-14 | オムロン株式会社 | Electronic device and method of manufacturing the same |
KR20220073009A (en) * | 2020-11-26 | 2022-06-03 | 삼성전자주식회사 | Semiconductor package and method of for fabricating the same |
GB2606841B (en) * | 2021-03-23 | 2024-08-14 | Skyworks Solutions Inc | Application of conductive via or trench for intra module EMI shielding |
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US6534859B1 (en) * | 2002-04-05 | 2003-03-18 | St. Assembly Test Services Ltd. | Semiconductor package having heat sink attached to pre-molded cavities and method for creating the package |
JP2003152131A (en) * | 2001-08-31 | 2003-05-23 | Mitsubishi Electric Corp | Hollow sealed package and its manufacturing method |
US20080061404A1 (en) * | 2006-09-12 | 2008-03-13 | Samsung Electronics Co.; Ltd | Electronic circuit package and fabricating method thereof |
WO2008062982A1 (en) * | 2006-11-21 | 2008-05-29 | Lg Innotek Co., Ltd | Electromagnetic shielding device, radio frequency module having the same, and method of manufacturing the radio frequency module |
US20120098109A1 (en) * | 2008-10-31 | 2012-04-26 | Dongkyun Ko | Chip package and manufacturing method thereof |
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JPH09162320A (en) * | 1995-12-08 | 1997-06-20 | Shinko Electric Ind Co Ltd | Semiconductor package and semiconductor device |
US7629674B1 (en) * | 2004-11-17 | 2009-12-08 | Amkor Technology, Inc. | Shielded package having shield fence |
JP5249173B2 (en) * | 2009-10-30 | 2013-07-31 | 新光電気工業株式会社 | Semiconductor device mounting wiring board and method for manufacturing the same |
WO2014065035A1 (en) * | 2012-10-22 | 2014-05-01 | 株式会社村田製作所 | Module with built-in electronic component |
US9337073B2 (en) * | 2013-03-12 | 2016-05-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D shielding case and methods for forming the same |
KR20170019023A (en) * | 2015-08-10 | 2017-02-21 | 에스케이하이닉스 주식회사 | Semiconductor package including EMI shielding and manufacturing method for the same |
-
2016
- 2016-04-01 US US15/088,857 patent/US20170287847A1/en not_active Abandoned
-
2017
- 2017-02-14 TW TW106104764A patent/TWI757267B/en active
- 2017-02-22 WO PCT/US2017/018879 patent/WO2017172119A1/en active Application Filing
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JP2003152131A (en) * | 2001-08-31 | 2003-05-23 | Mitsubishi Electric Corp | Hollow sealed package and its manufacturing method |
US6534859B1 (en) * | 2002-04-05 | 2003-03-18 | St. Assembly Test Services Ltd. | Semiconductor package having heat sink attached to pre-molded cavities and method for creating the package |
US20080061404A1 (en) * | 2006-09-12 | 2008-03-13 | Samsung Electronics Co.; Ltd | Electronic circuit package and fabricating method thereof |
WO2008062982A1 (en) * | 2006-11-21 | 2008-05-29 | Lg Innotek Co., Ltd | Electromagnetic shielding device, radio frequency module having the same, and method of manufacturing the radio frequency module |
US20120098109A1 (en) * | 2008-10-31 | 2012-04-26 | Dongkyun Ko | Chip package and manufacturing method thereof |
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TW201737424A (en) | 2017-10-16 |
TWI757267B (en) | 2022-03-11 |
US20170287847A1 (en) | 2017-10-05 |
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