WO2017171812A1

WO2017171812A1 - Micro light emitting diode

Info

Publication number: WO2017171812A1
Application number: PCT/US2016/025393
Authority: WO
Inventors: Peter L. Chang; Ricky J. TSENG; Ibrahim Ban; Fay Hua; Sanaz K. GARDNER
Original assignee: Intel Corporation
Priority date: 2016-03-31
Filing date: 2016-03-31
Publication date: 2017-10-05

Abstract

Methods of manufacturing, and devices including, a light emitting diode (LED). The LED includes a first electrode, a first epitaxial layer located adjacent the first electrode and having a contact surface, a second electrode, and a second epitaxial layer located adjacent the second electrode. A quantum well may be located between the first epitaxial layer and the second epitaxial layer of the LED. The quantum well may include a planar surface located adjacent the contact surface of the first epitaxial layer, and the planar surface may have a larger surface area than the contact surface of the first epitaxial layer

Description

Field

Examples of the present disclosure generally relate to the field of light emitting diodes, including micro light emitting diodes, which may be used in a display device.

Background

Light emitting diodes and/or other devices may be formed or otherwise positioned on a substrate associated with a display device. The overall size of light emitting diodes continues to decrease in response to various technologies and applications that may be associated with high resolution devices, low power displays, wearable devices, or other types of devices that may be configured with a light source. Known design and manufacturing techniques may be relatively difficult to apply to the relatively small dimensions associated with a micro light emitting diode.

A micro light emitting diode may be as small as five microns, and known processes for etching, layering, adhering, handling, manufacturing, or otherwise assembling the light emitting diodes may not produce the same results as when the processes are applied to more conventionally sized or larger light emitting diodes. In addition, as the size of the light emitting diodes decreases, the physical characteristics, performance and even flaws associated with the light emitting diodes may change or be magnified in effect. For example, known types of micro light emitting diodes may be particularly susceptible to the effects of sidewaii leakage of light or electrical current and incomplete adhesion to the display substrate.

Brief Description of the Drawings

Examples will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Apparatus, devices, systems and methods of manufacture are illustrated by way of non-exhaustive example in the figures of the accompanying drawings.

FIG, 1 illustrates an example process of fabricating LED elements. FIGS. 2A- illustrate cross-sectional and plan views of example LED elements.

FIG, 3A illustrates an example light emitting diode configured as a vertical stack.

FIG. 3B illustrates the example light emitting diode of FIG. 3A in an operational mode.

F!G. 4 illustrates a cross-sectional side view of an example light emitting diode.

FIG. S illustrates a top view of an example light emitting diode with an electrode formed as an array of contacts.

F G. 6 illustrates a top view of a further example light emitting diode with an electrode formed as an array of contacts.

FIG, 7 illustrates a cross-sectional side view of an example light emitting diode in an operational mode.

FIGS. 8A-8F graphically illustrate an example method of manufacturing a light emitting diode.

FIG, 9 illustrates an example light emitting diode.

FIG. 10 illustrates another example light emitting diode.

FIG. 11 illustrates yet another example light emitting diode.

FIGS. 12A-12E graphically illustrate an example method of assembling a display device including a light emitting diode.

FIGS. 13A-13E graphically illustrate another example method of assembling a display device including a light emitting diode.

FIGS. 14A-14C graphically illustrate an example method of assembling a display device including a light emitting diode and a reflective structure.

FIG. 16 illustrates an example display device comprising a plurality of light emitting diodes located within reflective structures.

FIG, 16 illustrates another example display device comprising a plurality of light emitting diodes located within reflective structures.

FIG. 17 illustrates an example process of manufacturing a light emitting diode.

FIG. 18 illustrates an example process of manufacturing a display device comprising a light emitting diode.

FIG, 19 illustrates an example system including a display device. Detailed Description

The present disclosure describes various configurations, systems, devices, methods of fabrication, methods of installation, and other processes and apparatus associated with light emitting diodes (LEDs). The light emitting diodes may be attached to a display panel or an integrated circuit (IC). The IC may include a plurality of devices, including transistors and the light emitting diodes, attached on a semiconductor substrate.

in the following detailed description, reference is made to the accompanying drawings which form a part hereof, wherein like numerals designate like parts throughout, and in which is shown by way of illustration examples in which the subject matter of the present disclosure may be practiced. It is to be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken as an exhaustive representation of all possible example embodiments, and the scope of examples is defined by the appended claims and their equivalents.

For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

The description may use perspective-based descriptions such as top/bottom, side, over/under, and the like. Such descriptions are merely used to facilitate the discussion and are not intended to restrict the application of examples described herein to any particular orientation.

The description may use the phrases "in an example," or "in examples," which may each refer to one or more of the same or different examples. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to examples of the present disclosure, are synonymous.

The term "coupled with," along with its derivatives, may be used herein. "Coupled" may mean one or more of the following. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term "directly coupled" may mean that two or more elements are in direct contact.

In various examples, the phrase "a first feature formed, deposited, or otheavise disposed on a second feature" may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a part of the first feature may be in direct contact (e.g. , direct physical and/or electrical contact) or indirect contact (e.g. , having one or more other features between the first feature and the second feature) with at least a part of the second feature.

As used herein, the term "circuitry" may refer to, be part of, or include an Application Specific i ntegrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality.

Disclosed herein are crystalline and/or micro LED (MLE D) display assemblies, and LED source substrates from which the LEDs may be transferred to the display assembly. In some examples, a display assembly may comprise hundreds of thousands or even millions of MLEDS. Additionally, a pLED, may have a lateral dimension on the micron scale, and in some examples the longest lateral length may be equal to or less than 5μιτι . Although described herein in the context of a few or even a single LED for the sake of clarity, the examples described herein may be understood to be applicable to the design, fabrication, assembly, or other processes associated with a large number of LEDs.

LEDs promise to offer much lower power display compared to current technologies using liquid crystal display (LCD) or organic LED (OLED). Due to high cost, the size of LEDs may need to be reduced to less than ten microns. At such small dimensions, the LEDs need to conduct current vertically between the top and the bottom electrodes (contacts on the same side consume too much area). The vertical LED could suffer from many processing problems: non-transparent top electrodes, sidewall leakage due to process damage, good electrical contact to the bottom electrode, and control of angular distribution of the emitted light

FIG, 1 illustrates an example process 101 of fabricating LED elements. At operation 1 05, an LED epitaxial substrate may be received, and at operation 1 10, a first electrode metal may be deposited over the LED film stack. At operation 1 1 5, the LED film and metal electrode stack may be coupled to a carrier, and at operation 120, the LED and metal electrode stack may be decoupled from the LED epi substrate. Operations 1 15 and 120 may comprise a wafer-level thin film transfer that allows the LED film stack to be sandwiched between two opposing metal electrodes. In some examples, operations 1 15 and 120 may be performed upstream of method 101 .

At operation 125, a second metal electrode film may be deposited over the surface of the LED film stack exposed by operation 120. The composition of the second electrode metal may vary as a function of the LED film stack, for example to provide a desired metal work function suitable for providing an ohmic contact, or a tunneling contact. In some examples, the metal deposited at operation 125 may comprise an n-type metal suitable for making contact to n-type doped semiconductor layer of an LED film stack.

At operation 130, a protective dielectric capping material may be deposited over the second metal electrode film. The capping material may be configured to protect the LED electrode metal from erosion during subsequent processing.

At operation 135, a plurality of LED elements may be formed by etching trenches into the LED semiconductor film stack. The dimensions of the mask features at operation 135 may be configured to substantially set the dimensions of the LED elements that will be incorporated into a display, in some examples, the etching operation 135 may etch through the first metal electrode film, through the second metal electrode film, and through the entire semiconductor LED film stack between the two electrodes defining sidewalis of each LED element.

At operation 140, a dielectric sidewali spacer may be formed over the LED element sidewalis, and at operation 145, LED element pressure sensitive adhesive and anchors may be patterned in preparation for a controlled release of the LED elements from the carrier. The LED element anchors may be formed within the trenches etched at operation 135, intersecting portions of the LED element sidewalis while still leaving access for a release agent to undercut the LED elements. With the presence of the dielectric spacer coating sidewalis of the LED elements, the LED anchors may be formed independent of concerns associated with encapsulation of the LED elements.

At operation 150, the anchored LED elements may be controllably released from the carrier. After release operation 150, the LED elements may remain affixed to the carrier only by the anchors formed at operation 145. In some examples, one or more LED elements may be released from the carrier by laterally etching a release layer disposed between the LED elements and the carrier.

FIGS. 2A- illustrate cross-sectional and plan views of example LED elements, such as may be illustrative of a method of fabricating crystalline LED elements for assembly in a display device. A LED source substrate may be formed from a semiconductor LED film stack. The semiconductor LED film stack may be a contiguous film covering an epitaxial substrate to form a monolithic body (e.g., an LED epi wafer).

At FIG. 2A, an epi wafer 201 may include an epitaxial substrate 205, a buffer layer 208 and a semiconductor LED film stack 207 formed on buffer layer 206. LED film stack 207 may include one or more semiconductor hetero- junctions, for example forming a quantum well, etc. Semiconductor LED film stack 207 may include at least two complementary doped semiconductor regions (layers), a p-type doped layer, and an n-type doped layer in a diodic stack architecture. Additionally, semiconductor LED film stack 207 may comprise a hetero-epitaxiai lll-N semiconductor film stack, for example comprising GaN and/or alloys thereof, such as InGaN.

Epitaxial substrate 205 may comprise silicon, germanium, SiGe, lll-V compounds like GaAs, InP, lll-N compounds like GaN, 3C-SiC, sapphire, other materials, or any combination thereof. Buffer iayer(s) 206 may be configured to transition from the composition/microstructure of epitaxial substrate 205 to that of LED film stack 207.

An electrode metal may be deposited over LED film stack 207. The composition of electrode metal may vary as a function of LED film stack 207, for example to provide a metal work function suitable for providing an ohmic contact, tunneling contact, etc. The deposited metal may comprise a p-type metal suitable for making contact to p-type doped semiconductor layer of an LED film stack. The metal may be deposited by one or more processes including PVD, CVD, electrolytic, electroless plating, other processes, or any combination thereof.

At F!G. 2B, a p-type metal film 210 may be blanket deposited over a p-type doped semiconductor layer of LED film stack 207. Additionally, a bonding/release material layer 212, such as SiOx, may be further deposited over p-type metal film 210.

The LED film and metal electrode stack may be coupled to a carrier. Additionally, the LED and metal electrode stack may be decoupled from the LED epi substrate. A wafer-level thin film transfer may be used to allow LED film stack 207 to be sandwiched between two opposing metal electrodes. The wafer-level film transfer may be omitted in examples in which the LED epi substrate already includes a metal electrode film buried below LED film stack 207.

The LED film and electrode stack may be coupled to a carrier using a (thermal) compression bonding between LED film and electrode stack to a carrier. In other examples, an electrostatic coupling may be used between the LED film and electrode stack and carrier. Additionally, the LED film and electrode stack may be decoupled from the epitaxial substrate. For example a laser liftoff or CMP/grind and clean may be utilized to remove the epitaxial substrate.

At F!G. 2C, a bonding material layer 212 (e.g., SiOx adhesive) may be bonded with a carrier 220, which may further include another bonding material layer 214 (e.g., SiOx adhesive). Alternatively, only one of bonding material 212 or 214 may be present. Carrier 220 may comprise a metal, a semiconductor, a dielectric material, other types of material, or any combination thereof. In some examples, carrier 220 may comprise a (mono) crystalline silicon substrate, for example a wafer of the type employed for IC fabrication.

At FfG. 2D, the LED film may be decoupled from the epitaxial substrate 205 (e.g., by laser liftoff) to expose a second doped semiconductor region (e.g., n-type doped layer) of LED film stack 207. A second metal electrode film may be deposited over the exposed surface of LED film stack 207.

At FUG. 2E, n-type metal film 225 may comprise a blanket deposited over an n-type doped semiconductor layer of LED film stack 207. in some examples, the metal film may be deposited with a liftoff process. A protective dielectric capping material may be deposited over the second metal electrode film to protect the LED electrode metal from erosion during subsequent processing.

At F!G, 2F, a carbon doped silicon nitride (CDN) or a silicon dioxide film 227 may be blanket deposited over the n-type metal LED electrode film 225. A plurality of LED elements may be formed by etching trenches info the LED semiconductor film stack, for example by using a photolithographic mask patterning and/or thin film etching process. The dimensions of the mask features may be configured to substantially set the dimensions of the LED elements that will be incorporated into a display,

in some examples, an etching process may comprise etching through the first metal electrode film, through the second metal electrode film, and through the entire semiconductor LED film stack between the two electrodes defining sidewails of each LED element. The footprint of the first metal electrode may be at least equal to the area occupied by the LED semiconductor film stack and second electrode (i.e., both LED electrodes have the same footprint and are coincident with the semiconductor film stack),

A dielectric sidewal! spacer may be formed (e.g., deposited) over the LED element sidewails and may comprise SiOx, SiON, SiN, CDO, CDN, other types of material, or any combination thereof. An anisotropic etch may then be performed using an anisotropic etch process to form an at least partially self-aligned sidewail coating over the metal and semiconductor sidewails of each LED element.

The dielectric spacer sidewail coatings may be configured to enable the subsequent anchoring process to be independent of LED encapsulation. Additionally, the degrees of freedom provide by the dielectric spacer sidewail coatings may further enable the anchoring force to be modulated to strengths below what might be possible if for example an anchoring material is employed also for LED encapsulation.

FIG. 2G illustrates a cross-sectional view of example crystalline LED elements 230 following a delineation process and encapsulation by a dielectric spacer. In some examples, the lateral element width We of each LED element 230 may be patterned to be no more than five micro-meters. Spacer dielectric 235 (e.g., CDN) may be configured to serve as a self-aligned sidewail dielectric coating on the LED elements 230. In examples including capping layer 227, LED elements 230 may be encapsulated on five of six sides by one or more dielectric material (e.g., CDN). Additionally, the thickness of the dielectric material utilized for spacer formation may be selected such that dielectric spacer 235 has a lateral thickness, or width Ws that is less than half the nominal lateral width Wt of the trenches 232 etched into LED film stack 207. The designated spacer width may be configured to provide that two dielectric spacers on adjacent LED elements leave a portion of substrate material (e.g. , bonding material 212) exposed at the bottom of trench 232.

FIG, 2H illustrates a top down plan view of example crystalline LED elements 230 at the same stage as FIG. 2G. Although LED elements 230 are illustrated as being rectangular (e.g. , square) in FIG. 2G, in some examples LED elements 230 may be patterned to have alternative shapes, including a circular footprint or micro-dot.

LED element anchors may be patterned in preparation for a controlled release of the LED elements from the carrier. The LED element anchors may be formed within the etched trenches, intersecting portions of the LED element sidewails while still leaving access for a release agent to undercut the LED elements. With the presence of the dielectric spacer coating sidewails of the LED elements, the LED anchors may be formed independent of the encapsulation of the LED elements.

At F!G. 21, at least a portion of one or more of bonding material layers 212, 214 may be recessed. Material layers 212, 214 may functionally comprise both bonding and release layers. In some examples, the release layer recessed as part of the LED element anchoring operation may be distinct or separate from the bonding layer.

The release layer may be recessed below dielectric spacer 235 with a blanket etch process masked by dielectric spacer 235 and capping material 227 protecting LED elements 230. An anisotropic etch through material layers 212, 214 may be configured to stop on carrier 220. Anchor material may then be deposited into the recessed trenches between adjacent LED elements 230, filling at least the recessed release layer and a portion of the trench lined by the dielectric spacer. Anchor material may be back filled into the trenches, pianarizing with a top surface of LED elements 230, for example with a spin-on process.

The planarized anchor material may then be patterned into a plurality of separate anchors. The degrees of freedom provided by the dielectric spacer sidewail coatings may enable the anchoring force to be modulated by reducing the anchor points below what might be possible if for example an anchoring material is also employed for LED encapsulation. In some examples, the anchor material may comprise a photosensitive polymeric material (e.g. , photoresist) spin-coated into the trenches.

F!G, 2J illustrates a plan view of the crystalline LED elements 230 depicted in FIG. 21. The photoresist may be lithographically patterned (i.e. , exposed and developed) into separate LED element anchors 245 filling the trench and maintaining separation between adjacent LED elements 230. The anchored LED elements may be controllably released from the carrier. After release, the LED elements may remain affixed to the carrier by the anchors. The LED elements may be released from the carrier by laterally etching a release layer disposed between the LED elements and the carrier.

FIG, 2K illustrates a cross-sectional view of an example crystalline LED bonding source substrate 250. A source LED bonding/release layers 212, 214 may be laterally etched, for example by an isotropic dry or wet chemical etchant (e.g. , HF), undercutting the plurality of crystalline LED elements 230. Anchors 245 landing on carrier 220 may then be surrounded by a free-space void 249 extending over the entire lateral area or footprint of each LED element 230. In examples where a photosensitive polymer may be employed for the anchor material, each anchor 245 may comprise a polymer pillar contacting the sidewali dielectric (spacer 235) coating at least two adjacent LED elements 230 (e.g. , four nearest LED elements 230 are connected by each anchor 245).

I n examples where a dielectric capping material is applied over the second metal LED electrode 225, this dielectric capping material may be removed to re- expose second metal LED electrode 225 in preparation for transfer of the LED elements to a display assembly. Following removal of dielectric capping material 227, a top surface of sidewali dielectric 235 may be made planar with the exposed surface of the first metal electrode 210 as well as the exposed surface of the second metal electrode 225. Depending on the selectivity of the technique employed to remove the capping material, anchors 245 may extend above the exposed surface of second metal electrode 225. Alternatively, anchors 245 may be recessed or substantially planar with the exposed surface of second metal electrode 225.

I n some examples, each LED element may be split into a plurality of LEDs. Additionally, one or more intra-element trench may be etched through the second metal electrode film and the LED semiconductor film stack of each LED element. The intra-element trench may be stopped on the first metal LED electrode so that all the LEDs within each element are electrically coupled in parallel by the first metal LED electrode. For example, the trench may be etched using two or more masking operations. In a first masking operation, the inter-element trenches may be define, and in a second masking operation the intra-element trenches may be defined. Following the trench etching operation(s), a dielectric spacer formation may be utilized to completely backfill the intra-element trenches.

FIG. 3A illustrates an example LED 300 configured as a vertical stack of layers. LED 300 may comprise a first electrode 310 and a first epitaxial layer 330 located adjacent the first electrode 310. Additionally, LED 300 may comprise a second electrode 320 and a second epitaxial layer 340 located adjacent the second electrode 320. A quantum well (QW) layer 350 may be located between the first epitaxial layer and the second epitaxial layer.

First electrode 310 may comprise a negative (N) metal electrode. Additionally, second electrode 320 may comprise a positive (P) metal electrode. Accordingly, in some examples, first epitaxial layer 330 may be referred to as an N-type or N-epi layer and second epitaxial layer 340 may be referred to as a P- type or P-epi layer.

First electrode 310 may comprise one or more types of material arranged in one or more layers. For example, first electrode 310 may comprise one or more stacked layers of N-contact metals, such as a germanium (Ge) layer and a gold (Au) layer, in some examples, a top electrode comprising two stacked layers including a Ge layer and a Au layer may be used to form a red LED. Additionally, first electrode 310 may comprise one or more layers of titanium (Ti), aluminum (Ai), and Au. In some examples, a green LED or a blue LED may be formed from a top electrode comprising four stacked layers, including a Ti layer, an Ai layer, a second Ti layer, and a Au layer.

Second electrode 320 may also comprise one or more types of material arranged in one or more layers. For example, second electrode 320 may comprise one or more stacked layers of P-contact metals, such as a Ti layer, a Au layer, and a ruthenium (Ru) layer. In some examples, a bottom electrode comprising two stacked layers including a Ti layer and a Au layer may be used to form a red LED. in other examples, a red LED may be formed from a bottom electrode comprising four stacked layers, including a Ti layer, a Au layer, a Ru layer, and a second Ti layer.

Additionally, second electrode 320 may comprise one or more layers of nickel (Ni), silver (Ag), Au, Ti, and/or Ru. In some examples, a green LED or a blue LED may be formed from a bottom electrode comprising five stacked layers, including a Ni layer, a Ag layer, a second Ni layer, a Au layer, and a Ti layer, in still other examples, a green LED or a blue LED may be formed from a bottom electrode comprising six stacked layers, including a Ni layer, a Ag layer, a second Ni layer, a Au layer, a Ru layer, and a Ti layer. The Ru layer may be used to reduce the amount of particulates, such as Au particulates, which may otherwise be produced during a dry-etch process.

The first epitaxial layer 330, or N-epi layer, may comprise one or more types of material and/or compounds. For example, first epitaxial layer 330 may comprise a gallium-based compound, such as gallium-arsenic (Ga~As), galiium- indium-phosphorus (Ga-ln-P), or gallium-nitrogen (Ga-N). Additionally, first epitaxial layer 330 may comprise a dopant, such as silicon (Si), in some examples, a red LED may be formed from an N-epi layer comprising a Ga-As compound or a Ga~in-P compound, and a green LED or blue LED may be formed from an N-epi layer comprising a Ga-N compound.

The second epitaxial layer 340, or P-epi layer, may also comprise one or more types of material and/or compounds. For example, second epitaxial layer 340 may comprise gallium-phosphorus (Ga-P), Ga-ln-P, Ga-N, or other gallium- based compounds. Additionally, second epitaxial layer 340 may comprise a dopant, such as magnesium (Mg). in some examples, a red LED may be formed from a P-epi layer comprising a Ga~P compound or a Ga-ln-P compound, and a green LED or blue LED may be formed from a P-epi layer comprising a Ga-N compound.

QW layer 350 may comprise one or more types of material and/or compounds, such as aluminum-gallium-indium-phosphorus (AI-Ga-ln-P), Ga-N, and/or indium-gallium-nitrogen (In-Ga-N). In some examples, a red LED may be formed from a QW layer comprising an AI-Ga-ln-P compound. Additionally, a green LED or a blue LED may be formed from a quantum well comprising two stacked layers including a Ga-N layer and an in-Ga-N layer. FIG. 3B illustrates the example LED 300 of FIG. 3A in an operational mode in which a current is applied between first electrode 310 and second electrode 320. The applied current may result in a biased voltage being formed between first epitaxial layer 330 and second epitaxial layer 340, causing electrons located in first epitaxial layer 330 and holes located in second epitaxial layer 340 to migrate to the QW layer 350.

The formation of an electron-hole pair may result in light being generated in the QW layer 350. Some of the light, such as a light ray 372, may exit out of a top (or front) surface 335 of LED 300, while other portions of the light, such as light ray 376, may exit out a sidewail 355 of LED 300 or be internally reflected within the LED 300, such as light ray 378. In some examples, the occurrence of non- radiative recombination at the sidewail 355 next to the QW layer 350 may degrade the power efficiency of LED 300.

Additionally, in some types of LEDs, first electrode 310 may comprise a substantially non-transparent material which may effectively block one or more rays of light, such as light ray 374, from exiting out the top surface 335 of LED 300. For example, red LEDs may be designed with non-transparent electrodes. in other types of LEDs, first electrode 310 may comprise a transparent material with a different index of refraction as compared to one or both of first epitaxial layer 330 and the QW layer 350. The index of refraction associated with first electrode 310 may cause one or more rays of light to exit the top surface 335 at an oblique angle or, in some examples, may cause the one or more rays of light to be internally reflected within the LED 300.

F!G, 4 illustrates a cross-sectional side view of an example light emitting diode 400. LED 400 may comprise a bottom electrode 420 and a first epitaxial layer 440 located adjacent the bottom electrode 420. A quantum well (QW) layer 450 may be located on first epitaxial layer 440. Additionally, a second epitaxial layer 430 may be located on the QW layer 450.

A fop electrode located on second epitaxial layer 430 may comprise an array of contacts, such as a first contact 410 and a second contact 412, interspersed with passageways, such as a passageway 415, to allow light emitted from within the QW layer 450, such as a light ray 474, to pass through the top electrode. The array of contacts may comprise p!asmonic patterns formed on second epitaxial layer 430. A transparent conductor layer 480, such as indium Tin Oxide, may be deposited over the top surface 435 to connect contacts 410 and 412 while allowing the light rays 474 to escape through the top surface 435.

In some examples, the configuration illustrated in FIG. 4 may increase the probability and/or luminance of light exiting from the top surface 435 of LED 400, as compared to LED 300 illustrated in FIGS. 3A-3B. Additionally, the luminance associated with the LED may be increased without compromising the N-side contact resistance of the LED.

FIG. 5 illustrates a top view of an example LED 500 with an electrode formed as an array of contacts, such as a first contact 510, a second contact 512, a third contact 514, and a fourth contact 518. The array of contacts may comprise a plurality of dots formed on an epitaxial layer 530 of LED 500. in some examples, the plurality of dots may comprise non-transparent dots.

The array of contacts may be designed for a specific wavelength of light being emitted from LED 500. For example, the size of and/or the spacing between contacts may be varied for different color LEDs, with relatively larger spacing provided for larger wavelengths, and with relatively smaller spacing provided for smaller wavelengths.

in some examples, the array of contacts may comprise a plurality of dots spaced apart from each other by a distance that is less than the wavelengths of the light emitted from LED 500. Additionally, the width of the dots themselves may be less than the wavelengths of the light emitted from LED 500. A region between two or more of the contacts may form a passageway 515 for light to exit LED 500. For example, passageway 515 may be approximately bounded by first contact 510, second contact 512, third contact 514, and fourth contact 516.

F G. 6 illustrates a top view of a further example LED 800 with an electrode formed as an array of contacts, such as a first contact 610, and a second contact 612. The array of contacts may comprise a plurality of gratings formed on a first epitaxial layer 630. In some examples, the gratings may be configured as a number of concentric circular shapes or rings to allow different polarization of light to get through. In some examples, the gratings may comprise non-transparent contacts.

The array of contacts may be designed for a specific wavelength of light being emitted from LED 600. For example, the size of and/or the spacing between contacts may be varied for different color LEDs. The array of contacts may comprise gratings formed on the first epitaxial layer as a number of concentric circular shapes that are spaced apart from each other by a distance that is less than the wavelengths of the light that is emitted from LED 600, Additionally, the width each individual grating may be less than the wavelengths of light emitted from LED 800.

The regions between two or more of the contacts may form a plurality of passageways for light to exit LED 800. For example, an annular passageway 815 may be approximately bounded by first contact 810 and second contact 812.

F!G. 7 illustrates a cross-sectional side view of an example LED 700 in an operational mode. In addition to a top electrode comprising an array of contacts, such as a first contact 710 and a second contact 712, a reflective sidewall 755 is illustrated as being formed adjacent to an edge of a QW layer 750 of LED 700. Reflective sidewall 755 may be configured to reflect light 772 emitted from within the QW layer 750.

Reflective sidewall 755 may comprise a self-aligned bilayer of dielectric insulating material and a metal sidewall formed about both the QW layer 750 and a lower epitaxial layer 740 formed on a bottom electrode 720 of LED 700. The dielectric layer in contact with layers 720, 740, and 750 may be configured to insulate the metal sidewall from these layers, hence avoid shorting through them. In some examples, the reflective sidewall 755 may be formed adjacent each of the lower epitaxial layer 740, the QW layer 750, and an upper epitaxial layer 730 on which the top electrode is formed.

Reflective sidewall 755 may be configured to control an angular distribution of light emitted from within the QW layer 750, so that a light ray 772 may be reflected through a passageway 715 located between first contact 710 and second contact 712. in some examples, reflective sidewall 755 may not be connected to bottom electrode 720. Reflective sidewall 755 may be formed from a different material or materials than bottom electrode 720. Additionally, reflective sidewall 755 may be configured to form a conducting path to the display substrate, as described at FIGS. 1 and 2.

A sidewall wet etch process used to remove etch defects on the sidewall of LED 700 can form a current injection area in the center of the device instead of sidewall. Reflective sidewall 755 may be configured to reflect light emitted sideways or towards bottom electrode 720, and thereby increase the overall amount or intensity of light that exits from a top surface 735 of LED 700. The array of contacts, including first contact 710 and second contact 712, and reflective side vall 755 may be co-optimized for displaying a particular viewing angle and/or light output associated with a display device,

FIGS. 8A-8F graphically illustrate an example method of manufacturing an

LED 800. At FIG. 8A, a first epitaxial layer 840 may be formed on a bottom electrode 820, and a quantum well (QW) layer 850 may be formed on first epitaxial layer 840. In some examples, the QW layer 850 may comprise a first planar surface 851 in contact with first epitaxial layer 840.

A second epitaxial layer 830 may be formed on the QW layer 850.

Second epitaxial layer 830 may comprise a contact surface 835 formed adjacent to a second planar surface 852 of the QW layer 850. Additionally, a top electrode 810 may be formed on second epitaxial layer 830. in some examples, a hard mask 880 may be formed around and/or over top electrode 810.

At F!G. 8B, second epitaxial layer 830 may be etched or otherwise modified to reduce a surface area of contact surface 835. For example, an N-epi etch of second epitaxial layer 830 may be performed with hard mask 880, followed by a selective wet etch to stop on the QW layer 850. By selectively etching second epitaxial layer 830 from the hard mask layer 880 towards the QW layer 850, the second planar surface 852 of the QW layer 850 may comprise a larger surface area than the contact surface 835 of second epitaxial layer 830. The reduction in surface area of contact surface 835 may be determined, at least in part, by a width of hard mask 880.

At FIG, 8C, a spacer 890 comprising an exterior surface 895 may be formed on the second planar surface 852 of the QW layer 850. Spacer 890 may extend from hard mask 880 to second planar surface 852. Additionally, spacer 890 may be located adjacent one or both of second epitaxial layer 830 and hard mask 880.

At FIG. 8D, the QW layer 850 may be etched, modified, and/or reduced in size until an outer edge of the QW layer 850 aligns with the exterior surface 895 of spacer 890, One or both of first epitaxial layer 840 and bottom electrode 820 may be etched, modified, and/or reduced in size to align with the exterior surface 895 of spacer 890. in some examples, a wet etch/clean process may be used to remove sidewail artifacts and/or surface irregularities that may have resulted from

- 18 - a dry etch. Additionally the etch/clean process may be followed by sidewall passivation and encapsulation of LED 800.

At FUG. 8E, the hard mask and at least a portion of spacer 890 may be removed to expose top electrode 810. In some examples, an interconnect may be formed on the exposed surface of top electrode 810.

At FIG. 8F, a reflective sidewall 805 may be formed adjacent to one or both of the QW layer 850 and first epitaxial layer 840. in some examples, reflective sidewall 805 may be formed after spacer 890 (FIG. 8E) has been removed, in other examples, reflective sidewall 805 may be formed adjacent spacer 890. Reflective sidewall 805 may be configured to reflect light emitted from within the QW layer 850 during operation of LED 800. Reflective sidewall 805 may comprise a self-aligned metal mirror that is deposited on the sidewall of LED 800 to control angular distribution of light.

F!G. 9 illustrates an example LED 900 comprising a first electrode 910 located adjacent a first epitaxial layer 930. A second electrode; 920 may be located adjacent a second epitaxial layer 940. Additionally, a QW layer 950 may be located between first epitaxial layer 930 and second epitaxial layer 940.

First epitaxial layer 930 may comprise a contact surface 935. The QW layer 950 may comprise a first planar surface 952 located adjacent the contact surface 935 of first epitaxial layer 930. First planar surface 952 may comprise a larger surface area than the contact surface 935 of first epitaxial layer 930.

The QW layer 950 may comprise an edge 954. First epitaxial layer 930 may be selectively etched away from the edge 954 of the QW layer 950. A biased voltage may be applied between first epitaxial layer 930 and second epitaxial layer 940 via the first and second electrodes 910, 920. The applied voltage may result in a plurality of electrons, such as electron 932, to migrate from first epitaxial layer 930 to the QW layer 950. Similarly a plurality of electron holes, such hole 942, may migrate from second epitaxial layer 940 to form an electron-hole pair in the QW layer 950. The formation of electron-hole pair may result in light being emitted from LED 900.

First epitaxial layer 930 may be approximately centrally located on first planar surface 952, such that a perimeter 934 of first epitaxial layer 930 forms a boundary region 905 that is laterally offset from the edge 954 of the QW layer 950. Electron holes vertically aligned with boundary region 905, such as hole 944, may not have a corresponding electron with which to create an electron-hole pair. The electron and hole injections that result from the applied voltage may be centrally concentrated in the QW layer 950 away from the exposed surfaces of region 905 and a sidewali 955 of the QW layer 950.

The boundary region 905 may form an exposed surface area of first planar surface 952 that operates to reduce an amount of non-radiative recombination from occurring within the QW layer 950. Additionally, the reduced surface area of first planar surface 952 may also increase the current density within the QW layer 950. For example, the configuration of LED 950 illustrated in FIG. 9 may increase the current density from 0.1 Amp per square centimeter (A/cm²) to approximately 0.5 A/cm² for a 2 μητι wide epitaxial layer located on top of a 5 pm wide QW layer (e.g. , approximately 4μηι² area vs 25 μνη² area).

in some examples, first electrode 910 may comprise an array of contacts formed on first epitaxial layer 930 and interspersed with passageways to allow light emitted from within the QW layer 950 to pass through first electrode 910 (e.g. , as shown in FIGS. 4-7).

FIG, 10 illustrates another example LED 1 000 in which a contact surface 1032 of a first epitaxial layer 1 030 located adjacent a top electrode 1010 may be less than a first planar surface 1052 of an adjacent QW layer 1050. Additionally, a second epitaxial layer 1040 may comprises a contact surface 1042 located adjacent a second planar surface 1054 of the QW layer 1050. The second planar surface 1 054 may comprise a larger surface area than the contact surface 1042 of the second epitaxial layer 1040,

One or both of second epitaxial layer 1040 and a bottom electrode 1020 may be etched or otherwise reduced in size such that a sidewali 1045 of second epitaxial layer 1040 may be substantially vertically aligned with, and/or approximately the same width as, a sidewali 1035 of first epitaxial layer 1030.

FIG. 11 illustrates yet another example LED 1 100, in which a contact surface 1 145 of a first epitaxial layer 1 130 located adjacent a bottom electrode 1 120 may be less than a planar surface 1 154 of an adjacent QW layer 1 150.

First epitaxial layer 1 140 may be selectively etched away from the edge of the QW layer 1 150. A biased voltage may be applied between first epitaxial layer 1 140 and a second epitaxial layer 1 120 via bottom electrode 1 120 and a top electrode 1 1 10. The applied voltage may result in a plurality of electrons, such as electron 1 132, to migrate from second epitaxial layer 1 130 to the QW layer 1 150, Similarly a plurality of electron holes, such as hole 1 142, may migrate from first epitaxial layer 1 140 to form an electron-hole pair in the QW layer 1 150. The formation of electron-hole pair may result in light being emitted from LED 1 100.

First epitaxial layer 1 140 may be approximately centrally located on planar surface 1 154, such that a perimeter of first epitaxial layer 1 140 may form a boundary region that is laterally offset from the edge of the QW layer 1 150. Electrons vertically aligned with the boundary region, such as electron 1 134, may not have a corresponding hole or electron carrier with which to create an electron- hole pair. The electron and hole injections that result from the applied voltage may be centrally concentrated in the QW layer 1 150 away from the exposed surfaces of LED 1 100, including the sidewail 1 155 of the QW layer 1 150. The exposed surface area of planar surface 1 154 may be configured to reduce an amount of non-radiative recombination from occurring within the QW layer 1 150.

The sidewail profiles shown in FIGS. 10 and 1 1 may be configured to provide a similar effect as the example LED 900 illustrated in FIG. 9, in avoiding sidewail damages and/or increasing conducting current density. After surface passivation, one or more of the sidewalis illustrated in any of FIGS. 9-1 1 may be encapsulated.

F!GS. 12A-12E graphically illustrate an example method of assembling a display device 1200 including an LED 1230. At FIG. 12A, a first substrate 1260 may be formed on a panel 1275. Additionally, a second substrate 1250 may be formed on first substrate 1260.

An LED 1230 may be transferred to panel 1275 by a pressure sensitive adhesive (PSA) 1240. In some examples, panel 1275 may comprise a bonding pad including one or both of first substrate 1260 and second substrate 1250. in some examples, first substrate 1260 may be configured to substantially operate as an interconnect layer that interconnects LED 1230 to second substrate 1250, and second substrate 1250 may be configured to substantially operate as a bonding pad for panel 1275. Additionally, the bonding pad may comprise a solder, an non-conductive adhesive, a conducting adhesive, other types of bonding material, or any combination thereof. Αΐ F!G. 12B, LED 1230 may be bonded onto the second substrate 1250. In some examples, first substrate 1260 and/or second substrate 1250 may be heated to create a solder joint that bonds LED 1230 to pane! 1275. First substrate 1260 may comprise a gold-based alloy, and second substrate 1250 may comprise an indium-based alloy. Additionally, the bottom electrode of LED 1230 may comprise a gold-based alloy. The substrate heating may create an indium-gold solder joint between LED 1230 and one or both of first substrate 1260 and second substrate 1250.

in conducting bonding using solder materials such as gold-tin (Au-Sn) or copper-tin (Cu-Sn), temperatures of 250 degrees Celsius or more may be required to form the solder joint. These temperatures may affect the alignment accuracy during the bonding process. For indium-gold (In-Au) solder bonding, heating the bottom substrate may result in interdiffusion of the indium (In) and gold (Au) materials, which can lead to a higher melting temperature. Still other types and/or materials associated with bonding may have issues related to joint reliability, solder uniformity and thickness, adhesion and bonding strength, or any combination thereof.

in and Au may be deposited on different substrates and only form the solder upon contact, in some examples, electrode 1220 on LED 1230 may comprise a nickel-gold (Ni-Au) alloy, and second substrate 1250 may comprise a copper-nickel-indium (Cu-Ni-ln) alloy. At approximately 190 degrees Celsius, an In to Au joint may be formed upon contact and, in some examples, may be annealed in an oven as part of the solder formation. The In-Au joint may provide a relatively strong bond, such that tacky pressure sensitive adhesive (PSA) may be used for pickup and transfer of LED 1230.

Post-bonding, the PSA 1240 (FIG. 12A) may be cleaned off with one or more processes comprising a wet chemistry, a thermal desorption, an oxygen plasma, or other types of removal.

At FIG. 12C, a reflective surface 1280 may be formed next to LED 1230 post-removal of a pressure sensitive adhesive. Reflective surface 1280 may be formed by deposition of a metal and directional plasma etch on a sidewa!l 1235 of LED 1230. In some examples, a masking operation followed by a wet etch may be used to form reflective surface 1280. Reflective surface 1280 may comprise a metal associated with high reflectivity at a particular wavelength. Different color LEDs may comprise reflective surfaces comprising different metai(s). in some examples, reflective surface 1280 may comprise Al, Au, Ag, Ni, other types of metals, or any combination thereof.

Additionally, reflective surface 1280 may comprise a self-aligned metal sidewail or mirror that may be configured to control the angular distribution of light emitted from LED 1230 and/or facilitate the formation of a conducting path to the display 1275,

At FIG, 12D, a planarization layer 1290 may be patterned to open up one or more contacts of LED 1230. Planarization layer 1290 may comprise a dielectric material such as oxide or a polymer, and may be deposited or spun on to LED 1230. in some examples, Planarization layer 1290 may comprise a photo- definable polymer which is transparent in the visible range, and thermally-stable up to 250 degrees Celsius. A first electrode 1210 and/or a top surface 1232 of LED 1230 may be exposed by etching an insulator 1215 (FIG. 12C) located on top of LED 1230, using planarization layer 1290 as a mask.

At FIG. 12E, following the contact opening illustrated in FIG. 12D, one or more interconnects 1270 and metal pads 1272, 1274 may be formed to connect LED 1230 with a transistor and/or other electronic devices mounted to or otherwise electrically coupled to panel 1275. Interconnects 1270 may be formed adjacent to, or in contact with, one or both of the top surface 1232 of LED 1230 and first electrode 1210.

in some examples, display device 1200 may comprise a plurality of transistors mounted to panel 1275, and a processing device configured to control a plurality of light emitting diodes, such as LED 1230, electrically connected to one or more of the plurality of transistors.

Additionally, display device 1200 may comprise first substrate 1260 formed on panel 1275, and second substrate 1250 formed on first substrate 1260. A interface between first substrate 1260 and second substrate 1250 may form an adhesive surface, and LED 1230 may be attached to panel 1275 by the adhesive surface.

In some examples, LED 1230 may comprise first electrode 1210, a first epitaxial layer located adjacent first electrode 1210, a second electrode 1220, and a second epitaxial layer located adjacent second electrode 1220. A quantum well (QW) layer may be located between the first epitaxial layer and the second epitaxial layer. In some examples, the QW layer may comprise a planar surface located adjacent the contact surface of the first epitaxial layer, and the planar surface may comprise a larger surface area than the contact surface of the first epitaxial layer.

First electrode 1210 may comprise an array of contacts interspersed with passageways to allow light emitted from within the QW layer of LED 1230 to pass through first electrode 1210. Additionally, display device 1200 may comprise one or more reflective surfaces 1280 formed adjacent to the sidewali 1235 of LED 1230 and configured to reflect light emitted from within the QW layer. In some examples, the sidewali 1235 of LED 1230 may comprise a spacer, an insulator, a passivation layer, or any combination thereof.

Display device 1200 may comprise an Au thin film deposited on a micro LED to form selective solder bonding. Additionally, eiectroless Cu plating may be applied post adhesive bonding for contacting second electrode 1220. For example, an eiectroless plating of In/Ni may be applied, in some examples, conducting adhesive may be used to form conducting bonding at low temperatures. Separation of in and Au from the same substrate prior to bonding may be used to avoid In-Au interdiffusion prior to bonding.

FIGS. 13A-13E graphically illustrate another example method of assembling a display device 1300 including an LED 1330. When a non- conductive adhesive is used, an electrical connection between a bottom electrode 1320 of LED 1330 and a panel substrate anode contact may be formed.

At FIG, 13A, a first substrate 1360 may be formed on a panel 1375, and a second substrate 1350 may be formed on first substrate 1360. LED 1330 may be transferred onto second substrate 1350. In some examples, at least a portion of second substrate 1350 may be undercut to expose a portion 1325 of bottom electrode 1320. Additionally, a spacer 1335 may be formed prior to an etch process, such that the sidewali of bottom electrode 1320 may also be exposed.

At FIG. 13B, a resist pattern 1305 may be formed about LED 1330.

At FIG, 13C, the resist pattern 1305 of FIG. 13B may be used to form an eiectroless plating material 1380 coupled to the exposed portion of bottom electrode 1320. In some examples, the eiectroless plating of metals such as Cu may be applied to make the connection after the resist patterning illustrated in FIG. 13B. The resist pattern 1305 may then be removed, in other examples, the electroiess plating process may be applied without resist. Rather, eiectroless plating materia! 1380 may be selectively applied on certain metal surfaces of LED 1330 and/or panel 1375.

The connection between bottom electrode 1320 and an anode may be formed through eiectroless plating material 1380. in some examples, eiectroless plating material 1380 may be used to join the substrate metal lines with bottom electrode 1320 post bonding.

At FIG. 13D, a dielectric 1390 may be deposited on LED 1330 and/or panel 1375 before the formation of a reflective surface 1380 (FIG. 13E). in some examples, dielectric 1390 may be configured to provide an etch-stop layer during metal etch.

FIGS. 14A-14C graphically illustrate an example method of assembling a display device 1400 including an LED 1430 and a reflective structure 1425. For example, display device 1400 may be configured with an external mirror to focus light that may otherwise escape from the sidewails of LED 1430.

At FIG, 14A, a housing 1410 may be formed on a substrate 1460 of a panel 1475. in some examples, housing 1410 may comprise a photo-definable polymer exposed with a grayscale-capable lithography system, or housing 1410 may be formed by using a gray scale mask in a binary litho-machine. Housing 1410 may be formed with a concave surface 1415.

At FIG. 14B, a reflective material 1420 may be deposited on the concave surface of housing 1410 to form reflective structure 1425. For example, a metal coating may be deposited by a sputter process, an evaporation process, or other type of process to provide a reflective surface or concave mirror.

At FIG. 14C, LED 1430 may be attached to panel 1475 by one or more substrates 1450, 1460 such that LED 1430 may be centrally located within reflective structure 1425. The height 1422 of the reflective structure 1425 may be approximately the same as the height 1432 of LED 1430. In some examples, the height 1422 of the reflective structure 1425 may be approximately equal to the height of 1432 of LED 1430. in some examples, LED 1430 may be bonded on the substrate 1450 prior to the formation of housing 1410. The curved surface 1415 and reflective structure 1425 may be formed as described above Display device 1400 may comprise reflective structure 1425 formed on or otherwise located on the panel 1475 with LED 1430 attached to the display device at an approximate central location within reflective structure 1425. A concave surface of reflective structure 1425 may be configured to reflect light emitted from the LED 1430 in a direction which is substantially perpendicular to panel 1475.

F!G. 15 illustrates an example display device 1500 comprising a plurality of light emitting diodes, such as an LED 1510, located within reflective structures, such as a reflective structure 1520. The plurality of LEDs may be substantially aligned as a number of parallel columns and/or rows. In some examples, an internally located LED 1550 may have four nearest neighboring LEDs that are approximately equally spaced apart from LED 1550.

FIG, 16 illustrates another example display device comprising a plurality of light emitting diodes, such as an LED 1810, located within reflective structures, such as a reflective structure 1620. The plurality of LEDs may be substantially aligned as a number of offset rows and/or offset columns, in some examples, an internally located LED 1650 may have six nearest neighboring LEDs approximately equally spaced from LED 1650.

FIG. 17 illustrates an example process 1700 of manufacturing a light emitting diode. At operation 1710, a first epitaxial layer may be formed on a substrate.

At operation 1715, a QW layer may be formed on the first epitaxial layer, wherein the QW layer comprises a first planar surface in contact with the first epitaxial layer;

At operation 1720, a second epitaxial layer may be formed on the QW layer. The second epitaxial layer may comprise a contact surface formed adjacent to a second planar surface of the QW layer.

At operation 1725, a first electrode metal may be deposited over the second epitaxial layer, and at operation 1730, the LED film and metal electrode stack may be coupled to a carrier.

At operation 1735, the LED and metal electrode stack may be decoupled from the LED substrate of operation 1710. Operations 1730 and 1735 may comprise a wafer-level thin film transfer that allows the LED film stack to be sandwiched between two opposing metal electrodes. At operation 1740, a second metal electrode film may be deposited over the surface of the first LED epitaxial layer in 1710 exposed by operation 1735, and at operation 1745, a protective dielectric capping material may be deposited over the second metal electrode film for subsequent epitaxial etch.

In some examples, operations 1725, 1730, 1735, 1740 and 1745 may be understood as corresponding to operations 1 10, 1 15, 120, 125 and 130, respectively, as described with reference to FIG. 1 .

At operation 1750, the second epitaxial layer may be etched to reduce a surface area of the contact surface so that the second planar surface of the QW layer comprises a larger surface area than the contact surface of the second epitaxial layer.

At operation 1755, a top electrode may be formed on the second epitaxial layer. Additionally, a hard mask may be formed around the top electrode. The second epitaxial layer may be selectively etched from the hard mask towards the QW layer, and the reduction in surface area of the contact surface may be determined, at least in part, by a width of the hard mask.

In some examples, a spacer may be formed that extends from the hard mask to the second planar surface of the QW layer. The spacer may comprise an exterior surface. The QW layer may be etched until an outer edge of the QW layer aligns with the exterior surface of the spacer. Additionally, the hard mask and at least a portion of the spacer may be removed to expose the top electrode, and an interconnect may be formed on the top electrode.

At operation 1760, a reflective sidewali may be formed adjacent to both the QW layer and the first epitaxial layer. The reflective sidewali may be configured to reflect light emitted from within the QW layer during operation of the light emitting diode.

in some examples, a concave housing may be formed on a substrate, and a reflective material may be deposited on the concave housing. A light emitting diode may be attached to the substrate so that the light emitting diode is centrally located within the concave housing, in some examples, the height of the concave housing may be approximately the same height as the light emitting diode.

Additionally, process 1700 may comprise forming a first substrate on a panel, forming a second substrate on the first substrate, and transferring the light emitting diode onto the second substrate. One or both of the first substrate and the second substrate may be heated to create a solder joint that bonds the light emitting diode to the panel.

The first substrate may comprise a gold-based alloy, and the second substrate may comprise an indium-based alloy. The bottom electrode of LED may comprise a gold-based alloy. Heating the first substrate and the second substrate may create an indium-gold solder joint between the LED and one or both of the first substrate and the second substrate.

in still other examples, process 1700 may comprise forming a first substrate on a panel, forming a second substrate on the first substrate, transferring the light emitting diode onto the second substrate, undercutting the second substrate to expose a portion of the bottom electrode, and applying an eiecfroless plating to the exposed portion of the bottom electrode.

FIG, 18 illustrates an example process 1800 of manufacturing a display device comprising a light emitting diode. At operation 1810, a first substrate may be formed on the display panel.

At operation 1820, a second substrate may be formed on the first substrate.

At operation 1830, a light emitting diode may be transferred onto the second substrate.

At operation 1840, the LED may be bonded to the display device. In some examples, the first substrate and the second substrate may be heated to create a solder joint that bonds the light emitting diode to the panel. For example, the first substrate may comprise a gold-based alloy, and the second substrate may comprise an indium-based alloy. Heating the first substrate and the second substrate may create an indium-gold solder joint.

in some examples, the first substrate may comprise a nickel-gold alloy, and the second substrate may comprise a copper-nickel-indium alloy. The bottom electrode of LED may comprise a gold-based alloy. A solder joint may be created by heating the LED, the first substrate and the second substrate to less than 200 degrees Celsius, for example approximately 190 degrees Celsius.

Alternatively, in other examples, an adhesive layer may be used to bond the LED to the panel, in which case at operation 1850 the second substrate may be undercut to expose the bottom electrode.

- 28 - At operation 1860, a reflective sidewali may be formed around the light emitting diode. Additionally, an insulator located on top of the light emitting diode may be etched through to expose at least a portion of the top electrode, and one or more interconnects may be formed from the top electrode to the display panel.

FIG. 19 illustrates an example system 1900 including a display device

1910. The display device 1910 may comprise a plurality of light emitting diodes electrically coupled with a processing device and one or more electronic devices, such as those described herein.

Components of system 1900 may be housed in an enclosure 1908 (e.g., housing) and a motherboard 1902. The motherboard 1902 may include a number of components, including but not limited to a processor 1904 and at least one communication chip 1908. The processor 1904 may be physically and electrically coupled to the motherboard 2002. in some examples, the at least one communication chip 1906 may also be physically and electrically coupled to the motherboard 1902. in further examples, the communication chip 1906 may be part of the processor 1904.

Depending on its applications, system 1900 may include other components that may or may not be physically and electrically coupled to the motherboard 1902. These other components may include, but are not limited to, volatile memory (e.g., DRA ), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a heads-up display device, a display controller, and input device, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an acceierometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 1906 may enable wireless communications for the transfer of data to and from the system 1900. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some examples they might not. The communication chip 1906 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.1 1 family), IEEE 802.16 standards (e.g., I EEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible broadband wireless access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards.

The communication chip 1906 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1906 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1906 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 1906 may operate in accordance with other wireless protocols in other examples.

System 1900 may include a plurality of communication chips 1906. For instance, a first communication chip 1906 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1906 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others.

The processor 1904 may include a die mounted in a package assembly that may be mounted on a circuit board such as the motherboard 1902. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The display 1910 may comprise a plurality of light emitting diodes, and the processor 1904 may be configured to operate the plurality of light emitting diodes.

In various implementations, the system 1900 may comprise or otherwise be electrically coupled with a mobile computing device, a head-up display, a virtual reality headset, virtual reality glasses, a projection device, a three-dimensional display device, wearable devices such as smart glasses and a smart watch, a laptop, a netbook, a notebook, an uitrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder, in further implementations, system 1900 may be any other electronic device that processes data.

Various examples may include any suitable combination of the above- described examples including alternative (or) examples of examples that are described in conjunctive form (and) above (e.g., the "and" may be "and/or"). Furthermore, some examples may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions, stored thereon, that when executed result in actions of any of the above-described examples. Moreover, some examples may include apparatuses or systems having any suitable means for carrying out the various operations of the above- described examples.

The above description of illustrated implementations, including what is described in the Abstract, is not intended to be exhaustive or to limit the examples of the present disclosure to the precise forms disclosed. While specific implementations and examples are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as those skilled in the relevant art will recognize.

These modifications may be made to examples of the present disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit various examples of the present disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. Example 1 is a light emitting diode comprising: a first electrode; a first epitaxial layer located adjacent the first electrode and comprising a contact surface; a second electrode; a second epitaxial layer located adjacent the second electrode; and a quantum well (QW) layer located between the first epitaxial layer and the second epitaxial layer, wherein the QW layer comprises a planar surface located adjacent the contact surface of the first epitaxial layer, and wherein the planar surface comprises a larger surface area than the contact surface of the first epitaxial layer.

Example 2 is the light emitting diode of example 1 , wherein the QW layer comprises an edge, wherein the first epitaxial layer is approximately centrally located on the planar surface, and wherein a perimeter of the first epitaxial layer forms a boundary region that is laterally offset from the edge.

Example 3 is the light emitting diode of example 2, wherein the boundary region forms an exposed surface area of the planar surface to reduce an amount of non-radiative recombination from occurring within the QW layer.

Example 4 is the light emitting diode of example 1 , further comprising a reflective sidewail formed adjacent to the edge of the QW layer and configured to reflect light emitted from within the QW layer.

Example 5 is the light emitting diode of example 4, wherein the reflective sidewail comprises a self-aligned dielectric insulating layer and metal sidewail formed about both the QW layer and the second epitaxial layer.

Example 8 is the light emitting diode of example 1 , wherein the second epitaxial layer comprises a contact surface, and wherein the QW layer further comprises a second planar surface located adjacent the contact surface of the second epitaxial layer.

Example 7 is the light emitting diode of example 6, wherein the second planar surface comprises a larger surface area than the contact surface of the second epitaxial layer.

Example 8 is the light emitting diode of example 1 , wherein the first electrode comprises an array of contacts formed on the first epitaxial layer and interspersed with passageways to aiiow iight emitted from within the QW layer to pass through the first electrode.

Example 9 is the light emitting diode of example 8, wherein the array of contacts comprises a plurality of dots spaced apart from each other by a distance that is less than wavelengths of Iight emitted from the iight emitting diode.

Example 10 is the Iight emitting diode of example 8, wherein the array of contacts comprises gratings formed on the first epitaxial layer as a number of concentric circular shapes that are spaced apart from each other by a distance that is less than wavelengths of Iight emitted from the iight emitting diode.

Example 1 1 is a method of fabricating a Iight emitting diode, comprising: forming a first epitaxial layer on a bottom electrode; forming a quantum well (QW) layer on the first epitaxial layer, wherein the QW layer comprises a first planar surface in contact with the first epitaxial layer; forming a second epitaxial layer on the QW layer, wherein the second epitaxial layer comprises a contact surface formed adjacent to a second planar surface of the QW layer; and etching the second epitaxial layer to reduce a surface area of the contact surface so that the second planar surface of the QW layer comprises a larger surface area than the contact surface of the second epitaxial layer.

Example 12 is the method of example 1 1 , further comprising: forming a top electrode on the second epitaxial layer; and forming a hard mask around the top electrode, wherein etching the second epitaxial layer comprises selectively etching the second epitaxial layer from the hard mask towards the QW layer, and wherein the reduction in surface area of the contact surface is determined, at least in part, by a width of the hard mask.

Example 13 is the method of example 12, further comprising: forming a spacer that extends from the hard mask to the second planar surface of the QW layer, wherein the spacer comprises an exterior surface; and etching the QW layer until an outer edge of the QW layer aligns with the exterior surface of the spacer.

Example 14 is the method of example 13, further comprising: removing the hard mask and at least a portion of the spacer to expose the top electrode; and forming an interconnect on the top electrode.

Example 15 is the method of any one of examples 1 1 to 14, further comprising forming a reflective sidewall adjacent to both the QW layer and the first epitaxial layer, wherein the reflective sidewali is configured to reflect light emitted from within the QW Iayer during operation of the light emitting diode.

Example 16 is the method of any one of claims 1 1 to 14, further comprising: forming a concave housing on a substrate; depositing a reflective material on the concave housing; and attaching the light emitting diode to the substrate so that the light emitting diode is centrally located within the concave housing.

Example 17 is the method of example 16, wherein a height of the concave housing is approximately the same height as the light emitting diode.

Example 18 is the method of any one of examples 1 1 to 14, further comprising: forming a first substrate on a panel; forming a second substrate on the first substrate; transferring the light emitting diode onto the second substrate; and heating the first substrate and the second substrate to create a solder joint that bonds the light emitting diode to the panel.

Example 19 is the method of example 18, wherein the first substrate comprises a gold-based alloy, wherein the second substrate comprises an indium- based alloy, wherein a bottom electrode of the light emitting diode comprises a gold-based alloy, and wherein heating the first substrate and the second substrate creates an indium-gold solder joint between the light emitting diode and the first and second substrates.

Example 20 is the method of any one of examples 1 1 to 14, further comprising: forming a first substrate on a panel; forming a second substrate on the first substrate; transferring the light emitting diode onto the second substrate; undercutting the second substrate to expose a portion of the bottom electrode; and applying an eiectroless plating to the exposed portion of the bottom electrode.

Example 21 is a light emitting diode comprising: a bottom electrode; a first epitaxial Iayer located adjacent the bottom electrode; a quantum well (QW) iayer located on the first epitaxial Iayer; a second epitaxial iayer located on the QW Iayer; and a top electrode located on the second epitaxial layer, wherein the top electrode comprises an array of contacts interspersed with passageways to allow light emitted from within the QW iayer to pass through the top electrode.

Example 22 is the light emitting diode of example 21 , wherein the array of contacts comprises a plurality of non-transparent dots formed on the first epitaxial Iayer. Example 23 is the light emitting diode of example 21 , wherein the array of contacts comprises gratings formed on the first epitaxial layer as a number of concentric circular shapes.

Example 24 is the light emitting diode of any one of examples 21 to 23, further comprising a reflective sidewail formed adjacent to an edge of the QW layer and configured to reflect light emitted from within the QW layer.

Example 25 is the light emitting diode of example 24, wherein the reflective sidewail comprises a self-aligned metal sidewail formed about both the QW layer and the first epitaxial layer.

Example 26 is the light emitting diode of example 24, wherein the reflective sidewail controls an angular distribution of the light emitted from within the QW layer so that the light is reflected through the passageways of the top electrode.

Example 27 is the light emitting diode of any one of examples 21 to 23, wherein: the bottom electrode comprises a titanium layer and a gold layer; the first epitaxial layer comprises a gallium-based compound with a silicon dopant; the QW layer comprises a gallium-based compound; the second epitaxial layer comprises a gallium-based compound with a magnesium dopant; and the top electrode comprises a gold layer.

Example 28 is the light emitting diode of example 27, wherein the bottom electrode further comprises a ruthenium layer.

Example 29 is a method of fabricating an array of light emitting diodes on a display panel, the method comprising: forming a first substrate on the display panel; forming a second substrate on the first substrate; transferring a light emitting diode onto the second substrate; and heating the first substrate and the second substrate to create a solder joint that bonds the light emitting diode to the panel.

Example 30 is the method of example 29, wherein the first substrate comprises a gold-based alloy, wherein the second substrate comprises an indium- based alloy, wherein a bottom electrode of the light emitting diode comprises a gold-based alloy, and wherein heating the first substrate and the second substrate creates an indium-gold solder joint between the light emitting diode and the first and second substrates.

Example 31 is the method of example 29, wherein the first substrate comprises a nickel-gold alloy, wherein the second substrate comprises a copper- nickel-indium alloy, and wherein the solder joint is created by heating the first substrate and the second substrate to less than 200 degrees Celsius.

Example 32 is the method of any one of examples 29 to 31 , further comprising: forming a reflective sidewail around the light emitting diode; etching through an insulator located on top of the light emitting diode to expose at least a portion of the top electrode; and forming an interconnect from the top electrode to the display panel.

Example 33 is a display device, comprising: a display panel; a plurality of transistors mounted to the display panel; a processing device configured to control a plurality of light emitting diodes electrically connected to one or more of the plurality of transistors; a first substrate formed on the display panel; a second substrate formed on the first substrate, wherein an interface between the first substrate and the second substrate forms an adhesive surface; and a light emitting diode attached to the display panel by the adhesive surface.

Example 34 is the display device of example 33, wherein the light emitting diode comprises: a first electrode; a first epitaxial layer located adjacent the first electrode and comprising a contact surface; a second electrode; a second epitaxial layer located adjacent the second electrode; and a quantum well (QW) layer located between the first epitaxial layer and the second epitaxial layer, wherein the QW layer comprises a planar surface located adjacent the contact surface of the first epitaxial layer, and wherein the planar surface comprises a larger surface area than the contact surface of the first epitaxial layer.

Example 35 is the display device of example 34, wherein the first electrode comprises an array of contacts interspersed with passageways to allow light emitted from within the QW layer to pass through the first electrode.

Example 36 is the display device of example 34 or example 35, further comprising a reflective sidewail formed adjacent to the edge of the QW layer and configured to reflect light emitted from within the QW layer.

Example 37 is the display device of example 34 or example 35, further comprising a concave housing mounted to the display panel, wherein the light emitting diode is attached to the display device at an approximate central location within the concave housing, and wherein the concave housing includes a reflective surface configured to reflect light emitted from the light emitting diode in a direction which is substantially perpendicular to the display panel.

Claims

Claims What is claimed is:

1 . A light emitting diode comprising:

a first electrode;

a first epitaxial layer located adjacent the first electrode and comprising a contact surface;

a second electrode;

a second epitaxial layer located adjacent the second electrode; and a quantum well (QW) layer located between the first epitaxial layer and the second epitaxial layer, wherein the QW layer comprises a planar surface located adjacent the contact surface of the first epitaxial layer, and wherein the planar surface comprises a larger surface area than the contact surface of the first epitaxial layer.

2. The light emitting diode of claim 1 , wherein the QW layer comprises an edge, wherein the first epitaxial layer is approximately centrally located on the planar surface, and wherein a perimeter of the first epitaxial layer forms a boundary region that is laterally offset from the edge.

3. The light emitting diode of claim 2, wherein the boundary region forms an exposed surface area of the planar surface to reduce an amount of non- radiative recombination from occurring within the QW layer.

4. The light emitting diode of claim 1 , further comprising a reflective sidewail formed adjacent to the edge of the QW layer and configured to reflect light emitted from within the QW layer.

5. The light emitting diode of claim 4, wherein the reflective sidewail comprises a self-aligned dielectric insulating layer and metal sidewail formed about both the QW layer and the second epitaxial layer.

6. The light emitting diode of claim 1 , wherein the second epitaxial layer comprises a contact surface, and wherein the QW layer further comprises a second planar surface located adjacent the contact surface of the second epitaxial layer.

7. The light emitting diode of claim 6, wherein the second planar surface comprises a larger surface area than the contact surface of the second epitaxial layer.

8. The light emitting diode of claim 1 , wherein the first electrode comprises an array of contacts formed on the first epitaxial layer and interspersed with passageways to allow light emitted from within the QW layer to pass through the first electrode.

9. The light emitting diode of claim 8, wherein the array of contacts comprises a plurality of dots spaced apart from each other by a distance that is less than wavelengths of light emitted from the light emitting diode.

10. The light emitting diode of claim 8, wherein the array of contacts comprises gratings formed on the first epitaxial layer as a number of concentric circular shapes that are spaced apart from each other by a distance that is less than wavelengths of light emitted from the light emitting diode.

1 1 . A method of fabricating a light emitting diode, comprising:

forming a first epitaxial layer on a bottom electrode;

forming a quantum well (QW) layer on the first epitaxial layer, wherein the QW layer comprises a first planar surface in contact with the first epitaxial layer; forming a second epitaxial layer on the QW layer, wherein the second epitaxial layer comprises a contact surface formed adjacent to a second planar surface of the QW layer; and

etching the second epitaxial layer to reduce a surface area of the contact surface so that the second planar surface of the QW layer comprises a larger surface area than the contact surface of the second epitaxial layer.

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12. The method of claim 1 1 , further comprising:

forming a top electrode on the second epitaxial layer; and

forming a hard mask around the top electrode, wherein etching the second epitaxial layer comprises selectively etching the second epitaxial layer from the hard mask towards the QW layer, and wherein the reduction in surface area of the contact surface is determined, at least in part, by a width of the hard mask.

13. The method of claim 12, further comprising:

forming a spacer that extends from the hard mask to the second planar surface of the QW layer, wherein the spacer comprises an exterior surface; and etching the QW layer until an outer edge of the QW layer aligns with the exterior surface of the spacer.

14. The method of claim 13, further comprising:

removing the hard mask and at least a portion of the spacer to expose the top electrode; and

forming an interconnect on the top electrode.

15. The method of any one of claims 1 1 to 14, further comprising forming a reflective sidewall adjacent to both the QW layer and the first epitaxial layer, wherein the reflective sidewall is configured to reflect light emitted from within the QW layer during operation of the light emitting diode.

16. The method of any one of claims 1 1 to 14, further comprising:

forming a concave housing on a substrate;

depositing a reflective material on the concave housing; and

attaching the light emitting diode to the substrate so that the light emitting diode is centrally located within the concave housing.

17. The method of claim 18, wherein a height of the concave housing is approximately the same height as the light emitting diode.

18. The method of any one of claims 1 1 to 14, further comprising:

forming a first substrate on a panel; forming a second substrate on the first substrate;

transferring the light emitting diode onto the second substrate; and heating the first substrate and the second substrate to create a solder joint that bonds the light emitting diode to the panel,

19. The method of claim 18, wherein the first substrate comprises a gold-based alloy, wherein the second substrate comprises an indium-based alloy, wherein a bottom electrode of the light emitting diode comprises a gold-based alloy, and wherein heating the first substrate and the second substrate creates an indium-gold solder joint between the light emitting diode and the first and second substrates.

20. The method of any one of claims 1 1 to 14, further comprising:

forming a first substrate on a panel;

forming a second substrate on the first substrate;

transferring the light emitting diode onto the second substrate;

undercutting the second substrate to expose a portion of the bottom electrode; and

applying an electroiess plating to the exposed portion of the bottom electrode.

21 . A light emitting diode comprising:

a bottom electrode;

a first epitaxial layer located adjacent the bottom electrode;

a quantum well (QW) layer located on the first epitaxial layer;

a second epitaxial layer located on the QW layer; and

a top electrode located on the second epitaxial layer, wherein the top electrode comprises an array of contacts interspersed with passageways to allow light emitted from within the QW layer to pass through the fop electrode.

22. The light emitting diode of claim 21 , wherein the array of contacts comprises a plurality of non-transparent dots formed on the first epitaxial layer.

23. The light emitting diode of claim 21 , wherein the array of contacts comprises gratings formed on the first epitaxial layer as a number of concentric circular shapes,

24. The light emitting diode of any one of claims 21 to 23, further comprising a reflective sidewail formed adjacent to an edge of the QW layer and configured to reflect light emitted from within the QW layer, wherein the reflective sidewail controls an angular distribution of the light emitted from within the QW layer so that the light is reflected through the passageways of the top electrode.

25. The light emitting diode of any one of claims 21 to 23, wherein:

the bottom electrode comprises a titanium layer and a gold layer;

the first epitaxial layer comprises a gallium-based compound with a silicon dopant;

the QW layer comprises a gallium-based compound;

the second epitaxial layer comprises a gallium-based compound with a magnesium dopant; and

the top electrode comprises a gold layer.