WO2017167923A1 - Semiconductor on insulator substrate for rf applications - Google Patents

Semiconductor on insulator substrate for rf applications Download PDF

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Publication number
WO2017167923A1
WO2017167923A1 PCT/EP2017/057614 EP2017057614W WO2017167923A1 WO 2017167923 A1 WO2017167923 A1 WO 2017167923A1 EP 2017057614 W EP2017057614 W EP 2017057614W WO 2017167923 A1 WO2017167923 A1 WO 2017167923A1
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Prior art keywords
layer
semiconductor
substrate
penetration
insulator substrate
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PCT/EP2017/057614
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French (fr)
Inventor
Arnaud Castex
Oleg Kononchuk
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Soitec SA
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Soitec SA
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Priority to CN201780026817.8A priority Critical patent/CN109075120B/en
Priority to US16/090,349 priority patent/US10886162B2/en
Priority to KR1020187030528A priority patent/KR102172705B1/en
Priority to DE112017001617.7T priority patent/DE112017001617T5/en
Priority to JP2018550442A priority patent/JP6657516B2/en
Publication of WO2017167923A1 publication Critical patent/WO2017167923A1/en
Anticipated expiration legal-status Critical
Priority to US17/090,608 priority patent/US11626319B2/en
Priority to US18/192,016 priority patent/US12616005B2/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3204—Materials thereof being Group IVA semiconducting materials
    • H10P14/3211—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3238—Materials thereof being insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3242—Structure
    • H10P14/3244—Layer structure
    • H10P14/3251—Layer structure consisting of three or more layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1922—Preparing SOI wafers using silicon etch back techniques, e.g. BESOI or ELTRAN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Definitions

  • the invention relates to a semiconductor on insulator substrate for use in RF applications, in particular a silicon on insulator substrate, comprising a semiconductor top layer, a buried oxide layer and a passivation layer over a silicon support substrate and a corresponding method.
  • the invention also relates to an RF device.
  • Known substrates for radio frequency (RF) applications comprise a trilayer structure of silicon Si on silicon dioxide Si02 in turn on a polycrystalline Si layer. This trilayer structure is provided on a bulk high resistivity support substrate with a low interstitial oxygen content ("low Oi").
  • the interstitial oxygen content is in a range between 5-10 ppma instead of 20-25 ppma for standard Oi or 25-30 ppma for high Oi substrates.
  • High resistivity in this context typically relates to resistivity values of 3000 ⁇ or more. This high bulk resistivity is needed in RF devices so as to limit or suppress parasitic signals coming from all material below the active device, also called the substrate losses.
  • the polycrystalline Si layer is needed to suppress further parasitic losses which can occur due to surface charges which exist at the interface between the support substrate and the silicon dioxide layer under the influence of an electrical field.
  • This polycrystalline Si layer acts as a passivation layer and can therefore reduce signal losses.
  • Interstitial oxygen is known to give thermal donors following thermal treatments and therefore decreases the bulk resistivity of the support substrate and thereby increasing substrate losses, thus the need of a low Oi substrate.
  • the use of low Oi is, however, not without drawbacks.
  • a low Oi content makes silicon more sensitive to dislocation migration. Oxygen interstitial atoms tend to attach to silicon atoms and aggregates into Si0 2 small precipitate that prevents dislocation to migrate into the crystal lattices. With low Oi content there are less Si0 2 precipitates present in the material leading to increased dislocation migration upon thermal treatment during manufacturing of the semiconductor on insulator substrate and/or the RF devices leading to an unwanted modification of the crystal structure and the appearance of so called sliplines. The dislocation migration can also lead to plastic deformation of the substrate which during CMOS processing can lead to overlay problems during lithography.
  • a semiconductor on insulator substrate in particular a silicon on insulator substrate, comprising a semiconductor top layer, a buried oxide layer and a passivation layer over a silicon support substrate characterized in that a penetration layer is provided between the passivation layer and the silicon support substrate wherein the penetration layer is a higher resistive silicon layer with lower interstitial oxygen content than the silicon support substrate.
  • the invention is not limited to a semiconductor top layer but can be applied to other types of materials of the top layer as for instance piezoelectric materials, in particular Lithium Tantalate or Lithium Niobate.
  • a specific layer the penetration layer with a low Oi content is introduced so that a support substrate can be used in which the slipline and overlay problem can be reduced by lowering the ability of dislocations to migrate within the support substrate.
  • the low Oi content is just needed to a certain depth, starting from the Silicon layer, depending on how far an RF signal of an RF device that will be prepared on the substrate will penetrate into the Semiconductor on Insulator substrate.
  • the passivation layer and the penetration layer can be of the same material. In this case negative impacts of lattice mismatch at the interface can be reduced or even suppressed.
  • the passivation layer can be a polycrystalline layer and the penetration layer can be a monocrystalline material.
  • the polycrystalline layer acts as a trap for charges and allows a reduction of parasitic losses, whereas the monocrystalline layer has the advantage that layers with low surface roughness can be obtained independently of the thickness of the layer.
  • the penetration layer can be a polycrystalline layer.
  • the polycrystalline layer is provided with a sufficient thickness to fulfill both roles, the reduction of surface related parasitic losses and the substrate losses.
  • low interstitial oxygen content can relate to a concentration of less than 15 ppma, in particular 5 to 10 ppma. In this concentration range the desired resistivity level can be reached in the passivation layer to reduce the substrate losses.
  • high resistive can relate to a resistivity of 2000 ⁇ or more, in particular 3000 fim or more, and this even after thermal treatments of duration of at least 1 hour at temperatures higher than 450°C.
  • the passivation layer and the penetration layer have a combined thickness of about 3 ⁇ to 30 ⁇ " ⁇ , in particular 4 ⁇ to ⁇ ⁇ , even more in particular about ⁇ .
  • the prior art semiconductor on insulator substrates with low Oi silicon support substrates having a thickness of typically 725 ⁇ " ⁇ only a thin part of the semiconductor on insulator substrate will be subject to migration of dislocations in low Oi regions.
  • the lithography steps of subsequent device manufacturing can be simplified.
  • the object of the invention is also achieved with a Radio Frequency (RF) device.
  • the inventive RF device comprises electrically isolated device structures, in particular conductive lines within a device might be electrically isolated to each other, having a minimal distance d between each other provided on and/or in a semiconductor on insulator substrate as described above and is characterized in that the thickness of buried oxide layer, the passivation layer, and the penetration layer together is such that RF signals at most penetrate into the penetration layer.
  • the thickness of the buried oxide layer, the passivation layer, and the penetration layer together can be such that it does not exceed ten times, in particular 5 times, the distance d.
  • the object of the invention is also achieved with the method for fabricating a semiconductor on insulator substrate as described above, wherein the penetration layer is epitaxially grown on the support substrate and the semiconductor top layer and the buried oxide layer are transferred onto the passivation layer by a layer transfer process, in particular comprising a bonding method.
  • a layer transfer process in particular comprising a bonding method.
  • both the passivation and the penetration layer are epitaxially grown.
  • the object is further achieved with an alternative method for fabricating a semiconductor on insulator substrate as described above, wherein the penetration layer is transferred onto the support substrate by layer transfer method, in particular a bonding method.
  • a Smart CutTM type process comprising the steps of forming a predetermined splitting area inside the 01 substrate, bonding the 01 substrate to the support substrate and detaching the remainder of the 01 substrate, e.g. by a thermal treatment, to obtain the penetration layer on the support substrate.
  • the object of the invention is also achieved with a method for fabricating a Radio Frequency device as described above and comprising the steps of: providing a plurality of
  • Figure 1 illustrates a first embodiment of the semiconductor on insulator substrate according to the invention
  • Figure 2 illustrates a second embodiment of the semiconductor on insulator substrate according to the invention
  • Figure 3 illustrates a third embodiment of the invention, namely an RF device on a semiconductor on insulator substrate according to the invention
  • Figure 4 illustrates a fourth embodiment of the invention, namely a method to fabricate a semiconductor on insulator substrate according to the invention
  • Figure 5 illustrates a fifth embodiment of the invention, namely an alternative method to fabricate a semiconductor on insulator substrate according to the invention
  • Figure 6 illustrates a sixth embodiment of the invention, namely a method to choose the thickness of the penetration layer of a semiconductor on insulator substrate according to the invention.
  • Figure 1 illustrates schematically a semiconductor on insulator substrate (Sol substrate) 1 according to a first embodiment of the invention.
  • the Sol substrate 1 according to this embodiment is for use as a starting material of the manufacture of radio frequency (RF) devices, e.g. used in communication devices, like mobile phones, smartphones, tablets or personal computers.
  • RF radio frequency
  • the invention is not limited to a semiconductor top layer but can be applied to other types of materials of the top layer as for instance piezoelectric materials, in particular Lithium Tantalate or Lithium Niobate.
  • piezoelectric materials in particular Lithium Tantalate or Lithium Niobate.
  • a semiconductor top layer which may in a general way be a top layer comprising semiconductor material or a piezoelectric material.
  • a Sol type substrate comprising a piezoelectric top layer would also be in the scope of the invention.
  • the Sol substrate 1 comprises a Silicon support substrate 3, a penetration layer 5, a passivation layer 7, a buried oxide layer 9 and a semiconductor top layer 1 1.
  • the Silicon support substrate 3 is a standard silicon (Si) substrate or Si Wafer, with a standard resistivity of 15 ⁇ , an interstitial oxygen content of about 20 to 25 ppma and a thickness of the order of 700 to 750 ⁇ " ⁇ .
  • the buried oxide layer 7, also called box layer, in this embodiment is a silicon dioxide (Si02) layer with a typical thickness of 100 to 1000nm.
  • the semiconductor layer in this embodiment is a silicon layer with a thickness of about 50nm to 200nm.
  • the penetration layer 5 in this embodiment is a Silicon layer with a high resistivity layer, with a resistivity value of 2000 ⁇ or more, in particular a layer of 3000 ⁇ or more, and a low interstitial oxygen content relates to a concentration of interstitial oxygen of less than 15ppma, in particular 5 to 10ppma.
  • a resistivity value is maintained even after a thermal treatment of at least 1 hour at a temperature higher than 450°C.
  • the penetration layer 5 thus has a higher resistivity and lower interstitial oxygen content than the Silicon support substrate 3.
  • the penetration layer 5 in this embodiment is monocrystalline layer.
  • the passivation layer 7 in this embodiment is a polycrystalline Si layer with a typical thickness of about 200 to 2500nm.
  • the Sol substrate is of particular interest for RF applications.
  • One problem associated with RF devices is the occurrence of signal losses.
  • the passivation layer 7 and the penetration layer 5 are introduced in the Sol substrate structure to reduce the losses.
  • Parasitic losses occur when a signal passes through a signal line of a RF device present in or on the Si layer.
  • Parasitic signals pass via the buried oxide layer into the Si substrate and can reach other signal lines of the RF device. The corresponding losses are called substrate losses.
  • the penetration layer 5 is high resistance layer of low Oi content thus with a much higher resistance than a standard normal Oi Si substrate. Due to the high resistance, the losses can be reduced.
  • the layers together have a combined thickness of at least 3 ⁇ and at most 30 ⁇ " ⁇ , in particular at most ⁇ ⁇ , more in particular at most ⁇ .
  • FIG. 2 illustrates schematically a semiconductor on insulator substrate (Sol substrate) 13 according to a second embodiment of the invention.
  • Sol substrate 14 of the second embodiment the passivation layer and the penetration layer are made of the same material, namely Silicon and are of the same crystalline structure, namely polycrystalline.
  • they are forming one modified passivation layer 15 with a thickness that goes far beyond the thickness of passivation layers in the prior art.
  • FIG 3 schematically illustrates a radio frequency (RF) device 17 according to a third embodiment of the invention.
  • the RF device 17 is arranged on or in the Sol substrate 1 , in particular in the Si layer 1 1 as illustrated in Figure 1.
  • Features of the third embodiment which are the same as in the first and second embodiment carry the same reference numeral and it is referred to their description above.
  • the Sol substrate 13 as illustrated in Figure 2 could be used.
  • the RF device 17 comprises a plurality of electrically isolated device structures 19a, 19b, 19c with a minimal distance d between two structures, here 19a, 19b.
  • parasitic signals 21 pass through the Sol substrate. According to the invention, their impact is reduced by the penetration layer 5 and the passivation layer 7 as explained in detail above with respect to the first and second embodiment.
  • the thickness d' is chosen such that it does not exceed ten times, in particular five times, the distance d of the RF device 17.
  • the RF parasitic signals 21 can only reach the penetration layer 5 with its higher resistivity and do not pass via the better conducting Si support substrate 3.
  • Step a) consists in providing a standard Si substrate 3 with normal interstitial oxygen content (Oi) of about 20 to 25ppma. This type of substrate is commonly used in the semiconductor industry.
  • step b) first a monocrystalline Si layer, the penetration layer 5 is homoepitaxially grown on the Si support substrate 3. The growth conditions are chosen such that a lower Oi content of 5 to ppma oxygen concentration is achieved. Thus, a higher resistivity of at least 2000 ⁇ or more, in particular 3000 ⁇ , can be obtained compared to the Si support substrate 3 is obtained in the epitaxial layer.
  • the growth conditions are changed to then obtain a polycrystalline layer corresponding to the passivation layer 7.
  • the thickness d" of the two layers 5 and 7 is determined according to the parameters described above with respect to the embodiments 1 to 3 to achieve the thickness d' of the layers 5, 7 and 9.
  • step b) could be replaced by step b') during which the modified passivation layer 15, fulfilling the role of both the penetration layer 5 and the passivation layer 7 at the same time, is grown as a polycrystalline layer directly onto the Si support substrate 3.
  • Step c) consist in preparing a donor substrate 23 comprising a Si donor substrate 25 with a Silicon dioxide layer 27 and a predetermined splitting area 29 in the Si donor substrate 25, e.g. achieved by ion implantation as known in the art.
  • the donor substrate 23 is attached, e.g. by bonding, via the surface of the Silicon dioxide layer 27 to the surface of the passivation layer 7 in the first alternative or to the modified passivation layer 15 in the second alternative.
  • a detachment treatment e.g. a thermal treatment, is carried out to achieve a detachment at the predetermined splitting area 29 to thereby transfer a Si layer 31 of the Si donor substrate 23 and the Silicon dioxide layer 27 onto the passivation layer 7 in the first alternative or to the modified passivation layer 15 in the second alternative.
  • Layer 27 thus corresponds to the buried oxide layer 9 and layer 31 to the semiconductor top layer of the first and second embodiment.
  • Figure 5 illustrates a fifth embodiment of the invention, namely an alternative method to fabricate a semiconductor on insulator substrate according to the invention.
  • the method illustrated in Figure 5 is suitable to fabricate a Sol substrate 1 according to the first embodiment.
  • Features of the fifth embodiment which are the same as in the first embodiment and the method according to the fourth embodiment carry the same reference numeral and it is referred to their description above.
  • Step a) consists in providing a standard Si support substrate 3, e.g. a Si wafer, thus with normal interstitial oxygen content and normal resistivity and in providing a low interstitial oxygen content Si substrate 33, e.g. a low Oi Si wafer, having an Oi content of 5 to 10 ppma and a resistivity of more than 2000 ⁇ , in particular more than 3000 ⁇ .
  • Step b) consists in attaching, e.g. by bonding, Si support substrate 3 to the low Oi Si substrate 33.
  • step c) the low Oi Si substrate 33 is etched back to obtain a penetration layer 5 of the desired thickness as described above.
  • Step d) then consists in growing the polycrystalline Si passivation layer 7 over the penetration layer 5, typically with a thickness of 200 to 2500nm.
  • the etch back of step c) can be used to obtain a modified passivation layer fulfilling the role of the passivation layer 7 and the penetration layer 5 at the same time.
  • step d) is then not realized.
  • Step e) consist in preparing a donor substrate 23 comprising a Si donor substrate 25 with a Silicon dioxide layer 27 and a predetermined splitting area 29 in the Si donor substrate 25, e.g. achieved by ion implantation as known in the art.
  • the donor substrate 23 is attached, e.g. by bonding, via the surface of the Silicon dioxide layer 27 to the surface of the passivation layer 7.
  • a detachment treatment e.g. a thermal treatment, is carried out to obtain a detachment at the predetermined splitting area 29 to thereby transfer a Si layer 31 of the Si donor substrate 23 and the Silicon dioxide layer 27 onto the passivation layer 7.
  • Layer 27 thus corresponds to the buried oxide layer 9 and layer 31 to the semiconductor top layer 1 1 of the first.
  • a Sol substrate 1 according to the first embodiment is thus obtained.
  • Figure 6 illustrates a sixth embodiment of the invention, namely a method to choose the thickness of the penetration layer of a semiconductor on insulator substrate according to the invention. The choice depends on the RF devices to be fabricated on or in the Sol substrate 1 , 13 according to the invention.
  • the reference numerals used in the following relate to the features as already described above and carrying the same reference numeral.
  • the first step a) consists in providing a plurality of semiconductor on insulator substrates 1 with different thicknesses of the penetration layer 5.
  • the thicknesses are chosen such that the overall of thickness of the buried oxide layer 9, the passivation layer 7 and the penetration layer 5 together remains in a range between about 3 ⁇ up to about 30 ⁇ " ⁇ .
  • radio frequency devices like RF device 17, are formed on or in the semiconductor insulator substrates 1 , 13.
  • the same RF devices 17 using the same fabrication process will be manufactured.
  • the penetration depth of parasitic RF signals is determined, by determining the parasitic signal in neighboring RF device structures, e.g. 19a or 19c in case the reference single passes via structure 19b.
  • the attenuation of the parasitic signal can also be determined.
  • the semiconductor on insulator substrate 1 or 13 with the thickness of the penetration layer 5 (or the modified passivation layer 15) for which the parasitic RF signal penetrates at most into the penetration layer 5 (or the modified passivation layer 15) is chosen.
  • the one with the thinnest penetration layer 5 (or the thinnest modified passivation layer 15) is the one with optimized thickness parameters.
  • the semiconductor layer 1 1 was made of silicon and the buried oxide layer of Si02. According to further variants other suitable materials, like SiGe or GaAs, can also be used. Instead of polycrystalline Si other charge trapping layers could also be used for the passivation layer 7.

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  • Formation Of Insulating Films (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

The invention relates to a semiconductor on insulator substrate (1) for use in RF applications, in particular a silicon on insulator substrate, comprising a semiconductor top layer (11), a buried oxide layer (9) and a passivation layer (7) over a silicon support substrate (3) and a corresponding method. The invention also relates to an RF device (17). In addition a penetration layer (5) is introduced between the passivation layer (7) and the silicon support substrate (3) to ensure sufficient high resistivity of underneath RF features while dislocation movements in the support substrate (3) can be kept low.

Description

Semiconductor on insulator substrate for RF applications
The invention relates to a semiconductor on insulator substrate for use in RF applications, in particular a silicon on insulator substrate, comprising a semiconductor top layer, a buried oxide layer and a passivation layer over a silicon support substrate and a corresponding method. The invention also relates to an RF device. Known substrates for radio frequency (RF) applications comprise a trilayer structure of silicon Si on silicon dioxide Si02 in turn on a polycrystalline Si layer. This trilayer structure is provided on a bulk high resistivity support substrate with a low interstitial oxygen content ("low Oi"). For such a substrate the interstitial oxygen content is in a range between 5-10 ppma instead of 20-25 ppma for standard Oi or 25-30 ppma for high Oi substrates. High resistivity in this context typically relates to resistivity values of 3000ΩΓΤΙ or more. This high bulk resistivity is needed in RF devices so as to limit or suppress parasitic signals coming from all material below the active device, also called the substrate losses.
The polycrystalline Si layer is needed to suppress further parasitic losses which can occur due to surface charges which exist at the interface between the support substrate and the silicon dioxide layer under the influence of an electrical field. This polycrystalline Si layer acts as a passivation layer and can therefore reduce signal losses.
Interstitial oxygen is known to give thermal donors following thermal treatments and therefore decreases the bulk resistivity of the support substrate and thereby increasing substrate losses, thus the need of a low Oi substrate. The use of low Oi is, however, not without drawbacks.
A low Oi content makes silicon more sensitive to dislocation migration. Oxygen interstitial atoms tend to attach to silicon atoms and aggregates into Si02 small precipitate that prevents dislocation to migrate into the crystal lattices. With low Oi content there are less Si02 precipitates present in the material leading to increased dislocation migration upon thermal treatment during manufacturing of the semiconductor on insulator substrate and/or the RF devices leading to an unwanted modification of the crystal structure and the appearance of so called sliplines. The dislocation migration can also lead to plastic deformation of the substrate which during CMOS processing can lead to overlay problems during lithography.
It is therefore an object of the present invention to provide an improved semiconductor on insulator substrate suitable for RF applications that overcomes or at least reduces the problems identified before
This object is achieved with a semiconductor on insulator substrate according to the invention, in particular a silicon on insulator substrate, comprising a semiconductor top layer, a buried oxide layer and a passivation layer over a silicon support substrate characterized in that a penetration layer is provided between the passivation layer and the silicon support substrate wherein the penetration layer is a higher resistive silicon layer with lower interstitial oxygen content than the silicon support substrate.
The invention is not limited to a semiconductor top layer but can be applied to other types of materials of the top layer as for instance piezoelectric materials, in particular Lithium Tantalate or Lithium Niobate. According to the invention a specific layer, the penetration layer with a low Oi content is introduced so that a support substrate can be used in which the slipline and overlay problem can be reduced by lowering the ability of dislocations to migrate within the support substrate. Indeed, the low Oi content is just needed to a certain depth, starting from the Silicon layer, depending on how far an RF signal of an RF device that will be prepared on the substrate will penetrate into the Semiconductor on Insulator substrate.
According to an embodiment, the passivation layer and the penetration layer can be of the same material. In this case negative impacts of lattice mismatch at the interface can be reduced or even suppressed.
According to an embodiment, the passivation layer can be a polycrystalline layer and the penetration layer can be a monocrystalline material. The polycrystalline layer acts as a trap for charges and allows a reduction of parasitic losses, whereas the monocrystalline layer has the advantage that layers with low surface roughness can be obtained independently of the thickness of the layer.
According to a variant, the penetration layer can be a polycrystalline layer. In this case the polycrystalline layer is provided with a sufficient thickness to fulfill both roles, the reduction of surface related parasitic losses and the substrate losses. According to an embodiment of the invention, low interstitial oxygen content can relate to a concentration of less than 15 ppma, in particular 5 to 10 ppma. In this concentration range the desired resistivity level can be reached in the passivation layer to reduce the substrate losses. Further, the term high resistive can relate to a resistivity of 2000ΩΓΤΙ or more, in particular 3000 fim or more, and this even after thermal treatments of duration of at least 1 hour at temperatures higher than 450°C. It shall be understood that other impurities which normally influence the electrical behavior of silicon, also known as donors and acceptors, have a concentration less than 1 x1012 cm-3, to obtain the relationship between interstitial oxygen content and the resistivity level. According to an embodiment, the passivation layer and the penetration layer have a combined thickness of about 3μηι to 30μη"ΐ, in particular 4μηι to Ι Ομηη, even more in particular about δμηη. Compared to the prior art semiconductor on insulator substrates with low Oi silicon support substrates having a thickness of typically 725μη"ΐ, only a thin part of the semiconductor on insulator substrate will be subject to migration of dislocations in low Oi regions. Thus the lithography steps of subsequent device manufacturing can be simplified.
The object of the invention is also achieved with a Radio Frequency (RF) device. The inventive RF device comprises electrically isolated device structures, in particular conductive lines within a device might be electrically isolated to each other, having a minimal distance d between each other provided on and/or in a semiconductor on insulator substrate as described above and is characterized in that the thickness of buried oxide layer, the passivation layer, and the penetration layer together is such that RF signals at most penetrate into the penetration layer. Thus by adjusting the thickness of the penetration layer to the particular dimension d of the RF design, substrate losses can be reduced while manufacturability, in particular with respect to overlay during lithography, can be kept high. According to an embodiment of the invention, the thickness of the buried oxide layer, the passivation layer, and the penetration layer together can be such that it does not exceed ten times, in particular 5 times, the distance d.
The object of the invention is also achieved with the method for fabricating a semiconductor on insulator substrate as described above, wherein the penetration layer is epitaxially grown on the support substrate and the semiconductor top layer and the buried oxide layer are transferred onto the passivation layer by a layer transfer process, in particular comprising a bonding method. Preferably, both the passivation and the penetration layer are epitaxially grown. The object is further achieved with an alternative method for fabricating a semiconductor on insulator substrate as described above, wherein the penetration layer is transferred onto the support substrate by layer transfer method, in particular a bonding method. This could for instance be achieved by bonding the support substrate and low 01 substrate and then etching back the Oi substrate to the desired thickness or by applying a Smart Cut™ type process comprising the steps of forming a predetermined splitting area inside the 01 substrate, bonding the 01 substrate to the support substrate and detaching the remainder of the 01 substrate, e.g. by a thermal treatment, to obtain the penetration layer on the support substrate. With the above mentioned methods, the advantageous substrates can be obtained.
The object of the invention is also achieved with a method for fabricating a Radio Frequency device as described above and comprising the steps of: providing a plurality of
semiconductor on insulator substrates with different thicknesses of the penetration layer, forming radio frequency devices on or in the semiconductor insulator substrates, determining the penetration depth of RF signals in the plurality of semiconductor on insulator substrates, choosing the semiconductor on insulator substrate with the thickness of the penetration layer for which the RF signal penetrates at most into the penetration layer. In this way an optimized penetration layer thickness can be determined so that manufacturability is optimized while keeping the RF devices working. Additional benefits and advantages of the disclosed embodiments will become apparent from the specification and drawings. The benefits and/or advantages may be individually obtained by the various embodiments and features of the specification and drawings, which need not all be provided in order to obtain one or more of such benefits and/or advantages.
The above and other objects and features of the present invention will become more apparent from the following description and preferred embodiments given in conjunction with the accompanying drawings in which:
Figure 1 illustrates a first embodiment of the semiconductor on insulator substrate according to the invention,
Figure 2 illustrates a second embodiment of the semiconductor on insulator substrate according to the invention,
Figure 3 illustrates a third embodiment of the invention, namely an RF device on a semiconductor on insulator substrate according to the invention, Figure 4 illustrates a fourth embodiment of the invention, namely a method to fabricate a semiconductor on insulator substrate according to the invention,
Figure 5 illustrates a fifth embodiment of the invention, namely an alternative method to fabricate a semiconductor on insulator substrate according to the invention, Figure 6 illustrates a sixth embodiment of the invention, namely a method to choose the thickness of the penetration layer of a semiconductor on insulator substrate according to the invention.
Figure 1 illustrates schematically a semiconductor on insulator substrate (Sol substrate) 1 according to a first embodiment of the invention. The Sol substrate 1 according to this embodiment is for use as a starting material of the manufacture of radio frequency (RF) devices, e.g. used in communication devices, like mobile phones, smartphones, tablets or personal computers.
As already stated above, the invention is not limited to a semiconductor top layer but can be applied to other types of materials of the top layer as for instance piezoelectric materials, in particular Lithium Tantalate or Lithium Niobate. Such a generalization holds for all embodiments as described in the following with respect to a semiconductor top layer which may in a general way be a top layer comprising semiconductor material or a piezoelectric material. Thus a Sol type substrate comprising a piezoelectric top layer would also be in the scope of the invention. The Sol substrate 1 comprises a Silicon support substrate 3, a penetration layer 5, a passivation layer 7, a buried oxide layer 9 and a semiconductor top layer 1 1.
The Silicon support substrate 3 is a standard silicon (Si) substrate or Si Wafer, with a standard resistivity of 15 ΩΓΤΙ, an interstitial oxygen content of about 20 to 25 ppma and a thickness of the order of 700 to 750μη"ΐ. The buried oxide layer 7, also called box layer, in this embodiment is a silicon dioxide (Si02) layer with a typical thickness of 100 to 1000nm. The semiconductor layer in this embodiment is a silicon layer with a thickness of about 50nm to 200nm.
Sandwiched between the Si substrate 3 and the buried oxide layer 9 are the penetration layer 5 and the passivation layer 7. In this embodiment the penetration layer 5 in this embodiment is a Silicon layer with a high resistivity layer, with a resistivity value of 2000ΩΓΤΙ or more, in particular a layer of 3000ΩΓΤΙ or more, and a low interstitial oxygen content relates to a concentration of interstitial oxygen of less than 15ppma, in particular 5 to 10ppma. As already mentioned above such resistivity value is maintained even after a thermal treatment of at least 1 hour at a temperature higher than 450°C. According to the invention the penetration layer 5 thus has a higher resistivity and lower interstitial oxygen content than the Silicon support substrate 3. The penetration layer 5 in this embodiment is monocrystalline layer.
The passivation layer 7 in this embodiment is a polycrystalline Si layer with a typical thickness of about 200 to 2500nm.
The Sol substrate is of particular interest for RF applications. One problem associated with RF devices is the occurrence of signal losses. The passivation layer 7 and the penetration layer 5 are introduced in the Sol substrate structure to reduce the losses. Parasitic losses occur when a signal passes through a signal line of a RF device present in or on the Si layer. Parasitic signals pass via the buried oxide layer into the Si substrate and can reach other signal lines of the RF device. The corresponding losses are called substrate losses.
To reduce the losses the penetration layer 5 is high resistance layer of low Oi content thus with a much higher resistance than a standard normal Oi Si substrate. Due to the high resistance, the losses can be reduced.
Further, losses which might occur due to surface charges accumulating at the surface of the penetration layer 5 are reduced by the presence of the polycrystalline passivation layer 7 hindering the contribution of such surface charges to electrical conduction and thus reducing surface charge related signal losses.
By combining a low Oi penetration layer 5 together with a standard Si substrate 3 with normal Oi concentration instead of using a low Oi Si substrate only like in the prior art, it becomes possible to reduce the occurrence of unwanted slip lines and dislocation migration having a negative impact on the production yield. The thickness of buried oxide layer 9, the passivation layer 7 and the penetration layer 5 are thereby chosen such, that the parasitic signals arising from the signal running through a RF design reach at most into the penetration layer 5 and thus do not "see" the lower resistance in the standard Si support substrate 3. As a consequence the layers together have a combined thickness of at least 3μηι and at most 30μη"ΐ, in particular at most Ι Ομηη, more in particular at most δμηη.
At the same time a standard Si substrate 3 can be used which allows RF device manufactures to use standard CMOS fabrication methods. Figure 2 illustrates schematically a semiconductor on insulator substrate (Sol substrate) 13 according to a second embodiment of the invention. Features of the second embodiment which are the same as in the first embodiment carry the same reference numeral and it is referred to their description above. The difference between the second and the first embodiment is that in the Sol substrate 14 of the second embodiment the passivation layer and the penetration layer are made of the same material, namely Silicon and are of the same crystalline structure, namely polycrystalline. Thus they are forming one modified passivation layer 15 with a thickness that goes far beyond the thickness of passivation layers in the prior art. Figure 3 schematically illustrates a radio frequency (RF) device 17 according to a third embodiment of the invention. The RF device 17 is arranged on or in the Sol substrate 1 , in particular in the Si layer 1 1 as illustrated in Figure 1. Features of the third embodiment which are the same as in the first and second embodiment carry the same reference numeral and it is referred to their description above. As an alternative the Sol substrate 13 as illustrated in Figure 2 could be used.
The RF device 17 comprises a plurality of electrically isolated device structures 19a, 19b, 19c with a minimal distance d between two structures, here 19a, 19b. When an RF signal passes through device structure 19b, parasitic signals 21 pass through the Sol substrate. According to the invention, their impact is reduced by the penetration layer 5 and the passivation layer 7 as explained in detail above with respect to the first and second embodiment.
According to this embodiment of the invention, the thickness d' is chosen such that it does not exceed ten times, in particular five times, the distance d of the RF device 17. In this case the RF parasitic signals 21 can only reach the penetration layer 5 with its higher resistivity and do not pass via the better conducting Si support substrate 3.
Figure 4 illustrates a fourth embodiment of the invention, namely a first method to fabricate a semiconductor on insulator substrate according to the first or second embodiment of the invention. Again, features of the fourth embodiment which are the same as in the first to third embodiments carry the same reference numeral and it is referred to their description above. Step a) consists in providing a standard Si substrate 3 with normal interstitial oxygen content (Oi) of about 20 to 25ppma. This type of substrate is commonly used in the semiconductor industry. During step b) first a monocrystalline Si layer, the penetration layer 5 is homoepitaxially grown on the Si support substrate 3. The growth conditions are chosen such that a lower Oi content of 5 to ppma oxygen concentration is achieved. Thus, a higher resistivity of at least 2000ΩΓΤΙ or more, in particular 3000 ΩΓΤΙ, can be obtained compared to the Si support substrate 3 is obtained in the epitaxial layer.
Subsequent to the epitaxial growth, the growth conditions are changed to then obtain a polycrystalline layer corresponding to the passivation layer 7.
The thickness d" of the two layers 5 and 7 is determined according to the parameters described above with respect to the embodiments 1 to 3 to achieve the thickness d' of the layers 5, 7 and 9.
According to an alternative, step b) could be replaced by step b') during which the modified passivation layer 15, fulfilling the role of both the penetration layer 5 and the passivation layer 7 at the same time, is grown as a polycrystalline layer directly onto the Si support substrate 3. Step c) consist in preparing a donor substrate 23 comprising a Si donor substrate 25 with a Silicon dioxide layer 27 and a predetermined splitting area 29 in the Si donor substrate 25, e.g. achieved by ion implantation as known in the art.
During step d), the donor substrate 23 is attached, e.g. by bonding, via the surface of the Silicon dioxide layer 27 to the surface of the passivation layer 7 in the first alternative or to the modified passivation layer 15 in the second alternative.
During step e), a detachment treatment, e.g. a thermal treatment, is carried out to achieve a detachment at the predetermined splitting area 29 to thereby transfer a Si layer 31 of the Si donor substrate 23 and the Silicon dioxide layer 27 onto the passivation layer 7 in the first alternative or to the modified passivation layer 15 in the second alternative. Layer 27 thus corresponds to the buried oxide layer 9 and layer 31 to the semiconductor top layer of the first and second embodiment.
Using this method the Sol substrate 1 according to the first embodiment or the Sol substrate 13 according to the second embodiment can be obtained. This substrate can then be used for the fabrication of RF devices, e.g. using CMOS process steps. Figure 5 illustrates a fifth embodiment of the invention, namely an alternative method to fabricate a semiconductor on insulator substrate according to the invention. The method illustrated in Figure 5 is suitable to fabricate a Sol substrate 1 according to the first embodiment. Features of the fifth embodiment which are the same as in the first embodiment and the method according to the fourth embodiment carry the same reference numeral and it is referred to their description above.
Step a) consists in providing a standard Si support substrate 3, e.g. a Si wafer, thus with normal interstitial oxygen content and normal resistivity and in providing a low interstitial oxygen content Si substrate 33, e.g. a low Oi Si wafer, having an Oi content of 5 to 10 ppma and a resistivity of more than 2000ΩΓΤΙ, in particular more than 3000ΩΓΤΙ .
Step b) consists in attaching, e.g. by bonding, Si support substrate 3 to the low Oi Si substrate 33. During step c), the low Oi Si substrate 33 is etched back to obtain a penetration layer 5 of the desired thickness as described above.
Step d) then consists in growing the polycrystalline Si passivation layer 7 over the penetration layer 5, typically with a thickness of 200 to 2500nm.
According to an alternative, in case that the low interstitial oxygen content Si substrate 33 is of polycrystalline nature, the etch back of step c) can be used to obtain a modified passivation layer fulfilling the role of the passivation layer 7 and the penetration layer 5 at the same time. In this alternative, step d) is then not realized.
Step e) consist in preparing a donor substrate 23 comprising a Si donor substrate 25 with a Silicon dioxide layer 27 and a predetermined splitting area 29 in the Si donor substrate 25, e.g. achieved by ion implantation as known in the art.
During step f), the donor substrate 23 is attached, e.g. by bonding, via the surface of the Silicon dioxide layer 27 to the surface of the passivation layer 7.
During step g) a detachment treatment, e.g. a thermal treatment, is carried out to obtain a detachment at the predetermined splitting area 29 to thereby transfer a Si layer 31 of the Si donor substrate 23 and the Silicon dioxide layer 27 onto the passivation layer 7. Layer 27 thus corresponds to the buried oxide layer 9 and layer 31 to the semiconductor top layer 1 1 of the first. A Sol substrate 1 according to the first embodiment is thus obtained.
Figure 6 illustrates a sixth embodiment of the invention, namely a method to choose the thickness of the penetration layer of a semiconductor on insulator substrate according to the invention. The choice depends on the RF devices to be fabricated on or in the Sol substrate 1 , 13 according to the invention. The reference numerals used in the following relate to the features as already described above and carrying the same reference numeral.
The first step a) consists in providing a plurality of semiconductor on insulator substrates 1 with different thicknesses of the penetration layer 5. The thicknesses are chosen such that the overall of thickness of the buried oxide layer 9, the passivation layer 7 and the penetration layer 5 together remains in a range between about 3μηι up to about 30μη"ΐ. The same applies to the Sol substrate 13 according to the second embodiment and the modified passivation layer 15.
In the next step b), radio frequency devices, like RF device 17, are formed on or in the semiconductor insulator substrates 1 , 13. For each one of the different Sol substrates with different penetration layer 5 thicknesses, the same RF devices 17 using the same fabrication process will be manufactured.
Subsequently during step c), the penetration depth of parasitic RF signals is determined, by determining the parasitic signal in neighboring RF device structures, e.g. 19a or 19c in case the reference single passes via structure 19b. Alternatively, the attenuation of the parasitic signal can also be determined.
Finally, according to step d), the semiconductor on insulator substrate 1 or 13 with the thickness of the penetration layer 5 (or the modified passivation layer 15) for which the parasitic RF signal penetrates at most into the penetration layer 5 (or the modified passivation layer 15) is chosen. Amongst the Sol substrates 1 or 13 satisfying the condition, the one with the thinnest penetration layer 5 (or the thinnest modified passivation layer 15) is the one with optimized thickness parameters.
Following this feedback loop, mass production of Sol substrates 1 or 13 with optimized thickness of the penetration layer 5 or modified passivation layer 15 can then be started. In the above embodiments, the semiconductor layer 1 1 was made of silicon and the buried oxide layer of Si02. According to further variants other suitable materials, like SiGe or GaAs, can also be used. Instead of polycrystalline Si other charge trapping layers could also be used for the passivation layer 7.

Claims

Claims
1 . Semiconductor on insulator substrate, in particular a silicon on insulator substrate, comprising a semiconductor top layer (1 1 ), a buried oxide layer (9) and a passivation layer (7) over a Silicon support substrate (3), characterized in that a penetration layer (5) is provided between the passivation layer (7) and the silicon support substrate (3) wherein the penetration layer (5) is a higher resistive Silicon layer with lower interstitial oxygen content than the Silicon support substrate (3).
2. Semiconductor on insulator substrate according to claim 1 , wherein the passivation layer (5) and the penetration layer (7) are of the same material.
3. Semiconductor on insulator substrate according to claim 1 or 2, wherein the
passivation layer (7) is a polycrystalline layer and the penetration layer (5) a monocrystalline material.
4. Semiconductor on insulator substrate, according to one of claims 1 or 2, wherein the penetration layer (13) is a polycrystalline layer.
5. Semiconductor on insulator substrate, according to one of claims 1 to 4, wherein low interstitial oxygen content relates to a concentration of less than 15 ppma, in particular 5 to 10 ppma.
6. Semiconductor on insulator substrate, according to one of claims 1 to 5, wherein the term high resistive relates to a resistivity of 2000ΩΓΤΙ or more, in particular 3000 Qm or more.
7. Semiconductor on insulator substrate, according to one of claims 1 to 6, wherein the buried oxide layer (9), the passivation layer (7) and the penetration layer (5) have a combined thickness of 3μηι to 30μη"ΐ, in particular 4μηι to Ι Ομηη, even more in particular about 5μη-ι.
8. Radio Frequency device with electrically isolated device structures (19a, 19b, 19c) having a minimal distance d between each other provided on and/or in a
semiconductor on insulator substrate according to one of claims 1 to 6, characterized in that the thickness (cT) of the passivation layer (7) and the penetration layer (5) together is such that RF signals at most penetrate into the penetration layer (5).
Radio Frequency device according to claim 8, wherein the thickness of the buried oxide layer (9), the passivation layer (7) and the penetration layer (5) together is such that it does not exceed ten times, in particular five times, the distance d.
0. Method for fabricating a semiconductor on insulator substrate according to one of claims 1 to 7, wherein the penetration layer is epitaxially grown on the support substrate and the semiconductor top layer and the buried oxide layer are transferred onto the passivation layer by a layer transfer process, in particular comprising a bonding method.
1. Method for fabricating a semiconductor on insulator substrate according to one of claims 1 to 7, wherein the penetration layer is transferred onto the support substrate by layer transfer method, in particular a bonding method.
2. Method for fabricating a Radio Frequency device according to one of claims 8 and 9, comprising the steps of:
providing a plurality of semiconductor on insulator substrates with different thicknesses of the penetration layer
forming radio frequency devices on or in the semiconductor insulator substrates
determining the penetration depth of RF signals in the plurality of
semiconductor on insulator substrates
choosing the semiconductor on insulator substrate with the thickness of the penetration layer for which the RF signal penetrates at most into the penetration layer.
PCT/EP2017/057614 2016-03-31 2017-03-30 Semiconductor on insulator substrate for rf applications Ceased WO2017167923A1 (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019536260A (en) * 2016-10-26 2019-12-12 グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． High resistivity silicon-on-insulator substrate with improved charge trapping efficiency
WO2020072212A1 (en) * 2018-10-01 2020-04-09 Applied Materials, Inc. Method of forming an rf silicon on insulator device
EP3713085A4 (en) * 2018-11-09 2021-01-13 NGK Insulators, Ltd. ASSEMBLED BODY OF PIEZOELECTRIC MATERIAL SUBSTRATE AND SUPPORT SUBSTRATE, ITS MANUFACTURING PROCESS AND ACOUSTIC WAVE ELEMENT
WO2021111062A1 (en) * 2019-12-05 2021-06-10 Soitec Method for forming a handling substrate for a composite structure intended for rf applications and handling substrate
US11875935B2 (en) 2019-11-25 2024-01-16 Commissariat A L'energie Atomique Et Aux Energies Alternatives Integrated electronic device comprising a coil and method for manufacturing such a device

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3049763B1 (en) 2016-03-31 2018-03-16 Soitec SEMICONDUCTOR SUBSTRATE ON INSULATION FOR RF APPLICATIONS
FR3079662B1 (en) * 2018-03-30 2020-02-28 Soitec SUBSTRATE FOR RADIO FREQUENCY APPLICATIONS AND MANUFACTURING METHOD THEREOF
CN110890418B (en) * 2019-12-02 2021-11-05 中国科学院上海微系统与信息技术研究所 A kind of transistor structure with double buried oxide layer and preparation method thereof
JP7392578B2 (en) * 2020-06-05 2023-12-06 信越半導体株式会社 High frequency semiconductor device manufacturing method and high frequency semiconductor device
FR3119046B1 (en) * 2021-01-15 2022-12-23 Applied Materials Inc SILICON SUPPORT SUBSTRATE SUITABLE FOR RADIO FREQUENCY APPLICATIONS AND ASSOCIATED MANUFACTURING METHOD
CN114823903A (en) * 2021-01-27 2022-07-29 中国科学院微电子研究所 Single-junction transistor structure and manufacturing method thereof
TWI761255B (en) 2021-07-08 2022-04-11 環球晶圓股份有限公司 Wafer and manufacturing method of wafer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120235283A1 (en) * 2011-03-16 2012-09-20 Memc Electronic Materials, Inc. Silicon on insulator structures having high resistivity regions in the handle wafer
US20140084290A1 (en) * 2011-03-22 2014-03-27 Commissariat A L'energie Atomique Et Aux Energies Alternatives Manufacturing method for a semiconductor on insulator type substrate for radiofrequency applications
WO2015112308A1 (en) * 2014-01-23 2015-07-30 Sunedison Semiconductor Limited High resistivity soi wafers and a method of manufacturing thereof

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001168308A (en) 1999-09-30 2001-06-22 Canon Inc Method for manufacturing silicon thin film, method for manufacturing SOI substrate, and semiconductor device
JP2004537161A (en) * 2001-04-11 2004-12-09 エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド Control of thermal donor generation in high resistivity CZ silicon
US7529433B2 (en) * 2007-01-12 2009-05-05 Jds Uniphase Corporation Humidity tolerant electro-optic device
US8078565B2 (en) * 2007-06-12 2011-12-13 Kana Software, Inc. Organically ranked knowledge categorization in a knowledge management system
US7883990B2 (en) * 2007-10-31 2011-02-08 International Business Machines Corporation High resistivity SOI base wafer using thermally annealed substrate
FR2953640B1 (en) * 2009-12-04 2012-02-10 S O I Tec Silicon On Insulator Tech METHOD FOR MANUFACTURING A SEMICONDUCTOR TYPE STRUCTURE ON INSULATION, WITH REDUCED ELECTRICAL LOSSES AND CORRESPONDING STRUCTURE
US8536035B2 (en) * 2012-02-01 2013-09-17 International Business Machines Corporation Silicon-on-insulator substrate and method of forming
FR2999801B1 (en) * 2012-12-14 2014-12-26 Soitec Silicon On Insulator METHOD FOR MANUFACTURING A STRUCTURE
US9853133B2 (en) * 2014-09-04 2017-12-26 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity silicon-on-insulator substrate
EP4120320A1 (en) * 2015-03-03 2023-01-18 GlobalWafers Co., Ltd. Charge trapping polycrystalline silicon films on silicon substrates with controllable film stress
FR3049763B1 (en) * 2016-03-31 2018-03-16 Soitec SEMICONDUCTOR SUBSTRATE ON INSULATION FOR RF APPLICATIONS

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120235283A1 (en) * 2011-03-16 2012-09-20 Memc Electronic Materials, Inc. Silicon on insulator structures having high resistivity regions in the handle wafer
US20140084290A1 (en) * 2011-03-22 2014-03-27 Commissariat A L'energie Atomique Et Aux Energies Alternatives Manufacturing method for a semiconductor on insulator type substrate for radiofrequency applications
WO2015112308A1 (en) * 2014-01-23 2015-07-30 Sunedison Semiconductor Limited High resistivity soi wafers and a method of manufacturing thereof

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019536260A (en) * 2016-10-26 2019-12-12 グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． High resistivity silicon-on-insulator substrate with improved charge trapping efficiency
JP2021005720A (en) * 2016-10-26 2021-01-14 グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． High resistivity silicon-on-insulator substrate with improved charge capture efficiency
WO2020072212A1 (en) * 2018-10-01 2020-04-09 Applied Materials, Inc. Method of forming an rf silicon on insulator device
EP3713085A4 (en) * 2018-11-09 2021-01-13 NGK Insulators, Ltd. ASSEMBLED BODY OF PIEZOELECTRIC MATERIAL SUBSTRATE AND SUPPORT SUBSTRATE, ITS MANUFACTURING PROCESS AND ACOUSTIC WAVE ELEMENT
US12101079B2 (en) 2018-11-09 2024-09-24 Ngk Insulators, Ltd. Method of producing a bonded body of piezoelectric material substrate
US11875935B2 (en) 2019-11-25 2024-01-16 Commissariat A L'energie Atomique Et Aux Energies Alternatives Integrated electronic device comprising a coil and method for manufacturing such a device
WO2021111062A1 (en) * 2019-12-05 2021-06-10 Soitec Method for forming a handling substrate for a composite structure intended for rf applications and handling substrate
FR3104322A1 (en) * 2019-12-05 2021-06-11 Soitec METHOD FOR FORMING A HANDLING SUBSTRATE FOR A COMPOSITE STRUCTURE TARGETING RF APPLICATIONS
US12362226B2 (en) 2019-12-05 2025-07-15 Soitec Method for forming a handling substrate for a composite structure intended for RF applications and handling substrate

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