WO2017157108A1 - 逆变器启动短路保护方法和装置 - Google Patents

逆变器启动短路保护方法和装置 Download PDF

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WO2017157108A1
WO2017157108A1 PCT/CN2017/072237 CN2017072237W WO2017157108A1 WO 2017157108 A1 WO2017157108 A1 WO 2017157108A1 CN 2017072237 W CN2017072237 W CN 2017072237W WO 2017157108 A1 WO2017157108 A1 WO 2017157108A1
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signal
pwm
state
flag
pwm signal
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English (en)
French (fr)
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娄贺伟
陈勇
陈宁宁
蒋世用
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Gree Electric Appliances Inc of Zhuhai
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Gree Electric Appliances Inc of Zhuhai
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration

Definitions

  • the present invention relates to the field of inverters, and in particular to an inverter startup short circuit protection method and apparatus.
  • a plurality of PWM output modules are integrated inside the DSP, wherein each PWM output module can issue two complementary PWM control signals.
  • each PWM output module can issue two complementary PWM control signals.
  • the inverter is controlled by the DSP, for the two-level inverter, two of the upper and lower arms of the same phase can share the two PWM control signals sent by the same PWM module for control.
  • the dead time and the control mode are properly set, there is no problem that the upper and lower arms are simultaneously turned on, and the DC bus is not short-circuited.
  • a method and a device for initiating short circuit protection of an inverter are provided to solve the defects in the prior art due to the design of the DSP itself, and the PWM control signals of the switching tubes of the upper and lower bridge arms of the same phase cannot be ensured at the startup, resulting in The problem of the inverter starting a short circuit.
  • an embodiment of the present invention provides an inverter startup short circuit protection device, including: a first PWM input terminal; a second PWM input terminal; a first logic unit, and the first PWM input terminal and the a second PWM input terminal is configured to generate a flag signal in a first state when an input signal of the first PWM input terminal and an input signal of the second PWM input terminal are both high levels, or generate a second state a flag signal; a second logic unit, and the first PWM The input terminal and the first logic unit are connected to filter an input signal of the first PWM input terminal when the flag signal is in the first state, and when the flag signal is in the second state Holding an input signal of the first PWM input terminal; a third logic unit connected to the second PWM input terminal and the first logic unit, configured to filter out when the flag signal is in the first state An input signal of the second PWM input terminal and an input signal of the second PWM input terminal when the flag signal is in the second state.
  • said first logical unit is an AND gate.
  • said second logic unit and said third logic unit are XOR gates.
  • the present invention also provides an inverter startup short circuit protection method, comprising: acquiring a first PWM signal and a second PWM signal; generating a first state when the first PWM signal and the second PWM signal are both high levels a flag signal, otherwise generating a flag signal in a second state; filtering the first PWM signal and the second PWM signal when the flag signal is in the first state, and at the flag signal The first PWM signal and the second PWM signal are maintained in the second state.
  • the flag signal is generated by logically ANDing the first PWM signal and the second PWM signal.
  • the corresponding first PWM signal or the second PWM signal is filtered/held by means of performing a logical exclusive OR operation on the flag signal and the first PWM signal or the second PWM signal.
  • the present invention also provides an inverter startup short circuit protection device, comprising: an acquisition module, configured to acquire a first PWM signal and a second PWM signal; a flag signal generation module, configured to be in the first PWM signal and the second Generating a flag signal in a first state when the PWM signal is at a high level, otherwise generating a flag signal in a second state; the signal processing module is configured to filter the first signal when the flag signal is in the first state The PWM signal and the second PWM signal, and maintaining the first PWM signal and the second PWM signal when the flag signal is in the second state.
  • the flag signal generating module generates the flag signal by performing a logical AND operation on the first PWM signal and the second PWM signal.
  • the signal processing module filters/holds the corresponding first one by performing a logical exclusive OR operation on the flag signal and the first PWM signal or the second PWM signal PWM signal or the second PWM signal.
  • the invention can shield the erroneous PWM control signal sent by the DSP by hardware, avoiding the short circuit problem caused by the wrong PWM signal when the T-type three-level inverter starts, and ensuring the normality of the T-type three-level inverter. Start and run, with a simple structure and low cost.
  • FIG. 1 is a schematic diagram of an inverter start short circuit protection device according to an embodiment of the present invention
  • FIG. 2 is a circuit schematic diagram of a single-phase T-type three-level structure used in an embodiment of the present invention
  • FIG. 3 is a flow chart of a method for starting short circuit protection of an inverter according to an embodiment of the present invention
  • FIG. 4 is a schematic structural view of an inverter start short circuit protection device according to an embodiment of the present invention.
  • PWM1 first PWM input terminal
  • PWM2 second PWM input terminal
  • an embodiment of the present invention provides an inverter startup short circuit protection device, including: a first PWM input terminal PWM1, a second PWM input terminal PWM2, a first logic unit 1, a second logic unit 2, and a Three logical units 3.
  • the two input ends of the first logic unit 1 are respectively connected to the first PWM input terminal PWM1 and the second PWM input terminal PWM2, and the first logic unit 1 is at the input signal of the first PWM input terminal PWM1 and the second PWM input terminal.
  • the flag signal in the first state is generated, otherwise the flag signal in the second state is generated.
  • the two input ends of the second logic unit 2 are respectively connected to the first PWM input terminal PWM1 and the output end of the first logic unit 1, and the second logic unit 2 filters out the first PWM input terminal PWM1 when the flag signal is in the first state.
  • the input signal eg, output low level
  • the two input ends of the third logic unit 3 are respectively connected to the second PWM input terminal PWM2 and the output end of the first logic unit 1, and the third logic unit 3 filters out the second PWM input terminal PWM2 when the flag signal is in the first state.
  • Input signal such as output low level
  • the flag signal is in the second In the state, the input signal of the second PWM input terminal PWM2 is maintained to output the signal PWM2-2.
  • the first logic unit 1 when the two PWM signals provided to the inverter are not complementary (that is, both are high), the first logic unit 1 generates a flag signal in a first state, and the first state indicates two PWMs.
  • the signal is turbulent; otherwise, the flag signal in the second state is generated, and the second state indicates that the two PWM signals are in a normal state.
  • the flag signal of the first state is simultaneously transmitted to the second logic unit 2 and the third logic unit 3.
  • the second logic unit 2 and the third logic unit 3 are respectively connected with a PWM signal, so that the second logic unit 2 and the third logic unit 3 can input the corresponding PWM signals according to the state of the flag signal. Process it. For example, when the flag signal is in the first state, the corresponding PWM signal is filtered out, so that both PWM signals become inactive levels (eg, low level), and thus the T-type three-level inverter is not caused.
  • the upper and lower arms of the same phase are simultaneously turned on to avoid the problem of short-circuiting of the DC bus; when the flag signal is in the second state, the corresponding PWM signal is kept unchanged.
  • the present invention can shield the erroneous PWM control signal sent by the DSP by hardware, and avoid the short circuit problem caused by the erroneous PWM signal when the T-type three-level inverter starts, and ensure the T-type three-level inverter.
  • the normal startup and operation have the characteristics of simple structure and low cost.
  • the first logic unit 1, the second logic unit 2, and the third logic unit 3 of the present invention may be implemented by using discrete logic devices.
  • the first logic unit 1 may be an AND gate
  • the first Both the logic unit 2 and the third logic unit 3 may be XOR gates.
  • those skilled in the art can also use other combined circuits to implement the functions of the above devices, and all of them belong to the equivalent of the present invention.
  • FIG. 2 shows a circuit schematic of a single-phase three-level topology. As shown in FIG. 2, it has four switch tubes, which are 6, 7, 8, and 9, respectively.
  • the same group of PWM modules of the DSP control the two switch tubes, therefore, Two PWM modules (ie PWM module 1 and PWM module 2).
  • the two PWM signals sent by the same PWM module are self-complementary, and there is no risk of causing the DC bus to be short-circuited.
  • PWM module 1 When working, PWM module 1 issues PWM signals: PWM1 and PMW4, while PWM module 2 Issue the PWM signal: PWM2 and PWM3.
  • PWM1 controls the switching tube 6
  • PWM2 controls the opening tube 7
  • PMW3 controls the switching tube 8
  • PWM4 controls the switching tube 9.
  • the pulse form of each PWM module at startup is uncontrollable. Therefore, when the T-type three-level inverter is started, there is a risk that the PWM signals issued by the DSP are not complementary and the DC bus is short-circuited.
  • the present invention processes the PWM signal sent by the DSP, shields the falsified PWM signal from starting, and protects the DC bus from short circuit.
  • the present invention first passes PWM1 and PWM2 through the AND gate to obtain a flag signal.
  • the truth table for this flag signal as it passes through the AND gate is as follows:
  • PWM1 PWM2 Sign signal 0 0 0 0 0 1 0 1 0 0 1 1 1
  • PWM1 and PWM2 are XORed by an exclusive OR gate and the flag signal respectively.
  • the two XOR gate logics in the present invention are as follows:
  • the present invention can also be implemented by using a large-scale logic device such as an FPGA or a CPLD.
  • a large-scale logic device such as an FPGA or a CPLD.
  • each logic unit can be integrated into one chip and implement corresponding functions.
  • the present invention further provides an inverter startup short circuit protection method, including the following steps: First, acquiring a first PWM signal and a second PWM signal, the two PWM signals may be from two different DSPs.
  • the PWM module therefore has the possibility of not being complementary. And generating a flag signal according to the first PWM signal and the second PWM signal, where the flag signal includes two states, wherein the flag signal in the first state is generated when the first PWM signal and the second PWM signal are both high levels, Otherwise a flag signal in the second state is generated.
  • the first PWM signal and the second PWM signal are filtered out when the flag signal is in the first state, and the first PWM signal and the second PWM signal are held while the flag signal is in the second state.
  • the flag signal in the first state is generated, and the first state indicates that the two PWM signals are disordered; Conversely, a flag signal in the second state is generated, and the second state indicates that the two PWM signals are in a normal state.
  • the corresponding PWM signal input thereto can be processed according to the state of the flag signal. For example, when the flag signal is in the first state, the corresponding PWM signal is filtered out, so that both PWM signals become inactive levels (eg, low level), and thus the T-type three-level inverter is not caused.
  • the upper and lower arms of the same phase are simultaneously turned on, avoiding the problem of DC bus short circuit; when the flag signal is in the second state, the corresponding PWM signal is kept unchanged.
  • the present invention can shield the erroneous PWM control signal sent by the DSP, avoid the short circuit problem caused by the erroneous PWM signal when the T-type three-level inverter starts, and ensure the normal startup and operation of the T-type three-level inverter. .
  • the flag signal may be generated by performing a logical AND operation on the first PWM signal and the second PWM signal. Further, the flag signal may be logically different from the first PWM signal or the second PWM signal.
  • the OR operation mode filters out/maintains the corresponding first PWM signal or second PWM signal.
  • those skilled in the art can also use other logic operations or algorithms to generate a flag signal or filter or maintain the corresponding PWM signal.
  • the present invention further provides an inverter starting short circuit protection device, which is a device corresponding to the above method, which can be used to implement the above method, and therefore, where the method overlaps with the above method, Let me repeat.
  • the inverter starting short circuit protection device comprises: an acquisition module, a flag signal generation module and a signal processing module.
  • the acquiring module is configured to obtain the first PWM signal and the second PWM signal; the flag signal generating module generates the flag signal in the first state when the first PWM signal and the second PWM signal are both high, otherwise the generating is in the second The flag signal of the status.
  • the signal processing module filters out the first PWM signal and the second PWM signal when the flag signal is in the first state, and maintains the first PWM signal and the second PWM signal when the flag signal is in the second state.
  • the signal generating module when the two PWM signals provided to the inverter are not complementary (that is, both are high), the signal generating module generates a flag signal in a first state, and the first state indicates that two PWM signals occur.
  • the disorder is reversed; the flag signal in the second state is generated, and the second state indicates that the two PWM signals are in a normal state.
  • the T-type three-level inverter can process the corresponding PWM signal input according to the state of the flag signal. For example, when the flag signal is in the first state, the corresponding PWM signal is filtered out, so that both PWM signals become inactive levels, so that the upper and lower arms of the same phase of the T-type three-level inverter are not simultaneously Turning on, avoiding the problem of DC bus short circuit; when the flag signal is in the second state, the corresponding PWM signal is kept unchanged.
  • the flag signal generating module generates the flag signal by performing a logical AND operation on the first PWM signal and the second PWM signal.
  • the signal processing module filters/holds the corresponding first PWM signal or the second PWM signal by performing a logical exclusive OR operation on the flag signal and the first PWM signal or the second PWM signal.
  • the invention solves the problem that the DSP is applied to the inverter (especially the T-type three-level inverter), and the startup of the inverter is caused by the signal turbulence caused by the DSP, causing the short circuit of the upper and lower arms of the same phase to be short-circuited. Reliability and security. After the PWM control signal processed by the invention, the requirements of the upper and lower arms of the inverter can be met at different times, and the inverter is prevented from being damaged by the short circuit of the upper and lower arms during startup, thereby ensuring the safe operation of the inverter and improving the safety of the inverter. Inverter reliability.
  • the present invention is applicable not only to a single-phase T-type three-level inverter, but also to a three-phase T-type three-level inverter, etc., where the upper and lower arms are not simultaneously turned on.

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Abstract

一种逆变器启动短路保护方法和装置。该装置包括：第一PWM输入端(PWM1)；第二PWM输入端(PWM2)；第一逻辑单元(1)，与第一PWM输入端及第二PWM输入端连接，用于在第一PWM输入端的输入信号和第二PWM输入端的输入信号均为高电平时生成处于第一状态的标志信号，否则生成处于第二状态的标志信号；第二逻辑单元(2)，与第一PWM输入端及第一逻辑单元连接，用于在标志信号处于第一状态时滤除第一PWM输入端的输入信号、并在标志信号处于第二状态时保持第一PWM输入端的输入信号。该方法和装置可屏蔽由DSP发出的错误PWM控制信号，避免T型三电平逆变器启动时发生的短路问题。

Description

逆变器启动短路保护方法和装置
本申请要求于2016年03月16日提交中国专利局、申请号为201610150723.9、发明名称为“逆变器启动短路保护方法和装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及逆变器领域，具体而言，涉及一种逆变器启动短路保护方法和装置。
背景技术
在DSP内部集成有多个PWM输出模块，其中，每个PWM输出模块可发出两个互补的PWM控制信号。当采用DSP来控制逆变器时，对于两电平结构的逆变器来说，其同一相上下桥臂中的两个开关管可共用同一个PWM模块发出的两个PWM控制信号进行控制，这样，在死区时间及控制方式设置合理的情况下，不会存在上下桥臂同时导通的问题，也不会导致直流母线短路。
然而，对于基于T型三电平拓扑结构研发的逆变器来说，现有技术中用于控制其同一相上下桥臂的两个开关管的PWM控制信号是由不同的PWM模块分别发出的。由于DSP自身设计的缺陷，在启动时不能确保同一相上下桥臂的开关管的PWM控制信号互补。因此，如果不对上下桥臂开关管上的PWM控制信号进行处理，那么基于DSP设计的T型三电平逆变器就会存在启动短路的风险。
发明内容
本发明实施例中提供一种逆变器启动短路保护方法和装置，以解决现有技术中由于DSP自身设计的缺陷，在启动时不能确保同一相上下桥臂开关管的PWM控制信号互补，导致逆变器启动短路的问题。
为实现上述目的，本发明实施例提供一种逆变器启动短路保护装置，包括：第一PWM输入端；第二PWM输入端；第一逻辑单元，与所述第一PWM输入端及所述第二PWM输入端连接，用于在所述第一PWM输入端的输入信号和所述第二PWM输入端的输入信号均为高电平时生成处于第一状态的标志信号，否则生成处于第二状态的标志信号；第二逻辑单元，与所述第一PWM 输入端及所述第一逻辑单元连接，用于在所述标志信号处于所述第一状态时滤除所述第一PWM输入端的输入信号、并在所述标志信号处于所述第二状态时保持所述第一PWM输入端的输入信号；第三逻辑单元，与所述第二PWM输入端及所述第一逻辑单元连接，用于在所述标志信号处于所述第一状态时滤除所述第二PWM输入端的输入信号、并在所述标志信号处于所述第二状态时保持所述第二PWM输入端的输入信号。
作为优选，所述第一逻辑单元为与门。
作为优选，所述第二逻辑单元和所述第三逻辑单元均为异或门。
本发明还提供了一种逆变器启动短路保护方法，包括：获取第一PWM信号及第二PWM信号；在所述第一PWM信号及第二PWM信号均为高电平时生成处于第一状态的标志信号，否则生成处于第二状态的标志信号；在所述标志信号处于所述第一状态时滤除所述第一PWM信号和所述第二PWM信号、并在所述标志信号处于所述第二状态时保持所述第一PWM信号和所述第二PWM信号。
作为优选，采用将所述第一PWM信号及第二PWM信号进行逻辑与运算的方式生成所述标志信号。
作为优选，采用将所述标志信号与所述第一PWM信号或所述第二PWM信号进行逻辑异或运算的方式滤除/保持相应的所述第一PWM信号或所述第二PWM信号。
本发明还提供了一种逆变器启动短路保护装置，包括：获取模块，用于获取第一PWM信号及第二PWM信号；标志信号生成模块，用于在所述第一PWM信号及第二PWM信号均为高电平时生成处于第一状态的标志信号，否则生成处于第二状态的标志信号；信号处理模块，用于在所述标志信号处于所述第一状态时滤除所述第一PWM信号和所述第二PWM信号、并在所述标志信号处于所述第二状态时保持所述第一PWM信号和所述第二PWM信号。
作为优选，所述标志信号生成模块采用将所述第一PWM信号及第二PWM信号进行逻辑与运算的方式生成所述标志信号。
作为优选，所述信号处理模块采用将所述标志信号与所述第一PWM信号或所述第二PWM信号进行逻辑异或运算的方式滤除/保持相应的所述第一 PWM信号或所述第二PWM信号。
本发明可通过硬件的方式，屏蔽由DSP发出的错误的PWM控制信号，避免T型三电平逆变器启动时由于错误PWM信号发生的短路问题，保证T型三电平逆变器的正常启动和运行，具有结构简单、成本低的特点。
附图说明
图1是本发明实施例的逆变器启动短路保护装置的原理图；
图2是本发明实施例中使用的单相T型三电平结构的电路原理图；
图3是本发明实施例的逆变器启动短路保护方法的流程图；
图4是本发明实施例的逆变器启动短路保护装置的结构示意图。
附图标记说明：PWM1、第一PWM输入端；PWM2、第二PWM输入端；1、第一逻辑单元；2、第二逻辑单元；3、第三逻辑单元；6、开关管；7、开关管；8、开关管；9、开关管。
具体实施方式
下面结合附图和具体实施例对本发明作进一步详细描述，但不作为对本发明的限定。
请参考图1，本发明实施例提供了一种逆变器启动短路保护装置，包括：第一PWM输入端PWM1、第二PWM输入端PWM2、第一逻辑单元1、第二逻辑单元2和第三逻辑单元3。
其中，第一逻辑单元1的两个输入端分别与第一PWM输入端PWM1及第二PWM输入端PWM2连接，第一逻辑单元1在第一PWM输入端PWM1的输入信号和第二PWM输入端PWM2的输入信号均为高电平时生成处于第一状态的标志信号，否则生成处于第二状态的标志信号。
第二逻辑单元2的两个输入端分别与第一PWM输入端PWM1及第一逻辑单元1的输出端连接，第二逻辑单元2在标志信号处于第一状态时滤除第一PWM输入端PWM1的输入信号(例如输出低电平)、并在标志信号处于第二状态时保持第一PWM输入端PWM1的输入信号从而输出信号PWM1-1。
第三逻辑单元3的两个输入端分别与第二PWM输入端PWM2及第一逻辑单元1的输出端连接，第三逻辑单元3在标志信号处于第一状态时滤除第二PWM输入端PWM2的输入信号(例如输出低电平)、并在标志信号处于第二 状态时保持第二PWM输入端PWM2的输入信号从而输出信号PWM2-2。
在上述技术方案中，当提供给逆变器的两个PWM信号不互补(即均为高平时)，第一逻辑单元1生成处于第一状态的标志信号，该第一状态即表明两个PWM信号发生了紊乱；反之，生成处于第二状态的标志信号，第二状态表明两个PWM信号处于正常状态。
T型三电平逆变器为例，该第一状态的标志信号被同时发送给了第二逻辑单元2和第三逻辑单元3。而第二逻辑单元2和第三逻辑单元3又分别连接有一个PWM信号，这样，第二逻辑单元2和第三逻辑单元3便可根据标志信号的状态，来对输入其中的相应的PWM信号进行处理。例如，在标志信号为第一状态时，滤除掉相应的PWM信号，这样，两个PWM信号均变成无效电平(例如低电平)，因而不会使T型三电平逆变器同一相的上下臂同时导通，避免了直流母线短路的问题；当标志信号为第二状态时，则保持相应的PWM信号不变。
因此，本发明可通过硬件的方式，屏蔽由DSP发出的错误的PWM控制信号，避免T型三电平逆变器启动时由于错误PWM信号发生的短路问题，保证T型三电平逆变器的正常启动和运行，具有结构简单、成本低的特点。
在一个实施例中，本发明的上述第一逻辑单元1、第二逻辑单元2和第三逻辑单元3均可采用分立的逻辑器件实现，例如，第一逻辑单元1可以为与门，而第二逻辑单元2和第三逻辑单元3均可为异或门。当然，本领域技术人员也可以采用其他组合电路来实现上述各器件的功能，均属于本发明的等同替代方式。
下面以下具体的实施例，对本发明中的上述装置工作时的原理进行详细说明。
图2示出了单相三电平拓扑结构的电路原理图。如图2所示，其具有四个开关管，分别为6、7、8、9，其中，在用DSP控制四个开关管时，DSP的同一组PWM模块控制两个开关管，因此，需要两个PWM模块(即PWM模块1和PWM模块2)。同一PWM模块发出的两个PWM信号自身存在互补性，不存在导致直流母线短路的风险。
工作时，PWM模块1发出PWM信号：PWM1和PMW4，而PWM模块 2发出PWM信号：PWM2和PWM3。其中，PWM1控制开关管6，PWM2控制开头管7，PMW3控制开关管8，PWM4控制开关管9。
由于控制开关管6和7的PWM1和PMW2分别由不同的PWM模块发出，导致启动时各PWM模块发出的脉冲形式是不可控的。因此，T型三电平逆变器启动时存在由DSP发出的PWM信号不互补导致直流母线短路的风险。为了解决这个问题，本发明对DSP发出的PWM信号进行处理，屏蔽启动时发生错乱的PWM信号，保护直流母线不发生短路。
本发明首先使PWM1和PWM2经过与门，从而得到标志信号。该标志信号经过与门时的真值表如下所示：
PWM1 PWM2 标志信号
0 0 0
0 1 0
1 0 0
1 1 1
可见，当输入与门的PWM1和PWM2均为高电平(即1)时，输出高电平(即1)的标志信号(即第一状态)。上表中，标志信号为0(即低电平时)为第二状态。
然后，再将PWM1和PWM2分别通过一个异或门与标志信号进行异或运算，本发明中的两个异或门逻辑情况如下：
Figure PCTCN2017072237-appb-000001
在上表中，实际上并不存在PWM1/PWM2为0、且标志信号为1的情况(即上表第2行)，这并不会对上述硬件电路的控制结果产生影响。
例如，当PWM1和PWM2均为1时，标志信号为1。此时，经过异或门后，PWM1和PWM2所对应的异或门的输出信号O均为0，从而避免了上下 桥臂短路的问题。
在另一个实施例中，本发明还可以采用FPGA、CPLD等大规模逻辑器件来实现，此时，各逻辑单元可集成在一块芯片中，并实现相应的功能。
请参考图3，本发明还提供了一种逆变器启动短路保护方法，包括以下步骤：首先，获取第一PWM信号及第二PWM信号，这两个PWM信号可来自于DSP的两个不同的PWM模块，因此存在不互补的可能性。接着，根据第一PWM信号和第二PWM信号生成标志信号，该标志信号包括两个状态，其中，在第一PWM信号及第二PWM信号均为高电平时生成处于第一状态的标志信号，否则生成处于第二状态的标志信号。然后，在标志信号处于第一状态时滤除第一PWM信号和第二PWM信号、并在标志信号处于第二状态时保持第一PWM信号和第二PWM信号。
在上述技术方案中，当提供给逆变器的两个PWM信号不互补(即均为高平时)，生成处于第一状态的标志信号，该第一状态即表明两个PWM信号发生了紊乱；反之，生成处于第二状态的标志信号，第二状态表明两个PWM信号处于正常状态。
T型三电平逆变器为例，当生成不同状态的标志信号时，可根据标志信号的状态，来对输入其中的相应的PWM信号进行处理。例如，在标志信号为第一状态时，滤除掉相应的PWM信号，这样，两个PWM信号均变成无效电平(例如低电平)，因而不会使T型三电平逆变器同一相的上下桥臂同时导通，避免了直流母线短路的问题；当标志信号为第二状态时，则保持相应的PWM信号不变。
因此，本发明可屏蔽由DSP发出的错误的PWM控制信号，避免T型三电平逆变器启动时由于错误PWM信号发生的短路问题，保证T型三电平逆变器的正常启动和运行。
在一个实施例中，可采用将第一PWM信号及第二PWM信号进行逻辑与运算的方式生成标志信号，进一步地，也可采用将标志信号与第一PWM信号或第二PWM信号进行逻辑异或运算的方式滤除/保持相应的第一PWM信号或第二PWM信号。当然，本领域技术人员也可以采用其他的逻辑运算方式或算法，生成标志信号或对相应的PWM信号进行滤除或保持处理。
请参考图4，本发明还提供了一种逆变器启动短路保护装置，该装置是与上述方法对应的装置，其可用于实现上述的方法，因此，与上述方法重复之处，在此不再赘述。
在一个优选的实施例中，该逆变器启动短路保护装置包括：获取模块、标志信号生成模块和信号处理模块。
其中，获取模块可用来获取第一PWM信号及第二PWM信号；标志信号生成模块在第一PWM信号及第二PWM信号均为高电平时生成处于第一状态的标志信号，否则生成处于第二状态的标志信号。而信号处理模块则在标志信号处于第一状态时滤除第一PWM信号和第二PWM信号、并在标志信号处于第二状态时保持第一PWM信号和第二PWM信号。
在上述技术方案中，当提供给逆变器的两个PWM信号不互补(即均为高平时)，信号生成模块生成处于第一状态的标志信号，该第一状态即表明两个PWM信号发生了紊乱；反之，生成处于第二状态的标志信号，第二状态表明两个PWM信号处于正常状态。
T型三电平逆变器为例，信号处理模块可根据标志信号的状态，来对输入其中的相应的PWM信号进行处理。例如，在标志信号为第一状态时，滤除掉相应的PWM信号，这样，两个PWM信号均变成无效电平，因而不会使T型三电平逆变器同一相的上下臂同时导通，避免了直流母线短路的问题；当标志信号为第二状态时，则保持相应的PWM信号不变。
优选地，标志信号生成模块采用将第一PWM信号及第二PWM信号进行逻辑与运算的方式生成标志信号。
优选地，信号处理模块采用将标志信号与第一PWM信号或第二PWM信号进行逻辑异或运算的方式滤除/保持相应的第一PWM信号或第二PWM信号。
本发明解决了DSP应用于逆变器(特别是T型三电平逆变器)中，在启动时，由于DSP发出信号紊乱导致同一相上下桥臂短路的问题，增加了逆变器运行的可靠性和安全性。经过本发明处理后的PWM控制信号，可满足逆变器上下桥臂不同时导通的要求，避免启动时上下桥臂短路造成逆变器的损毁，保证了逆变器的安全运行，提高了逆变器的可靠性。
本发明不但适用于单相T型三电平结构的逆变器，而且适用于三相T型三电平结构的逆变器等要求上下桥臂不同时导通的场合。
当然，以上是本发明的优选实施方式。应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明基本原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围。

Claims (9)

  1. 一种逆变器启动短路保护装置，其特征在于，包括：
    第一PWM输入端(PWM1)；
    第二PWM输入端(PWM2)；
    第一逻辑单元(1)，与所述第一PWM输入端(PWM1)及所述第二PWM输入端(PWM2)连接，用于在所述第一PWM输入端(PWM1)的输入信号和所述第二PWM输入端(PWM2)的输入信号均为高电平时生成处于第一状态的标志信号，否则生成处于第二状态的标志信号；
    第二逻辑单元(2)，与所述第一PWM输入端(PWM1)及所述第一逻辑单元(1)连接，用于在所述标志信号处于所述第一状态时滤除所述第一PWM输入端(PWM1)的输入信号、并在所述标志信号处于所述第二状态时保持所述第一PWM输入端(PWM1)的输入信号；
    第三逻辑单元(3)，与所述第二PWM输入端(PWM2)及所述第一逻辑单元(1)连接，用于在所述标志信号处于所述第一状态时滤除所述第二PWM输入端(PWM2)的输入信号、并在所述标志信号处于所述第二状态时保持所述第二PWM输入端(PWM2)的输入信号。
  2. 根据权利要求1所述的逆变器启动短路保护装置，其特征在于，所述第一逻辑单元(1)为与门。
  3. 根据权利要求1所述的逆变器启动短路保护装置，其特征在于，所述第二逻辑单元(2)和所述第三逻辑单元(3)均为异或门。
  4. 一种逆变器启动短路保护方法，其特征在于，包括：
    获取第一PWM信号及第二PWM信号；
    在所述第一PWM信号及第二PWM信号均为高电平时生成处于第一状态的标志信号，否则生成处于第二状态的标志信号；
    在所述标志信号处于所述第一状态时滤除所述第一PWM信号和所述第二PWM信号、并在所述标志信号处于所述第二状态时保持所述第一PWM信号和所述第二PWM信号。
  5. 根据权利要求4所述的逆变器启动短路保护方法，其特征在于，采用 将所述第一PWM信号及第二PWM信号进行逻辑与运算的方式生成所述标志信号。
  6. 根据权利要求4所述的逆变器启动短路保护方法，其特征在于，采用将所述标志信号与所述第一PWM信号或所述第二PWM信号进行逻辑异或运算的方式滤除/保持相应的所述第一PWM信号或所述第二PWM信号。
  7. 一种逆变器启动短路保护装置，其特征在于，包括：
    获取模块，用于获取第一PWM信号及第二PWM信号；
    标志信号生成模块，用于在所述第一PWM信号及第二PWM信号均为高电平时生成处于第一状态的标志信号，否则生成处于第二状态的标志信号；
    信号处理模块，用于在所述标志信号处于所述第一状态时滤除所述第一PWM信号和所述第二PWM信号、并在所述标志信号处于所述第二状态时保持所述第一PWM信号和所述第二PWM信号。
  8. 根据权利要求7所述的逆变器启动短路保护装置，其特征在于，所述标志信号生成模块采用将所述第一PWM信号及第二PWM信号进行逻辑与运算的方式生成所述标志信号。
  9. 根据权利要求7所述的逆变器启动短路保护装置，其特征在于，所述信号处理模块采用将所述标志信号与所述第一PWM信号或所述第二PWM信号进行逻辑异或运算的方式滤除/保持相应的所述第一PWM信号或所述第二PWM信号。
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