WO2017156838A1 - 液晶面板驱动系统中的切角电路 - Google Patents

液晶面板驱动系统中的切角电路 Download PDF

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Publication number
WO2017156838A1
WO2017156838A1 PCT/CN2016/081200 CN2016081200W WO2017156838A1 WO 2017156838 A1 WO2017156838 A1 WO 2017156838A1 CN 2016081200 W CN2016081200 W CN 2016081200W WO 2017156838 A1 WO2017156838 A1 WO 2017156838A1
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signal
circuit
liquid crystal
crystal panel
signal converter
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PCT/CN2016/081200
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English (en)
French (fr)
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曹丹
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深圳市华星光电技术有限公司
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Priority to US15/110,190 priority Critical patent/US10186227B2/en
Publication of WO2017156838A1 publication Critical patent/WO2017156838A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0693—Calibration of display systems
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation

Definitions

  • the present invention generally relates to the field of liquid crystal panel driving, and more particularly to a chamfering circuit in a liquid crystal panel driving system.
  • the LCD driving system In order to improve the uniformity of the liquid crystal panel (LCD), it is necessary to reduce the feedback voltage and the line-varying effect.
  • the LCD driving system can be added.
  • the chamfering circuit adjusts the slope of the driving voltage waveform (that is, the chamfer angle) through the chamfering circuit. Since the chamfering voltage of the existing chamfering circuit is fixed, the peripheral circuit can only be increased and the peripheral resistor is changed. To adjust the cut-off voltage (as shown in Figure 1), however, this method not only makes the peripheral circuit wiring more cumbersome, but also increases the cost of the chamfer circuit.
  • the object of the present invention is to provide a chamfering circuit in a liquid crystal panel driving system, so as to solve the existing method of adjusting the corner-cut voltage by arranging a peripheral resistor outside the power management chip to make the peripheral circuit wiring of the power management chip relatively. Troublesome and costly defects.
  • An exemplary embodiment of the present invention provides a chamfering circuit in a liquid crystal panel driving system, wherein the chamfering circuit includes: a controller for providing a first signal to a signal converter; and a signal converter for Converting the first signal into a second signal for controlling discharge of the discharge circuit, and supplying the second signal to the discharge circuit; and the discharge circuit for generating a cut of the chamfer circuit according to the second signal provided by the signal converter Angle voltage.
  • the discharge circuit includes a plurality of current sources connected in parallel and a switch that controls a current source to be turned on or off corresponding to each current source, wherein each switch is turned on in response to a second signal corresponding thereto Or cut off, the outputs of the plurality of parallel current sources are connected to each other to output a corner angle voltage of the chamfer circuit.
  • the controller is a timing controller.
  • the signal converter and the discharge circuit are disposed in a power management chip.
  • the controller provides a first signal to the signal converter based on a parallel communication protocol.
  • each of the first signals includes a clock signal and a data signal.
  • the chamfering circuit in the liquid crystal panel driving system provided by the exemplary embodiment of the present invention, not only the chamfer voltage can be automatically adjusted, but also the peripheral circuit is simplified, and the cost is reduced.
  • FIG. 1 is a structural diagram showing a peripheral resistor provided in a peripheral circuit of a power management chip in the prior art
  • FIG. 2 illustrates a block diagram of a chamfering circuit in a liquid crystal panel driving system according to an exemplary embodiment of the present invention
  • FIG. 3 illustrates an example of a chamfering circuit in a liquid crystal panel driving system according to an exemplary embodiment of the present invention.
  • FIG. 4 illustrates a timing diagram of a chamfer voltage according to an exemplary embodiment of the present invention
  • FIG. 5 is a block diagram showing an internal power supply management chip of the prior art model HX5562R11U;
  • FIG. 6 illustrates an example of a chamfering circuit in a liquid crystal panel driving system according to an exemplary embodiment of the present invention.
  • FIG. 2 illustrates a block diagram of a chamfering circuit in a liquid crystal panel driving system according to an exemplary embodiment of the present invention.
  • the chamfering circuit in the liquid crystal panel driving system includes a controller 10, a signal converter 20, and a discharge circuit 30.
  • controller 10 is operative to provide a first signal to signal converter 20.
  • the controller 10 can provide a first signal to the signal converter 20 based on a parallel communication protocol.
  • each of the first signals may include a clock signal and a data signal, wherein the clock signal and the data signal may pass through a clock pin (SCL pin) of the timing controller, respectively.
  • SCL pin clock pin
  • SDA pin data pin
  • the signal converter 20 is for converting the first signal into a second signal for controlling discharge of the discharge circuit 30, and supplying the plurality of second signals to the discharge circuit 30.
  • the signal converter 20 may convert the first signal into a second signal for controlling discharge of the discharge circuit 30.
  • the interface of the signal converter 20 for example, the SCL pin and the SDA pin
  • the first signal can be parsed into a second signal, for example, when in a first signal.
  • the clock signal and the data signal are both 1, and the signal converter 20 can resolve the first signal into a high level signal.
  • the signal converter 20 can parse a second signal corresponding to each of the first signals.
  • the signal converter 20 can be constructed by any of the existing components that can achieve the above functions.
  • the discharge circuit 30 is operative to generate a chamfer voltage of the chamfer circuit based on the second signal provided by the signal converter 20.
  • the discharge circuit 30 can include a plurality of current sources connected in parallel and a switch that controls the current source to be turned on or off corresponding to each current source, wherein each switch is turned on in response to a second signal corresponding thereto or The output ends of the plurality of parallel current sources are connected to each other to output a corner angle voltage of the chamfer circuit.
  • the switch corresponding to each current source may be a field effect transistor such as an NMOS transistor or a PMOS transistor used as an electronic switch. Specifically, when the switch is turned on, the current source corresponding to the turned-on switch is discharged, so that the corner angle voltage of the chamfer circuit changes.
  • the switch is an NMOS transistor, it is turned on when a high level signal is received, and a current source connected in series with the turned-on NMOS transistor is discharged, so that the corner angle voltage of the chamfer circuit changes.
  • the cut angle voltage can be automatically adjusted.
  • FIG. 3 illustrates an example of a chamfering circuit in a liquid crystal panel driving system according to an exemplary embodiment of the present invention.
  • the signal converter 20 and the discharge circuit 30 may be disposed in the power management chip 100.
  • the discharge circuit 30 in the chamfer circuit may include a plurality of current sources.
  • the discharge circuit 30 in the chamfer circuit of FIG. 3 may include seven parallel current sources A1-A7.
  • each current source is connected in series with a switch.
  • the switch is an NMOS transistor, and the control terminals of each switch (ie, Q1-Q7) are respectively connected to corresponding outputs of the signal converter 20.
  • Pins a1-a7 for example, the a1 output pin of the signal converter 20 is connected to the control terminal of the switch Q1 corresponding to the current source A1. Further, the total output line of the discharge circuit 30 including the current sources A1-A7 (i.e., the total output line after the outputs of the plurality of parallel current sources are connected to each other) can be connected to the cut-angle voltage output terminal VGHM of the power management chip 100.
  • the controller 10 may be disposed outside the power management chip 100.
  • the controller 10 is the timing controller T-CON
  • the clock pin and data pin and timing control of the signal converter 20 The clock pin of the T-CON is connected to the data pin.
  • the control switch pin b of the signal converter 20 is for receiving a control signal.
  • the timing controller T-CON can program and control the signal converter 20 in the power management chip 100 by parallel communication.
  • the timing controller T-CON can pass the clock pin and the data pin according to user settings.
  • Sending a first signal to the signal converter 20 the signal converter 20 can receive the first signal sent by the timing controller T-CON through the clock pin and the data pin when receiving the control signal, and the first signal is sent to the first signal
  • the analysis is performed. For example, when the clock signal and the data signal included in the first signal are 1, the signal converter 20 can resolve the first signal into a high level signal.
  • the signal converter 20 may interpret the plurality of first signals into a plurality of second signals that control switches in series with the current source in chronological order, where as an example, the signal converter 20 may store the parsed plurality of second signals of the switches in series with the current source, and when the predetermined number (eg, 7) is reached, provide the plurality of second signals to The switches in the discharge circuit 30 in series with each current source cause each switch to be turned on or off in response to a signal corresponding thereto, thereby outputting a chamfer voltage of the chamfer circuit.
  • the predetermined number eg, 7
  • FIG. 4 illustrates a timing diagram of a chamfer voltage according to an exemplary embodiment of the present invention.
  • the discharge circuit 30 receives a plurality of second signals at a time to form a single discharge slope and receives a plurality of second signals again, the discharge slope can be changed again.
  • the second signal can form more or even close to the arcuate fillet, and when it reaches a certain level, it will not change.
  • FIG. 5 shows an internal block diagram of the power management chip 100 of the prior art model HX5562R11U.
  • FIG. 6 illustrates an example of a chamfering circuit in a liquid crystal panel driving system according to an exemplary embodiment of the present invention.
  • the signal converter 20 and the discharge circuit 30 may be substituted for the drive circuit PRE_DRV101 and the PMOS transistor Q2102 of FIG. 2, and further, the controller 10 is disposed outside the power management chip 100.
  • the controller 10, the signal converter 20, and the discharge circuit 30 are the same as in FIG.
  • the clock pin and the data pin of the signal converter 20 are respectively connected to the clock pin of the timing controller T-CON and the data pin, and the output of the control switch pin b of the signal converter 20 and the output of the OR circuit.
  • the output of the switch corresponding to each parallel current source in the discharge circuit 30 is connected to the output pin of the signal converter 20, and the total output line of the discharge circuit 30 is connected to the node B.
  • the present invention The connection relationship of the elements of the other circuits in FIG. 6 is the same as the connection relationship of the elements in FIG. 5 in the prior art, and will not be described herein.
  • the power management chip 100 may also be a power management chip other than the HX5562R11U model chip.
  • the chamfering circuit in the liquid crystal panel driving system not only automatically adjusts the corner-cut voltage, but also simplifies the peripheral circuit and reduces the cost.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
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Abstract

一种液晶面板驱动系统的切角电路和包括切角电路的液晶面板驱动系统，其中，切角电路包括：控制器10，用于向信号转换器20提供第一信号；信号转换器20，用于将第一信号转换成用于控制放电电路30放电的第二信号，将第二信号提供给放电电路30；放电电路30，用于根据信号转换器20提供的第二信号产生切角电路的切角电压。根据切角电路，不仅可以自动调节切角电压，还精简了外围电路，降低了成本。

Description

液晶面板驱动系统中的切角电路 技术领域
本发明总体说来涉及液晶面板驱动领域，更具体地讲，尤其涉及一种液晶面板驱动系统中的切角电路。
背景技术
为改善液晶面板(LCD)的均齐度，需要降低回馈电压与线变效应，通常，在现有的LCD的驱动架构中，为降低回馈电压与线变效应，可以在LCD的驱动系统中加入切角电路，并通过切角电路来调整驱动电压波形的斜率(即产生切角)，由于现有的切角电路的切角电压固定，因此，只能增加外围电路并通过变更外围电阻的方式来调整切角电压(如图1所示)，但是，这种方式不仅使得外围电路布线较为繁琐，还提高了切角电路的成本。
发明内容
有鉴于此，本发明目的是提供一种液晶面板驱动系统中的切角电路，以解决现有的通过在电源管理芯片外部布置外围电阻来调整切角电压的方式使电源管理芯片外围电路布线较为繁琐以及成本较高的缺陷。
本发明示例性实施例提供一种液晶面板驱动系统中的切角电路，其特征在于，所述切角电路包括：控制器，用于向信号转换器提供第一信号；信号转换器，用于将所述第一信号转换成用于控制放电电路放电的第二信号，将所述第二信号提供给放电电路；放电电路，用于根据信号转换器提供的第二信号产生切角电路的切角电压。
可选地，所述放电电路包括多个并联的电流源以及与每个电流源相应的控制电流源导通或截止的开关，其中，每个开关响应于与其相应的第二信号导通 或截止，所述多个并联的电流源的输出端彼此相连以输出切角电路的切角电压。
可选地，所述控制器为时序控制器。
可选地，所述信号转换器和放电电路设置于电源管理芯片中。
可选地，所述控制器基于并行通信协议向信号转换器提供第一信号。
可选地，每个第一信号包括一个时钟信号和一个数据信号。
根据本发明示例性实施例提供的液晶面板驱动系统中的切角电路，不仅可以自动调节切角电压，还精简了外围电路，降低了成本。
附图说明
通过下面结合附图进行的详细描述，本发明示例性实施例的上述和其它目的、特点和优点将会变得更加清楚，其中：
图1示出现有技术中电源管理芯片的外围电路中设置有外围电阻的结构图；
图2示出根据本发明示例性实施例的液晶面板驱动系统中的切角电路的框图；
图3示出根据本发明示例性实施例的液晶面板驱动系统中的切角电路的示例。
图4示出根据本发明示例性实施例的切角电压的时序图；
图5示出现有技术中型号为HX5562R11U的电源管理芯片的内部框图；
图6示出根据本发明的示例性实施例的液晶面板驱动系统中的切角电路的示例。
具体实施方式
现在，将参照附图更充分地描述不同的示例实施例，其中，一些示例性实施例在附图中示出，其中，相同的标号始终表示相同的部件。
图2示出根据本发明示例性实施例的液晶面板驱动系统中的切角电路的框图。
如图2所示，根据本发明的液晶面板驱动系统中的切角电路包括：控制器10、信号转换器20和放电电路30。
具体说来，控制器10用于向信号转换器20提供第一信号。
这里，所述控制器10可基于并行通信协议向信号转换器20提供第一信号。当所述控制器10为时序控制器时，每个第一信号可包括一个时钟信号和一个数据信号，其中，所述时钟信号和数据信号可分别通过时序控制器的时钟引脚(SCL pin)和数据引脚(SDA pin)输出。
信号转换器20用于将所述第一信号转换成用于控制放电电路30放电的第二信号，将所述多个第二信号提供给放电电路30。
这里，作为示例，信号转换器20可将所述第一信号转换成用于控制放电电路30放电的第二信号。具体说来，当所述信号转换器20的接口(例如，SCL pin和SDA pin)接收到一个第一信号时，可将第一信号解析成第二信号，例如，当一个第一信号中的时钟信号和数据信号都为1，信号转换器20可将该第一信号解析为一个高电平信号。类似地，当按时间顺序接收多个第一信号时，信号转换器20可解析出与所述每个第一信号对应的第二信号。这里，应理解，信号转换器20可通过现有的任何可以实现上述功能的元件构成。
放电电路30用于根据信号转换器20提供的第二信号产生切角电路的切角电压。
作为示例，所述放电电路30可包括多个并联的电流源以及与每个电流源相应的控制电流源导通或截止的开关，其中，每个开关响应于与其相应的第二信号导通或截止，所述多个并联的电流源的输出端彼此相连以输出切角电路的切角电压。这里，作为示例，所述与每个电流源相应的开关可以是被用作电子开关的NMOS管、PMOS管等场效应管。具体说来，当开关导通时，与该导通的开关相应的电流源放电，使得所述切角电路的切角电压发生改变。例如，当开关为NMOS管时，在接收到高电平信号时导通，与该导通的NMOS管串联的电流源放电，使得所述切角电路的切角电压发生改变。
通过上述方式，可以自动地调节切角电压。
图3示出根据本发明示例性实施例的液晶面板驱动系统中的切角电路的示例。
参照图3，作为示例，所述信号转换器20和放电电路30可设置于电源管理芯片100中。具体说来，切角电路中的放电电路30可包括多个电流源，例如，图3中切角电路中的放电电路30可包括7个并联的电流源A1-A7，当然，也可以更多或少，但至少两个以上，每个电流源都串联一个开关，作为示例，所述开关为NMOS管，每个开关(即，Q1-Q7)的控制端分别连接信号转换器20相应的输出引脚a1-a7，例如，信号转换器20的a1输出引脚连接电流源A1所对应的开关Q1的控制端。此外，包括电流源A1-A7的放电电路30的总输出线(即，多个并联的电流源的输出端彼此相连后的总输出线)可连接电源管理芯片100的切角电压输出端VGHM。此外，作为示例，控制器10可设置于电源管理芯片100之外，这里，在控制器10为时序控制器T-CON的情况下，信号转换器20的时钟引脚与数据引脚与时序控制器T-CON的时钟引脚与数据引脚相连。信号转换器20的控制开关引脚b用于接收控制信号。
以下，对根据本发明示例性实施例的液晶面板驱动系统中的切角电路的工作原理进行描述。
具体说来，时序控制器T-CON可以通过并行通信方式对电源管理芯片100中的信号转换器20进行编程控制，例如，时序控制器T-CON可根据用户设置通过时钟引脚和数据引脚向信号转换器20发送第一信号，信号转换器20可在接收到控制信号时，通过时钟引脚和数据引脚接收时序控制器T-CON发送的第一信号，并对所述第一信号进行解析，例如，当第一信号包括的时钟信号和数据信号为1时，信号转换器20可将该第一信号解析为一个高电平信号。类似地，当有多个(例如，7个)第一信号时，信号转换器20可按时间顺序将多个第一信号解析为多个控制与电流源串联的开关的第二信号，这里，作为示例，信号转换器20可将解析后的多个控制与电流源串联的开关的第二信号进行存储，当到达预定数量(例如，7个)时，将所述多个第二信号提供给放电电路30中与每个电流源串联的开关，使每个开关响应于与其相应的信号导通或截止，从而输出切角电路的切角电压。
图4示出根据本发明示例性实施例的切角电压的时序图。
由于放电电路30通过一次接收多个第二信号以形成一次放电斜率，再次接收多个第二信号时，放电斜率可以再次发生改变，当然，可以推断，如图4所示，通过发送更多次第二信号，可以形成更多甚至接近弧线形的圆角，当到达一定程度时，将不再变化。
下面，将以所述切角电路应用于HX5562R11U型号电源管理芯片100为例来进行描述，图5示出现有技术中型号为HX5562R11U的电源管理芯片100的内部框图。图6示出根据本发明的示例性实施例的液晶面板驱动系统中的切角电路的示例。
参照图5和图6，作为示例，可将信号转换器20和放电电路30替代图2中的驱动电路PRE_DRV101和PMOS管Q2102，此外，控制器10设置于电源管理芯片100外。这里，控制器10、信号转换器20和放电电路30与图3中相同。具体说来，信号转换器20的时钟引脚与数据引脚分别与时序控制器T-CON的时钟引脚与数据引脚相连，信号转换器20的控制开关引脚b与或门电路的输出端相连，放电电路30中的与每个并联的电流源相应的开关的输出端与信号转换器20的输出引脚相连，放电电路30的总输出线连接节点B，这里，应注意，本发明不限于此，图6中的其他电路的元件的连接关系与现有技术中的图5中的元件的连接关系相同，在此就不再赘述。此外，应理解，电源管理芯片100还可以是除了HX5562R11U型号芯片之外的其他电源管理芯片。
综上所述，根据本发明示例性实施例的液晶面板驱动系统中的切角电路，不仅可以自动地调节切角电压，还精简了外围电路，降低了成本。
显然，本发明的保护范围并不局限于上诉的具体实施方式，本领域的技术人员可以对发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (12)

  1. 一种液晶面板驱动系统中的切角电路，其中，所述切角电路包括：
    控制器，用于向信号转换器提供第一信号；
    信号转换器，用于将所述第一信号转换成用于控制放电电路放电的第二信号，将所述第二信号提供给放电电路；
    放电电路，用于根据信号转换器提供的第二信号产生切角电路的切角电压。
  2. 如权利要求1所述的切角电路，其中，所述放电电路包括多个并联的电流源以及与每个电流源相应的控制电流源导通或截止的开关，其中，每个开关响应于与其相应的第二信号导通或截止，所述多个并联的电流源的输出端彼此相连以输出切角电路的切角电压。
  3. 如权利要求1所述的切角电路，其中，所述控制器为时序控制器。
  4. 如权利要求1所述的切角电路，其中，所述信号转换器和放电电路设置于电源管理芯片中。
  5. 如权利要求1所述的切角电路，其中，所述控制器基于并行通信协议向信号转换器提供第一信号。
  6. 如权利要求1所述的切角电路，其中，每个第一信号包括一个时钟信号和一个数据信号。
  7. 一种液晶面板驱动系统，包括切角电路，其中，所述切角电路包括：
    控制器，用于向信号转换器提供第一信号；
    信号转换器，用于将所述第一信号转换成用于控制放电电路放电的第二信号，将所述第二信号提供给放电电路；
    放电电路，用于根据信号转换器提供的第二信号产生切角电路的切角电压。
  8. 如权利要求7所述液晶面板驱动系统，其中，所述放电电路包括多个并联的电流源以及与每个电流源相应的控制电流源导通或截止的开关，其中，每个开关响应于与其相应的第二信号导通或截止，所述多个并联的电流源的输出端彼此相连以输出切角电路的切角电压。
  9. 如权利要求7所述液晶面板驱动系统，其中，所述控制器为时序控制器。
  10. 如权利要求7所述液晶面板驱动系统，其中，所述信号转换器和放电电路设置于电源管理芯片中。
  11. 如权利要求7所述液晶面板驱动系统，其中，所述控制器基于并行通信协议向信号转换器提供第一信号。
  12. 如权利要求7所述液晶面板驱动系统，其中，每个第一信号包括一个时钟信号和一个数据信号。
PCT/CN2016/081200 2016-03-18 2016-05-06 液晶面板驱动系统中的切角电路 WO2017156838A1 (zh)

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