WO2017147811A1 - 一种高性能新型定时器 - Google Patents

一种高性能新型定时器 Download PDF

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Publication number
WO2017147811A1
WO2017147811A1 PCT/CN2016/075304 CN2016075304W WO2017147811A1 WO 2017147811 A1 WO2017147811 A1 WO 2017147811A1 CN 2016075304 W CN2016075304 W CN 2016075304W WO 2017147811 A1 WO2017147811 A1 WO 2017147811A1
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resistor
integrated circuit
transistor
circuit
externally connected
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PCT/CN2016/075304
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French (fr)
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马骏
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马骏
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/28—Modifications for introducing a time delay before switching

Definitions

  • the invention relates to a high performance novel timer.
  • the technical problem to be solved by the present invention is to provide a high-performance novel timer in order to overcome the deficiencies of the prior art that the volume is too large and the performance is low.
  • a high performance novel timer including a timing circuit, the timing circuit including a first stage delay circuit and a second level delay circuit, and the first stage delay circuit and Secondary delay circuit connection;
  • the first stage delay circuit includes a first integrated circuit, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, and a first resistor a ten-resistor, a first capacitor, a first triode, and a second triode, wherein the first integrated circuit is of type CA3089, and the input end of the first integrated circuit is externally connected to a 9V DC voltage source through the first capacitor.
  • the input end of the first integrated circuit is grounded through a series circuit composed of a sixth resistor and a seventh resistor, and the power supply terminal and the current control terminal of the first integrated circuit are externally connected with a 9V DC voltage power supply, and the current of the first integrated circuit
  • the feedback terminal is externally connected to the 9V DC voltage power supply through the fourth resistor, the ground end of the first integrated circuit is grounded, and the high-level reference end of the first integrated circuit is externally connected to the 9V DC voltage power supply through the first resistor, the first set a high-level reference terminal of the circuit is connected to a low-level reference terminal of the first integrated circuit through a second resistor, and a low-level reference terminal of the first integrated circuit is grounded through a third resistor, the first integrated circuit
  • the output terminal is externally connected to the 9V DC voltage power supply through the fifth resistor, and the output end of the first integrated circuit is connected to the base of the first triode through an eighth resistor, and the output end of the first integrated circuit passes through the ninth resistor
  • the second-stage delay circuit includes a second integrated circuit, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, and a tenth An eight-resistor, a second capacitor, a third transistor, and a fourth transistor, wherein the second integrated circuit is of the type CA3089, and the input end of the second integrated circuit is externally connected to the 9V DC voltage source through the second capacitor.
  • the input end of the second integrated circuit is connected to the collector of the fourth triode through a series circuit composed of a sixteenth resistor and a seventeenth resistor, and the power supply terminal and the current control terminal of the second integrated circuit are externally connected with 9V DC.
  • a voltage power supply the current feedback end of the second integrated circuit is externally connected to the 9V DC voltage power supply through the fourteenth resistor, the ground end of the second integrated circuit is grounded, and the high-level reference end of the second integrated circuit passes the tenth a resistor is externally connected to the 9V DC voltage source, and the high-level reference terminal of the second integrated circuit is connected to the low-level reference terminal of the second integrated circuit through the twelfth resistor, and the low-level reference terminal of the second integrated circuit Through the first
  • the three-resistor is grounded, the output end of the second integrated circuit is externally connected to the 9V DC voltage source through the fifteenth resistor, and the output end of the second integrated circuit is connected to the base of the third triode through the eighte
  • the emitter of the fourth transistor is grounded, the emitter of the third transistor is externally connected to a 9V DC voltage source, and the base of the fourth transistor is connected to the collector of the second transistor.
  • the collector of the fourth transistor is connected to the collector of the third transistor through a seventeenth resistor.
  • the first triode and the third triode are both PNP triodes.
  • the second triode and the fourth triode are both NPN triodes.
  • the capacitance of the second capacitor is 16 uF.
  • the beneficial effect of the invention is that the high-performance new timer performs a first-level delay through the first-stage delay circuit, and then triggers the second-level delay circuit, and the second-level delay circuit continues to perform the second-level delay, thereby realizing The delay time of several hours ensures the reliability of the timer delay.
  • the circuit is dominated by the second integrated circuit, and the resistance of the sixteenth resistor is 22M ⁇ , the seventeenth The resistance of the resistor is 100k ⁇ , and the capacitance of the second capacitor is 16 ⁇ F, which ensures that the delay time of the two-stage delay circuit reaches the hour, which reduces the volume of the timer and improves the high performance of the timer.
  • FIG. 1 is a circuit schematic diagram of a timing circuit of a high performance novel timer of the present invention
  • First stage delay circuit 2. Second stage delay circuit, U1. First integrated circuit, U2. Second integrated circuit, R1. First resistance, R2. Second resistance, R3. Third resistance , R4. Fourth resistor, R5. Fifth resistor, R6. Sixth resistor, R7. Seventh resistor, R8. Eighth resistor, R9. Ninth resistor, R10. Tenth resistor, R11. Eleventh resistor, R12. Twelfth resistor, R13. Thirteenth resistor, R14. Fourteenth resistor, R15. Fifteenth resistor, R16. Sixteenth resistor, R17. Seventeenth resistor, R18. Eighteenth resistor, C1 The first capacitor, C2. second capacitor, Q1. first triode, Q2. second triode, Q3. third triode, Q4. fourth triode.
  • a high performance novel timer includes a timing circuit, and the timing circuit includes a first delay circuit 1 and a second delay circuit 2, and the first stage delay circuit 1 and the second stage delay Circuit 2 is connected;
  • the first stage delay circuit 1 includes a first integrated circuit U1, a first resistor R1, and a second resistor R2. Three resistor R3, fourth resistor R4, fifth resistor R5, sixth resistor R6, seventh resistor R7, eighth resistor R8, ninth resistor R9, tenth resistor R10, first capacitor C1, first transistor Q1 And the second transistor Q2, the first integrated circuit U1 is of the type CA3089, the input end of the first integrated circuit U1 is externally connected to the 9V DC voltage source through the first capacitor C1, and the input of the first integrated circuit U1 The terminal is grounded through a series circuit composed of a sixth resistor R6 and a seventh resistor R7.
  • the power supply terminal and the current control terminal of the first integrated circuit U1 are externally connected with a 9V DC voltage power supply, and the current feedback end of the first integrated circuit U1 passes through
  • the fourth resistor R4 is externally connected to the 9V DC voltage source, the ground of the first integrated circuit U1 is grounded, and the high-level reference terminal of the first integrated circuit U1 is externally connected to the 9V DC voltage source through the first resistor R1, the first The high-level reference terminal of the integrated circuit U1 is connected to the low-level reference terminal of the first integrated circuit U1 through the second resistor R2, and the low-level reference terminal of the first integrated circuit U1 is grounded through the third resistor R3.
  • the output of the first integrated circuit U1 passes through the fifth
  • the resistor R5 is externally connected to the 9V DC voltage source, and the output end of the first integrated circuit U1 is connected to the base of the first transistor Q1 through the eighth resistor R8, and the output end of the first integrated circuit U1 passes through the ninth resistor R9.
  • the emitter of the second transistor Q2 is grounded, the emitter of the first transistor Q1 is externally connected to a 9V DC voltage source, and the first transistor Q1
  • the collector is grounded through a seventh resistor R7, and the collector of the second transistor Q2 is externally connected to a 9V DC voltage source through a tenth resistor R10;
  • the second-stage delay circuit 2 includes a second integrated circuit U2, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, and a sixteenth resistor R16.
  • the seventeenth resistor R17, the eighteenth resistor R18, the second capacitor C2, the third transistor Q3 and the fourth transistor Q4, the second integrated circuit U2 is of the type CA3089, the second integrated circuit
  • the input end of the U2 is externally connected to the 9V DC voltage source through the second capacitor C2, and the input end of the second integrated circuit U2 passes through the series circuit of the sixteenth resistor R16 and the seventeenth resistor R17 and the set of the fourth triode Q4.
  • Electrode connection, the power supply end and the current control end of the second integrated circuit U2 are externally connected with a 9V DC voltage power supply, the second set The current feedback terminal of the circuit U2 is externally connected to the 9V DC voltage power supply through the fourteenth resistor R14, the ground terminal of the second integrated circuit U2 is grounded, and the high-level reference terminal of the second integrated circuit U2 passes the eleventh resistor R11.
  • the high-level reference terminal of the second integrated circuit U2 is connected to the low-level reference terminal of the second integrated circuit U2 through the twelfth resistor R12, and the low level of the second integrated circuit U2
  • the reference terminal is grounded through the thirteenth resistor R13, the output end of the second integrated circuit U2 is externally connected to the 9V DC voltage source through the fifteenth resistor R15, and the output end of the second integrated circuit U2 is passed through the eighteenth resistor R18 and the
  • the base of the triode Q3 is connected, the emitter of the fourth transistor Q4 is grounded, the emitter of the third transistor Q3 is externally connected to a 9V DC voltage source, and the base of the fourth transistor Q4 is The pole is connected to the collector of the second transistor Q2, and the collector of the fourth transistor Q4 is connected to the collector of the third transistor Q3 through the seventeenth resistor R17.
  • the first transistor Q1 and the third transistor Q3 are both PNP transistors.
  • the second transistor Q2 and the fourth transistor Q4 are both NPN transistors.
  • the capacitance of the second capacitor C2 is 16 uF.
  • the timing circuit includes a first-stage delay circuit 1 and a second-stage delay circuit 2, first performing a first-level delay through the first-stage delay circuit 1, and then triggering the second-level delay circuit 2, The stage delay circuit 2 continues the two-stage delay, thereby achieving a delay time of up to several hours.
  • the first integrated circuit U1 of the first-stage delay circuit 1 is CA3098, and the circuit is mainly composed of the first integrated circuit U1, and is passed through the first resistor R1, the second resistor R2, and the third resistor R3.
  • the precision measurement of an integrated circuit U1 is followed by the input of the first capacitor C1. As the first capacitor C1 is attenuated, the signal voltage at the input changes.
  • the first integrated circuit U1 controls.
  • the second diode Q2 is turned on, and then the second capacitor C2 is turned on, then the second delay circuit 2 continues to start delay;
  • the second integrated circuit U2 in the second delay circuit 2 is of the type CA3098, the circuit
  • the second integrated circuit U2 is mainly used, and the resistance of the sixteenth resistor R16 is 22 M ⁇ , and the resistance of the seventeenth resistor R17 is The capacitance of 100k ⁇ and the second capacitor C2 is 16 ⁇ F, so that the delay time of the second delay circuit 2 can be guaranteed to reach 4 hours.
  • the high-performance new timer performs a first-level delay through the first-stage delay circuit 1, and then triggers the second-level delay circuit 2, and the second-level delay circuit 2 continues the second-level delay.
  • the delay time of several hours is realized, and the reliability of the timer delay is ensured;
  • the circuit is mainly composed of the second integrated circuit U2, and the resistance of the sixteenth resistor R16
  • the resistance of the seventeenth resistor R17 is 100k ⁇
  • the capacitance of the second capacitor C2 is 16 ⁇ F

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Abstract

一种高性能新型定时器，包括定时电路，所述定时电路包括一级延时电路（1）和二级延时电路（2），所述一级延时电路（1）与二级延时电路（2）连接，该高性能新型定时器通过一级延时电路（1）进行一级延时，随后触发二级延时电路（2），二级延时电路（2）就会继续进行二级延时，从而实现了长达几小时的延时时间，保证了定时器延时的可靠性；同时二级延时电路（2）中，该电路以第二集成电路（U2）为主，第十六电阻（R16）的阻值为22MΩ、第十七电阻（R17）的阻值为100kΩ、第二电容（C2）的容值为16Μf，则就能够保证二级延时电路（2）的延时时间达到小时，进而降低了定时器的体积，提高了定时器的高性能。

Description

一种高性能新型定时器 技术领域
本发明涉及一种高性能新型定时器。
背景技术
随着科技的发展和社会的进步，我国的科学技术水平得到了显著的提升，而电力电子技术也有着明显的进步。
在我国的定时器市场上，很多都是采用的大容量、低漏电的电容器来进行长时间地定时，但是由于随着人们对于产品小型化和高性能的要求越来越高，这种以大体积且高性能的电容器为主的定时电路已经无法满足人们的需求。
发明内容
本发明要解决的技术问题是：为了克服现有技术体积过大且性能低的不足，提供一种高性能新型定时器。
本发明解决其技术问题所采用的技术方案是：一种高性能新型定时器，包括定时电路，所述定时电路包括一级延时电路和二级延时电路，所述一级延时电路与二级延时电路连接；
所述一级延时电路包括第一集成电路、第一电阻、第二电阻、第三电阻、第四电阻、第五电阻、第六电阻、第七电阻、第八电阻、第九电阻、第十电阻、第一电容、第一三极管和第二三极管，所述第一集成电路的型号为CA3089，所述第一集成电路的输入端通过第一电容外接9V直流电压电源，所述第一集成电路的输入端通过第六电阻和第七电阻组成的串联电路接地，所述第一集成电路的电源端和电流控制端均外接9V直流电压电源，所述第一集成电路的电流反馈端通过第四电阻外接9V直流电压电源，所述第一集成电路的接地端接地，所述第一集成电路的高电平基准端通过第一电阻外接9V直流电压电源，所述第一集 成电路的高电平基准端通过第二电阻与第一集成电路的低电平基准端连接，所述第一集成电路的低电平基准端通过第三电阻接地，所述第一集成电路的输出端通过第五电阻外接9V直流电压电源，所述第一集成电路的输出端通过第八电阻与第一三极管的基极连接，所述第一集成电路的输出端通过第九电阻与第二三极管的基极连接，所述第二三极管的发射极接地，所述第一三极管的发射极外接9V直流电压电源，所述第一三极管的集电极通过第七电阻接地，所述第二三极管的集电极通过第十电阻外接9V直流电压电源；
所述二级延时电路包括第二集成电路、第十一电阻、第十二电阻、第十三电阻、第十四电阻、第十五电阻、第十六电阻、第十七电阻、第十八电阻、第二电容、第三三极管和第四三极管，所述第二集成电路的型号为CA3089，所述第二集成电路的输入端通过第二电容外接9V直流电压电源，所述第二集成电路的输入端通过第十六电阻和第十七电阻组成的串联电路与第四三极管的集电极连接，所述第二集成电路的电源端和电流控制端均外接9V直流电压电源，所述第二集成电路的电流反馈端通过第十四电阻外接9V直流电压电源，所述第二集成电路的接地端接地，所述第二集成电路的高电平基准端通过第十一电阻外接9V直流电压电源，所述第二集成电路的高电平基准端通过第十二电阻与第二集成电路的低电平基准端连接，所述第二集成电路的低电平基准端通过第十三电阻接地，所述第二集成电路的输出端通过第十五电阻外接9V直流电压电源，所述第二集成电路的输出端通过第十八电阻与第三三极管的基极连接，所述第四三极管的发射极接地，所述第三三极管的发射极外接9V直流电压电源，所述第四三极管的基极与第二三极管的集电极连接，所述第四三极管的集电极通过第十七电阻与第三三极管的集电极连接。
作为优选，所述第一三极管和第三三极管均为PNP三极管。
作为优选，所述第二三极管和第四三极管均为NPN三极管。
作为优选，所述第二电容的容值为16uF。
本发明的有益效果是，该高性能新型定时器通过一级延时电路进行一级延时，随后触发二级延时电路，二级延时电路就会继续进行二级延时，从而实现了长达几小时的延时时间，保证了定时器延时的可靠性；同时二级延时电路中，该电路以第二集成电路为主，第十六电阻的阻值为22MΩ、第十七电阻的阻值为100kΩ、第二电容的容值为16μF，则就能够保证二级延时电路的延时时间达到小时，进而降低了定时器的体积，提高了定时器的高性能。
附图说明
下面结合附图和实施例对本发明进一步说明。
图1是本发明高性能新型定时器的定时电路的电路原理图；
图中：1.一级延时电路，2.二级延时电路，U1.第一集成电路，U2.第二集成电路，R1.第一电阻，R2.第二电阻，R3.第三电阻，R4.第四电阻，R5.第五电阻，R6.第六电阻，R7.第七电阻，R8.第八电阻，R9.第九电阻，R10.第十电阻，R11.第十一电阻，R12.第十二电阻，R13.第十三电阻，R14.第十四电阻，R15.第十五电阻，R16.第十六电阻，R17.第十七电阻，R18.第十八电阻，C1.第一电容，C2.第二电容，Q1.第一三极管，Q2.第二三极管，Q3.第三三极管，Q4.第四三极管。
具体实施方式
现在结合附图对本发明作进一步详细的说明。这些附图均为简化的示意图，仅以示意方式说明本发明的基本结构，因此其仅显示与本发明有关的构成。
如图1所示，一种高性能新型定时器，包括定时电路，所述定时电路包括一级延时电路1和二级延时电路2，所述一级延时电路1与二级延时电路2连接；
所述一级延时电路1包括第一集成电路U1、第一电阻R1、第二电阻R2、第 三电阻R3、第四电阻R4、第五电阻R5、第六电阻R6、第七电阻R7、第八电阻R8、第九电阻R9、第十电阻R10、第一电容C1、第一三极管Q1和第二三极管Q2，所述第一集成电路U1的型号为CA3089，所述第一集成电路U1的输入端通过第一电容C1外接9V直流电压电源，所述第一集成电路U1的输入端通过第六电阻R6和第七电阻R7组成的串联电路接地，所述第一集成电路U1的电源端和电流控制端均外接9V直流电压电源，所述第一集成电路U1的电流反馈端通过第四电阻R4外接9V直流电压电源，所述第一集成电路U1的接地端接地，所述第一集成电路U1的高电平基准端通过第一电阻R1外接9V直流电压电源，所述第一集成电路U1的高电平基准端通过第二电阻R2与第一集成电路U1的低电平基准端连接，所述第一集成电路U1的低电平基准端通过第三电阻R3接地，所述第一集成电路U1的输出端通过第五电阻R5外接9V直流电压电源，所述第一集成电路U1的输出端通过第八电阻R8与第一三极管Q1的基极连接，所述第一集成电路U1的输出端通过第九电阻R9与第二三极管Q2的基极连接，所述第二三极管Q2的发射极接地，所述第一三极管Q1的发射极外接9V直流电压电源，所述第一三极管Q1的集电极通过第七电阻R7接地，所述第二三极管Q2的集电极通过第十电阻R10外接9V直流电压电源；
所述二级延时电路2包括第二集成电路U2、第十一电阻R11、第十二电阻R12、第十三电阻R13、第十四电阻R14、第十五电阻R15、第十六电阻R16、第十七电阻R17、第十八电阻R18、第二电容C2、第三三极管Q3和第四三极管Q4，所述第二集成电路U2的型号为CA3089，所述第二集成电路U2的输入端通过第二电容C2外接9V直流电压电源，所述第二集成电路U2的输入端通过第十六电阻R16和第十七电阻R17组成的串联电路与第四三极管Q4的集电极连接，所述第二集成电路U2的电源端和电流控制端均外接9V直流电压电源，所述第二集 成电路U2的电流反馈端通过第十四电阻R14外接9V直流电压电源，所述第二集成电路U2的接地端接地，所述第二集成电路U2的高电平基准端通过第十一电阻R11外接9V直流电压电源，所述第二集成电路U2的高电平基准端通过第十二电阻R12与第二集成电路U2的低电平基准端连接，所述第二集成电路U2的低电平基准端通过第十三电阻R13接地，所述第二集成电路U2的输出端通过第十五电阻R15外接9V直流电压电源，所述第二集成电路U2的输出端通过第十八电阻R18与第三三极管Q3的基极连接，所述第四三极管Q4的发射极接地，所述第三三极管Q3的发射极外接9V直流电压电源，所述第四三极管Q4的基极与第二三极管Q2的集电极连接，所述第四三极管Q4的集电极通过第十七电阻R17与第三三极管Q3的集电极连接。
作为优选，所述第一三极管Q1和第三三极管Q3均为PNP三极管。
作为优选，所述第二三极管Q2和第四三极管Q4均为NPN三极管。
作为优选，所述第二电容C2的容值为16uF。
该高性能新型定时器中，该定时电路包括一级延时电路1和二级延时电路2，首先通过一级延时电路1进行一级延时，随后触发二级延时电路2，二级延时电路2就会继续进行二级延时，从而实现了长达几小时的延时时间。其中一级延时电路1中的第一集成电路U1的型号为CA3098，该电路以第一集成电路U1为主，通过第一电阻R1、第二电阻R2和第三电阻R3为基准，通过第一集成电路U1的精密测量，随后由第一电容C1连接输入信号，随着第一电容C1的衰减，则输入端的信号电压发生改变，当信号到达一定值时，第一集成电路U1就会控制第二二极管Q2导通，继而使得第二电容C2导通，则二级延时电路2继续开始延时；二级延时电路2中的第二集成电路U2的型号为CA3098，该电路以第二集成电路U2为主，第十六电阻R16的阻值为22MΩ、第十七电阻R17的阻值为 100kΩ、第二电容C2的容值为16μF，则就能够保证二级延时电路2的延时时间达到4小时。
与现有技术相比，该高性能新型定时器通过一级延时电路1进行一级延时，随后触发二级延时电路2，二级延时电路2就会继续进行二级延时，从而实现了长达几小时的延时时间，保证了定时器延时的可靠性；同时二级延时电路2中，该电路以第二集成电路U2为主，第十六电阻R16的阻值为22MΩ、第十七电阻R17的阻值为100kΩ、第二电容C2的容值为16μF，则就能够保证二级延时电路2的延时时间达到4小时，进而降低了定时器的体积，提高了定时器的高性能。
以上述依据本发明的理想实施例为启示，通过上述的说明内容，相关工作人员完全可以在不偏离本项发明技术思想的范围内，进行多样的变更以及修改。本项发明的技术性范围并不局限于说明书上的内容，必须要根据权利要求范围来确定其技术性范围。

Claims (4)

  1. 一种高性能新型定时器，其特征在于，包括定时电路，所述定时电路包括一级延时电路(1)和二级延时电路(2)，所述一级延时电路(1)与二级延时电路(2)连接；
    所述一级延时电路(1)包括第一集成电路(U1)、第一电阻(R1)、第二电阻(R2)、第三电阻(R3)、第四电阻(R4)、第五电阻(R5)、第六电阻(R6)、第七电阻(R7)、第八电阻(R8)、第九电阻(R9)、第十电阻(R10)、第一电容(C1)、第一三极管(Q1)和第二三极管(Q2)，所述第一集成电路(U1)的型号为CA3089，所述第一集成电路(U1)的输入端通过第一电容(C1)外接9V直流电压电源，所述第一集成电路(U1)的输入端通过第六电阻(R6)和第七电阻(R7)组成的串联电路接地，所述第一集成电路(U1)的电源端和电流控制端均外接9V直流电压电源，所述第一集成电路(U1)的电流反馈端通过第四电阻(R4)外接9V直流电压电源，所述第一集成电路(U1)的接地端接地，所述第一集成电路(U1)的高电平基准端通过第一电阻(R1)外接9V直流电压电源，所述第一集成电路(U1)的高电平基准端通过第二电阻(R2)与第一集成电路(U1)的低电平基准端连接，所述第一集成电路(U1)的低电平基准端通过第三电阻(R3)接地，所述第一集成电路(U1)的输出端通过第五电阻(R5)外接9V直流电压电源，所述第一集成电路(U1)的输出端通过第八电阻(R8)与第一三极管(Q1)的基极连接，所述第一集成电路(U1)的输出端通过第九电阻(R9)与第二三极管(Q2)的基极连接，所述第二三极管(Q2)的发射极接地，所述第一三极管(Q1)的发射极外接9V直流电压电源，所述第一三极管(Q1)的集电极通过第七电阻(R7)接地，所述第二三极管(Q2)的集电极通过第十电阻(R10)外接9V直流电压电源；
    所述二级延时电路(2)包括第二集成电路(U2)、第十一电阻(R11)、第 十二电阻(R12)、第十三电阻(R13)、第十四电阻(R14)、第十五电阻(R15)、第十六电阻(R16)、第十七电阻(R17)、第十八电阻(R18)、第二电容(C2)、第三三极管(Q3)和第四三极管(Q4)，所述第二集成电路(U2)的型号为CA3089，所述第二集成电路(U2)的输入端通过第二电容(C2)外接9V直流电压电源，所述第二集成电路(U2)的输入端通过第十六电阻(R16)和第十七电阻(R17)组成的串联电路与第四三极管(Q4)的集电极连接，所述第二集成电路(U2)的电源端和电流控制端均外接9V直流电压电源，所述第二集成电路(U2)的电流反馈端通过第十四电阻(R14)外接9V直流电压电源，所述第二集成电路(U2)的接地端接地，所述第二集成电路(U2)的高电平基准端通过第十一电阻(R11)外接9V直流电压电源，所述第二集成电路(U2)的高电平基准端通过第十二电阻(R12)与第二集成电路(U2)的低电平基准端连接，所述第二集成电路(U2)的低电平基准端通过第十三电阻(R13)接地，所述第二集成电路(U2)的输出端通过第十五电阻(R15)外接9V直流电压电源，所述第二集成电路(U2)的输出端通过第十八电阻(R18)与第三三极管(Q3)的基极连接，所述第四三极管(Q4)的发射极接地，所述第三三极管(Q3)的发射极外接9V直流电压电源，所述第四三极管(Q4)的基极与第二三极管(Q2)的集电极连接，所述第四三极管(Q4)的集电极通过第十七电阻(R17)与第三三极管(Q3)的集电极连接。
  2. 如权利要求1所述的高性能新型定时器，其特征在于，所述第一三极管(Q1)和第三三极管(Q3)均为PNP三极管。
  3. 如权利要求1所述的高性能新型定时器，其特征在于，所述第二三极管(Q2)和第四三极管(Q4)均为NPN三极管。
  4. 如权利要求1所述的高性能新型定时器，其特征在于，所述第二电容(C2)的容值为16uF。
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