WO2017138628A1

WO2017138628A1 - Voltage adjustment circuit

Info

Publication number: WO2017138628A1
Application number: PCT/JP2017/004877
Authority: WO
Inventors: 田野井　聡; 哲郎遠藤
Original assignee: 国立大学法人東北大学
Priority date: 2016-02-12
Filing date: 2017-02-10
Publication date: 2017-08-17
Also published as: JP6656660B2; JPWO2017138628A1

Abstract

With improved integration levels of semiconductor integrated circuits, and advances in lower voltage for power supply voltage in order to reduce power consumption, there is a tendency for there to be a large effect even with small voltage errors. Therefore, in order to stabilize output voltage promptly in a prescribed time, with higher resolution, higher precision, and superior linearity using a voltage adjustment circuit, this voltage adjustment circuit is provided with a current control unit (Amp) that uses reference voltage as an input, a first resistor (R_L), and a variable resistor (TR1) connected between the output of the current control unit and the first resistor. The variable resistor is configured from a plurality of resistance selection circuits (SEL1, SEL2, …). Each of the resistance selection circuits is respectively provided with: a second resistor (Rs1, Rs2, …) connected to the output of the current control unit; a first switch (S1, S2, …) connected between the first resistor and the second resistor; and a second switch (S1f, S2f, …) connected between the second resistor and the input of the current control unit, the second switch applying voltage feedback. The first switch and the second switch are linked for turning on and off.

Description

Voltage adjustment circuit

The present invention relates to a voltage adjustment circuit for a semiconductor integrated circuit.

In a semiconductor integrated circuit, various reference voltages are required for a predetermined operation. Examples of such a reference voltage include a PTAT (Proportional to Absolute Temperature) voltage that is proportional to temperature. In the case of the PTAT voltage, it is desirable that the voltage is determined only by a predetermined parameter and temperature without being affected by a power supply voltage to be applied (hereinafter, may be abbreviated as “V _DD ”) or a change in manufacturing conditions. .

Therefore, a voltage adjustment circuit is used in conjunction with the reference voltage generation circuit in order to cancel the influence of fluctuations in the power supply voltage V _DD and manufacturing conditions. FIG. 3 is a diagram showing an application example of the voltage adjustment circuit in the technical field of the present invention, and FIG. 3A is a basic configuration diagram thereof. Reference voltage generating circuit reference voltage V _R generated by is inputted to the voltage regulator circuit, voltage regulator circuit, the input voltage V _IN is a reference voltage ₍₌ V _R) is output after being adjusted to a predetermined voltage V _out The The output voltage is adjusted according to the digital control signal, for example, in steps of several steps in a range of ± 10% or ± 20% around a predetermined output voltage value _Vout0 .

As a reference voltage generation circuit in the case of the PTAT voltage, a circuit configuration example shown in FIG. 3B is known (note that an initialization circuit used together with this circuit is omitted). In the example shown in (b) of FIG. 3, MOS transistors M31 and M33 are designed to operate in the weak inversion region, the reference voltage V _R which is proportional to the temperature is generated. The reference voltage V _R becomes fraction less low voltage V _DD for the following reasons. Since the MOS transistor M31 is in the weak inversion region, its gate voltage V _GN is designed to be lower than the threshold voltage (hereinafter referred to as “V _T ”) of the MOS transistor in the strong inversion region. Thus, the reference voltage _{V R} is even lower _{V T} content of the MOS transistor M33 than the potential _{V GN,} thus becomes a low voltage to the power supply voltage _{V DD.} For example, in the power supply voltage _{V DD} is 1V around the circuit for the minimum operation, the reference voltage _{V R} is very low as about 100 ~ 200 mV. Meanwhile, the generated reference voltage V _R, typically is applied to the gate of the MOS transistor in the other circuit blocks, since it is desirable to generally MOS transistors of the other circuit blocks operating in strong inversion region, it is necessary to convert the reference voltage V _R to a higher potential. That is, in the voltage adjustment circuit for PTAT voltage, the reference voltage V _R which is a low voltage is input as the input voltage V _IN, the input voltage V _{IN (=} V _R) than a predetermined voltage slightly higher and the power supply voltage It is required to output a voltage _Vout that is less affected by variations in V _DD and manufacturing conditions.

In recent years, in the field of semiconductor integrated circuits, low _VDD has been developed to improve the degree of integration and reduce power consumption, and even a slight voltage error tends to have a large effect. For this reason, adjustment of the voltage _Vout with higher resolution and higher accuracy has been demanded with the progress of low V _DD .

Next, a voltage adjustment circuit according to the prior art will be described.
First, as Conventional Example 1, a voltage adjustment circuit that outputs a voltage higher than the input reference voltage _{VIN by a} predetermined voltage is taken as an example. FIG. 4 is a diagram showing a configuration example of the voltage adjustment circuit of Conventional Example 1. As this voltage adjustment circuit, for example, a voltage regulator described in Patent Document 1 corresponds.
As shown in FIG. 4A, the voltage adjustment circuit includes a current control unit Amp, a variable resistance unit TR40, and a resistor _RL . The variable resistance unit TR40 has a function of controlling the resistance between the terminals A and B. The terminal A is connected to the output of the current control unit Amp, and the terminal B is connected to the resistance _RL and the feedback input of the current control unit Amp. Is done. FIG. 4B shows a configuration example of the variable resistance unit TR40. A plurality of resistors R41 and R42 (both having a resistance value r _u ) connected in series are included, and a switch unit S42 (for example, a MOS transistor) is connected in parallel to these resistors. The load current I ₀ flows from the V _DD to the ground GND through the variable resistance unit TR40 and the resistance _RL , and the voltage V _{x of} the node X (terminal B) is equal to the input voltage V _IN by the current control unit Amp. It is controlled to become. As a result, when the voltage drop of the variable resistance unit TR40 is V _AB , the output voltage V _out is the sum of the voltage V _IN and the voltage V _AB . The voltage V _AB of the variable resistor unit TR40 can be adjusted by appropriately controlling on / off of the switch unit S42 and controlling its resistance value. If the resistance of the switch unit is 0Ω when the switch unit S42 is ON (ideal value), the resistance between the terminals A and B of the variable resistor unit TR40 is _ru , and the following equation (1) Is established.
V _out = V _IN + V _AB = V _IN + ru _u · I ₀ Formula (1)

Table 1 shows the relationship between the operating state and the resistance value of the variable resistance unit TR40 in Conventional Example 1. Regarding the resistance (R _AB ) of the variable resistance unit TR40, the case where the resistance of the switch unit S42 is the ideal value (0Ω) and the case of r _N are shown.

As described above, by controlling the resistance value of the variable resistance unit TR40, the voltage V _{AB and} , in turn, the output voltage V _out can be adjusted.

However, the voltage adjustment circuit of Conventional Example 1 cannot perform voltage adjustment with sufficiently high accuracy as a problem. The reason is that the switch unit in the variable resistance portion TR40 is provided only on the path of the load current I _0, is that the voltage feedback to the differential amplifier OP1 is made via the switching unit load current I ₀ flows.
For example, when the switch unit S42 is ON, the output voltage V _out when the on-resistance of the switch section S42 is in the ideal state of 0Ω Where the formula (1), when the ON resistance r _N of the switch unit S42 is larger Causes a voltage drop ΔVs in the switch unit S42 and an error occurs in the output voltage. When the operating power supply voltage is lowered, the on-resistance of the switch unit S42 is increased, so that an error in the output voltage increases (characteristics shown in FIG. 6 as described later). As described above, in Conventional Example 1, it is difficult to obtain a highly accurate output voltage _Vout particularly in the low power supply voltage operation. The details of the output voltage error in Conventional Example 1 will be described later in comparison with the embodiment of the present invention.

Next, as a conventional example 2, a voltage adjustment circuit that is not easily affected by the on-resistance of the switch unit will be described. FIG. 7 is a diagram illustrating a configuration example of the voltage adjustment circuit of Conventional Example 2. As this voltage adjustment circuit, for example, a power supply circuit described in Patent Document 2 (the power supply circuit illustrated in FIG. 12 of Patent Document 2) is shown. 13) is applicable.
The variable resistance unit TR70 in Conventional Example 2 includes a plurality of resistors R70, R71, R72,... Connected in series between the terminal A and the terminal B, and between each node between these resistors and the terminal C. , A plurality of switch units S70, S71, S72,... Are provided, and the terminal C is connected to the feedback input of the current control unit Amp. The resistance between the terminal A and the terminal B of the variable resistance unit TR70 is constant regardless of the on / off state of the switch unit, and the resistance between the terminal A and the terminal C and the resistance between the terminal C and the terminal B are adjusted by the switch unit. The

Table 2 shows the relationship between the operating state and the resistance value of the variable resistance unit TR70 in Conventional Example 2. In Conventional Example 2, the switch units S70, S71, S72,..., Send of the variable resistance unit TR70 are provided only on the voltage feedback path, not on the current path. Therefore, by using the current control unit Amp having a high input impedance, the voltage drop of the switch units S70, S71, S72,... Can be sufficiently reduced, and the output voltage error due to the switch unit can be suppressed. Note that. Table 2, the switch portion of the variable resistor TR70 and S70, S71 and S72, show the case where 0Ω to R70, the resistance value of R71 and R72 was _{r u.}

However, in the circuit configuration of Conventional Example 2, since the relationship between the state of the switch unit and the increase / decrease in the output voltage is nonlinear, fine adjustment is difficult. The reason is that the load current I ₀ changes not only according to the input voltage _VIN but also depending on which switch section is turned on. Generally, in adjusting the voltage, it is desirable that the state of the switch unit adjusted by the control digital code (G70, G71, G72,... Shown in FIG. 7) and the output voltage have a linear relationship. Further, in a semiconductor integrated circuit, it is necessary to connect a plurality of resistors having the same material and the same shape in series and parallel to reduce manufacturing variations.

However, in the conventional example 2, if the resistors Rs71, Rs72,. For example, when the switch unit S70 is on, the resistance of the variable resistor TR70 Rs71, Rs72, ..., and the input voltage _{V IN} is applied to the resistor _{R L.} On the other hand, when the switch unit Send is on, the input voltage _VIN is applied only to the resistor _RL . As described above, in the conventional example 2, the load current I ₀ increases or decreases depending on the on / off state of the switch unit. For this reason, if the resistors Rs71, Rs72,... Are all set to the same resistance value, the relationship between the state of the switch section adjusted by the control digital code and the output voltage becomes nonlinear (the characteristics shown in FIG. 9 will be described later). . That is, in the conventional example 2, it is difficult to perform linear adjustment so that the increment of voltage adjustment is constant. Details of this non-linearity will be described later in comparison with an embodiment of the present invention.

In Conventional Example 2, since the load current I ₀ changes depending on the state of the switch unit adjusted as described above, the time until the output voltage stabilizes also changes depending on the state of the switch unit. The resistor _RL formed on the semiconductor substrate has a large resistance value and is generally accompanied by a large parasitic capacitance. For this reason, in the conventional example 2, when the resistance value of the resistor _RL is large, there is a problem in that the time until the output voltage is stabilized changes depending on the state of the switch unit that is adjusted, and the stable operation of the circuit is impaired.

Japanese Patent Laying-Open No. 2015-79307 JP 2004-319034 A

An object of the present invention is to provide a voltage adjustment circuit capable of adjusting the output voltage with high accuracy and quickly stabilizing it in a predetermined time, and having a large number of adjustable gradations and excellent linearity. That is.
Furthermore, even when a low reference voltage close to the ground potential GND such as a PTAT voltage is adjusted and output under the condition of low V _DD , as described above, high accuracy, a large number of gradations, and good Voltage regulation circuit that exhibits excellent characteristics such as linearity, quickly stabilizes the output voltage in a predetermined time, and enables circuit pattern layout with high area efficiency, making it less susceptible to variations in manufacturing and manufacturing conditions The purpose is to provide.

In order to solve the above-described problem, a voltage regulator circuit according to the present invention is connected between a current control unit that receives a reference voltage, a first resistor, an output of the current control unit, and a first resistor. A variable resistance unit, and the variable resistance unit includes a plurality of resistance selection circuits. Each of the resistance selection circuits includes a second resistor connected to an output of the current control unit, a first resistor, and a second resistor. A first switch unit connected between the second resistor and the current control unit, and a second switch unit configured to apply voltage feedback between the second resistor and the current control unit. It is characterized by being turned on and off in conjunction with the switch part.

According to the voltage adjustment circuit of the present invention, even when the resistance of the switch unit included in the variable resistor unit and the load current are large under the condition of a low power supply voltage, the output voltage error is suppressed to be small and highly accurate voltage adjustment is performed. At the same time, the output voltage can be linearly adjusted and quickly stabilized in a predetermined time.

FIG. 1 is a basic configuration diagram of a voltage regulator circuit according to the present invention. FIG. 2 is a diagram showing an output voltage adjustment flow of the voltage adjustment circuit according to the present invention. FIG. 3 is a diagram showing an application example of the voltage adjustment circuit in the technical field of the present invention. FIG. 4 is a diagram illustrating a configuration example of the voltage adjustment circuit of the first conventional example. FIG. 5 is a diagram showing an equivalent circuit simplified around the variable resistance portion in the voltage adjustment circuit. FIG. 6 is a diagram showing characteristics relating to the output voltage error of Conventional Example 1 and the present invention. FIG. 7 is a diagram illustrating a configuration example of the voltage adjustment circuit of the second conventional example. FIG. 8 is a diagram showing a simplified equivalent circuit centering on the variable resistance portion of Conventional Example 2. FIG. 9 is a diagram showing the relationship between the adjustment state and output voltage by Conventional Example 2 and the switch unit of the present invention. FIG. 10 is a diagram illustrating the configuration of the voltage adjustment circuit according to the first embodiment. FIG. 11 is a diagram showing a configuration of a differential amplifier used in the present invention. FIG. 12 is a diagram illustrating the configuration of the variable resistor portion of the voltage adjustment circuit according to the second embodiment. FIG. 13 is a diagram illustrating a configuration example of a logic circuit having a decoding function according to the second embodiment. FIG. 14 is a diagram illustrating the configuration of the variable resistor portion of the voltage adjustment circuit according to the third embodiment. FIG. 15 is a diagram illustrating the configuration of the variable resistor portion of the voltage adjustment circuit according to the fourth embodiment. FIG. 16 is a diagram illustrating the configuration of the variable resistor portion of the voltage adjustment circuit according to the fifth embodiment. FIG. 17 is a diagram illustrating the configuration of the variable resistor portion of the voltage adjustment circuit according to the sixth embodiment. FIG. 18 is a diagram illustrating the configuration of the voltage adjustment circuit according to the seventh embodiment. FIG. 19 is a diagram illustrating a circuit configuration employed in the switch unit of the voltage regulator circuit according to the eighth and ninth embodiments. FIG. 20 is a diagram illustrating the vertical MOS transistor employed in the voltage adjustment circuit according to the tenth embodiment.

FIG. 1 is a circuit diagram showing a basic configuration of a voltage regulator circuit according to the present invention. The voltage adjustment circuit includes a current control unit Amp, a variable resistance unit TR1, and a first resistance _RL . The variable resistance unit TR1 includes a plurality of resistance selection circuits (SEL1, SEL2,...), And each resistance selection circuit SEL1, SEL2,... Is connected to the first resistance _RL and forms a current path. , Second switch units S1f, S2f,... Connected to the current control unit Amp to form a voltage feedback path, and second resistors connected to the first and second switch units It is comprised from Rs1, Rs2,. The first and second switch sections in each resistance selection circuit (SEL1, SEL2,...) Are connected to the second resistors Rs1, Rs2,. Further, the second resistors Rs1, Rs2,... Have different resistance values in the respective resistance selection circuits (SEL1, SEL2,...).

Next, an operation mode in the basic configuration of the voltage regulator circuit according to the present invention will be described.
First, a predetermined resistance selection circuit included in the variable resistance unit TR1 is selected, a switch unit included therein is turned on, and switch units of other resistance selection circuits are turned off. For example, when the resistance selection circuit SEL1 is selected, the resistance between the terminal A and the terminal B and the resistance between the terminal A and the terminal C of the variable resistance unit are set to predetermined values determined by the resistance value of the second resistor Rs1. (Here, when the on-resistance of the switch section is set to an ideal state of 0Ω, the resistance value of the second resistor Rs1 is equal). Further, when the resistance selection circuit SEL2 is selected, the resistance between the terminals is determined by the second resistance Rs2. In this way, the output voltage is adjusted by the operation of the current control unit Amp after the state of the variable resistance unit TR1 is appropriately controlled. A load current I ₀ flows from the output of the current control unit Amp to the terminal A, the terminal B, and the first resistor _{RL of} the variable resistance unit TR1. In the variable resistance part TR1, it is assumed that the resistance selection circuit having the second resistance having the resistance value Rs is selected, the input impedance of the current control part Amp is sufficiently high, and the current passing through the terminal C is negligible. (This condition can be easily satisfied at the input part of the current control part Amp by using, for example, a MOSFET as the current control part Amp).
Here, assuming that the resistance selection circuit SEL1 is selected, the potential V _{Z1 of the} node Z1 becomes equal to the feedback potential V _F of the current control unit Amp, so the output voltage V _out is as follows. Note that “Rs” is used for convenience for the resistance values of the second resistors Rs1, Rs2,.
V _out = V _Z1 + I ₀ R _S = V _F + I ₀ Rs Formula (A1)

FIG. 2 is a diagram showing an output voltage adjustment flow of the voltage adjustment circuit according to the present invention. The current control unit Amp works as follows as shown in the flow of FIG. That is, if the input voltage _VIN of the current control unit Amp is higher than the feedback voltage V _F (V _IN > V _F ), the current I ₀ is increased. Conversely, if the input potential _VIN is lower than the feedback potential V _F ( V _IN <V _F ), the current I ₀ is decreased. When the absolute value of the difference between the input potential V _IN and the feedback potential V _F becomes smaller than a predetermined value (| V _IN −V _F | <predetermined value), the current I ₀ becomes stable and the following output voltage V _out is obtained. .
V _out = V _IN + I ₀ Rs Formula (A2)
As described above, since the resistance value Rs is adjusted to a desired value by appropriately controlling the variable resistance portion TR1, a desired voltage can be adjusted.

Next, the fact that the voltage adjustment circuit according to the present invention enables voltage adjustment with higher accuracy than the conventional known voltage adjustment circuit will be described using mathematical expressions.
First, the output voltage error in the voltage adjustment circuit of Conventional Example 1 shown in FIG. 4 will be described in detail.
FIG. 5 is a diagram showing an equivalent circuit simplified around the variable resistance portion in the voltage adjustment circuit. FIG. 5A is an equivalent circuit diagram simplified around the variable resistance part TR40 in the voltage adjustment circuit of the first conventional example. Here, it is assumed that the switch unit s42 is turned on. r _u is a resistance value of the resistors R41 and R42, r _N is an on-resistance of the switch unit s42, and I ₀ is a current flowing through the resistor _RL . In this case, the resistance minimum step of adjusting, i.e. adjustment resolution becomes r _u. The output voltage of this circuit is the center of the adjustment by the voltage drop across the resistor R _L is Sadamari rough, further finely adjusted by adjusting in increments of resistance r _u of the variable resistor TR40. Therefore, it is designed under the condition of R _L > r _{u and} it is necessary to design under the condition of R _L > r _{N in} order to roughly determine the output voltage based on the voltage drop of the resistor R _L.

Here, the combined resistance r _uN of r _u and r _N is as follows.

By the action of a differential amplifier OP1 constituting a current control unit Amp, since the potential _{V x} of the terminal B or nodes X becomes equal to the input voltage _{_{V IN,} V} _out is as follows.

On the other hand, the output voltage V _o-ideal in an ideal state where the on-resistance of the switch unit s42 is 0Ω is as follows.

The error | ΔV _out | of the output voltage of the voltage adjustment circuit of Conventional Example 1 is as follows from the equations (1.2) and (1.3).

Therefore, the normalized output voltage error | E _conv | normalized by the ideal output voltage V _o-ideal is as follows from the equations (1.1), (1.3), and (1.4).

Next, the output voltage error of the voltage adjustment circuit according to the present invention shown in FIG. 1 will be described in detail. Here, it is assumed that the switch section in the resistance selection circuit SEL1 in FIG. 1 is on and the switch sections of the other resistance selection circuits are off.
FIG. 5B is an equivalent circuit diagram simplified around the variable resistance portion TR1 of the voltage adjusting circuit according to the present invention. The first and second switch parts S1 and S1f correspond to the switch part in the resistance selection circuit SEL1 shown in FIG. r _u is the resistance value of the resistor Rs1, r _N is the on-resistance of the first switch unit S1, r _N ′ is the on-resistance of the second switch unit S1f, and I ₀ is the current flowing through the resistor _RL . Here, minimum step i.e. adjustment resolution of resistance adjustment becomes r _u. In the present invention, the output voltage is the center of the adjustment by the voltage drop across the resistor R _L is Sadamari rough and fine adjustment by further adjusting the resistance of the variable resistor TR1 in increments of resistance r _u. Thus _practically, it is designed under conditions of R L> _{r u} and _{_R} L> _{r N.}

In the present invention, the current I ₀ flows so that the potential Vc of the terminal C in the variable resistance unit TR1 becomes equal to the input voltage _{VIN by} the action of the current control unit Amp. The current I ₀ flows in from the terminal A of the variable resistance unit TR1, flows through the first resistor Rs1, the first switch unit S1, and the terminal B of the variable resistance unit TR1, and flows to the resistor _RL . Therefore, when the potential of the node Z1 between the first and second switch portions S1 and S1f and the resistor Rs1 is V _Z1 , the output voltage V _out is as follows.

On the other hand, the current control unit Amp can realize a sufficiently high input impedance by using, for example, a MOS transistor. That is, the direct current flowing through the switch unit S1f is extremely small and may be regarded as zero. As a result, the voltage drop caused by the on-resistance of the switch section S1f is sufficiently small and can be ignored in considering the output voltage error. Then, the potential V _{Z1 of the} node Z1 becomes equal to the input voltage _VIN .

Since this potential V _Z1 (= V _IN ) is also the sum of the voltage drop generated in the on-resistance r _N and the resistance _RL of the switch unit S1,

The equation (2.4), it is important that the resistance value r _u is not included. That is, the equation (2.4) relating to the load current I ₀ is established regardless of which switch unit is turned on and which resistor is selected. The effect will be described later by comparison with Conventional Example 2.

On the other hand, the output voltage V _out is as follows from the equations (2.1), (2.2), and (2.3).

Also in the present invention, in the ideal state where the ON resistance r _N of the switch unit S1 is 0Ω, the output voltage (V _o-ideal ) is the same as the above equation (1.3). Therefore, the error | ΔV _out | of the output voltage of the present invention is

Therefore, the normalized output voltage error | E _pro | normalized by the ideal output voltage V _o-ideal from the equations (1.3) and (2.6) is as follows.

_{Comparing the} expression (1.5) indicating the normalized output voltage error | E _conv | of the conventional example 1 with the expression (2.7) indicating the normalized output voltage error | E _pro | Only the second term is different. That is, the second term of the formula (1.5) is 1 / (r _u + r _N ), whereas the second term of the formula (2.7) is 1 / (R _L + r _N ). As described above, since any circuit is practically designed under the conditions of R _L > r _u and R _L > r _N , the following holds.
1 / (r _u + r _N )> 1 / (R _L + r _N ) Expression (2.8)
| E _conv |> | E _pro | Expression (2.9)
That is, the normalized output voltage error | E _pro | of the present invention can be suppressed sufficiently smaller than the normalized output voltage error | E _conv | of the first conventional example.

FIG. 6 is a diagram showing characteristics relating to the normalized output voltage error | E _conv | of the conventional example 1 and the normalized output voltage error | E _pro | of the present invention. FIG. 6A shows how each error is affected by the on-resistance r _N of the switch section. Both errors are normalized by the output voltage V _o-ideal under the ideal condition (r _N = 0), and are calculated using the previous equations (1.5) and (2.7). . In this calculation, _{r u} is 5 k.OMEGA, _{R L} is assumed to 50kohm. When r _N is in a range of several kΩ or less, which is smaller than R _L , the error in the present invention can be suppressed to 1% or less, which is a fraction of that of Conventional Example 1 under the same conditions.

Next, the dependence of the output voltage error on the power supply voltage V _DD in each circuit will be described. The previous equations (1.5) and (2.7) do not include the term of the power supply voltage V _DD . However, in an actual circuit, when the power supply voltage V _DD decreases, the on-resistance of the switch unit increases, and thus the output voltage error increases.

FIG. 6B shows the dependence characteristics of the output voltage error on the power supply voltage V _DD in the conventional example 1 and the present invention. The switch section is assumed to be composed of MOS transistors, and the output voltage error is calculated from the result of circuit simulation. In circuit simulation, both Conventional Example 1 and the present invention use the same transistor parameters. The aspect ratio (gate width W / gate length L) of the MOS transistor corresponding to the switch unit (S42 of the conventional example 1 and S1 of the present invention) is assumed to be two types of W / L = 50 and 25, and the current control unit Amp is An ideal model. It should be noted that even if the aspect ratio (W / L) of the second switch portions S1f, S2f,... Of the present invention is extremely small, it does not cause an error. Here, the value is 1/5 (two types of 10 and 5) of the corresponding first switch units S1, S2,. In the characteristics shown in FIG. 6B, any output voltage error is normalized by the ideal output voltage value at which the ON resistance of the switch section is 0Ω.

In the conventional example 1, when the power supply voltage V _DD is lowered to 0.6 V or less, the error increases to 2% or more in either case of the

aspect ratio

50 or 25. On the other hand, in the present invention, the error is 1% or less even when the power supply voltage V _DD is 0.6V. As described above, according to the present invention, it is possible to suppress the output error to be smaller than that of the conventional example 1 designed with the same circuit parameters. In particular, when the power supply voltage V _DD is lowered, in other words, it is low. When operating with the power supply voltage V _DD , the advantage over the conventional example 1 and its effect become significant.

As described above, the conventional example 1, the load current because the I ₀ is the voltage feedback to the differential amplifier OP1 of the current control unit Amp through the switch unit S42 flows is made, feedback voltage originating from on-resistance of the switch unit S42 An error occurs and the accuracy of the output voltage deteriorates. On the other hand, the present invention, the load current I ₀ Apart from the first switch section S1 of the path through which the current control unit Amp of the second even on a path current does not flow in the voltage feedback path to the differential amplifier Therefore, the feedback voltage error caused by the on-resistance of the switch unit does not occur. As a result, it is possible to obtain a high-accuracy voltage adjustment circuit with less errors than the conventional example 1 at a particularly low power supply voltage V _DD .

Next, the fact that the present invention does not cause the problem of non-linearity of the output that the voltage adjustment circuit of Conventional Example 2 has will be described using mathematical expressions.
First, output nonlinearity in the configuration of the voltage adjustment circuit of the second conventional example shown in FIG. 7 will be described. FIG. 8 is a diagram showing a simplified equivalent circuit centering on the variable resistance portion TR70 of the second conventional example. In Figure 8, for simplicity of explanation, the resistance R70 of FIG. 7 is a 0 .OMEGA, resistance of the resistor R71 and the resistor R72 is assumed to _{r u.} Here, a node between the resistor R71 and the resistor R72 is Z1, and its potential is _VZ1 . Further, the load current flowing through the resistor _RL is I ₀ . In FIG. 8, three switch units S70, S71, and S72 are mounted. That is, voltage adjustment of three gradations is performed. The on-resistance r _N of each switch unit is assumed.

8A shows a case where the switch unit S70 is turned on and others are turned off, and FIG. 8B shows a case where the switch unit S71 is turned on and others are turned off. c) shows the case where the switch part S72 is on and the others are off. In addition, the switch part which is turned off is omitted and not shown.

First, the state of FIG. 8A will be described. In the circuit configuration of a conventional example 2 as described above, the switch section S70 ~ S72 is not on the path through which the load current I _0, is provided on the voltage feedback path to the differential amplifier OP1 of the current control unit Amp . Therefore, in the conventional example 2, when the input impedance of the differential amplifier OP1 is high, the influence of the voltage drop due to the switch units S70 to S72 can be ignored, and the potential V _A of the terminal _A becomes equal to the potential V _{C of the} terminal C. In FIG. 8A, since the potential V _{A of the} terminal A is the same as the output voltage V _out and the potential V _C becomes equal to the input voltage _VIN due to the action of the differential amplifier OP1, the following relationship is established. .
V _out = V _A = V _C = V _IN Formula (3.1)

Next, the state shown in FIG. 8B will be described. Also in this case, the influence of the voltage drop caused by the switch unit S71 can be ignored, and the potential VZ1 of the node _Z1 is as follows.
V _Z1 = V _C = V _IN Formula (3.3)
V _IN = I ₀ · (r _u + R _L ) Equation (3.4)
In addition, the output voltage _{V out} is as follows.
_{_{_{V out = I 0 · (2r}}} u + R L) ··· formula (3.5)
From the equations (3.4) and (3.5), the following relationship holds in FIG. 8B.

Next, the state shown in FIG. 8C will be described.
V _B = V _IN = I ₀ R _L (Equation 3.8)
Since the equation (3.5) is established even in this state, the following relationship is established in FIG.

As described above, in the conventional example 2, as indicated by the equations (3.2), (3.7), and (3.10), the load current I ₀ varies depending on the states of the switch units S70 to S72. As a result, in Conventional Example 2, it is difficult to perform linear voltage adjustment with respect to the states of the switch units S70 to S72. That is, the ratios of the output voltage Vouta in FIG. 8A, the output voltage Voutb in FIG. 8B, and the output voltage Voutc in FIG. 8C are expressed by the equations (3.1) and (3.6). ) And formula (3.9),

From this equation (3.11), the conventional example 2 cannot make the adjustment range constant when performing voltage adjustment by changing the state of the switch section. FIG. 9 is a diagram showing the relationship between the output voltage and the case where the switch state is turned on / off corresponding to the digital value as the adjustment state by the switch unit in Conventional Example 2 and the present invention. The vertical axis is normalized based on the voltage that is the center of adjustment. FIG. 9 shows the case of a circuit that performs five gradation adjustments (5 steps from −2 to 2). In the conventional example 2, there are five switch parts shown in FIG. 7 (S70, S71, S72, S73 and S74). As shown in FIG. 9, the output voltage of Conventional Example 2 changes in a curved shape with respect to the horizontal axis indicating the adjustment state by the switch unit, and linear adjustment is difficult. In addition, the deviation from the linearity of the output voltage of Conventional Example 2 is determined by the resistance R _L , the resistance _ru, or the number of gradations, and it cannot be improved even if the on-resistance of the switch unit is significantly reduced. is required.

Next, in the present invention, it will be described that linear adjustment is easy. In the basic configuration of the voltage adjustment circuit shown in FIG. 1, for example, when the resistance selection circuit SEL1 is selected, the switch unit and the second resistor are operated by the second switch unit S1f provided in the voltage feedback path. The potential V _Z1 of the node Z1 with Rs1 becomes equal to the input voltage _VIN . As a result, the switch unit of any one of the plurality of resistance selection circuits is turned on, and the expression relating to the load current I ₀ regardless of whether the second resistance included in the turned-on resistance selection circuit is selected. (2.4) holds.
Here, the second resistor Rs (collectively referred to as "Rs") included in the resistor selection circuit of the present invention the resistance value of 0, r _{u, 2r u,} as _..., ON of the switch portion among them If the configuration is such that the resistance value of the second resistor Rs is selected, the following is obtained from the equation (2.5).

As described above, in the present invention, the expression (2.4) relating to the load current I ₀ is established regardless of the state of the switch section. Therefore, from equation (3.12),

As described above, the voltage adjustment circuit according to the present invention can make the voltage adjustment range constant. That is, linear adjustment is possible by making the adjustment switch state correspond to the digital value. FIG. 9 shows the relationship between the adjustment state of the switch unit and the output voltage in the present invention, together with that of Conventional Example 2. The relationship shown in FIG. 9 is that the present invention is capable of adjusting five gradations, that is, includes five resistance selection circuits (SEL0, SEL1,... SEL4), and each resistance selection circuit has a resistance value of 0Ω, ru _, It is assumed that 2r _u ,. The vertical axis is normalized with reference to the voltage at the center of adjustment, and the states “−2”, “−1”, “0”,... In FIG. Corresponding to 2,. From the relationship shown in FIG. 9, the conventional example 2 cannot be linearly adjusted, but the present invention can adjust the linearity well. Since the deviation from the linearity shown in the conventional example 2 is regarded as an error in adjustment, the present invention enables more accurate adjustment.

As described above, the resistance of the variable resistor TR1 in the present invention, it should be noted that we have to have an integral multiple of the predetermined resistance value r _u. That is, in order to make the variable resistance portion TR1 comprises resistance in the present invention with a predetermined resistance value r _u, it can be realized by connecting a resistor of the same material and the same shape in series or in parallel. Thereby, a circuit pattern layout with high area efficiency is possible, and it is easy to realize a circuit pattern that is not easily affected by manufacturing variations and manufacturing condition variations. Furthermore, the load current I ₀ in the present invention is determined by the input voltage and the resistance, and is a predetermined value that does not depend on the adjustment state of the switch section. Therefore, according to the present invention, a stable output voltage can be obtained in a predetermined time regardless of the adjustment state of the switch unit.

FIG. 10 is a diagram showing a configuration of the voltage adjustment circuit according to the first embodiment of the present invention. As illustrated in FIG. 10A, the first embodiment includes a current control unit Amp, a variable resistor unit TR10, and a first resistor _RL, and receives a reference voltage _VIN , and an adjusted output voltage V _out. Is output. The variable resistance unit TR10 includes a terminal A, a terminal B, and a feedback terminal C. The connection mode is such that the terminal A of the variable resistance unit TR10 is connected to the output of the current control unit Amp and the output V _OUT of the voltage adjusting circuit. The terminal B of the variable resistor unit TR10 is connected to one terminal of the resistor _RL , and the terminal C of the variable resistor unit TR10 is connected to the feedback input terminal of the current controller Amp. Further, it has a function capable of digitally controlling the resistance between the terminals AB and the resistance between the terminals AC.

As shown in FIG. 10B, the variable resistor TR10 according to the first embodiment includes, as constituent elements, resistors R101 (resistance value r _u ), R102 (resistance value 2r _u ),..., First switch unit S101. , S102,... And second switch units S101f, S102f,..., And a plurality of resistance selection circuits SEL101, SEL102,.

In the connection mode in one resistance selection circuit SEL101, one end of the resistor R101 is connected to the terminal A of the variable resistor unit TR10, the other end of the resistor R101 is connected to the terminal d of the first switch unit S101, and the first switch unit S101. Terminal s is connected to the terminal B of the variable resistor section TR10, the other end of the resistor R101 is connected to the terminal d of the second switch section S101f, and the terminal s of the second switch section S101f is connected to the terminal of the variable resistor section TR10. It is connected to the terminal C for feedback. The first switch unit S101 and the second switch unit S101f are controlled in conjunction with each other by the input signal G101. If the first switch unit S101 is on, the second switch unit S101f is also on, and if the first switch unit S101 is off, the second switch unit S101f is also off. NMOS transistors shown in FIG. 10C are used for the first and second switch sections. Symbols g, d, and s in FIG. 10C correspond to the terminals g, d, and s of each switch unit in FIG.

In the first embodiment, the input reference voltage _VIN does not need to be restricted as long as it is between V _DD and the ground GND. However, the input reference voltage _VIN is described as being a low voltage close to the ground GND. In this case, NMOS transistors are suitable as the first and second switch sections. If it is a PMOS transistor, the transistor does not turn on unless the voltage at the terminal A is higher than the gate voltage by the threshold voltage | V _T |. Therefore, when the reference voltage _VIN is low and the voltage at the terminal A is also set to be as low as the input reference voltage _VIN , it is difficult to use a PMOS transistor.

The current controller Amp is composed of a differential amplifier OP1 and a PMOS transistor P1. The output of the differential amplifier OP1 is connected to the gate of the PMOS transistor P1, and the drain of the PMOS transistor P1 is connected to the output of the current control unit Amp. As the differential amplifier OP1, it is desirable to use a sufficiently high input impedance. For example, a known current mirror amplifier is used. A circuit example of the differential amplifier OP1 is shown in FIG.

In applying the voltage adjustment circuit of the present invention, as described above, the input reference voltage _VIN may be a low voltage close to the ground GND. In this case, a differential amplifier having the configuration shown in FIG. 11B can be used. As a circuit configuration, a level shifter is provided for each input pair of the differential amplifier shown in FIG. As the level shifter, as shown in FIG. 11B, the PMOS transistors (P113, P114) whose gates are connected to the input terminals (IN), and currents for supplying current to the PMOS transistors (P113, P114) A source composed of sources (IS111, IS112) is used. Even in this circuit configuration, a differential amplifier having a sufficiently high input DC resistance can be obtained.

Next, the operation mode of the first embodiment will be described.
In the voltage adjustment circuit shown in FIG. 10A, the load current I ₀ flows between the terminals AB of the variable resistance unit TR10 and flows to the resistor _RL . As a result of the load current I ₀ being controlled by the differential amplifier OP1 and the MOS transistor P1, the voltage VF at the node _F and the input reference voltage _VIN are equal under the condition that the gain of the differential amplifier OP1 is sufficiently high. Since the input impedance of the differential amplifier OP1 is sufficiently high, almost no current flows through the second switch portions S101f and S102f shown in FIG. 10B, and the voltage drop can be regarded as 0V. Therefore, the voltage V _{F at the} node F becomes equal to the voltage V _Z1 or V _{Z2 at} the node Z101 or Z102 of the switch unit turned on in the resistance selection circuit SEL101 and the resistor connected to the switch unit. For example, when the first and second switch units S101 and S101f of the resistance selection circuit SEL101 are on and the switch unit of the remaining resistance selection circuit SEL102 is off, the nodes of the resistor R101 and the second switch unit S101f potential _{V (Z101)} is equal to the voltage _{V F} i.e. voltage _{V iN.} Here, the voltage drop _r u · _{I 0} next to the resistor R101 (resistance value _{r u),} the output voltage _{V out} is the voltage _{_V} IN (= _V _F) and the voltage drop _r u · _{I 0} of the sum _(V IN + r _u · I ₀ ). At this time, between and between terminals A-C terminal A-B of the variable resistor TR10, ideal resistance value without the resistance of the switch unit is r _u.

As described above, in the first embodiment, since the state of the voltage adjustment circuit is fed back to the differential amplifier through a path different from the path of the load current I ₀ , the difference between the output voltage V _out and the input voltage _VIN is determined by the switch unit. The voltage drop can be excluded. Note that by appropriately turning on and off the switch portion of the variable resistor portion TR10, the resistance value between the terminals AB and the terminals AC can be controlled, so that the voltage drop can be changed. For example, when the first switch unit S102 and the second switch unit S102f are on and the other switch units are off, between the terminals AB and between the terminals AC of the variable resistor unit TR10 of the first embodiment. The resistance value is 2r _u , the voltage drop is 2r _u · I ₀ , and the output voltage V _out is the sum of the voltage V _R and the voltage drop 2r _u I ₀ (V _R + 2r _u · I ₀ ). As described above, according to the first embodiment, the output voltage _Vout can be adjusted.

Table 3 shows the relationship between the state of the switch part and the resistance of the variable resistance part TR10 in Example 1. Table 3, when the resistance value of the switch portion is r _N, and are also described for the resistance of the variable resistor TR10. Each element of the control digital code in Table 3 corresponds to a control signal of each switch unit. For example, in the state “a”, the control signals G101 and G102 have the logical values “0” and “1”, respectively, and the first and second switch units S101, S102, and S101f that have the logical value “1”, Control is performed so that S102f is turned on. As shown in Table 3, in the variable resistance unit TR10, various resistance values can be selected depending on the state of the switch group controlled by the control digital code. The control signals G101 and G102 relating to the generation of the control digital code are generated and supplied by a processing unit (not shown) for controlling the voltage adjustment circuit.

As described above, in the first embodiment, the voltage feedback path to the differential amplifier in which no current flows, separately from the first switch unit on the path through which the load current I ₀ flows, as in the basic configuration described above. Since the second switch unit is also provided on the top, no feedback voltage error caused by the on-resistance of the switch unit is generated. Therefore, a high-accuracy voltage adjustment circuit with less error than the conventional example 1 can be obtained, a linear adjustment can be performed as compared with the conventional example 2, and an excellent voltage adjustment function can be obtained in which the output voltage is stable for a predetermined time. . In addition, the current control unit Amp in the first embodiment can increase the DC resistance of the input sufficiently even when the input reference voltage _VIN is a low voltage close to the ground GND. Can be provided.

FIG. 12 is a circuit diagram illustrating a configuration of a variable resistance unit, which is a circuit configuration part different from that of the first embodiment, as a configuration of the voltage adjusting circuit according to the second embodiment of the present invention. The configuration shown in FIG. 12 replaces the variable resistance unit TR10 in the first embodiment shown in FIG. 10B, and in addition to the two resistance selection circuits SEL101 and SEL constituting the variable resistance unit TR10 in the first embodiment. , A resistance selection circuit SEL100 including a connection wiring portion S as a resistance of 0Ω is added. Here, the connection wiring portion S is a unit in which a plurality of unit circuits are described as a resistance of 0Ω, and is actually short-circuited with a sufficiently low resistance wiring material such as metal. Further, the resistors R101 and R102 shown in FIG. 10 (b), in Example 2, replacing the resistor R121 and R122, has a resistance value with the same resistance value 2r _u. In addition, since the other component part of variable resistance part TR10 in Example 2 is the same structure as Example 1, the same symbol is provided to the same structural member and the description is abbreviate | omitted.

In the second embodiment, the variable resistor unit has a decoding function for individually or simultaneously turning on / off the switch units in the plurality of resistor selection circuits (SELs 100, 101, and 102) according to the logic state of the control digital code. FIG. 13 is a diagram showing a configuration example of a logic circuit (decoder) having this decoding function. Table 4 shows the truth table, and Table 5 shows the relationship between the control digital code, the operating state of the variable resistor section, and the resistance value.

Next, the operation mode of the second embodiment will be described.
The second embodiment provides a state in which the switch units of a plurality of resistance selection circuits in the variable resistance unit are simultaneously turned on when the control digital code is in a predetermined state. For example, in Tables 4 and 5, when the input codes C2 and C1 before decoding are “1” and “0”, respectively, “b”, the decoded output codes G102, G101, and G100 are They are “1”, “1” and “0”, respectively. In response to this input, the first switch units S101 and S102 and the second switch units S101f and S102f of the variable resistance unit shown in FIG. 12 are simultaneously turned on. As a result, the load current I ₀ flows through both resistors R121 and R122, the resistance value between and between A-C terminal A-B of the variable resistor becomes r _u ideal conditions no resistance of the switch unit . This is because the parallel circuit of resistors R121 and R122 are both resistance 2r _u configured.

As described above, also in Example 2, the voltage states of the voltage regulating circuit, the second switch portion S100f on different paths and flowing path load current I _0, is fed back to the differential amplifier via a S101f and S102f Therefore, the error due to the resistance of the switch portion can be reduced as in the first embodiment. Therefore, in the same way as in the first embodiment, the voltage adjustment in the second embodiment can be performed with higher accuracy than in the first conventional example, and the output voltage is linear in a predetermined time as compared with the second conventional example. It provides an excellent voltage regulation function that is stable.

Further, the resistors R121 and R122 of the variable resistor portion in the second embodiment are all of the same resistance value except for the connection wiring portion S as a resistance of 0Ω, so that the resistance elements having the same material and the same shape are used. be able to. As a result, a circuit pattern layout with high area efficiency is possible in a semiconductor integrated circuit, and a circuit that is not easily affected by manufacturing variations and manufacturing condition fluctuations can be obtained.

FIG. 14 is a circuit diagram showing a configuration of a variable resistance unit, which is a circuit configuration part different from that of the first embodiment, as a configuration of the voltage adjusting circuit according to the third embodiment of the present invention. The configuration shown in FIG. 14 replaces the variable resistance unit TR10 in the first embodiment shown in FIG. 10B, and the variable resistance unit is configured by two circuit blocks of the circuit block 1 and the circuit block 2. .

Since the circuit block 1 has a configuration similar to that of the variable resistance unit in the second embodiment shown in FIG. 12, differences from the configuration of the second embodiment will be described. In the circuit block 1, a terminal D12 is provided in the variable resistance unit of FIG. 12, and a node R102, a node Z102 of the first switch unit S102 and the second switch unit S102f is connected to the terminal D12. The resistance values of the resistors R121 and R122 are _{r u,} the terminal A in FIG. 12, B and C, respectively corresponding to the terminal A12, B12 and C12. Other parts of the circuit block 1 are the same as those of the variable resistance unit of FIG.

The circuit block 2 includes a plurality of resistance selection circuits SEL143 and SEL144. Each of the resistance selection circuits SEL143 and SEL144 includes resistors R143 and R144, first switch units S103 and S104, and second switch units S103f and S104f, respectively. Composed. In the connection mode in the circuit block 2, one end of the resistors R143 and R144 is connected to the terminal A13, and the other end of the resistors R143 and R144 is connected to the first switch units S103 and S104 and the second switch units S103f and S104f. Connected to the respective terminals d, the terminals s of the first switch sections S103 and S104 are connected to the terminal B13, and the terminals s of the second switch sections S103f and S104f are connected to the terminal C13.

The circuit block 1 and the circuit block 2 are connected in such a manner that the terminal A13 of the circuit block 2 is connected to the terminal D12 of the circuit block 1, and the terminal A12 of the circuit block 1 becomes the terminal A of the variable resistance unit. The terminal B12 of the circuit block 2 and the terminal B13 of the circuit block 2 become the terminal B of the variable resistance unit, and the terminal C12 of the circuit block 1 and the terminal C13 of the circuit block 2 become the terminal C of the variable resistance unit.

Next, the operation mode of the third embodiment will be described.
Table 6 shows the relationship between the operating state of the variable resistance unit and the resistance value in Example 3. In the third embodiment, according to the state of the control digital code, the load current I ₀ flows only through the circuit block 1 and flows from the circuit block 1 to the circuit block 2 via the terminal D12. Provide a pattern that flows through both.

For example, in the state “e” shown in Table 6, the control digital code [G104, G103, G102, G101, G100] is set to [10000]. In this case, all the switch units of the circuit block 1 are It is turned off, and the first and second switch sections S104 and S104f of the circuit block 2 are turned on. As a result, the load current I ₀ passes through the terminal A12 (terminal A), the resistor R122, and the terminal D12 of the circuit block 1, and passes through the terminal A13, the resistor R144, the first switch unit S104, and the terminal B13 (terminal B) of the circuit block 2. ). As a result, the equivalent resistance between the terminals A-B of the variable resistor in ideal conditions, the 2r _u shown in Table 6. Then, the voltage of the node Z104 of the circuit block 2 in this state is fed back to the differential amplifier OP1 via the second switch unit S104f and the terminal C13 (terminal C).

In the state “d” shown in Table 6, the control digital code [G104, G103, G102, G101, G100] is set to [11000]. In this case, all the switch units of the circuit block 1 are It is turned off and all the switch parts of the circuit block 2 are turned on. As a result, the load current I ₀ passes through the resistor R122 in the circuit block 1, and passes through both the resistors R143 and R144 (as a parallel circuit) in the circuit block 2. As a result, the equivalent resistance between the terminals A-B of the variable resistor in ideal conditions, the 1.5r _u.
The other states (“a” to “c”) are the same as those in the second embodiment (states “a” to “c”) shown in Table 5. However, since the resistance value _{r u} resistor R121 and R122, the equivalent resistance between the terminals A-B of the variable resistor in ideal conditions, a state "a", "b", "c", respectively 0 , 0.5 r _u , r _u (1/2 of the values shown in Table 5).

As described above, also in Example 3, since the switch portion of the feedback path to the differential amplifier load current I ₀ does not flow, as in the previous embodiment, can reduce the error of the output voltage. Further, in any state (“a” to “e”) determined by the control digital code shown in Table 6, the switch part is passed only once in both the load current I ₀ path and the feedback path. Since the circuit configuration is adopted, the resistance of the switch portion is not greatly affected unlike the conventional example.

Further, in the third embodiment, a configuration is adopted in which a resistor in a predetermined resistance selection circuit and a node of the switch unit are drawn to a terminal (terminal D12 in FIG. 14) and connected to another circuit block. As a result, some of the resistors in the circuit block are used in multiple circuit states. For example, the load current I ₀ flows through the resistor R122 in four states of circuit states “b” to “e”.

As described above, the third embodiment can perform the voltage adjustment with higher accuracy than the conventional example 1 as the same effect as the previous embodiment, and is more linear than the conventional example 2 and The present invention provides an excellent voltage adjustment function that stabilizes the output voltage in a predetermined time. In addition, since resistances other than the connection wiring portion S shown as a 0Ω resistance element can have the same resistance value, it is advantageous in terms of area efficiency, manufacturing variations, and resistance to manufacturing condition variations.

Furthermore, Example 3 has an original effect. That is, by using some of the resistors in the circuit block in common in a plurality of states shown in Table 6, there is an advantage that a desired number of gradations can be realized with a minimum resistance. For example, in the case of adjusting the five gradations by Example 1 includes resistance _{_{_{0, r u, 2r u,}}} 3r u, a resistor (connection wiring portion 4r _u becomes five (0 .OMEGA and four) ) requires, also, from the viewpoint of suppressing the production variation, when constructed using only the resistance of one resistor value r _u, it is necessary to ten resistors. However, in order to adjust the five gradations in Example 3, will be satisfied by the resistance of four resistance values r _u, in light of the difficulty of miniaturization of resistance as compared to the switch section of the semiconductor integrated circuit The reduction in the number of resistors is effective for improving the area efficiency.

As in the third embodiment, the voltage adjustment circuit according to the fourth embodiment includes a current control unit Amp, a first resistor _RL, and a variable resistor unit including a second resistor. These are the same as in the third embodiment. However, the internal configuration of the variable resistance portion is different from that of the third embodiment. FIG. 15 is a circuit diagram showing an internal configuration of a variable resistance portion different from that of the third embodiment as a configuration of the voltage adjusting circuit according to the fourth embodiment of the present invention.
The variable resistance unit according to the fourth embodiment includes a first resistance selection circuit SEL201 and a second resistance selection circuit SEL143.

The first resistance selection circuit SEL201 includes a second resistor R122, a first switch unit S102, and a second switch unit S102f. One end of the second resistor R122 is connected to the output of the current control unit Amp and the output terminal OUT of the voltage adjustment circuit through the terminal A of the variable resistance unit, as in the third embodiment. A wiring is drawn from a connection point Z102 of the second resistor 122, the first switch unit S102, and the second switch unit S102f, and is connected to the second resistance selection circuit SEL143.

The second resistance selection circuit SEL143 includes a second resistor R143, a first switch unit S103, and a second switch unit S103f. One end of the second resistor 143 is connected to the connection point Z102 of the first resistance selection circuit SEL201. The other end of the second resistor R143 is connected to a connection point Z103 which is one end of the first switch unit S103 and one end of the second switch unit S103f.

In addition, one end of each of the first switch unit S102 of the resistance selection circuit SEL201 and the first switch unit S103 of the resistance selection circuit SEL143 is connected to the terminal B of the variable resistance unit, and the negative overcurrent _I0 is It will flow to the resistor _RL . Further, one end of each of the second switch unit S102f of the resistance selection circuit SEL201 and the second switch unit S103f of the resistance selection circuit SEL143 is connected to the terminal C of the variable resistance unit, and voltage feedback is performed to the current control unit Amp. Will be.

Next, the operation mode of the fourth embodiment will be described.
The fourth embodiment provides a simple circuit connection and easy control. Table 7 shows the relationship between the operating state of the variable resistance unit and the resistance value in Example 4. In Table 7, similarly to the above, the resistance value of the resistor R122 and R143 and _{r u,} and the resistance of each switch unit in the _{r N.} As shown in the table, since there is only one resistance selection circuit in which the switch is turned on in each state of the control digital code, a complicated decoding circuit is unnecessary. Further, the number of second resistors constituting the variable resistance unit is equal to the number of states of the control digital code.

As described above, also in the fourth embodiment, since the load current I0 does not flow through the switch unit on the feedback path to the current control unit Amp, the error of the output voltage can be reduced as in the previous embodiment. Further, in any state (“a” and “b”) determined by the control digital code shown in Table 7, the load current I ₀ has a circuit configuration that only passes through the switch unit once. Like this, the resistance of the switch part does not have a great influence. Furthermore, since the resistor R122 is shared by both the state “a” and the state “b”, for example, as in the third embodiment, the number of resistors can be minimized.

In the voltage adjustment circuit according to the fifth embodiment, the resistance selection circuit configuring the variable resistance section of the fourth embodiment is added to the variable resistance section by adding the number of stages in a cascade in the B terminal direction (that is, the first resistance _RL side). The other parts (current control unit Amp and first resistor R _L ) are the same as those in the third and fourth embodiments. FIG. 16 shows a circuit configuration when the number of stages of the resistance selection circuit is three, and the same components as those in the fourth embodiment shown in FIG.

Specifically, the variable resistance unit according to the fifth embodiment is configured by adding one more resistance selection circuit SEL203 to the resistance selection circuits SEL201 and SEL143 that configure the variable resistance unit according to the fourth embodiment. . The resistance selection circuit SEL203 includes a resistor R203, which is a second resistor in the voltage adjustment circuit, a first switch unit S203, and a second switch unit S203f. One end of the resistor R203 is connected to the connection point Z103 between the resistor R143 in the resistance selection circuit SEL143 and the first switch unit S103 and the second switch unit S103f, and the other end is a first switch in the resistance selection circuit SEL203. It is connected to one end of the part S203 and a connection point Z203 which is one end of the second switch part S203f. The other end of the first switch unit S203 is connected to the terminal B of the variable resistor unit, and the other end of the second switch unit S203f is connected to the terminal C of the variable resistor unit.

Next, the operation mode of the fifth embodiment will be described.
In the fifth embodiment, the number of gradations of the fourth embodiment is expanded, and Table 8 shows the relationship between the operation state of the variable resistance unit and the resistance value in the fifth embodiment. In Table 8, as before, the resistance value of the resistor R122, R143 and R203 and _{r u,} and the resistance of each switch unit in the _{r N.} In the fifth embodiment, as in the fourth embodiment, there is only one resistance selection circuit in which the switch is turned on in each state of the control digital code, so that a complicated decoding circuit is unnecessary. Further, the number of second resistors constituting the variable resistance unit is equal to the number of states of the control digital code.

Further, in the fifth embodiment, the same effects as the effects shown in the fourth embodiment can be obtained. In the fifth embodiment, as shown in FIG. 16, a resistance selection circuit is added and repeatedly connected to the cascade. In this way, the number of gradations is expanded. That is, a multi-gradation product can be realized by repeating the same circuit connection form. Therefore, this configuration is suitable for integrated circuit designs in which the same pattern is often repeatedly arranged to increase the density.

Note that the second resistor in the variable resistor portion of the fifth embodiment may have a different value as necessary. For example, the resistor R122 shown in FIG. 16 may be replaced with a connection wiring portion S that works as a substantially 0Ω resistor. In this case, the resistance values R _AB (ideal values) between the variable resistor portions AB corresponding to the states “a”, “b”, and “c” shown in Table 8 are “0Ω”, “r _u ”, and “r _u ”, respectively. 2r _u ”. The value of resistance including a resistance _{r N} switches, each _{_{_{"0Ω + r N", "}}} r u + r N", becomes _"2r u + _{r _N".}

FIG. 17 is a circuit diagram illustrating a configuration of a variable resistance unit, which is a circuit configuration part different from that of the first embodiment, as a configuration of the voltage adjustment circuit according to the sixth embodiment of the present invention. The configuration shown in FIG. 17 replaces the variable resistance portion TR10 in the first embodiment shown in FIG. 10B, and includes a plurality of variable resistance portions in the third embodiment shown in FIG. It is applied to each of the second variable resistance section and connected as follows. In other words, the terminal A ₂ of the _second variable resistor unit is connected in common with the terminal A _{1 of} the first variable resistor unit via the fixed resistor unit, and becomes the terminal A of the entire variable resistor unit. Further, the terminals B ₁ and C ₁ of the first variable resistance section and the terminals B ₂ and C ₂ of the _second variable resistance section are connected in common to become terminals B and C of the entire variable resistance section. Here, the fixed resistance portion is a resistance of the resistance value r _u which was connected in parallel for example, four, to generate a r _{u /} 4 as the combined resistance value. With the above configuration, as described _later, at r _u /4=0.25r u increments, it is to allow to adjust the resistance of the variable resistor.

Next, the operation mode of the sixth embodiment will be described.
Table 9 shows the relationship between the operating state of the variable resistance unit and the resistance value in Example 6. The sixth embodiment provides the nine states “a” to “i” shown in Table 9, among which five of the states “a”, “c”, “e”, “g”, and “i” are provided. In the case of one state, the load current I ₀ is controlled to flow only through the first variable resistance unit. In these five states, the control signal (control digital code [GB104, GB103, GB102, GB101, GB100]) input to the second variable resistor section is set to all bits “0”, and the first variable The resistance portion is controlled to be the same as each of the five states “a” to “e” shown in Table 6 of the third embodiment.

In the case of the four states “b”, “d”, “f”, and “h” shown in Table 9, the load current I ₀ is controlled to flow through the second variable resistance unit. In these four states, the control signal (control digital code [GA104, GA103, GA102, GA101, GA100]) input to the first variable resistor section is set to all bits “0”, and the second variable The resistance section is controlled to be the same as each of the four states of circuit states “a” to “d” shown in Table 6 of the third embodiment.

In the variable resistance unit according to the sixth embodiment, the resistance value between the terminals AB and the terminal AC of the variable resistance unit is set to 0.25 _{r u} by the combination of the first and second control signals shown in Table 9. It can be adjusted in steps. Note that the principle of adjusting the output voltage _Vout by adjusting the resistance of the variable resistance unit is the same as that of each of the embodiments described above.
In the above, the sixth embodiment, by applying respectively the variable resistor portion in the embodiment 3 in the first and second variable resistor, the resistance value of the entire variable resistor can be adjusted in 0.25 R _u increments Although shown as a configuration, it is not limited to this configuration. For example, the first embodiment can be realized by appropriately combining the resistance values obtained from the first and second variable resistor portions without providing the fixed resistor portion, or as the first and second variable resistor portions. Alternatively, by applying the variable resistance unit in the second embodiment, it is possible to adjust the resistance value of the entire variable resistance unit with different step values.

As described above, since each of the first and second variable resistance units of the sixth embodiment has the same configuration as that of the previous embodiment, the load current I ₀ does not flow through the switch unit on the feedback path. . Therefore, it is possible to stabilize the output voltage quickly and with high accuracy as compared with Conventional Example 1, and provide a voltage adjustment function having excellent linearity as compared with Conventional Example 2. In addition, it is possible to cope with an increase in the number of gradations for voltage adjustment and subdivision of resolution for voltage adjustment.

FIG. 18 is a diagram illustrating the configuration of the voltage regulator circuit according to the seventh embodiment of the present invention. 18A is an overall configuration diagram of the seventh embodiment. In FIG. 18, the variable resistor TR1 in the basic configuration of the voltage regulator circuit according to the present invention shown in FIG. 1 or the first embodiment shown in FIG. Instead of the variable resistance part TR10, a variable resistance part TR160 is adopted. The variable resistance unit TR160 is provided with a plurality of terminals B1 and B2 instead of the terminal B shown in FIG. 1 or FIG. 10A, and the terminals B1 and B2 are respectively connected to the first resistors R _L1 and R _L2. Connect to. In FIG. 18, the number of terminal groups related to the terminal B is two, but the number of terminals can be expanded to three or more, and a first resistor is connected to each of them. The configuration of other parts of the voltage adjustment circuit is the same as the basic configuration shown in FIG. 1 or the first embodiment shown in FIG.

FIG. 18B is a partial circuit diagram of the variable resistance unit in the seventh embodiment. The description will focus on the differences from the configuration of the variable resistance portion in the second embodiment shown in FIG. In the seventh embodiment, the first switch section provided for each resistance of the variable resistance section and each connection wiring section is expanded to a switch section group including a plurality of switch sections.
For example, as shown in FIG. 18B, the first switch section group is connected to each of the node Z100 of the resistance selection circuit SEL160 and the node Z101 of the resistance selection circuit SEL161. Each terminal d of the first switch unit groups S100a and S100b is connected to the node Z100, and each terminal d of the first switch unit groups S101a and S101b is connected to the node Z101. Also, the terminals s of S100a and S101a of the first switch section group are connected to the terminal B1 of the variable resistance section, and the terminals s of S100b and S101b of the first switch section group are connected to the terminal B2 of the variable resistance section. Each is connected. Then, S100a and S101a of the first switch unit group are controlled by control signals G100a and G101a, and S100b and S101b of the first switch unit group are controlled by control signals G100b and G101b, respectively. When these control signals are “1”, the corresponding switch unit group is turned on. The configuration of the other part of the variable resistance unit is the same as that of the second embodiment shown in FIG. 12 (however, the resistance value of the second resistor is r _u ).

Further, in the above description of the circuit configuration of the seventh embodiment, an example in which the variable resistance portion in the second embodiment shown in FIG. 12 is expanded and configured is shown. In the variable resistance portion TR160 shown in FIG. It is also possible to apply the variable resistance portion in the first, third, and fourth embodiments. That is, a plurality of (B1 and B2) terminals B of each variable resistance unit are connected to the first resistor, and a first switch unit is connected to each of the plurality of terminals B (B1 and B2). The first switch section group can be expanded to the circuit configuration of the seventh embodiment. Thereby, it is possible to select a plurality of types of first resistors, and voltage adjustment with the same number of gradations can be performed for each selected first resistor.

Next, the operation mode of the seventh embodiment will be described.
In the seventh embodiment, the load current I ₀ is controlled so as to selectively flow through either the resistor R _L1 or R _L2 . If the resistance _{R L1} is selected, the control signal G100b and G101b are all set to "0", respective control signals G100 and G101 and the control signal G100a and G101a are set to the same logic value. That is, G100 = G100a and G101 = G101a are set. On the other hand, when the resistance _{R L2} is selected, the control signal G100a and G101a are all set to "0", respective control signals G100 and G101 and the control signal G100b and G101b are set to the same logic value. That is, G100 = G100b and G101 = G101b are set. Here, the relationship between the resistance value of the variable resistance unit and the control signals G100 and G101 does not relate to which of the first resistors R _{L1 and} R _L2 is selected. In the seventh embodiment, the variable resistance portion of the first embodiment is expanded as described above, and the relationship between the resistance value and the control signal is the same as that in Table 3. That is, if G100 = 0, G101 = 1 and G102 = 0, the resistance value of the variable resistor becomes _{r u.} In addition, the relationship between the resistance value of the variable resistor section and the output voltage is determined by matching R _L in the expressions (4) to (11) in the description of the first embodiment with R _L1 or It is equivalent to replacing any of R _L2 . Thus, also in Example 7, the resistance value of the variable resistance unit can be changed by the control signal.

As described above, also in the seventh embodiment, the load current I ₀ does not flow through the second switch units S100f, S101f,... On the feedback path. Therefore, Example 7 has the effect shown in previous Example 1, and can change the resistance value of the 1st resistance connected to a variable resistance part in addition. Therefore, as compared with the first embodiment, voltage adjustment with higher flexibility and higher flexibility is possible. Further, when the variable resistor section in the second to fourth embodiments is expanded to have the circuit configuration of the seventh embodiment, in addition to the effects exhibited by each, it is possible to perform more flexible and flexible voltage adjustment.

The voltage adjustment circuit according to the eighth embodiment of the present invention includes a switch circuit having the configuration shown in FIG. 19A as the first switch unit and the second switch unit configuring the variable resistor unit described above. Adopted. That is, the switch circuit includes an NMOS transistor N171, a PMOS transistor P171, and an inverter INV. The drain of the NMOS transistor N171 and the source of the PMOS transistor P171 are connected to the terminal d, and the source of the NMOS transistor N171 and the drain of the PMOS transistor P171 are connected to the terminal s. The gate of the NMOS transistor N171 and the input of the inverter INV are connected to the terminal g, and the gate of the PMOS transistor P171 is connected to the output of the inverter INV. Further, the substrate of the NMOS transistor N171 is connected to the ground GND, and the substrate of the PMOS transistor P171 is connected to _VDD . Note that the terminals d, s, and g shown in FIG. 19 are connected corresponding to the symbols d, s, and g of the switch portion in each of the embodiments described above.

Next, the operation mode of the eighth embodiment will be described.
When the input reference voltage _VIN is a low voltage, it is effective to use NMOS transistors for the first switch portion and the second switch portion. However, when the input reference voltage _VIN rises or V _DD falls due to process fluctuations or a high use temperature, the gate-source voltage of the NMOS transistor becomes small. When the gate-source voltage decreases to _VT or less, the NMOS transistor can no longer hold the on state, and circuit operation may be disabled. In the eighth embodiment, even when the input reference voltage _VIN is increased or the V _DD is decreased and the NMOS transistor is turned off, the PMOS transistor is designed to be turned on instead. Enables stable operation.
Also in the eighth embodiment, since the variable resistor section that constitutes the switch circuit described above as the switch section has the same circuit topology itself, the load current I ₀ does not flow through the second switch section for feedback. Absent. Therefore, there is no change in the function and effect exhibited by each of the embodiments described above.

The voltage regulator circuit according to the ninth embodiment of the present invention employs the NMOS transistor N172 shown in FIG. 19B as the first switch section and the second switch section that constitute the variable resistor section described above. Is. The drain d, gate g, and source s of the NMOS transistor N172 are connected as described above as the respective terminals of each switch unit, and the substrate of the NMOS transistor N172 is connected to the source s.

In the ninth embodiment, the source potential of the NMOS transistor N172 to which the input reference voltage _VIN is applied is always equal to the substrate potential. Therefore, the input reference voltage V _IN is the equivalent resistance of the V _T increases the transistor of the transistor is increased by increasing the so-called back bias effect does not occur. As a result, it is possible to perform voltage adjustment over a wider range of the input reference voltage _VIN and under a lower _VDD condition than when the substrate of the NMOS transistor N172 is connected to the ground GND. However, in the ninth embodiment, the range of the operable input reference voltage _VIN and the power supply voltage V _DD is slightly narrower than that in the eighth embodiment, but on the other hand, the area efficiency is reduced because the number of constituent elements of each switch unit is small. It will be excellent.
Also in the ninth embodiment, since the circuit topology itself is the same in the variable resistor portion configured by using the NMOS transistor as a switch portion, the load current I ₀ does not flow through the second switch portion for feedback. Absent. Therefore, there is no change in the function and effect exhibited by each of the embodiments described above.

The voltage adjustment circuit according to the tenth embodiment of the present invention is a vertical circuit in which a channel is formed in the vertical direction with respect to the surface of the silicon substrate as the first switch unit and the second switch unit constituting the variable resistor unit described above. A type MOS transistor is employed. FIG. 20 shows a vertical MOS transistor employed as Example 10, FIG. 20 (a) is a schematic diagram showing the structure of the vertical MOS transistor, and FIG. 20 (b) shows a vertical MOS transistor. It is sectional drawing.

The vertical MOS transistor has a structure in which a channel from the source to the drain is formed in the vertical direction with respect to the surface of the silicon substrate, and the channel is surrounded by the gate electrode through the oxide film SiO ₂ . As a result, the center of the channel is completely insulated from the substrate. With this structure, the vertical MOS transistor also does not generate the back bias effect described above. That is, the on-resistance does not increase even when the source potential is increased. Therefore, as in the ninth embodiment, the operation can be performed over a wide range of the input reference voltage _VIN and under the condition of the lower power supply voltage V _DD .

FIG. 20 (c) shows the correspondence between the electrodes of the vertical MOS transistor N180 and the terminals of the switch sections in the variable resistance section of the present invention. The drain, source and gate of the vertical MOS transistor correspond to the terminals d, s and g. Note that the vertical MOS transistor has no substrate electrode.

As described above, since the vertical MOS transistor does not generate the back bias effect, the voltage adjustment circuit employing the tenth embodiment extends over a wide range of the input reference voltage _VIN as in the ninth embodiment and is lower. It is possible to adjust the voltage under the condition of the power supply voltage V _DD . Further, since the vertical MOS transistor employed as the tenth embodiment has no substrate electrode, unlike the eighth embodiment, a large distance is required between the transistors in order to electrically separate the substrate electrodes of different MOS transistors. It becomes unnecessary to take. Therefore, it is possible to provide a voltage regulator circuit that is more area efficient than the above-described embodiments.
Also in the tenth embodiment, since the circuit topology itself is the same for the variable resistor portion configured with the vertical MOS transistor as the switch portion, the load current I ₀ does not flow through each switch portion for feedback. Therefore, there is no change in the function and effect exhibited by each of the embodiments described above.

Note that the present invention is not limited to the above-described embodiments, and includes various modifications. For example, it is possible to insert a resistor, a diode, or the like between the PMOS transistor P1 constituting the current control unit Amp and the variable resistor unit, or between the variable resistor unit and the first resistor. As a result, it is possible to achieve highly accurate voltage adjustment for obtaining a desired output voltage. In addition, the polarity of each MOS transistor used in the circuit configuration described above can be switched so that V _DD is replaced with ground GND and ground GND is replaced with V _DD . Also in the above modification, the point that the load current does not flow through the switch part on the path returning to the input of the current control part Amp (differential amplifier OP1), which is an important point of the present invention, is not changed. There is no change in the operational effects of the above-described embodiments.

OP1... Differential amplifiers TR1, TR10, TR40, TR70, TR160... Variable resistance units SEL1, SEL2, SEL100, SEL101, SEL102, SEL143, SEL144, SEL160, SEL161, SEL201, SEL203. , S100b, S101a, S101b, S201 to S203... First switch unit S1f, S100f to S104f, S203f... Second switch unit G100 to G104, GA100 to GA104, GB100 to GB104, G100 to G100b, G101 to G101b, G203 …Control signal

Claims

A current control unit having a reference voltage as an input; a first resistor; and a variable resistance unit connected between the output of the current control unit and the first resistor,
The variable resistance unit is composed of a plurality of resistance selection circuits connected in parallel,
Each of the resistance selection circuits includes a second resistor connected to the output of the current control unit, a first switch unit connected between the first resistor and the second resistor, and the second resistor. And a second switch unit for applying voltage feedback by connecting between a connection point between the first switch unit and the input of the current control unit, the first switch unit and the second switch unit A voltage regulator circuit that is turned on and off in conjunction with.
The voltage regulator circuit according to claim 1,
The first switch unit and the second switch unit may be turned on and off in conjunction with a control signal supplied to the first switch unit and the second switch unit included in each of the resistance selection circuits. A voltage regulator circuit that is controlled.
The voltage regulator circuit according to claim 2, wherein
A voltage regulator circuit that causes at least two of the resistance selection circuits to function simultaneously by a combination of the control signals.
The voltage regulator circuit according to any one of claims 1 to 3,
An output of the current control unit including the plurality of variable resistance units, and the connection point of the arbitrary resistance selection circuit included in the one variable resistance unit connected to the resistance selection circuit included in the other variable resistance unit Instead of the above, the voltage adjusting circuit is configured as a new variable resistance unit connected to the second resistor.
The voltage regulator circuit according to claim 4, wherein
A plurality of the new variable resistor units and a series of fixed resistor units connected to the new variable resistor units are connected in parallel, or a plurality of the new variable resistor units are connected in parallel. Voltage adjustment circuit.
A current control unit that receives a reference voltage; a plurality of first resistors connected in parallel; and a variable resistance unit connected between the output of the current control unit and the plurality of first resistors.
The variable resistance unit is composed of a plurality of resistance selection circuits connected in parallel,
Each of the resistance selection circuits includes a second resistor connected to the output of the current control unit, and a first switch unit connecting between each of the plurality of first resistors and the second resistor. A first switch section group comprising: a second switch section for applying voltage feedback by connecting between a connection point between the second resistor and the first switch section group and an input of the current control section; And a voltage adjustment circuit that is turned on and off in conjunction with the second switch section for each of the first switch sections.
A current control unit having a reference voltage as an input; a first resistor; and a variable resistance unit connected between the output of the current control unit and the first resistor,
The variable resistance unit includes N + 1 (N is an integer of 1 or more) resistance selection circuits connected in parallel.
Each of the resistance selection circuits includes a second resistor, a first switch unit connected between the first resistor and the second resistor, and a second resistor and the first switch unit. A second switch unit connected between the connection point and the input of the current control unit to apply voltage feedback;
Connecting the second resistance of the first resistance selection circuit to the output of the current control unit;
Connecting the second resistance of the (N + 1) th resistance selection circuit to a connection point between the second resistance of the Nth resistance selection circuit and the first switch unit;
A voltage regulator circuit that turns on and off the first switch unit and the second switch unit in conjunction with each other.
The voltage regulator circuit according to claim 7, wherein
The first switch unit and the second switch unit may be turned on and off in conjunction with a control signal supplied to the first switch unit and the second switch unit included in each of the resistance selection circuits. A voltage regulator circuit which is controlled and causes one of the resistance selection circuits to function according to a combination of the control signals.
A voltage regulator circuit according to any one of claims 1 to 8,
The voltage regulator circuit, wherein the second resistors included in each of the resistance selection circuits have different resistance values.
The voltage regulator circuit according to claim 9, wherein
The voltage adjusting circuit, wherein the second resistor includes a connection wiring as a 0Ω resistor.
The voltage regulator circuit according to any one of claims 1 to 10,
Each of the first switch unit and the second switch unit is composed of a parallel circuit of a PMOS transistor and an NMOS transistor, and connects the source of the PMOS transistor and the drain of the NMOS transistor to the second resistance side, A voltage adjustment circuit, wherein the on / off signal is input to each gate of the PMOS transistor and the NMOS transistor.
The voltage regulator circuit according to any one of claims 1 to 10,
Each of the first switch unit and the second switch unit is composed of an NMOS transistor, the drain of the NMOS transistor is connected to the second resistance side, and the substrate of the NMOS transistor is connected to the source of the NMOS transistor The voltage adjustment circuit is characterized in that the on / off signal is input to the gate of the NMOS transistor.
The voltage regulator circuit according to any one of claims 1 to 10,
Each of the first switch unit and the second switch unit is composed of a vertical MOS transistor in which a channel is formed in the vertical direction with respect to the surface of the silicon substrate, and the drain of the vertical MOS transistor is connected to the second resistance side. And a signal for turning on and off is input to the gate of the vertical MOS transistor.