JP2015191280A - Semiconductor device and current source control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a current source control method capable of reducing the current consumption of a current source in an operation state.SOLUTION: The semiconductor device includes: a capacitor 22 whose one end is connected to the output terminal of an arithmetic amplifier 22, and whose other end is connected to the inverted input terminal of the arithmetic amplifier 22; a first switch SW1 capable of switching a connection state and non-connection state between a voltage divider 25 and a ground part 24B; a second switch SW2 capable of switching an input state that a feedback voltage Vis input to the other end of the capacitor C2 and a non-input state that the feedback voltage Vis not input to the other end of the capacitor C2; and a signal supply terminal 26 for supplying a control signal to the first switch SW1 and the second switch SW2 such that the connection state and non-connection state by the first switch SW1 are repeatedly switched, and that the input state and non-input state by the second switch SW2 are repeatedly switched.

Description

  The present invention relates to a semiconductor device and a current source control method.

  As a method for reducing the power consumption of a regulator (current source) mounted on a semiconductor device, a method for stopping the operation of the regulator is known (for example, see Patent Document 1).

  FIG. 6 shows an example of the configuration of the conventional regulator 100. As an example, as shown in FIG. 6, the regulator 100 includes a detection circuit 110, an operational amplifier 120, an output circuit 130, a connection cutoff circuit 140, and a voltage setting circuit 150. A driving voltage HV is input to the operational amplifier 120 and the output circuit 130. A control signal ENREG whose signal level transitions between a high level (H level) and a low level (L level) is input to the detection circuit 110 and the operational amplifier 120. The detection circuit 110 and the operational amplifier 120 receive the control signal ENREG. It is controlled according to the signal level.

The detection circuit 110 detects the output voltage _Vout of the output terminal 100A of the regulator 100, and generates and outputs a feedback voltage _VFB corresponding to the detected output voltage _Vout . The operational amplifier 120 has a non-inverting input terminal, an inverting input terminal, and an output terminal. The reference voltage V _REF input to the inverting input terminal and the feedback voltage V of the detection circuit 110 input to the non-inverting input terminal. A comparison result V _AOUT comparing with _FB is output. The output circuit 130 supplies a current to the output terminal 100A based on the comparison result _VAOUT input from the operational amplifier 120 and maintains the output voltage _out .

The connection cutoff circuit 140 switches between a connection state and a non-connection state between the output terminal 110A of the detection circuit 110 and the non-inverting input terminal of the operational amplifier 120. The voltage setting circuit 150 sets the feedback voltage _VFB to a predetermined voltage.

The output terminal 100A of the regulator 100, a smoothing capacitor 160 to suppress voltage fluctuation of the output voltage _{V out,} and the load circuit 170 is connected is a supply destination of the output voltage _{V out.} The load circuit 170 includes a current source IL and a switch SW. When the switch SW is turned on, a current based on the output voltage _Vout is supplied to the current source IL.

  The regulator 100 configured as described above is switched between an operating state and a stopped state according to the signal level of the control signal ENREG. That is, when the switch SW is turned on, the control signal ENREG becomes H level, and the regulator 100 enters an operating state. When the switch SW is turned off, the control signal ENREG becomes L level, and the regulator 100 is stopped.

JP 2006-146421 A

However, when the regulator 100 is in an operating state, as shown in FIG. 6, the H-level control signal ENREG is constantly input to the gate of the N-channel transistor N ₀ which is a component of the detection circuit 110, and the N-channel transistor N ₀ The on state is continued. Therefore, there is a problem that current is consumed in the detection circuit 110 while the regulator 100 is in an operating state.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device and a current source control method capable of reducing current consumption of a current source in an operating state.

  In order to achieve the above object, in the semiconductor device according to claim 1, one end is connected to an output terminal of an operational amplifier having a non-inverting input terminal to which a reference voltage is input, and the other is connected to the inverting input terminal of the operational amplifier. A capacitive element to which an end is connected, a voltage divider that divides the additional voltage input from a supply terminal that supplies an additional voltage obtained by adding the voltage of the capacitive element to the output voltage of the output terminal to a load, and a low voltage A first switching unit capable of switching between a connection state and a non-connection state with a voltage source, and an input state in which a feedback voltage obtained by dividing the additional voltage by the voltage divider is input to the other end of the capacitive element And a second switching unit capable of switching between a non-input state where the feedback voltage is not input to the other end of the capacitive element, the connection state and the non-connection state are repeatedly switched, and the input state and the Non-input state is repeated A control signal for controlling the first switching unit and the second switching unit to be switched returns including a supply section for supplying to said first switching unit and the second switching unit.

  In order to achieve the above object, the current source control method according to claim 13 has one end connected to an output terminal of an operational amplifier having a non-inverting input terminal to which a reference voltage is input, and the inverting input terminal of the operational amplifier. And a voltage divider that divides the additional voltage input from a supply terminal that supplies an additional voltage obtained by adding the voltage of the capacitive element to the output voltage of the output terminal to a load. A first switching unit capable of switching between a connection state and a non-connection state between the voltage source and the low voltage source, and a feedback voltage obtained by dividing the additional voltage by the voltage divider is input to the other end of the capacitive element. A second switching unit capable of switching between an input state and a non-input state in which the feedback voltage is not input to the other end of the capacitive element, and the connection state and the non-connection state in the semiconductor device are repeatedly switched, And said Supplying the force status and control signals for controlling the first switching unit as the non-input state is switched repeatedly and the second switching unit to the first switching unit and the second switching unit, comprising a.

  According to the present invention, it is possible to reduce the current consumption of the operating current source.

It is a schematic block diagram which shows an example of the principal part structure of the semiconductor device which concerns on embodiment. It is a time chart which shows an example of the flow of operation | movement of the regulator contained in the semiconductor device which concerns on embodiment. It is a time chart which shows the modification of the flow of operation | movement of the regulator contained in the semiconductor device which concerns on embodiment. It is a schematic block diagram which shows the modification of the principal part structure of the semiconductor device which concerns on embodiment. It is a schematic block diagram which shows the modification of the principal part structure of the semiconductor device which concerns on embodiment. It is a schematic block diagram which shows an example of the conventional regulator.

  Embodiments for carrying out the present invention will be described below in detail with reference to the drawings.

  As an example, as illustrated in FIG. 1, the semiconductor device 10 includes a regulator 12 and a control unit 14. Although not illustrated in FIG. 1, the semiconductor device 10 according to the present embodiment includes a main regulator and a sub-regulator, and an output current of the main regulator and an output current of the sub-regulator with respect to a load 18 to be described later. Is selectively input. In the present embodiment, for convenience of explanation, a case where the regulator 12 is used as a sub-regulator will be described as an example. However, the present invention is not limited to this, and the regulator 12 may be used as a main regulator. .

The output terminal 12A of the regulator 12 (an example of a supply terminal according to the present invention) is connected to the capacitor C1 and the load 18. The capacitor C1 is a so-called bypass capacitor. One end of the capacitor C1 is connected to the output terminal 12A, and the other end of the capacitor C1 is grounded. The load 18 is a supply destination of the current I _load based on the output voltage V _out of the regulator 12 (the voltage of the output terminal 12A) (a load that operates when the current I _load is supplied). Examples of the load 18 include a circuit corresponding to the load circuit 170 illustrated in FIG. 6, a storage element (for example, a nonvolatile memory), a CPU (Central Processing Unit), or an ASIC (Application Specific Integrated Circuit).

  The control unit 14 controls the regulator 12 by supplying the regulator 12 with a control signal whose signal level transitions between the H level and the L level. An example of the control unit 14 is a CPU or an ASIC.

  The regulator 12 includes a reference voltage circuit 20, an operational amplifier 22, a detection circuit 24, a capacitor C2 (an example of a capacitive element according to the present invention), a second switch SW2 (an example of a second switching unit according to the present invention), and a signal A supply terminal 26 (an example of a supply unit according to the present invention) is included.

The reference voltage circuit 20 is grounded and generates and outputs a reference voltage V _ref based on the driving voltage input by the driving voltage HV.

The operational amplifier 22 includes an inverting input terminal, a non-inverting input terminal, and an output terminal. The operational amplifier 22 is grounded and is driven when a driving voltage is input. The reference voltage V _ref is input to the non-inverting input terminal of the operational amplifier 22. The output terminal of the operational amplifier 22 is negatively fed back to the inverting input terminal. A capacitor C2 that is a phase compensation capacitor for the operational amplifier 22 is inserted in the negative feedback path. That is, the output terminal of the operational amplifier 22 is connected to the non-inverting input terminal via the capacitor C2. Specifically, one end of the capacitor C2 is connected to the output terminal of the operational amplifier 22, and the other end of the capacitor C2 is connected to the inverting input terminal of the operational amplifier 22.

The detection circuit 24 detects the output voltage V _out (≈the output voltage of the operational amplifier 22 (reference voltage V _ref ) + the voltage V _{C of the} capacitor C 2), which is an example of the additional voltage according to the present invention, and detects the detected output voltage V It is a circuit that generates and outputs a feedback voltage V _FB corresponding to _out .

The detection circuit 24 includes a series circuit of a voltage divider 25 using resistors R1 and R2 and a first switch SW1 (an example of a first switching unit according to the present invention). The voltage divider 25 extracts the feedback voltage V _FB (an example of the feedback voltage according to the present invention) by dividing the output voltage V _out input from the output terminal 12. The first switch SW1 is a switch that can switch between a connection state and a non-connection state between the voltage divider 25 and the ground unit 24B (an example of the low voltage source according to the present invention) that is set to the ground voltage.

The voltage divider 25 is connected to the ground unit 24B, which is an example of the low voltage source according to the present invention, via the first switch SW1. That is, one end of the first switch SW1 is grounded by being connected to the ground part 24B, and the other end of the first switch SW1 is connected to one end of the resistor R1. The other end of the resistor R1 is connected to one end of the resistor R2. The other end of the resistor R2 is connected to the output terminal 12A. Note that the feedback voltage V _FB (an example of the feedback voltage according to the present invention) is extracted from a connection point 24A between the resistor R1 and the resistor R2 in the voltage divider 25.

The second switch SW2, the feedback voltage V _FB is the non-input state and a switchable switch the input state and the feedback voltage V _FB that is input to the other end is not inputted to the other end of the capacitor C2 of the capacitor C2.

  The second switch SW2 is inserted between the other end of the capacitor C2 and the connection point 24A. That is, one end of the second switch SW2 is connected to the connection point 24A, and the other end of the second switch SW2 is connected to the other end of the capacitor C2. In the following, for convenience of explanation, when it is not necessary to distinguish between the first switch SW1 and the second switch SW2 (when referring to both the first switch SW1 and the second switch SW2), they are referred to as “switch SW”. ).

  The signal supply terminal 26 supplies a control signal to the switch SW so that the connection state and the non-connection state are repeatedly switched by the first switch SW1, and the input state and the non-input state are repeatedly switched by the second switch SW2.

  The signal supply terminal 26 is connected to the switch SW. The signal supply terminal 26 is connected to the control unit 14, and a control signal is input by the control unit 14, and the input control signal is supplied to the switch SW.

  The switch SW is, for example, an N channel type transistor. In the N-channel transistor used as the first switch SW1, the gate is connected to the signal supply terminal 26, the drain is connected to one end of the resistor R1, and the source is connected to the ground unit 24B. In the N-channel transistor used as the second switch SW2, the gate is connected to the signal supply terminal 26, the drain is connected to the connection point 24A, and the source is connected to the other end of the capacitor C2. Therefore, the conduction state and the non-conduction state between the drain and the source are switched according to the signal level of the control signal input to the gate of each N-channel transistor. That is, the first switch SW1 and the second switch SW2 are switched in synchronization according to the signal level of the input control signal.

In the present embodiment, the switch SW is turned on when an H level control signal is input to the switch SW, and the switch SW is turned off when an L level control signal is input to the switch SW. Therefore, when an H level control signal is input and the first switch SW1 is turned on, current is supplied to the detection circuit 24. When the first switch SW1 is turned off, supply of current to the detection circuit 24 is stopped. The When the second switch SW2 is turned off, the feedback voltage _VFB is not input to the inverting input terminal of the operational amplifier 22, and when the second switch SW2 is turned on, the feedback voltage _VFB is applied to the inverting input terminal of the operational amplifier 22. _FB is input.

  Next, the operation of the regulator 12 will be described with reference to FIG. Hereinafter, for convenience of explanation, a case where the regulator 12 is set to the stop mode or the operation mode by the control unit 14 will be described. The stop mode refers to, for example, a state in which the switch SW is turned off and the driving voltage HV is not input to the reference voltage circuit 20 and the operational amplifier 22. The operation mode refers to, for example, a state where the driving voltage HV is input to the reference voltage circuit 20 and the operational amplifier 22 (a state where the regulator 12 is driven). The operation mode is roughly classified into a normal operation mode and an intermittent operation mode. In the example shown in FIG. 2, the regulator 12 shifts from the normal operation mode to the intermittent operation mode and returns from the intermittent operation mode to the normal operation mode.

  First, when the regulator 12 shifts from the stop mode to the normal operation mode, the driving voltage HV is input to the reference voltage circuit 20 and the operational amplifier 22, and an H level control signal is sent from the control unit 14 to the signal supply terminal 26. Entered. The H level control signal is input from the signal supply terminal 26 to the switch SW, and the switch SW is turned on accordingly. When the switch SW is turned on, the normal operation mode is started.

When the normal operation mode is started, a voltage obtained by adding the voltage V _{C of the} capacitor C 2 to the reference voltage V _ref is set as the output voltage V _out, and this output voltage V _out is input to the capacitor C 1 and the load 18. The voltage V _{C of the} capacitor C2 is a voltage corresponding to a difference (potential difference) between the reference voltage V _ref and the feedback voltage V _FB , for example. In this case, a current is supplied from the output terminal 12 </ b> A to the detection circuit 24, and the current is consumed by the detection circuit 24.

  Next, an L level control signal is input from the control unit 14 to the signal supply terminal 26 in the normal operation mode. The L level control signal is input from the signal supply terminal 26 to the switch SW, and the switch SW is turned off accordingly. When the switch SW is turned off, the normal operation mode is shifted to the intermittent operation mode.

When the intermittent operation mode is started, first, the switch SW is turned off in the hold period, and the switch SW is turned on in the next sampling period. The hold period refers to a period that is predetermined as a period for holding the output voltage _Vout within a previously allowed voltage range. The sampling period refers to a period set in advance as a period for returning the output voltage _Vout to the voltage at the time when the intermittent operation mode is started (when the normal operation mode is finished), for example.

In the intermittent operation mode, one cycle is formed by the hold period and the sampling period. In the intermittent operation mode, a plurality of cycles are performed such that the output voltage _Vout is maintained within a voltage range that is allowed in advance (for example, a voltage range that the load 18 can accept). Here, the execution of a plurality of cycles means that the hold period and the sampling period are repeatedly switched. In the present embodiment, since each of the hold period and the sampling period is an invariant time (fixed time), the hold period and the sampling period are switched periodically (regularly).

In the hold period, the switch SW is turned off. Therefore, the operational amplifier 22 operates as a voltage follower. However, since a leak current (current leaking from the capacitor C2) is generated in the capacitor C2 (since the capacitor C2 is discharged), the output voltage _Vout in the hold period shown in FIG. 2 gradually decreases. Then, when a first predetermined time (for example, 1 millisecond) elapses after the switch SW is turned off, an H level control signal is input from the control unit 14 to the signal supply terminal 26. The H level control signal is input from the signal supply terminal 26 to the switch SW, and the sampling period is started accordingly.

Here, the first predetermined time which is an example of the first time according to the present invention is, for example, the output voltage _Vout after the switch SW is turned off to the allowable lower limit voltage (an example of the first threshold according to the present invention). The time to reach is the time obtained in advance by simulation or experiment. The allowable lower limit voltage refers to, for example, a lower limit voltage within a voltage range in which the operation of the load 18 can be compensated (a lower limit voltage allowed by the load 18). In this embodiment, the voltage range that can compensate the operation of the load 18 is 1.35 volts or more and less than 1.52 volts, the output voltage _Vout in the normal operation mode is 1.5 volts, and the allowable lower limit voltage is 1 However, the present invention is not limited to this. For example, instead of the allowable lower limit voltage, a voltage greater than 1.35 volts and smaller than 1.5 volts (for example, 1.4 volts) may be employed.

  In the present embodiment, the invariant time is adopted as the first predetermined time, but the present invention is not limited to this. A variable time customized according to a user instruction (for example, an instruction received by a user interface connected to the control unit 14) or a variable time adjusted by the control unit 14 according to a change in environmental conditions. It may be adopted. The environmental conditions refer to, for example, the temperature and humidity of the installation environment of the semiconductor device 10 and the strength of a shield that protects the semiconductor device 10 or the regulator 12 (particularly, the capacitor C2) from electromagnetic disturbance.

  In the sampling period, the switch SW is turned on. Therefore, charging of the capacitor C2 is started. When a second predetermined time (for example, 30 microseconds) has elapsed after the switch SW is turned on, when an L level control signal is input from the control unit 14 to the switch SW via the signal supply terminal 26, A hold period of 1 cycle is started. If the H level control signal is continuously input to the switch SW when the second predetermined time has elapsed after the switch SW is turned on, the intermittent operation mode is shifted to the normal operation mode.

Here, the second predetermined time, which is an example of the second time according to the present invention, is, for example, the output voltage _Vout after the switch SW is turned on, for example, the normal operation mode voltage (for example, at the end of the normal operation mode). Time until reaching voltage (1.5 volts) refers to time obtained in advance by simulation or experiment. Here, the normal operation mode voltage is illustrated as an example of the second threshold value according to the present invention. However, the present invention is not limited to this, and instead of the normal operation mode voltage, a voltage lower than the normal operation mode voltage or a normal operation is used. The voltage may exceed the mode voltage. However, in this case, a voltage lower than the voltage in the normal operation mode or a voltage exceeding the voltage in the normal operation mode is larger than the allowable lower limit voltage and within a voltage range that can compensate the operation of the load 18 (for example, 1 .45 volts).

  Further, in this embodiment, invariant time is adopted as the second predetermined time, but the present invention is not limited to this, variable time customized according to user instructions, or environmental conditions You may employ | adopt the variable time adjusted by the control part 14 according to a change.

  As described above, in the semiconductor device 10 according to this embodiment, the regulator 12 operates intermittently under the control of the control unit 14. That is, in the intermittent operation mode of the regulator 12, the on / off state of the switch SW is repeated according to the signal level of the control signal supplied from the signal supply terminal 26 to the switch SW. This means that current is consumed in the detection circuit 24 only while the switch SW is on, and no current is consumed in the detection circuit 24 while the switch SW is off. Therefore, the semiconductor device 10 according to the present embodiment can reduce the current consumption of the regulator 12 in the operating state as compared with the configuration without the switch SW and the signal supply terminal 26.

Further, in the semiconductor device 10 according to the present embodiment, the switch SW is switched between the on state and the off state so that the output voltage V _out is maintained within a previously permitted voltage range. As a result, the semiconductor device 10 has a stable voltage with respect to the load 18 as compared with the case where the switch SW is not switched between the on state and the off state so that the output voltage V _out is maintained within a previously permitted voltage range. Supply can be realized.

Further, in the semiconductor device 10 according to the present embodiment, the switch SW is switched between the on state and the off state so that the output voltage V _out is maintained within a voltage range in which the operation of the load 18 can be compensated. As a result, the semiconductor device 10 has an output voltage within the voltage range that can compensate for the operation of the load 18 as compared with the case where the output voltage V _out does not have a configuration in which the operation is performed within the voltage range that can compensate for the operation of the load 18. V _out can be stably supplied to the load 18.

  Further, in the semiconductor device 10 according to the present embodiment, each of the first predetermined time and the second predetermined time is fixed to be a time, so that the ON state and the OFF state of the switch SW are periodically changed in the intermittent operation mode. Repeated. Thereby, the semiconductor device 10 can switch the on / off state of the switch SW with simple control compared to the case where the on / off state of the switch SW is irregularly switched in the intermittent operation mode.

In the semiconductor device 10 according to the present embodiment, in the intermittent operation mode, the switch SW is turned on when a first predetermined time has elapsed since the switch SW was turned off. As a result, the semiconductor device 10 can maintain the output voltage V _out within a range that does not fall below the lower limit value (allowable lower limit voltage) of the voltage range that is allowed in advance with a simple configuration.

In the semiconductor device 10 according to the present embodiment, in the intermittent operation mode, the switch SW is turned off when the second predetermined time has elapsed since the switch SW was turned on. As a result, the semiconductor device 10 can maintain the output voltage _Vout within a range that does not exceed the upper limit (voltage in the normal operation mode) of the voltage range allowed in advance with a simple configuration.

In the semiconductor device 10 according to the present embodiment, the operational amplifier 22 operates as a voltage follower when the switch SW is turned off in the intermittent operation mode of the regulator 12. Thereby, the semiconductor device 10 can suppress a decrease in the output voltage _Vout of the regulator 12 with a simple configuration as compared with the case where the operational amplifier 22 does not operate as a voltage follower.

Further, in the semiconductor device 10 according to the present embodiment, the phase compensation capacitor of the operational amplifier 22 is used as the capacitor C2. Thereby, the semiconductor device 10 can suppress a decrease in the output voltage _Vout during the hold period with a simple configuration as compared with a case where the phase compensation capacitor of the operational amplifier 22 is not used as the capacitor C2.

  In the semiconductor device 10 according to the present embodiment, the switching operation of the first switch SW1 and the switching operation of the second switch SW2 are synchronized. Thereby, the semiconductor device 10 can smoothly switch between the hold period and the sampling period as compared with the case where the switching operation of the first switch SW1 and the switching operation of the second switch SW2 are not synchronized in the intermittent operation mode. Can do.

  In the semiconductor device 10 according to the present embodiment, the control unit 14 that supplies a control signal to the signal supply terminal 26 is provided outside the regulator 12. Thereby, the semiconductor device 10 can simplify the configuration of the regulator 12 as compared with a case where a circuit for generating a control signal is mounted in the regulator 12.

  In the above embodiment, the case where the normal operation mode and the intermittent operation mode are selectively set by the control unit 14 is exemplified, but the present invention is not limited to this. For example, as shown in FIG. 3, only the intermittent operation mode may be adopted as the operation mode without including the normal operation mode. In this case, the current consumption of the regulator 12 in the operating state can be reduced as compared with the case where the normal operation mode and the intermittent operation mode are used together. Further, control for switching between the normal operation mode and the intermittent operation mode becomes unnecessary.

  Further, in the above embodiment, the case where the second switch SW2 is inserted between the connection point 24A and the other end of the capacitor C2 is illustrated, but the present invention is not limited to this, and the semiconductor device 10 is not limited thereto. Instead, the semiconductor device 50 shown in FIG. 4 may be employed as an example.

  As an example, as illustrated in FIG. 4, the semiconductor device 50 is different from the semiconductor device 10 illustrated in FIG. 1 in that a regulator 52 is provided instead of the regulator 12. The regulator 52 is different from the regulator 12 in that the second switch SW2 between the connection point 24A and the capacitor C2 is removed, and the connection point 24A and the other end of the capacitor C2 are directly connected. Further, the regulator 52 is different from the regulator 12 in that it includes a second switch SW2A. One end of the second switch SW2A is connected to the other end of the resistor R2, and the other end of the second switch SW2A is connected to the output terminal 12A. Even with the semiconductor device 50 configured as described above, the same effects as those of the semiconductor device 10 described in the above embodiment can be obtained.

  In the above-described embodiment, the case where the switch SW is switched between the on state and the off state based on the first predetermined time and the second predetermined time is exemplified. However, the present invention is not limited to this, and the semiconductor device Instead of 10, as an example, the semiconductor device 60 shown in FIG.

As an example, as illustrated in FIG. 5, the semiconductor device 60 is different from the semiconductor device 10 illustrated in FIG. 1 in that a detection unit 62 is inserted between the output terminal 12 </ b> A and one end of the capacitor C <b> 1. The detection unit 62 detects whether or not the output voltage V _out has reached the first threshold value, and detects whether or not the output voltage V _out has reached a second threshold value that is greater than the first threshold value.

Here, although a circuit including a comparator is employed as an example of the detection unit 62, the present invention is not limited to this, and it is detected whether the output voltage _Vout has reached the first threshold value, and the output voltage _{Vout Any} circuit that detects whether or not _out has reached the second threshold value may be used. Here, the lower limit value of the voltage range that can compensate the operation of the load 18 (for example, a voltage corresponding to the allowable lower limit voltage) is adopted as the first threshold value. Here, as the second threshold value, a value larger than the first threshold value (for example, a voltage corresponding to the voltage in the normal operation mode) is adopted in a voltage range in which the operation of the load 18 can be compensated.

The detection unit 62 is connected to the control unit 14 and outputs the detection result of the detection unit 62 to the control unit 14. The control unit 14 switches the switch SW between an on state and an off state according to the input detection result. For example, when the switch SW is in an off state and the detection unit 62 detects that the output voltage V _out has reached the first threshold value, the control unit 14 switches the switch SW from the off state to the on state. The control unit 14 switches the switch SW from the on state to the off state when the switch SW is on and the detection unit 62 detects that the output voltage _Vout has reached the second threshold value.

Therefore, the semiconductor device 60 falls below the first threshold value compared to the case where the switch SW is not turned on when it is detected that the output voltage _Vout has reached the first threshold value after the switch SW is turned off. The output voltage _Vout can be maintained with high accuracy within the range.

In addition, the semiconductor device 60 has a simple configuration as compared with a case where the switch SW is not turned off when the output voltage _Vout is detected to have reached the second threshold after the switch SW is turned on. The output voltage _Vout can be held with high accuracy within a range not exceeding the second threshold.

Further, the semiconductor device 60 outputs the output voltage V _out within the voltage range in which the operation of the load 18 can be compensated, compared to the case where the first threshold value and the second threshold value are not set to values in the voltage range in which the operation of the load 18 can be compensated. Can be held with high accuracy.

  In the above embodiment, the switching operation of the first switch SW1 and the switching operation of the second switch SW2 are synchronized, but the present invention is not limited to this. For example, the switching operation of the second switch SW2 may be performed before the switching operation of the first switch SW1.

In the above-described embodiment, the case where the switch SW is switched so that the output voltage _Vout is held within a previously permitted voltage range is illustrated, but the present invention is not limited to this. For example, the switch SW does not have to be turned on even when the output voltage _Vout falls below the allowable lower limit voltage in the intermittent operation mode. In this case, for example, while the output voltage _Vout is below the allowable lower limit voltage, a complementary voltage is supplied to the load 18 from a regulator (for example, a main regulator) (not shown) other than the regulator 12. That's fine.

10, 50, 60 Semiconductor device 12A Output terminal 14 Control unit 18 Load 22 Operational amplifier 24 Detection circuit 24A Connection point 24B Grounding unit 25 Voltage divider 26 Signal supply terminal 62 Detection unit C1, C2 Capacitor R1, R2 Resistor SW1 First switch SW2 , SW2A Second switch

Claims (13)

A capacitive element having one end connected to an output terminal of an operational amplifier having a non-inverting input terminal to which a reference voltage is input, and the other end connected to an inverting input terminal of the operational amplifier;
Connection state and non-connection state of a voltage divider that divides the additional voltage input from a supply terminal that supplies an additional voltage obtained by adding the voltage of the capacitive element to the output voltage of the output terminal to a load and a low voltage source A first switching unit capable of switching between,
An input state in which a feedback voltage obtained by dividing the additional voltage by the voltage divider is input to the other end of the capacitive element, and a non-input state in which the feedback voltage is not input to the other end of the capacitive element. A second switching unit capable of switching between,
The control signal for controlling the first switching unit and the second switching unit is switched so that the connection state and the non-connection state are repeatedly switched, and the input state and the non-input state are repeatedly switched. Supply section to supply the second switching section,
A semiconductor device including:   The switching between the connected state and the non-connected state by the first switching unit and the switching between the input state and the non-input state by the second switching unit are held within a voltage range in which the additional voltage is allowed in advance. The semiconductor device according to claim 1, which is performed as described above.   The semiconductor device according to claim 2, wherein the voltage range is a voltage range in which the operation of the load can be compensated.   4. The semiconductor device according to claim 1, wherein the connection state and the non-connection state are periodically switched, and the input state and the non-input state are periodically switched.   The control signal is switched from the connected state to the disconnected state, and when the predetermined first time has elapsed since the input state was switched to the non-input state, the disconnected state 5. The device according to claim 1, wherein the first switching unit and the second switching unit are supplied so as to be switched from the non-input state to the input state. A semiconductor device according to 1.   The control signal is switched from the non-connected state to the connected state, and when the second time shorter than the first time has elapsed since the non-input state is switched to the input state, The semiconductor device according to claim 5, wherein the semiconductor device is supplied to the first switching unit and the second switching unit so as to be switched from the connected state to the non-connected state and from the input state to the non-input state. A detector for detecting whether the additional voltage has reached a first threshold;
The control signal is switched from the non-connected state to the connected state and from the non-input state to the input state when it is detected that the additional voltage has reached the first threshold value. The semiconductor device according to claim 1, wherein the semiconductor device is supplied to the first switching unit and the second switching unit. The detection unit further detects whether the additional voltage has reached a second threshold value greater than the first threshold value,
The control signal is switched from the connected state to the disconnected state and from the input state to the non-input state when it is detected that the additional voltage has reached the second threshold value. The semiconductor device according to claim 7, wherein the semiconductor device is supplied to the first switching unit and the second switching unit.   9. The operational amplifier according to claim 1, wherein the operational amplifier operates as a voltage follower when the connection state is switched to the non-connection state and when the input state is switched to the non-input state. A semiconductor device according to 1.   The semiconductor device according to claim 1, wherein the capacitive element is a phase compensation capacitor of the operational amplifier.   The control signal includes the first switching so that the switching operation of the connected state and the non-connected state by the first switching unit and the switching operation of the input state and the non-input state by the second switching unit are synchronized. The semiconductor device according to claim 1, wherein the semiconductor device is supplied to a first switching unit and the second switching unit.   The semiconductor device according to claim 1, further comprising a control unit that supplies the control signal to the supply unit. A capacitive element having one end connected to the output terminal of an operational amplifier having a non-inverting input terminal to which a reference voltage is input, and the other end connected to the inverting input terminal of the operational amplifier, and the output voltage of the output terminal to the output voltage A first switching unit capable of switching between a connection state and a non-connection state between a voltage divider for dividing the additional voltage input from a supply terminal for supplying an additional voltage to which a voltage of the capacitive element is added to a load and a low voltage source And an input state in which the feedback voltage obtained by dividing the additional voltage by the voltage divider is input to the other end of the capacitive element and a non-input in which the feedback voltage is not input to the other end of the capacitive element A second switching unit capable of switching between states, wherein the connection state and the non-connection state in the semiconductor device are repeatedly switched, and the input state and the non-input state are repeatedly switched. A control signal for controlling the switching unit and the second switching unit to supply to the first switching unit and the second switching unit,
A current source control method.

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