WO2017137092A1 - Sous-module de convertisseur en chaîne - Google Patents

Sous-module de convertisseur en chaîne Download PDF

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Publication number
WO2017137092A1
WO2017137092A1 PCT/EP2016/053026 EP2016053026W WO2017137092A1 WO 2017137092 A1 WO2017137092 A1 WO 2017137092A1 EP 2016053026 W EP2016053026 W EP 2016053026W WO 2017137092 A1 WO2017137092 A1 WO 2017137092A1
Authority
WO
WIPO (PCT)
Prior art keywords
submodule
semiconductor structure
reverse
bridge
blocking
Prior art date
Application number
PCT/EP2016/053026
Other languages
English (en)
Inventor
Christopher Townsend
Alireza NAMI
Munaf Rahimo
Hector Zelaya De La Parra
Francisco Canales
Roberto ALVES
Torsten Nilsson
Original Assignee
Abb Schweiz Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Abb Schweiz Ag filed Critical Abb Schweiz Ag
Priority to PCT/EP2016/053026 priority Critical patent/WO2017137092A1/fr
Priority to GB1812425.5A priority patent/GB2562420B/en
Priority to DE112016006420.9T priority patent/DE112016006420T5/de
Priority to CN201680081637.5A priority patent/CN108604877B/zh
Publication of WO2017137092A1 publication Critical patent/WO2017137092A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
    • H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
    • H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters
    • H02P27/08—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation
    • H02P27/14—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation with three or more levels of voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/4835—Converters with outputs that each can have more than two voltages levels comprising two or more cells, each including a switchable capacitor, the capacitors having a nominal charge voltage which corresponds to a given fraction of the input voltage, and the capacitors being selectively connected in series to determine the instantaneous output voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/49—Combination of the output voltage waveforms of a plurality of converters

Definitions

  • the present disclosure relates to a submodule for a chain link converter leg for an electrical converter.
  • Multilevel converters are found in many high power applications in which medium to high voltage levels are present in the system. By virtue of their design, multilevel converters share the system voltage, eliminating the need of series connection of devices.
  • modular converters have become popular, where a number of cells, each containing a number of semiconductor switching elements and an energy storage element in the form of a Direct Current (DC) capacitor, are connected in series to form a variable voltage source. These converters can be used for Drive, High-Voltage Direct Current (HVDC) and Flexible Alternating Current, AC, Transmission Systems (FACTS) applications.
  • HVDC High-Voltage Direct Current
  • FACTS Flexible Alternating Current
  • Figure 1 depicts a typical three-phase chain-link converter in delta configuration, each phase leg constructed with series connections of full-bridge (also called H-bridge) cells (so called cascaded or chain-link connected cells).
  • Figure 2 depicts a three-phase modular multi-level converter where each phase leg comprises an upper and a lower arm, each arm constructed with a series connections of half-bridges.
  • Total semiconductor loss is made up of both switching and conduction loss.
  • the conduction loss is the dominant loss component.
  • Conduction loss typically reduces as the number of semiconductor devices in the current path is reduced.
  • the voltage and current waveforms associated with each phase-leg are 90 0 out of phase. This implies that when the current waveform is close to its peak, the majority of H-bridge cells are bypassed. If the number of devices in the current path during this time can be reduced then the total conduction loss, and hence total loss, will substantially decrease.
  • EP 2 413 489 discloses a DC to AC converter circuit, in particular a half- bridge inverter for converting a DC to an AC voltage.
  • the half-bridge inverter for converting a DC input voltage to provide an AC output voltage at an output terminal comprising a first switching circuit connected to at least one input terminal and to the output terminal and configured to provide a high or a low voltage level at the output terminal.
  • a second switching circuit is connected to the output terminal and configured to provide a connection to an intermediate voltage level, the intermediate voltage level being between the high and the low voltage level.
  • the second switching circuit is further connected to the at least one input terminal allowing the second switching circuit to provide the high or the low voltage level at the output terminal.
  • EP 2 413 489 uses two different semiconductor switches, Insulated-Gate Bipolar Transistor (IGBT) and Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) connected in parallel so that the IGBT conducts steady state current while the MOSFET performs the switching transitions in order to lower overall losses.
  • IGBT Insulated-Gate Bipolar Transistor
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • the submodule for a chain link converter leg.
  • the submodule comprises a first semiconductor structure forming a first current path through the submodule, and a second semiconductor structure, connected in parallel to the first semiconductor structure, forming a second current path through the submodule.
  • At least the first semiconductor structure comprises a DC capacitor
  • at least the second semiconductor structure comprises a reverse-blocking arrangement.
  • the submodule is configured for, when in a bypass mode, allow current to pass through the reverse-blocking
  • phase leg for a converter comprising a plurality of chain linked submodules of the present disclosure.
  • Fig l is a schematic illustration of a full-bridge delta connected converter according to prior art.
  • Fig 2 is a schematic illustration of a half-bridge modular multi-level converter according to prior art.
  • Fig 3 is a schematic circuit diagram of a converter phase leg of embodiments of the present invention.
  • Fig 4 is a schematic circuit diagram of an embodiment of a submodule of the present invention.
  • Fig 5 is a schematic circuit diagram of another embodiment of a submodule of the present invention.
  • Fig 6 is a schematic circuit diagram of another embodiment of a submodule of the present invention.
  • Fig 7 is a schematic circuit diagram of another embodiment of a submodule of the present invention.
  • any other three-quadrant device may be used.
  • any other four quadrant device may be used. It may also be mentioned that these devices may be wideband devices whereby the switching losses may be reduced.
  • the proposed invention reduces conduction loss using a new submodule structure within a chain link converter. The proposed submodule and resulting phase leg are shown in figures 4 and 3, respectively.
  • Figure 3 illustrates part of a phase leg 2 of a converter 1.
  • the phase leg 2 comprises a plurality of series connected (chain link), typically identical, submodules 3, which submodules are discussed in more detail with reference to figure 4.
  • Figure 4 illustrates an embodiment of a submodule 3 of the present invention.
  • the submodule 3 comprises a first semiconductor structure 4a and a second semiconductor structure 4b.
  • the first and second semiconductor structures 4 are connected in parallel to each other in the submodule 3.
  • the first semiconductor structure 4a comprises a DC capacitor 5 as an energy storage unit
  • the second semiconductor structure 4b comprises a reverse-blocking arrangement 8.
  • the reverse-blocking arrangement is formed by two antiparallel Reverse Blocking IGBTs (RBIGBT), i.e. the two RBIGBTs are connected in parallel but arranged for allowing current in opposite directions in the reverse-blocking arrangement 8.
  • RBIGBT antiparallel Reverse Blocking IGBTs
  • each of the antiparallel RBIGBTs may be exchanged for a MOSFET with a series connected diode.
  • the first semiconductor structure 4a comprises a half-bridge cell with a DC capacitor 5 in parallel with a leg of an upper semiconductor switch and a first lower semiconductor switch.
  • the second semiconductor structure 4b comprises a half-bridge cell with a DC capacitor 5 in parallel with a leg of an upper semiconductor switch and a second lower semiconductor switch.
  • the half-bridge of the first semiconductor structure 4a is antiparallel to the half-bridge of the second semiconductor structure 4b (i.e. they form two opposite polarity half-bridges connected in parallel).
  • the first semiconductor structure 4a forms a first current path through the submodule and is used to synthesize positive voltage
  • the second semiconductor structure 4b forms a second current path through the submodule and is used to synthesize negative voltage.
  • semiconductor switches e.g. RBIGBTs in each half-bridge is turned on to conduct half the current passed the submodule.
  • the first semiconductor structure 4a comprises a half-bridge cell with a DC capacitor 5 in parallel with a leg of an upper semiconductor switch and said second lower semiconductor switch. Consequently, the same lower semiconductor switch is shared between both the first 4a and second 4b semiconductor structures (not shown in figure 4).
  • the upper semiconductor switch in each half bridge is according to this topology capable of blocking 2.0 Udc.
  • Each of the two reverse-blocking arrangements 8 is capable of blocking 1.0 Udc in both directions, hence the inclusion of the RBIGBTs.
  • +ve current - current flows through one IGBT 6 rated at 2.0 Udc bypass
  • +ve current - half the current flows through one RBIGBT (of the first semiconductor structure 4a) rated at 1.0 Udc
  • the other half of the current flows through another RBIGBT (of the second semiconductor structure 4b) rated at 1.0 Udc.
  • bypass -ve current - half the current flows through one RBIGBT (of the first semiconductor structure 4a) rated at 1.0 Udc
  • the other half of the current flows through another RBIGBT (of the second semiconductor structure 4b) rated at 1.0 Udc.
  • both lower switches (the reverse-blocking arrangement 8 in each half bridge) is turned on to share current between the two parallel connected reverse- blocking arrangements. This reduces the silicon area required for these switches since their peak current is up to 50% lower than the phase-leg current.
  • each RBIGBT in the lower switch position of each half bridge could alternatively be implemented with a series connection of
  • the reverse blocking arrangement comprises two antiparallel RBIGBTs.
  • the reverse blocking arrangement comprises two antiparallel sets of a MOSFET in series with a diode.
  • the first semiconductor structure 4a comprises a first half-bridge cell and the second semiconductor structure 4b comprises a second half-bridge cell which is antiparallel to the first half-bridge cell.
  • each of the first and second half-bridge cells comprises a DC capacitor 5 and a reverse- blocking arrangement 8.
  • the submodule 3 is configured for, when in the bypass mode, allow current to pass through both the reverse-blocking arrangements 8 of the first and second half-bridge cells.
  • only the second half-bridge cell 4b comprises a reverse-blocking arrangement 8. The reverse-blocking arrangement 8 is then shared between the first and second half-bridge cells.
  • Figures 5-7 discloses embodiments of the inventive submodule with full- bridge cells 9, which are alternative embodiments to the embodiment of figure 4, while the inventive concept is the same with a reverse-blocking arrangement 8 in the second semiconductor structure 4b.
  • An advantage with a full-bridge topology is that it is possible to design the commutation process such that the RBIGBTs do not incur switching loss, meaning their design can be optimized for conduction loss only.
  • Figure 5 shows an embodiment where the RBIGBTs are external to and connected in series with a full-bridge cell 9 in the second semiconductor structure 4b.
  • the first semiconductor structure 4a comprises two full-bridge cells 9 in series, where each full-bridge cell comprises a DC capacitor 5 and two parallel legs, each with an upper and a lower semiconductor switch
  • each of the four switches e.g. IGBT 6 with antiparallel diode 7
  • each of the four switches may be exchanged for antiparallel RBIGBTs in the full-bridge 9.
  • this may not provide significant conduction loss reduction since the RBIGBTs must then each be rated to block 1.5 Udc.
  • the full-bridge in the second semiconductor structure 4b may be removed, leaving only the reverse-blocking arrangement, here in the form of two sets of antiparallel RBIGBT pairs in series.
  • the reverse-blocking arrangement 8 may be preferred since it is proportional to the reverse blocking voltage and the total main loop voltage. It is the same number as the number of cells if the reverse blocking voltage of the RBIGBTs is the same as the blocking voltage of the IGBTS.
  • the first semiconductor structure 4a comprises at least one full-bridge cell.
  • the first semiconductor structure 4a comprises two series connected full- bridge cells (as in the embodiments of figures 5-7). Additionally or
  • the second semiconductor structure 4b comprises a full-bridge cell (as in the embodiments of figures 5 or 6).
  • the reverse-blocking arrangement 8 is connected in series with the full-bridge cell in the second semiconductor structure 4b (as in the embodiment of figure 5).
  • the full-bridge cell comprises four reverse-blocking arrangements 8 (as in the embodiment of figure 6).
  • semiconductor structure 4b comprises two series connected reverse-blocking arrangements 8 (as in the embodiment of figure 7).
  • the embodiment of figure 7 also represents that in some embodiments, the second
  • semiconductor structure 4b does not comprise neither a half-bridge nor a full-bridge cell, but only one, or a plurality of series connected, reverse- blocking arrangement(s) 8.
  • Example - Commutation process The submodule embodiment of figure 4 does not require a specially designed commutation process to transition between switching states inside the submodule. This is due to the anti-parallel diode in the upper switch of each half-bridge which ensures a path for current to flow even when all IGBTs 6 and RBIGBTs are blocked. This means that a simple dead-time mechanism may be used during transitions. However, this is not the case for the full- bridge embodiments of figures 5-7, the commutation process of which will now be discussed with reference to figure 7.
  • the commutation process comprises the following steps:
  • RBIGBTs can be bypassed, i.e. turned on or opened. This causes the current to commutate between paths from the first current path of the first semiconductor structure 4a to the second current path (via the RBIGBTs) of the second semiconductor structure 4b.
  • the process for current commutation in the opposite direction comprises the following steps: 1) The process again begins at the completion of the previous control cycle as in step 3) above.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)
  • Dc-Dc Converters (AREA)
  • Power Conversion In General (AREA)

Abstract

La présente invention concerne un sous-module (3) pour une branche de convertisseur en chaîne (2). Le sous-module comprend une première structure à semi-conducteurs (4a) formant un premier chemin de courant à travers le sous-module, et une seconde structure à semi-conducteurs (4b), connectée en parallèle avec la première structure à semi-conducteurs (4a), formant un second chemin de courant à travers le sous-module. Au moins la première structure à semi-conducteurs (4a) comprend un condensateur à courant continu (CC) (5), et au moins la seconde structure à semi-conducteurs (4b) comprend un montage de blocage de courant inverse (8). Le sous-module est configuré pour, quand il est dans un mode de dérivation, permettre à un courant de passer par le montage de blocage de courant inverse.
PCT/EP2016/053026 2016-02-12 2016-02-12 Sous-module de convertisseur en chaîne WO2017137092A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/EP2016/053026 WO2017137092A1 (fr) 2016-02-12 2016-02-12 Sous-module de convertisseur en chaîne
GB1812425.5A GB2562420B (en) 2016-02-12 2016-02-12 Submodule of a chain link converter
DE112016006420.9T DE112016006420T5 (de) 2016-02-12 2016-02-12 Submodul eines kaskadierten stromrichters
CN201680081637.5A CN108604877B (zh) 2016-02-12 2016-02-12 链式链路转换器的子模块

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2016/053026 WO2017137092A1 (fr) 2016-02-12 2016-02-12 Sous-module de convertisseur en chaîne

Publications (1)

Publication Number Publication Date
WO2017137092A1 true WO2017137092A1 (fr) 2017-08-17

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2016/053026 WO2017137092A1 (fr) 2016-02-12 2016-02-12 Sous-module de convertisseur en chaîne

Country Status (4)

Country Link
CN (1) CN108604877B (fr)
DE (1) DE112016006420T5 (fr)
GB (1) GB2562420B (fr)
WO (1) WO2017137092A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019149367A1 (fr) * 2018-02-02 2019-08-08 Siemens Aktiengesellschaft Convertisseur redresseur modulaire à plusieurs étages et module de commutation pour convertisseur redresseur modulaire à plusieurs étages
US11296686B2 (en) * 2019-06-04 2022-04-05 Audi Ag Method for operating an electrical circuit, electrical circuit, and motor vehicle

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006296098A (ja) * 2005-04-12 2006-10-26 Fuji Electric Systems Co Ltd 交流−交流変換装置
US20110170322A1 (en) * 2008-10-16 2011-07-14 Toshiba Mitsubishi-Electric Industrial System Corp Power conversion device
EP2413489A1 (fr) 2010-07-30 2012-02-01 Vinotech Holdings S.à.r.l. Convertisseur courant continu courant alternatif à demi-pont hautement efficace
US20130014384A1 (en) * 2010-02-15 2013-01-17 Siemins Corporation Single Phase Multilevel Inverter
EP2822164A2 (fr) * 2013-07-02 2015-01-07 LSIS Co., Ltd. Onduleur à moyenne tension et multiniveau

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5803683B2 (ja) * 2012-01-13 2015-11-04 富士電機株式会社 マルチレベル電力変換回路
CN104868748B (zh) * 2014-02-20 2017-12-22 南京南瑞继保电气有限公司 一种换流器模块单元、换流器、直流输电系统及控制方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006296098A (ja) * 2005-04-12 2006-10-26 Fuji Electric Systems Co Ltd 交流−交流変換装置
US20110170322A1 (en) * 2008-10-16 2011-07-14 Toshiba Mitsubishi-Electric Industrial System Corp Power conversion device
US20130014384A1 (en) * 2010-02-15 2013-01-17 Siemins Corporation Single Phase Multilevel Inverter
EP2413489A1 (fr) 2010-07-30 2012-02-01 Vinotech Holdings S.à.r.l. Convertisseur courant continu courant alternatif à demi-pont hautement efficace
EP2822164A2 (fr) * 2013-07-02 2015-01-07 LSIS Co., Ltd. Onduleur à moyenne tension et multiniveau

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019149367A1 (fr) * 2018-02-02 2019-08-08 Siemens Aktiengesellschaft Convertisseur redresseur modulaire à plusieurs étages et module de commutation pour convertisseur redresseur modulaire à plusieurs étages
US11296686B2 (en) * 2019-06-04 2022-04-05 Audi Ag Method for operating an electrical circuit, electrical circuit, and motor vehicle

Also Published As

Publication number Publication date
GB201812425D0 (en) 2018-09-12
GB2562420A (en) 2018-11-14
CN108604877A (zh) 2018-09-28
GB2562420B (en) 2021-07-28
DE112016006420T5 (de) 2018-11-15
CN108604877B (zh) 2021-07-13

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