WO2017133580A1 - Procédé et dispositif de traitement de codage de paquet de données, station de base et équipement utilisateur - Google Patents

Procédé et dispositif de traitement de codage de paquet de données, station de base et équipement utilisateur Download PDF

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WO2017133580A1
WO2017133580A1 PCT/CN2017/072427 CN2017072427W WO2017133580A1 WO 2017133580 A1 WO2017133580 A1 WO 2017133580A1 CN 2017072427 W CN2017072427 W CN 2017072427W WO 2017133580 A1 WO2017133580 A1 WO 2017133580A1
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packet
information
bits
bit
bit sequence
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PCT/CN2017/072427
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Chinese (zh)
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李立广
徐俊
许进
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中兴通讯股份有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0002—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission rate
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H04L1/0063—Single parity check

Definitions

  • the present application relates to, but is not limited to, the field of communications, and in particular, to a packet encoding processing method and apparatus, a base station, and a user equipment.
  • the transmission terminal and the receiving end are mostly two, wherein the general transmitting end includes an information source module, a channel coding module, a modulation module, and a transmitting module, and the receiving end includes a receiving signal module and a demodulation module. , channel decoding module and acquiring source data module.
  • channel coding is a key module, mainly to improve the reliability of data transmission, and to correct the errors in the transmission process by increasing the redundant information of the channel coding codeword, so as to resist the fading in the channel. And the impact of various noises on the transmitted data.
  • the more commonly used channel coding techniques include Turbo coding, Low Density Parity Check Code (LDPC) coding, convolutional coding, and RS (Reed-solomon) coding.
  • LDPC Low Density Parity Check Code
  • RS Random-solomon
  • LDPC is a low-density parity check coding, and its check matrix is very sparse, so the decoding complexity is not high, and at the same time, it has natural decoding parallelism, and can achieve higher decoding throughput by parallel decoding, and The performance is very close to the Shannon limit.
  • LDPC coding has been used in many communication systems; Turbo coding encodes information by two component codes, and iterative decoding by two-part component code can improve decoding performance.
  • the performance of the bit rate is very good, and the bit rate and code length can be flexibly set, which is very suitable for various communication data.
  • the Turbo coding mode is mainly adopted;
  • the current coded output of the convolutional code is not only related to the current information but also related to some previous information. Similar to the convolutional feature, the decoding effect is better, and it is also used in many systems;
  • RS coding is the shortest code distance.
  • the code can be decoded, and the decoding can be performed by pipeline decoding, and the decoding speed is high and the throughput is high.
  • the data packet or the codeword information block needs to be verified, that is, some check sequence is added, so that The receiving end uses the check sequence to determine whether the received data packet or the encoded codeword information block is correct or not.
  • a commonly used calibration method is the Cyclic Redundancy Check (Cyclic Redundancy Check, Referred to as CRC) sequence.
  • the Turbo coding scheme uses Parallel Concatenated Convolutional Code (PCCC), which uses two 8-state sub-encoders and one Turbo intra-code interleaver.
  • PCCC Parallel Concatenated Convolutional Code
  • the initial value of the shift register in the 8-state sub-encoder is 0, wherein the coding structure is as shown in FIG. Show.
  • the bits input to the Turbo encoder are denoted as c 0 , c 1 , c 2 , c 3 , ..., c K-1
  • the output bits of the first and second 8-state sub-encoders are z 0 , z 1 , respectively.
  • the output bits from the Turbo intra-code interleaver are denoted as c' 0 , c' 1 , ..., c' K-1 , which will be input to the second 8-state sub-encoder.
  • the forced-zero processing of Turbo coding is accomplished by obtaining the tail bits from the shift register feedback after all information bit encoding, and the tail bits are added after the information bit encoding.
  • the first three tail codes are used to terminate the first encoder, at which point the second sub-encoder is disabled.
  • the last three tail bits are used to terminate the second sub-encoder, at which point the first sub-encoder is disabled.
  • the transmission bits used for the grid termination scheme are:
  • the bits input into the Turbo code interleaver are denoted as c 0 , c 1 , ..., c K-1 , where K is the number of input bits.
  • the output of the Turbo code interleaver is denoted as c' 0 , c' 1 , ..., c' K-1 .
  • the rate matching of the codeword bit sequence output by Turbo coding is as shown in FIG. 11.
  • the rate matching process of the turbo coded transmission channel is as follows: first, three information bit streams are used. and Interleaving is performed separately, followed by bit collection, followed by generation of a circular buffer, and finally bit selection to obtain a transmitted bit sequence e k .
  • bit stream Interleaving according to a specific sub-block interleaver, the corresponding output sequences are respectively defined as
  • the output bit sequence generation process of the sub-block interleaver is:
  • the output of the sub-block interleaver is after the column transformation The bit sequence read out column by column in the dimension matrix.
  • the output bit of the sub-block interleaver is expressed as among them, Corresponding to y P(0) Corresponding to And for Press 6 to proceed.
  • bit selection the number of lines interleaved according to the transmission version number rv idx and sub-blocks
  • the bit length N cb of the Turbo coded block soft buffer determines the start bit of the bit selection: The selection starts from the k0th bit, and the padding bits are ignored. among them, Indicates rounding up.
  • the full name of the LDPC code is Low Density Parity Check Code (LDPC), which is a kind of linear block code with sparse check matrix proposed by Dr. Robert G. Gallage in 1963, which not only has approximation. Shannon has good performance, low decoding complexity and flexible structure. It has been widely used in deep space communication, optical fiber communication, satellite digital video and audio broadcasting.
  • the structured LDPC code is defined by a parity check matrix H of size (mb x z) x (nb x z), wherein the parity check matrix H is a base matrix Hb of size mb x nb, a spreading factor z and
  • the basic permutation matrix P is determined by three variables.
  • the hb ij power matrix of all elements in the base matrix Hb is replaced by a full 0 square matrix or a basic permutation matrix P to obtain an expanded parity check matrix H, where hb ij is an element in Hb.
  • the basic matrix Hb is defined as follows.
  • the expanded parity check matrix H is defined as follows.
  • the corresponding check matrices are H 2 and H q , respectively .
  • the element in H 2 is 0 or 1
  • H q is composed of elements 0, 1, ..., q-1
  • the decoding algorithm of the LDPC code includes the following three categories: hard decision decoding, soft decision decoding, and hybrid decoding.
  • the hard decision decoding first performs a hard decision on the received real sequence, and finally sends the obtained hard decision sequence to the hard decision decoder for decoding.
  • Soft decision decoding can make full use of the received channel information (soft information), channel information utilization is greatly improved, and excellent error performance can be obtained.
  • Hybrid decoding combines the features of soft decision decoding and hard decision decoding.
  • the Polar Code has a definite construction method and is the first and only known channel coding method that can be rigorously proven to "reach" the channel capacity.
  • N 2 n independent binary input channels W, where n is a natural number, a so-called channel combining operation and a channel division operation are performed, thereby obtaining N pre-dependent polarization channels.
  • these polarized channels exhibit polarization when the capacity and the capacity remain unchanged: the capacity of one part of the channel increases, and the capacity of the other part decreases.
  • the number of channels used to transmit the free bits is denoted by K, thereby forming a one-to-one mapping relationship from K information bits to N transmission bits, which is polarization coding.
  • K The number of channels used to transmit the free bits
  • N N transmission bits
  • SC serial cancellation
  • the basic principle of the cyclic redundancy check code is to add an L-bit check code after the k-bit information bit sequence, and the length becomes n bits.
  • This code is also called (n, k) code.
  • a check code for K-bit information can be generated from G(x), and G(x) is called a generator polynomial of this CRC code.
  • the generation process of the check code is as follows: the information bit sequence to be transmitted is represented by a polynomial M(X), and M(x) is shifted left by L bits (which can be expressed as M(x) ⁇ 2L), such that M(x) The L bit will be vacated on the right side, which is the position of the check code.
  • the remainder obtained by dividing M(x) ⁇ 2L by the generator polynomial G(x) is the check code.
  • the fundamental difference between the convolutional code and the block code is that it does not separately encode the information sequence and then separately encodes it, but obtains the continuously outputted encoded bit sequence from successively input information bit sequences. . That is, when performing block coding, the nk check elements in the group are only related to the k information elements of the group, but are independent of other groups of information; but in the convolutional code, the encoder will have k information codes. When the element is coded as n symbols, the n symbols are not only related to the k pieces of information of the current segment, but also related to the previous (m-1) segment information (m is the constraint length of the encoding).
  • the more the number of bits of the coding block the better the performance and the higher the transmission reliability, but the higher the requirements on the decoding hardware, the more the hardware complexity increases. Moreover, a larger cache is required, the cost is higher, and more decoding delays and reception delays are required. For wireless communication devices, handheld devices, mobile devices, etc., it is required to reduce complexity, high throughput, etc., generally using a shorter channel coding code length, thus sacrificing performance.
  • the embodiment of the invention provides a data packet coding processing method and device, a base station and a user equipment, so as to reduce coding complexity and ensure better performance.
  • the embodiment of the invention provides a data packet coding processing method, including:
  • the generating, by using the packet encoding, the A-coded information packet to generate the B-check packet may include:
  • the foregoing packet encoding processing method may further include: bit filling, wherein the bit filling may include one or more of the following manners:
  • adding CRC After adding a CRC bit sequence of length L to the C pieces of sub-information bit sequences, and performing channel coding on the sub-information bit sequences after adding the CRC to the C shares, adding CRC
  • K is a positive integer multiple of k
  • k is the number of bits of the channel coding input
  • H is the maximum of the number of bits of all coded packets.
  • the A-coded information packet and the B-part verification packet are divided into The output codeword bit sequence in the bit selection step does not include padding bits.
  • the number of bits of each rate matched codeword bit sequence is determined by any of the following parameter sets:
  • Parameter set one preset code rate, number of information bits of the coded information packet, number of codeword bit sequences of the coded information packet, number of coded information packets, and number of information bits of the B check packets;
  • Parameter set two preset code rate, number of bits of the input information bit sequence, number of codeword bit sequences of the encoded information packet, number of coded information packets, and number of information bits of the B check packets;
  • Parameter set three preset code rate, number of information bits of the codeword bit sequence, number of codeword bit sequences, and number of information bits of the B check packets;
  • Parameter set four the total number of transmission bits, the number of codeword bit sequences, and the number of information bits of the B check packets;
  • Parameter set five modulation order, number of preset resources, number of codeword bit sequences, and number of information bits of B check packets.
  • the data packet coding processing method may further include: interleaving the output codeword bit sequence .
  • the interleaving the output codeword bit sequence may include:
  • the interleaving method of all rate-matched codeword bit sequences belonging to the i-th encoded packet is different from the interleaving method belonging to the j-th encoded packet, where i is not equal to j, i and j are both 0 to (C- 1) an integer.
  • the data packet encoding processing method may further include: selecting C for the bit The rate-matched coded codeword bit sequences are respectively interleaved, wherein the interleaving methods of the different coded codeword bit sequences are different.
  • the foregoing packet encoding processing method may further include:
  • the performing cyclic bit selection on the A pieces of encoded information packets may include:
  • the A-coded packets are sequentially selected from a given start bit index position, and are selected from the first bit if the tail bit is selected.
  • the retransmitting the version number mode may include determining, by at least the retransmission version number, a starting bit index position of the retransmission bit sequence in the original coding bit sequence.
  • the sequential manner may include:
  • the retransmission coded bit sequence has a value of the start bit index position of the original coded bit sequence equal to the index position value of the tail bit of the previous transmission data plus one.
  • the B-rate matched retransmission check bit sequence is derived only from the information bits in the A-part encoded information packet.
  • the channel coding adopts any of the following coding modes: Turbo coding, low density parity check code coding, convolutional coding, inner (RS) coding, and polarization coding.
  • the embodiment of the invention provides a packet encoding and processing device, which is applied to a transmitting end, and includes:
  • a segmentation module configured to divide the input information bit sequence into C sub-information bit sequences, where C is an integer greater than or equal to 2;
  • Adding a module configured to add a CRC bit sequence of length L to the C sub-information bit sequence respectively, to obtain a sub-information bit sequence after C shares are added with a CRC, where L is an integer greater than or equal to 0;
  • a channel coding module configured to perform channel coding on the sub-information bit sequence after adding the CRC to the C shares, to obtain a C-coded codeword bit sequence
  • the dividing module is configured to divide the C coded codeword bit sequence into A coded block sets, and define each coded block set as a separately coded information packet; wherein A is a positive integer and A is smaller than Or equal to C;
  • a packet encoding module configured to generate, by using a packet encoding, the A-coded information packet to generate a B-check packet;
  • bit selection module configured to perform bit selection on the A-coded information packet and the B-check packet, respectively, to obtain a selected output codeword bit sequence, where the output codeword bit sequence includes the C And the rate-matched codeword bit sequence and the B-rate rate-matched check bit sequence are obtained only by the information bits in the A-part coded information packet.
  • the foregoing packet encoding processing apparatus may further include: a bit filling module; wherein the bit filling module is configured to perform bit filling by one or more of the following manners:
  • the input information bit sequence is filled with K-K0 bits, where K0 is the number of bits of the input information bit sequence;
  • K is a positive integer multiple of k
  • k is the number of bits of the channel coding input
  • H is the maximum of the number of bits of all coded packets.
  • the output codeword bit sequence of the bit selection module in the bit selection does not include padded bits.
  • the foregoing packet encoding processing apparatus may further include:
  • a determining module configured to determine a number of bits of the codeword bit sequence after each rate matching by any of the following parameter sets:
  • Parameter set one preset code rate, number of information bits of the coded information packet, number of codeword bit sequences of the coded information packet, number of coded information packets, and number of information bits of the B check packets;
  • Parameter set two preset code rate, number of bits of the input information bit sequence, number of codeword bit sequences of the encoded information packet, number of coded information packets, and number of information bits of the B check packets;
  • Parameter set three preset code rate, number of information bits of the codeword bit sequence, number of codeword bit sequences, and number of information bits of the B check packets;
  • Parameter set four the total number of transmission bits, the number of codeword bit sequences, and the number of information bits of the B check packets;
  • Parameter set five modulation order, number of preset resources, number of codeword bit sequences, and number of information bits of B check packets.
  • the foregoing packet encoding processing apparatus may further include:
  • the interleaving module is configured to interleave the output codeword bit sequence after the bit selection module performs bit selection.
  • the foregoing packet encoding processing apparatus may further include:
  • a retransmission processing module configured to process a retransmission codeword bit sequence corresponding to the output codeword bit sequence
  • the retransmission processing module is configured to process the retransmission codeword bit sequence corresponding to the output codeword bit sequence by: retransmitting the version number mode or the sequential mode, and performing the A coded information packet
  • the cyclic bit selection is performed to obtain a retransmission codeword bit sequence after C rate matching, and cyclic bit selection is performed on the B verification packets to obtain a B-rate matched retransmission parity bit sequence.
  • the foregoing packet encoding processing apparatus may further include:
  • a retransmission processing module configured to process a retransmission codeword bit sequence corresponding to the output codeword bit sequence, wherein the B-rate matched retransmission parity bit sequence is only based on the A-coded signal
  • the information bits in the packet are obtained.
  • An embodiment of the present invention further provides a base station, including: the foregoing packet encoding processing apparatus.
  • the embodiment of the invention further provides a user equipment, comprising: the packet encoding processing device described above.
  • the embodiment of the invention further provides a computer readable storage medium storing computer executable instructions, which are implemented by the processor to implement the above-described data packet encoding processing method.
  • the embodiments of the present invention provide a data packet coding method and apparatus, a base station, and a user equipment, which can solve the contradiction between performance and complexity, can reduce coding complexity and ensure better performance, and can also improve translation. Code speed and system throughput.
  • FIG. 1 is a flowchart of a packet encoding processing method according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a packet encoding processing apparatus according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a packet encoding processing apparatus including a bit stuffing module according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of a system for applying a packet encoding process according to Embodiment 1 of the present invention.
  • Figure 5 is a schematic diagram of packet coding according to Embodiment 1 of the present invention.
  • Embodiment 6 is a performance comparison diagram of Embodiment 1 of the present invention and an equivalent code length
  • Figure 7 is a comparison diagram of performance of the embodiment 1 and the long code length of the present invention.
  • Figure 9 is a schematic diagram of packet coding according to Embodiment 4 of the present invention.
  • FIG. 10 is a schematic diagram of a Turbo encoder structure with a code rate of 1/3 in a related art LTE system
  • 11 is a schematic diagram of rate matching of Turbo encoded output codeword bit sequences in a related art LTE system.
  • FIG. 1 is a flowchart of a packet encoding processing method according to an embodiment of the present invention, which is applied to a transmitting end, and includes the following steps:
  • Step S100 the dividing step, dividing the input information bit sequence into C sub-information bit sequences, where C is an integer greater than or equal to 2;
  • Step S101 adding a step of adding a CRC bit sequence of length L to the C pieces of sub-information bit sequences, respectively, to obtain a sub-information bit sequence after C shares are added with a CRC, where L is an integer greater than or equal to 0;
  • Step S102 a channel coding step, performing channel coding on the sub-information bit sequence after adding the CRC to the C shares, to obtain a C-coded codeword bit sequence;
  • Step S103 the dividing step, dividing the C-coded codeword bit sequence into A coded block sets, each code block set being defined as an encoded information packet; wherein A is a positive integer, and A is less than or equal to C;
  • Step S104 a packet encoding step of generating, by using packet coding, the A-coded information packet to generate a B-check packet;
  • Step S105 a bit selection step, performing bit selection on the A-coded information packet and the B-check packet, respectively, to obtain a selected output codeword bit sequence, where the output codeword bit sequence includes at least C And the rate-matched codeword bit sequence and the B-rate rate-matched check bit sequence are obtained only by the information bits in the A-part coded information packet.
  • the embodiment of the invention provides a data packet coding processing method, so as to at least solve the contradiction problem of the performance and complexity of the coding and decoding hardware in the related art, which can reduce coding complexity and delay, and can ensure better performance, and can also ensure better performance. Improve decoding speed and system throughput.
  • the packet encoding in step S104 may include:
  • the check code may be in any of the following coding modes:
  • the check code may also be a B-bit check code, where B is an integer greater than 1, and is not limited to the check coding mode described above.
  • the check code may also be shortened coding, punctured coding, or shortened coding and punctured coding of the coding mode described above, and a check set having a corresponding number of bits of B bits is obtained.
  • All channel coding blocks can be linked by packet coding, so that iterative decoding methods can be used in receiving decoding to improve decoding performance.
  • Cumulative XOR such as Where p0 is a check bit and a0...a(t-1) is a set of bits;
  • the BCH coding is a cyclic code with perfect algebraic theoretical calculation, which can correct multiple errors.
  • RS coding is a branch of BCH coding, which is multi-domain coding. It also needs a generator polynomial g(x).
  • the RM code is a block code, and a generator matrix G is required.
  • the check bit is taken out to obtain a check set;
  • the B-bit check code is as follows: the input bit set is s, binary exclusive-OR addition is performed on a subset of s Set0, to obtain a 0th check bit; a new set consisting of the bit set s and the 0th check bit A subset of Set1 is binary-OR-added to obtain a first parity bit; a binary difference is made to a subset of the new set of the set of bits s and the 0th check bit and the 1st check bit Or adding, obtaining the second check bit; and so on, performing a binary exclusive OR addition on a subset of the new set of s and the already calculated B-1 check bits, to obtain the first ( B-1) check bits.
  • multiple channel coding blocks can be linked, which is beneficial to improve the decoding gain.
  • the CRC sequence of length L is added. If L is equal to 0, it indicates that no addition is needed, otherwise it needs to be added.
  • the foregoing packet encoding processing method may further include: bit filling, wherein the bit filling may be one or more of the following manners:
  • the input information bit sequence is filled with K-K0 bits, where K0 is the number of bits of the input information bit sequence, where K is greater than or equal to K0, and if K is equal to K0, no padding is required;
  • the padding bits are intended to make the length of each information bit sequence equal to the channel coding requirement
  • the number of bits input is advantageous for channel coding and packet coding execution.
  • the padding of the input information bit sequence reaches K bits, the sub-information bit sequence is padded to k bits, and K satisfies a positive integer multiple of k, and k is channel coding.
  • the output codeword bit sequence does not include the padding bits described above.
  • H is the maximum of the number of bits of all encoded packets.
  • the number of bits of each rate matched codeword bit sequence is determined by any one of the following parameter sets:
  • Parameter set one preset code rate, number of information bits of the coded information packet, number of codeword bit sequences of the coded information packet, number of coded information packets, and number of information bits of the B check packets;
  • Parameter set two preset code rate, number of bits of the input information bit sequence, number of codeword bit sequences of the encoded information packet, number of coded information packets, and number of information bits of the B check packets;
  • Parameter set three preset code rate, number of information bits of the codeword bit sequence, number of codeword bit sequences, and number of information bits of the B check packets;
  • Parameter set four the total number of transmission bits, the number of codeword bit sequences, and the number of information bits of the B check packets;
  • Parameter set five modulation order, number of preset resources, number of codeword bit sequences, and number of information bits of B check packets.
  • the preset code rate is a ratio between a length of a system-set input information bit sequence and a length of a bit-selected output codeword bit sequence, the value being a real number greater than 0 and less than 1; information bits of the encoded information packet
  • the number is the number of all information bits in an encoded packet; the total number of transmitted bits is the total bit data of all transmissions, which is equal to the product of the modulation order and the number of preset resources, and the modulation order is the number of bits carried by a single constellation modulation symbol, such as BPSK (Binary Phase Shift Keying) modulation order is equal to 1, QPSK (Quadrature Phase Shift Keying) modulation order is equal to 2,8PSK (eight phase shift keying) modulation
  • the order number is equal to 3,16QAM (hexadecimal quadrature amplitude modulation) modulation order is equal to 4, 32QAM (32-ary quadrature amplitude modulation) modulation order is equal to 5,64QAM
  • the output codeword bit sequence may be interleaved such that channel fading and burst noise are resisted, improving system robustness.
  • the interleaving method may include:
  • the interleaving method of all rate-matched codeword bit sequences belonging to the i-th encoded packet is different from the interleaving method belonging to the j-th encoded packet, where i is not equal to j, i and j are both 0 to (C- The integer of 1), that is, the interleaving method of each encoded information packet is different, and when packet coding and decoding (decoding of the verification code), it can collect more information of other bits, thereby increasing the packet code translation. Code decoding performance and robustness.
  • bit sequences are interleaved differently so as not to affect the reception delay and decoding delay of each codeword bit sequence, while still obtaining corresponding performance benefits.
  • the processing step of the retransmission codeword bit sequence corresponding to the output codeword bit sequence may include:
  • cyclic bit selection is performed on the A coded information packets, and the retransmission codeword bit sequence after the C rate matching is obtained, and the B bit rate matching is performed on the B check packets to obtain the B rate matching.
  • the post-retransmission check bit sequence is performed on the A coded information packets, and the retransmission codeword bit sequence after the C rate matching is obtained, and the B bit rate matching is performed on the B check packets to obtain the B rate matching.
  • the cyclic bit selection may include: selecting from a given starting bit index position, and selecting from the first bit if the tail bit is selected.
  • the retransmitting the version number manner may include determining, by at least the retransmission version number, a starting bit index position of the retransmission bit sequence in the original coding bit sequence.
  • the sequential manner may include: retransmitting the encoded bit sequence with the starting bit index position value of the original encoded bit sequence being equal to the index position value of the tail bit of the previous transmitted data plus one.
  • the B-rate matched retransmission check bit sequence is obtained only from the information bits in the A-part encoded information packet, and the re-transmission codeword bit sequence is obtained using the bit selection method described above.
  • packet coding is also considered in retransmission, which can improve the throughput of the system and improve the robustness of the retransmission (HARQ) system.
  • the channel coding may adopt one of the following coding modes: Turbo coding, LDPC coding, convolutional coding, RS coding, and Polar coding.
  • FIG. 2 is a schematic diagram of a packet encoding processing apparatus according to an embodiment of the present invention, which is applied to a transmitting end, and includes the following modules:
  • the segmentation module 200 is configured to divide the input information bit sequence into C sub-information bit sequences, where C is an integer greater than or equal to 2;
  • the adding module 201 is configured to add a CRC bit sequence of length L to the C sub-information bit sequence respectively, to obtain a C information sub-information bit sequence after adding a CRC, where L is an integer greater than or equal to 0;
  • the channel coding module 202 is configured to perform channel coding on the sub-information bit sequence after adding the CRC to the C shares, to obtain a C-coded codeword bit sequence;
  • the dividing module 203 is configured to divide the C coded codeword bit sequence into A coded block sets, each code block set is defined as an encoded information packet; wherein A is a positive integer, and A is less than or equal to C;
  • the packet encoding module 204 is configured to generate a B check packet by using the A coded information packet by using a packet encoding
  • the bit selection module 205 is configured to perform bit selection on the A-coded information packet and the B-check packet, respectively, to obtain a selected output codeword bit sequence, where the output codeword bit sequence includes at least the C-share rate
  • the matched codeword bit sequence and the B-rate rate-matched check bit sequence are obtained only by the information bits in the A-part coded packet.
  • the check coding may adopt one of the following coding modes: single parity coding, BCH coding, RM coding, and RS coding.
  • the check code may also be encoded by B-bit check.
  • B-bit check code and the single-parity code, the BCH code, the RM code, and the RS code, refer to the foregoing method embodiments, and thus no further details are provided herein.
  • the packet encoding processing apparatus may further include: a bit stuffing module configured to perform bit filling by one or more of the following:
  • the input information bit sequence is filled with K-K0 bits, where K0 is the number of bits of the input information bit sequence;
  • K is a positive integer multiple of k
  • k is the number of bits of the channel coding input
  • H is the maximum of the number of bits of all coded packets.
  • the bit stuffing module 300 is configured to fill the input information bit sequence with K-K0 bits before the segmentation module 200 performs the segmentation, where K0 is the number of bits of the input information bit sequence;
  • the output codeword bit sequence in the bit selection does not include the padding bits described above.
  • the packet encoding processing apparatus may further include: a determining module configured to determine a number of bits of the codeword bit sequence after each rate matching by any one of the following parameter sets:
  • Parameter set one preset code rate, number of information bits of the coded information packet, number of codeword bit sequences of the coded information packet, number of coded information packets, and number of information bits of the B check packets;
  • Parameter set two preset code rate, number of bits of the input information bit sequence, number of codeword bit sequences of the encoded information packet, number of coded information packets, and number of information bits of the B check packets;
  • Parameter set three preset code rate, number of information bits of the codeword bit sequence, number of codeword bit sequences, and number of information bits of the B check packets;
  • Parameter set four the total number of transmission bits, the number of codeword bit sequences, and the number of information bits of the B check packets;
  • Parameter set five modulation order, number of preset resources, number of codeword bit sequences, and number of information bits of B check packets.
  • the packet encoding processing apparatus may further include: an interleaving module configured to interleave the output codeword bit sequence after the bit selection module 205 performs bit selection.
  • the data packet encoding processing apparatus may further include: a retransmission processing module configured to process a retransmission codeword bit sequence corresponding to the output codeword bit sequence; wherein the retransmission processing module The method may be configured to process the retransmission codeword bit sequence corresponding to the output codeword bit sequence by performing cyclic bit selection on the A coded information packet in a retransmission version number manner or a sequential manner to obtain a C rate. The matched retransmission codeword bit sequence is subjected to cyclic bit selection for the B check packets to obtain a B-rate matched retransmission check bit sequence.
  • the retransmission processing module may be configured to process the retransmission codeword bit sequence corresponding to the output codeword bit sequence by: B-rate matching retransmission check bit sequence The column is only obtained from the information bits in the A-coded packet.
  • the input information bit sequence is segmented to obtain a plurality of sub-information bit sequences, and a CRC sequence is added to each sub-information bit sequence to obtain a plurality of sub-information bit sequences;
  • the bit sequence is subjected to channel coding to obtain a plurality of coded codeword bit sequences and is divided into a plurality of coded information packets, and the plurality of coded information packets are packet-encoded to obtain a plurality of check packets; and the plurality of coded codeword bit sequences are encoded.
  • the channel coding is Turbo coding, which achieves very large error rate performance under the same code length and is close to or even better than the long code length. Moreover, the channel coding code length used is shorter, so the decoding delay and the reception delay are relatively small, and the complexity of coding/decoding per channel is small, and a pipeline-like method "fly on line" can be used at the same time. Work, each time a channel coding block is received, it can be decoded immediately. The decoding speed is faster and the delay is less, which can improve the throughput of the entire communication system.
  • a wireless data communication system which may be used for a base station, such as an access point (AP, Access Point), or may be referred to as a Node B, a radio network controller.
  • RNC Radio Network Controller
  • eNB Evolved Node B
  • BSC Base Station Controller
  • BTS Base Transceiver Station
  • BS Base Station
  • TF transceiver function body
  • radio router radio transceiver, basic service unit (BSS, Basic Service Set), extended service unit (ESS, Extended Service Set), radio base station (RBS, Radio Base Station), or some Other terms.
  • the transmitting end 400 transmits data to the receiving end 401, and the receiving end 401 sends a feedback signal to the transmitting end 400 according to the correct condition of receiving the data.
  • the sending end 400 may be a base station, and other devices or devices as described above; and the receiving end 401 may be a User Equipment (UE), such as a mobile phone, or may be a tablet computer, a reading machine, or an electronic device.
  • UE User Equipment
  • Handheld devices such as watches, and other electronic devices or connected electronic devices, wireless modems, laptop computers, personal computers, in-vehicle devices, automobiles, wireless access nodes, sensor nodes, and the like that require access to the Internet.
  • the various algorithms and methods and apparatus modules described in this embodiment of the invention may be used for transmissions between base station 400 and UE 401 in a wireless communication system.
  • the packet encoding processing method of the embodiment of the present invention can also be applied to an LTE communication system, a WiFi (Wireless Fidelity) system, a high frequency communication system, a 5G communication system, and the like.
  • FIG. 4 illustrates an embodiment of a direct communication embodiment of a base station and a handset.
  • the length of the input information bit sequence to be transmitted is 6000 bits, and the channel coding adopts Turbo coding in the LTE system, and the code rate set by the system is 1/2.
  • This embodiment may include the following steps:
  • each encoded information packet 500 includes only one turbo coded codeword bit sequence, and the ten turbo encoded codeword bit sequences are bit-collected data streams, the bits.
  • the first part of the collection is a Turbo code information bit sequence after sub-block interleaving, and the second part is obtained by interleaving the first and second parity bit sequences after sub-block interleaving, as shown in FIG. Code check bit sequence;
  • A 10
  • the check set has only 1 bit, so the check packet 501 is directly merged in order, and its length is 1836 bits, and the length of each encoded information packet is equal;
  • each Turbo coded block adopts the bit selection method of the LTE system, and is a start bit for determining the bit selection by the version number.
  • the simulation comparison is shown in Fig. 6.
  • the modulation mode is 16QAM (that is, the modulation order is 4), and the AWGN (additive white Gaussian noise) channel can be found in the case of the same system code rate 1/2, the data packet of this embodiment.
  • the encoding processing method can obtain a very large coding gain, and has a gain of about 0.8 decibels (dB) when the block error rate (PER, Packet Error Rate) is 10 -2 , and the dotted line in Fig. 6 corresponds to the conventional data encoding method, which also has 10 turbo coding blocks, the information bit sequence length is 608 bits, the code rate is 1/2, 16QAM, and the solid line in FIG. 6 corresponds to the packet coding processing method of the embodiment of the present invention.
  • the packet coding processing method of the embodiment of the present invention can obtain a very large gain under the equal code length, and is also compared with the performance of the long code length Turbo coding block, as shown in FIG.
  • the solid line in FIG. 7 corresponds to the method of this embodiment.
  • the dotted line in FIG. 7 corresponds to the performance of the long code length, and only one Turbo coded block has an information length of 6080. It can be seen that the performance is basically the same (even at a low SNR) Long code length is ok).
  • the data packet coding processing method in the embodiment of the present invention can reduce the length of the turbo coding block in the case that the coding performance does not change much, and thus can reduce the complexity of Turbo coding and decoding, as in this embodiment, if The traditional method needs to use the performance achieved by the length of 6080 bits, and the packet encoding processing method of this embodiment can be directly implemented with a length of 608 bits, which greatly reduces the channel coding and decoding complexity, and the reception delay and The decoding delay is also greatly reduced.
  • each Turbo codeword bit sequence can be decoded, without waiting for all bits to be completely received, the waiting time is greatly reduced, and each Turbo codeword bit is reduced.
  • the "fly on line" method can be used for decoding between sequences, which can greatly improve the decoding speed.
  • the bit selection is performed in a sequential manner, the index position of the start bit of the bit selection is 0, and the code-matched bit sequence after the rate matching is sequentially collected from the 0th bit, and the number of bits required is reached.
  • the bit selection is performed by the retransmission version number, and the ith retransmission version is corresponding to the ith starting bit index position st i , and the starting bit index position is determined by the retransmission version number r i and the total length of the Turbo coding block.
  • the output codeword bit sequence can be interleaved to resist channel fading and burst noise, improving system robustness.
  • the interleaving method may include: the interleaving method of all rate-matched codeword bit sequences belonging to the i-th encoded packet is different from the interleaving method belonging to the j-th encoded packet, where i is not equal to j i and j are integers from 0 to 9, for example, cyclically shifting mod (i ⁇ 11, 1155) bits of all rate-matched codeword bit sequences belonging to the i-th encoded packet.
  • the coded codeword bit sequence after the C rate matching of the bit is separately interleaved, for example, the i-th matrix block interleaving is performed after each i-rate matched coded codeword bit sequence, and the number of columns is i ⁇ 13; wherein the interleaving method of the different coded codeword bit sequences is different, that is, for each The codeword bit sequences are interleaved differently, so that the reception delay and decoding delay of each codeword bit sequence are not affected, and corresponding performance benefits can still be obtained.
  • the maximum number of retransmissions in this embodiment is 3 times (including the first transmission, and the maximum number of transmissions is 4 times).
  • the total number of bits of the secondary transmission data is equal to the number of first transmitted data bits.
  • the number of codeword bit sequence bits and the number of parity packets in the rate matching are determined by the following parameters:
  • the number of bits per codeword bit sequence is Bit
  • the number of bits of each codeword bit sequence of the second or third retransmission data and the check packet The number of bits is Bit.
  • the bit selection is performed in a sequential manner, and the code bit sequence of each rate matching of the 0th to 3rd transmission data and the start bit index position of the parity packet are as shown in Table 2.
  • the bit selection is performed according to the retransmission version number method.
  • the bit selection start bit index of each Turbo codeword bit sequence corresponding to each data transmission is respectively [40 1000 520 1480].
  • the simulation result is shown in FIG. 8 and compared with the conventional method, it can be found that the embodiment obtains a larger Throughput gain (HARQ scheme of this embodiment has better robustness), wherein the modulation mode is 16QAM (modulation order is 4), and the dotted line in FIG. 8 corresponds to the conventional method, 10 Turbo code blocks,
  • the number of information bits is 608 and the code rate is 0.5; the solid line in Fig. 8 is a simulation performed in accordance with an aspect of an embodiment of the present invention.
  • the preset resource refers to the number of constellation modulation symbols, and the number of codeword bit sequence bits after the rate matching is: pre-C1
  • C1 and N1 are calculated as:
  • the UE transmits data to the base station or the base station transmits data to the UE.
  • the length of the input information bit sequence to be transmitted is 19800 bits
  • the channel coding adopts Turbo coding in the LTE system
  • the code rate set by the system is 2/5
  • the number of information bits to be input by the Turbo coding is 1008.
  • Step 41 Fill the input information bit sequence with 200 bits, so that the number of bits reaches 20,000 bits;
  • each encoded information packet 900 includes 2 copies of the turbo coded codeword bit sequence, and the turbo coded codeword bit sequence is a bit-collected data stream, and the bit-collected
  • the first part is a turbo code information bit sequence after sub-block interleaving
  • the second part is obtained by interleaving the first and second parity bit sequences after sub-block interleaving;
  • the packet D1' has a bit number of 3036 bits, which is equal to the number of bits of each encoded information packet;
  • C 20 number of bits of the codeword bit sequence after rate matching, calculated as follows: the number of bits of the codeword bit sequence after 20 rate matching is
  • the final code rate is very close to the system preset code rate of 2/5, that is, 1008 ⁇ 20/(2399 ⁇ 20+2432) ⁇ 0.4.
  • bit selection is made, the selection is started from the start bit, and the padded bits are not selected.
  • an LTE data communication system is applicable to a UE or a base station, where the UE transmits data to the base station or the base station transmits data to the UE.
  • the length of the input information bit sequence (service data) to be transmitted is 53,760 bits
  • the channel coding adopts Turbo coding in the LTE system, and the coded preset code rate set by the system is 1/2, and the Turbo code needs to be input.
  • the number of information bits is 848.
  • each coded information packet includes 4 copies of the turbo coded codeword bit sequence, and the turbo coded codeword bit sequence is a bit-collected data stream, and the first part of the bit collection is sub-block interleaved.
  • the latter Turbo code information bit sequence, the second part is obtained by interleaving the first and second parity bit sequences after sub-block interleaving;
  • bit selection is made, the selection is started from the start bit, and the padded bits are not selected.
  • Embodiment 7 The difference between Embodiment 7 and Embodiment 1 to Embodiment 6 is the channel coding mode.
  • the channel coding method used in this embodiment is LDPC coding or RS coding or convolutional coding.
  • the embodiment further includes corresponding packet encoding processing means and modules, and the functions are implemented corresponding to the steps of the respective embodiments.
  • the performance of the overall data packet is improved, thereby improving the reception robustness, and the performance is superior to the conventional data encoding scheme.
  • an embodiment of the present invention further provides a computer readable storage medium storing computer executable instructions, where the computer executable instructions are executed by a processor to implement the data packet encoding processing method.
  • a computer-readable medium can include a computer storage medium (or non-transitory medium) and a communication medium (or transitory medium).
  • a computer storage medium includes volatile and nonvolatile, implemented in any method or technology for storing information, such as computer readable instructions, data structures, program modules or other data. Sex, removable and non-removable media.
  • Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridge, magnetic tape, magnetic disk storage or other magnetic storage device, or may Any other medium used to store the desired information and that can be accessed by the computer.
  • communication media typically includes computer readable instructions, data structures, program modules, or other data in a modulated data signal, such as a carrier wave or other transport mechanism, and can include any information delivery media. .
  • the embodiment of the present application provides a packet encoding processing method and device, which can solve the contradiction between performance and complexity, can reduce coding complexity while ensuring superior performance, and can also improve decoding speed and system throughput.

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Abstract

La présente invention concerne un procédé de traitement de codage de paquets de données qui consiste : à diviser une séquence de bits d'information en une sous-séquence de bits d'informations C ; à ajouter une séquence de bits de contrôle de redondance cyclique (CRC) possédant une longueur L à chacune des sous-séquences de bits d'informations C séparément ; à effectuer un codage de canal sur les sous-séquences de bit d'informations de CRC ajoutés C pour obtenir des séquences de bits de mot de code C ; à diviser les séquences de bits de mot de code codé C en des ensembles de blocs codés A et à définir chaque ensemble de blocs codés comme un paquet d'informations codées individuelles ; à générer, au moyen de codage de paquets, des paquets de vérification B à partir des paquets d'informations codées A ; et à effectuer une sélection de bits sur les paquets d'informations codées A et les paquets de vérification B, les séquences de bits de vérification adaptées au débit B étant obtenues uniquement sur la base des bits d'information dans les paquets d'informations codées A.
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