WO2017133356A1 - 一种电压模式驱动电路 - Google Patents

一种电压模式驱动电路 Download PDF

Info

Publication number
WO2017133356A1
WO2017133356A1 PCT/CN2016/112755 CN2016112755W WO2017133356A1 WO 2017133356 A1 WO2017133356 A1 WO 2017133356A1 CN 2016112755 W CN2016112755 W CN 2016112755W WO 2017133356 A1 WO2017133356 A1 WO 2017133356A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
driving tube
drive transistor
inverter
driving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/112755
Other languages
English (en)
French (fr)
Inventor
陈常勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
China Academy of Telecommunications Technology CATT
Original Assignee
China Academy of Telecommunications Technology CATT
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by China Academy of Telecommunications Technology CATT filed Critical China Academy of Telecommunications Technology CATT
Publication of WO2017133356A1 publication Critical patent/WO2017133356A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/30—Modifications for providing a predetermined threshold before switching
    • H03K17/302—Modifications for providing a predetermined threshold before switching in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/30—Modifications for providing a predetermined threshold before switching

Definitions

  • the present application relates to the field of communications technologies, and in particular, to a voltage mode driving circuit.
  • the supply voltage of the chip is getting lower and lower, and the drive voltage of the drive circuit specified by many protocol specifications is still high, so the supply voltage of the drive circuit is generally generated by an internal voltage regulator (LDO).
  • LDO internal voltage regulator
  • the driving circuit is in the voltage mode, the switching current is relatively large, and the average current is relatively small, so the output voltage of the LDO has a relatively large jitter.
  • the circuit bandwidth of the LDO can be increased to reduce the response time, which increases the static power consumption of the circuit.
  • the traditional voltage mode drive circuit is shown in Figure 1.
  • the traditional voltage mode drive circuit draws power directly from the LDO. Under the advanced chip manufacturing process, the internal circuit supply voltage has been reduced to 0.9V, the IO supply voltage is 1.8V, and some interfaces.
  • the drive circuit for example, the normal voltage of the output of the LP transmitter of the MIPI DPHY is 1.2V. If the voltage mode is used in the driver circuit, then an LDO is required to draw 1.2V from 1.8V. Voltage mode driving can reduce static power consumption, but increase the switching current, so that the LDO output 1.2V voltage will fluctuate. Increasing the bandwidth of this LDO can reduce the fluctuation, but also increase the static power consumption.
  • the voltage mode driving circuit of the prior art requires a large quiescent current and increases the static power consumption.
  • the embodiment of the present application provides a voltage mode driving circuit for reducing power consumption.
  • a voltage mode driving circuit provided by an embodiment of the present application includes a voltage regulator, a first driving tube connected to an output end of the voltage regulator, a second driving tube connected to the first driving tube, and a An inverter connected to the first driving tube and the second driving tube, and further comprising:
  • a dynamic current automatic compensation module connected to the first driving tube and the inverter for respectively supplying a dynamic current to the first driving tube according to a change of an output signal of the inverter.
  • the circuit can be detected when the driving circuit needs a large charging current, automatically providing the corresponding current, and when When charging current is not required, it can be automatically turned off, so power consumption can be significantly reduced.
  • the dynamic current automatic compensation module comprises: a resistor, a capacitor, and a third driving tube, wherein the first end of the resistor is connected to the first end of the capacitor, and the connection point of the resistor and the capacitor is a gate of the third driving transistor is connected, a second end of the capacitor is connected to an output end of the inverter, a second end of the resistor is connected to a power source, and a source of the third driving tube The power supply is connected, and the drain of the third drive tube is connected to the first drive tube.
  • the third driving tube is a PMOS tube.
  • the first driving tube is a PMOS tube.
  • the second driving tube is an NMOS tube.
  • an input end of the voltage regulator is connected to the power source, an output end of the voltage regulator is connected to a source of the first driving tube, and a source of the first driving tube is further connected to the first
  • the drains of the three drive transistors are connected, and the gate of the first drive transistor is connected to the output of the inverter.
  • a drain of the second driving transistor is connected to a drain of the first driving transistor, a source of the second driving transistor is grounded, a gate of the second driving transistor is opposite to the reverse phase The outputs of the devices are connected.
  • the input of the inverter acts as an input to the circuit for receiving an input signal of the circuit.
  • the connecting end of the first driving tube and the second driving tube serves as an output end of the circuit for outputting an output signal of the circuit.
  • the voltage regulator is a voltage regulator whose corresponding speed is lower than a preset threshold.
  • FIG. 1 is a schematic diagram of a voltage mode driving circuit in the prior art
  • FIG. 2 is a schematic diagram of a voltage mode driving circuit according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a gate voltage waveform of a driving tube PM0 according to an embodiment of the present application.
  • the embodiment of the present application provides a voltage mode driving circuit for reducing power consumption.
  • the voltage mode driving circuit provided by the embodiment of the present application directly takes power from the power source, thereby reducing the burden on the power supply circuit.
  • the voltage mode driving circuit provided by the embodiment of the present application, referring to FIG. 2, when the input signal in is converted from low to high, the output signal inb of the inverter will be converted from high to low, and the driving tube PM1 needs to be needed.
  • the current boosts the output voltage.
  • the embodiment of the present application uses a high-pass filter composed of R0 and C0. When it detects the high-to-low transition of inb, the gate voltage of the driving transistor PM0 is pulled low, thereby supplying current to PM1 by using PM0. It is the moment when PM1 needs a large current.
  • the gate voltage of PM0 also returns to the power supply voltage, thereby stopping the power supply and avoiding the voltage of the output signal vreg of the voltage regulator.
  • the values of the resistor R0 and the capacitor C0 need to be combined with the driving tube PM0 to apply different load currents. If the value is not suitable, it will cause insufficient or too much charging.
  • the gate voltage of the driving tube PM0 changes, and the waveform of the change is as shown in FIG.
  • T0 of the power supply voltage vth vth is the threshold voltage of PM0
  • the drive transistor PM0 charges the drive circuit.
  • the selection of the resistor R0 and the capacitor C0 requires that the charge charged by the drive transistor PM0 during the period T0 is equal to the charge required by the drive circuit.
  • the charge required to charge the drive tube PM0 during the period T0 is less than the charge required by the drive circuit to prevent overshoot. Simulation is required, and R0 and C0 are selected according to the voltage waveform of the output signal vreg of the regulator.
  • a voltage mode driving circuit includes: a voltage regulator (ie, an LDO in FIG. 2), and a first driving tube connected to an output end of the voltage regulator (ie, FIG. 2 PM1), a second drive tube connected to the first drive tube (ie, NM1 in FIG. 2), and an inverter connected to the first drive tube and the second drive tube (ie, in FIG. 2 Inverter) also includes:
  • a dynamic current automatic compensation module connected to the first driving tube and the inverter for respectively supplying a dynamic current to the first driving tube according to a change of an output signal of the inverter.
  • the circuit can detect when the drive circuit needs a large charging current, automatically supply the corresponding current, and can automatically turn off when the charging current is not needed, so the power consumption can be significantly reduced.
  • the dynamic current automatic compensation module specifically includes: a resistor R0, a capacitor C0, and a third driving tube (ie, PM3 in FIG. 2), wherein the first end of the resistor is connected to the first end of the capacitor, a connection point of the resistor and the capacitor is connected to a gate of the third driving tube, a second end of the capacitor is connected to an output end of the inverter, and a second end of the resistor is connected to a power source.
  • the source of the third driving tube is connected to the power source, and the drain of the third driving tube is connected to the first driving tube.
  • the third driving tube is a PMOS tube.
  • the first driving tube is a PMOS tube.
  • the second driving tube is an NMOS tube.
  • an input end of the voltage regulator is connected to the power source, and an output end of the voltage regulator is connected to the first driver a source of the tube, a source of the first driving tube is further connected to a drain of the third driving tube, and a gate of the first driving tube is connected to an output of the inverter.
  • a drain of the second driving transistor is connected to a drain of the first driving transistor, a source of the second driving transistor is grounded, a gate of the second driving transistor is opposite to the reverse phase The outputs of the devices are connected.
  • the input of the inverter acts as an input to the circuit for receiving an input signal of the circuit.
  • the connecting end of the first driving tube and the second driving tube serves as an output end of the circuit for outputting an output signal of the circuit.
  • the voltage regulator is a voltage regulator whose corresponding speed is lower than a preset threshold.
  • the technical solution provided by the embodiment of the present invention can detect when the driving circuit needs a large charging current, automatically provide a corresponding current, and can automatically turn off when the charging current is not needed, thereby being significantly reduced. Power consumption.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

Landscapes

  • Dc-Dc Converters (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

一种电压模式驱动电路，用以降低功耗。该电路包括：稳压器，与所述稳压器的输出端连接的第一驱动管，与所述第一驱动管连接的第二驱动管，以及与所述第一驱动管和第二驱动管连接的反相器，并且，还包括：分别与所述第一驱动管和所述反相器连接的用于根据所述反相器的输出信号的变化，为该第一驱动管提供动态电流的动态电流自动补偿模块。

Description

一种电压模式驱动电路
本申请要求在2016年02月04日提交中国专利局、申请号为201610080795.0、发明名称为“一种电压模式驱动电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，尤其涉及一种电压模式驱动电路。
背景技术
随着工艺的演进，芯片的供电电压越来越低，而很多协议规范规定的驱动电路的驱动电压仍然较高，这样驱动电路的供电电压一般由内部稳压器(LDO)产生。如果驱动电路为电压模式，则开关电流比较大，而平均电流比较小，因此LDO的输出电压会有比较大的抖动。为了降低抖动，可以增大LDO的电路带宽降低响应时间，而这样会增大电路的静态功耗。
传统的电压模式驱动电路参见图1，传统的电压模式驱动电路直接从LDO取电，在先进芯片制造工艺下，内部电路的供电电压已经降低到0.9V，IO供电电压为1.8V，而有些接口驱动电路，例如：MIPI DPHY的LP发送端的输出的正常电压为1.2V。如果驱动电路中采用电压模式，那么就需要一个LDO从1.8V取电产生1.2V的电压。电压模式驱动可以降低静态功耗，但增大了开关电流，这样LDO的输出1.2V电压就会有波动，增大此LDO的带宽可以降低波动，但同时也增大了静态功耗。
综上所述，现有技术中的电压模式驱动电路需要较大的静态电流，增大了静态功耗。
发明内容
本申请实施例提供了一种电压模式驱动电路，用以降低功耗。
本申请实施例提供的一种电压模式驱动电路包括稳压器，与所述稳压器的输出端连接的第一驱动管，与所述第一驱动管连接的第二驱动管，以及与所述第一驱动管和第二驱动管连接的反相器，并且，还包括：
分别与所述第一驱动管和所述反相器连接的用于根据所述反相器的输出信号的变化，为该第一驱动管提供动态电流的动态电流自动补偿模块。
通过该电路可以检测到驱动电路何时需要大的充电电流，自动提供相应电流，而且当 不需要充电电流时，可以自动关断，因此可以显著地降低功耗。
较佳地，所述动态电流自动补偿模块，具体包括：电阻、电容、第三驱动管，其中所述电阻的第一端和电容的第一端相连，所述电阻和电容的连接点与所述第三驱动管的栅极相连，所述电容的第二端与所述反相器的输出端相连，所述电阻的第二端与电源相连，所述第三驱动管的源极与所述电源相连，所述第三驱动管的漏级与所述第一驱动管相连。
较佳地，所述第三驱动管为PMOS管。
较佳地，所述第一驱动管为PMOS管。
较佳地，所述第二驱动管为NMOS管。
较佳地，所述稳压器的输入端连接所述电源，所述稳压器的输出端连接所述第一驱动管的源极，所述第一驱动管的源极还与所述第三驱动管的漏级相连，所述第一驱动管的栅极与所述反相器的输出端相连。
较佳地，所述第二驱动管的漏级与所述第一驱动管的漏级相连，所述第二驱动管的源极接地，所述第二驱动管的栅极与所述反相器的输出端相连。
较佳地，所述反相器的输入端作为所述电路的输入端，用于接收所述电路的输入信号。
较佳地，所述第一驱动管和第二驱动管的连接端作为所述电路的输出端，用于输出所述电路的输出信号。
较佳地，所述稳压器为相应速度低于预设门限值的稳压器。
附图说明
图1为现有技术中的电压模式驱动电路示意图；
图2为本申请实施例提供的电压模式驱动电路示意图；
图3为本申请实施例提供的驱动管PM0栅极电压波形示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本申请实施例提供了一种电压模式驱动电路，用以降低功耗。
本申请实施例提供的电压模式驱动电路直接从电源取电，从而降低供电电路负担。
本申请实施例提供的电压模式驱动电路，参见图2，当输入信号in发生从低到高的转换时，反相器的输出信号inb会发生从高到低的转换，此时驱动管PM1需要电流把输出电压冲高。本申请实施例使用由R0与C0所组成的高通滤波器，当它检测到inb从高到低的转换，把驱动管PM0的栅极电压拉低，从而利用PM0对PM1提供电流，此时也正是PM1需要大电流的时刻。当输入信号in完成转换后，PM0的栅极电压也会回到电源电压，从而停止供电，避免把稳压器的输出信号vreg的电压冲高。
本申请实施例中，电阻R0、电容C0的取值需要结合驱动管PM0去适用不同的负载电流。如果取值不合适，会造成充电不够或过大。对于任一组R0与C0的值，当反相器的输出信号inb从高到低发生转换时，引起驱动管PM0的栅极电压发生变化，变化的波形如图3所示，在它低于电源电压vth(vth为PM0的阈值电压)的时间周期T0内，驱动管PM0会对驱动电路充电。理想情况下，电阻R0与电容C0的选取，需要T0这段时间内驱动管PM0充电的电荷等于驱动电路所需的电荷。在实际电路设计的应用中，一般选取需要T0这段时间内驱动管PM0充电的电荷小于驱动电路所需的电荷以防止过冲。需要进行仿真，根据稳压器的输出信号vreg的电压波形，选择R0与C0。
由此可见，本申请实施例提供的一种电压模式驱动电路包括：稳压器(即图2中的LDO)，与所述稳压器的输出端连接的第一驱动管(即图2中的PM1)，与所述第一驱动管连接的第二驱动管(即图2中的NM1)，以及与所述第一驱动管和第二驱动管连接的反相器(即图2中的Inverter)，还包括：
分别与所述第一驱动管和所述反相器连接的用于根据所述反相器的输出信号的变化，为该第一驱动管提供动态电流的动态电流自动补偿模块。
通过该电路可以检测到驱动电路何时需要大的充电电流，自动提供相应电流，而且当不需要充电电流时，可以自动关断，因此可以显著地降低功耗。
较佳地，所述动态电流自动补偿模块，具体包括：电阻R0、电容C0、第三驱动管(即图2中的PM3)，其中所述电阻的第一端和电容的第一端相连，所述电阻和电容的连接点与所述第三驱动管的栅极相连，所述电容的第二端与所述反相器的输出端相连，所述电阻的第二端与电源相连，所述第三驱动管的源极与所述电源相连，所述第三驱动管的漏级与所述第一驱动管相连。
较佳地，所述第三驱动管为PMOS管。
较佳地，所述第一驱动管为PMOS管。
较佳地，所述第二驱动管为NMOS管。
较佳地，所述稳压器的输入端连接所述电源，所述稳压器的输出端连接所述第一驱动 管的源极，所述第一驱动管的源极还与所述第三驱动管的漏级相连，所述第一驱动管的栅极与所述反相器的输出端相连。
较佳地，所述第二驱动管的漏级与所述第一驱动管的漏级相连，所述第二驱动管的源极接地，所述第二驱动管的栅极与所述反相器的输出端相连。
较佳地，所述反相器的输入端作为所述电路的输入端，用于接收所述电路的输入信号。
较佳地，所述第一驱动管和第二驱动管的连接端作为所述电路的输出端，用于输出所述电路的输出信号。
较佳地，所述稳压器为相应速度低于预设门限值的稳压器。
综上所述，本申请实施例提供的技术方案，可以检测到驱动电路何时需要大的充电电流，自动提供相应电流，而且当不需要充电电流时，可以自动关断，因此可以显著地降低功耗。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明实施例的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (10)

  1. 一种电压模式驱动电路，包括稳压器，与所述稳压器的输出端连接的第一驱动管，与所述第一驱动管连接的第二驱动管，以及与所述第一驱动管和第二驱动管连接的反相器，其特征在于，还包括：
    分别与所述第一驱动管和所述反相器连接的用于根据所述反相器的输出信号的变化，为该第一驱动管提供动态电流的动态电流自动补偿模块。
  2. 根据权利要求1所述的电路，其特征在于，所述动态电流自动补偿模块，具体包括：电阻、电容、第三驱动管，其中所述电阻的第一端和电容的第一端相连，所述电阻和电容的连接点与所述第三驱动管的栅极相连，所述电容的第二端与所述反相器的输出端相连，所述电阻的第二端与电源相连，所述第三驱动管的源极与所述电源相连，所述第三驱动管的漏级与所述第一驱动管相连。
  3. 根据权利要求1所述的电路，其特征在于，所述第三驱动管为PMOS管。
  4. 根据权利要求3所述的电路，其特征在于，所述第一驱动管为PMOS管。
  5. 根据权利要求4所述的电路，其特征在于，所述第二驱动管为NMOS管。
  6. 根据权利要求5所述的电路，其特征在于，所述稳压器的输入端连接所述电源，所述稳压器的输出端连接所述第一驱动管的源极，所述第一驱动管的源极还与所述第三驱动管的漏级相连，所述第一驱动管的栅极与所述反相器的输出端相连。
  7. 根据权利要求6所述的电路，其特征在于，所述第二驱动管的漏级与所述第一驱动管的漏级相连，所述第二驱动管的源极接地，所述第二驱动管的栅极与所述反相器的输出端相连。
  8. 根据权利要求7所述的电路，其特征在于，所述反相器的输入端作为所述电路的输入端，用于接收所述电路的输入信号。
  9. 根据权利要求8所述的电路，其特征在于，所述第一驱动管和第二驱动管的连接端作为所述电路的输出端，用于输出所述电路的输出信号。
  10. 根据权利要求1～9任一权项所述的电路，其特征在于，所述稳压器为相应速度低于预设门限值的稳压器。
PCT/CN2016/112755 2016-02-04 2016-12-28 一种电压模式驱动电路 Ceased WO2017133356A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610080795.0 2016-02-04
CN201610080795.0A CN107040250B (zh) 2016-02-04 2016-02-04 一种电压模式驱动电路

Publications (1)

Publication Number Publication Date
WO2017133356A1 true WO2017133356A1 (zh) 2017-08-10

Family

ID=59500287

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/112755 Ceased WO2017133356A1 (zh) 2016-02-04 2016-12-28 一种电压模式驱动电路

Country Status (2)

Country Link
CN (1) CN107040250B (zh)
WO (1) WO2017133356A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109116901A (zh) * 2018-10-31 2019-01-01 上海艾为电子技术股份有限公司 一种线性稳压电路和集成电路
TWI697750B (zh) * 2019-08-07 2020-07-01 華邦電子股份有限公司 穩壓裝置及穩壓裝置的控制方法
US10845835B1 (en) 2019-09-05 2020-11-24 Winbond Electronics Corp. Voltage regulator device and control method for voltage regulator device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113093849A (zh) * 2021-03-31 2021-07-09 上海磐启微电子有限公司 一种实现干扰滤除功能的电路模块和集成电路系统

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04207630A (ja) * 1990-11-30 1992-07-29 Mitsubishi Electric Corp 半導体集積回路
CN102915061A (zh) * 2011-08-05 2013-02-06 深圳市汇春科技有限公司 极低静态电流的低压降稳压器
CN104111681A (zh) * 2013-04-22 2014-10-22 上海华虹宏力半导体制造有限公司 低压差分信号驱动器
US8922241B2 (en) * 2011-09-30 2014-12-30 Renesas Electronics Corporation Logic circuit and semiconductor integrated circuit
US9024558B2 (en) * 2012-05-28 2015-05-05 Rohm Co., Ltd. Bridge output circuit, motor driving device using the same, and electronic apparatus

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6215349B1 (en) * 1999-01-05 2001-04-10 International Business Machines Corp. Capacitive coupled driver circuit
JP4364664B2 (ja) * 2004-02-04 2009-11-18 シャープ株式会社 発光ダイオード駆動回路および光ファイバリンク用光送信機
CN1306703C (zh) * 2004-04-30 2007-03-21 华为技术有限公司 线驱动器及其控制输出信号的方法
CN101895281B (zh) * 2010-07-28 2012-12-26 佛山市顺德区瑞德电子实业有限公司 一种开关电源的新型mos管驱动电路
KR101822070B1 (ko) * 2012-08-13 2018-01-25 페어차일드코리아반도체 주식회사 피에조 구동 회로 및 피에조 구동 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04207630A (ja) * 1990-11-30 1992-07-29 Mitsubishi Electric Corp 半導体集積回路
CN102915061A (zh) * 2011-08-05 2013-02-06 深圳市汇春科技有限公司 极低静态电流的低压降稳压器
US8922241B2 (en) * 2011-09-30 2014-12-30 Renesas Electronics Corporation Logic circuit and semiconductor integrated circuit
US9024558B2 (en) * 2012-05-28 2015-05-05 Rohm Co., Ltd. Bridge output circuit, motor driving device using the same, and electronic apparatus
CN104111681A (zh) * 2013-04-22 2014-10-22 上海华虹宏力半导体制造有限公司 低压差分信号驱动器

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109116901A (zh) * 2018-10-31 2019-01-01 上海艾为电子技术股份有限公司 一种线性稳压电路和集成电路
CN109116901B (zh) * 2018-10-31 2023-09-15 上海艾为电子技术股份有限公司 一种线性稳压电路和集成电路
TWI697750B (zh) * 2019-08-07 2020-07-01 華邦電子股份有限公司 穩壓裝置及穩壓裝置的控制方法
US10845835B1 (en) 2019-09-05 2020-11-24 Winbond Electronics Corp. Voltage regulator device and control method for voltage regulator device

Also Published As

Publication number Publication date
CN107040250B (zh) 2019-09-17
CN107040250A (zh) 2017-08-11

Similar Documents

Publication Publication Date Title
US20170193885A1 (en) Shift register unit, driving method, gate driving circuit and display device
CN105446923B (zh) 具有上拉升压器和下拉升压器的差分驱动器
TWI621326B (zh) 改良電源漣波之抑制之線性穩壓器、其方法及提供位準電壓之電路
US9425690B2 (en) Current controlling mode direct current (DC)-DC converter
WO2017133356A1 (zh) 一种电压模式驱动电路
CN103092243A (zh) 信号产生电路
US8698543B1 (en) Interface to a serial communications bus
CN112286334B (zh) 用于mcu的低功耗电源切换电路及其实现方法
US9071185B2 (en) Constant voltage circuit and analog electronic clock
CN106128352A (zh) Goa单元、驱动方法、goa电路和显示装置
CN112765064A (zh) 上拉电阻调整方法、控制芯片及电子设备
EP3333680B1 (en) Drive unit, method and circuit for touch control drive electrode, and touch control display panel
TWI513155B (zh) 電源轉換系統
WO2016058343A1 (zh) Io接口电平转换电路、io接口电平转换方法及存储介质
CN115136480B (zh) 一种调压系统、片上系统及调压方法
US20060267673A1 (en) [modulator]
WO2025039733A1 (zh) 触控显示面板及显示装置
US10298180B2 (en) Control circuit, control method, and electronic device
CN104253594B (zh) 充电模块、驱动电路及驱动电路的操作方法
US10833899B2 (en) Low power physical layer driver topologies
US20140210537A1 (en) Electronic device
US20140253179A1 (en) Low voltage swing repeater
WO2017156838A1 (zh) 液晶面板驱动系统中的切角电路
CN113630114B (zh) 驱动电路以及电子设备
CN103413568A (zh) 参考电压提供电路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16889162

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16889162

Country of ref document: EP

Kind code of ref document: A1