WO2017130654A1 - Photovoltaic element - Google Patents

Photovoltaic element Download PDF

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Publication number
WO2017130654A1
WO2017130654A1 PCT/JP2017/000224 JP2017000224W WO2017130654A1 WO 2017130654 A1 WO2017130654 A1 WO 2017130654A1 JP 2017000224 W JP2017000224 W JP 2017000224W WO 2017130654 A1 WO2017130654 A1 WO 2017130654A1
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amorphous semiconductor
type amorphous
semiconductor layer
type
layer
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PCT/JP2017/000224
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French (fr)
Japanese (ja)
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公一 橋本
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長州産業株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a photovoltaic device.
  • solar cells have attracted particular attention as clean power generation means that does not generate CO 2 or other greenhouse gases, or as power generation means with high operational safety that can replace nuclear power generation.
  • One type of solar cell is a heterojunction solar cell with high power generation efficiency.
  • a heterojunction solar cell for example, a first intrinsic amorphous semiconductor layer and a p-type amorphous semiconductor layer are stacked in this order on one surface side of an n-type crystal semiconductor substrate, A second intrinsic amorphous semiconductor layer and an n-type amorphous semiconductor layer are stacked in this order on the other surface side of the n-type crystal semiconductor substrate.
  • a photovoltaic device having an n-type amorphous semiconductor layer side as a light incident surface has been proposed (Japanese Patent Application Laid-Open No. 2014-216334). And Japanese Unexamined Patent Application Publication No. 2014-216335).
  • the present invention has been made based on the above circumstances, and an object of the present invention is to provide a photovoltaic device that has low temperature dependence of output characteristics and can maintain good characteristics even at high temperatures. is there.
  • the present invention which has been made to solve the above problems, includes an n-type crystal semiconductor substrate, an n-type amorphous semiconductor layer stacked on the light incident surface side of the n-type crystal semiconductor substrate, and the n-type crystal semiconductor substrate.
  • a photovoltaic device comprising a p-type amorphous semiconductor layer laminated on the side opposite to the light incident surface side, wherein the semiconductor material forming the n-type amorphous semiconductor layer is an n-type It is characterized by being amorphous silicon oxide.
  • the temperature dependence of the output characteristics can be reduced because the n-type amorphous semiconductor layer is formed of amorphous silicon oxide.
  • the amorphous silicon oxide is preferably represented by Si 1-x O x (0.01 ⁇ x ⁇ 0.12). Since the n-type amorphous semiconductor layer is formed of amorphous silicon oxide having such an oxygen content, output characteristics such as conversion efficiency can be improved.
  • the semiconductor material forming the p-type amorphous semiconductor layer is preferably p-type amorphous silicon oxide.
  • the p-type amorphous semiconductor layer on the back side is also formed of amorphous silicon oxide, thereby making the temperature dependence of the output characteristics of the photovoltaic device more It can be reduced.
  • a second intermediate layer interposed between the n-type crystal semiconductor substrate and the p-type amorphous semiconductor layer is further provided, and the second intermediate layer is formed of an intrinsic amorphous semiconductor. Providing such a second intermediate layer also suppresses carrier recombination and can further enhance output characteristics.
  • amorphous in an amorphous semiconductor means not only a completely amorphous body but also one having microcrystals in the amorphous body.
  • an amorphous semiconductor including a microcrystal may be simply referred to as “amorphous semiconductor” or the like.
  • “Intrinsic” in an intrinsic amorphous semiconductor layer means that impurities are not intentionally doped, and includes impurities that are originally contained in raw materials or impurities that are unintentionally mixed in the manufacturing process. Meaning.
  • Amorphous silicon oxide as a semiconductor material refers to an amorphous compound having semiconductor characteristics formed by oxygen atoms and silicon atoms, and the ratio of oxygen atoms to silicon atoms is specified. It is not meant to be limited to those of the ratio.
  • the photovoltaic device of the present invention it is possible to provide a photovoltaic device that has low temperature dependence of output characteristics and can maintain good characteristics even at high temperatures.
  • FIG. 1 is a schematic cross-sectional view of a photovoltaic device according to an embodiment of the present invention. It is a graph which shows the conversion efficiency of the photovoltaic device in an Example. It is a graph which shows the external quantum efficiency, internal quantum efficiency, and reflectance of the power generation element which shines in an Example.
  • the photovoltaic element 10 in FIG. 1 includes an n-type crystal semiconductor substrate 11, a first intermediate layer 12 stacked in the following order on one surface side (upper side in FIG. 1) of the n-type crystal semiconductor substrate 11, and an n-type crystal.
  • a second intermediate layer 15 laminated on the amorphous semiconductor layer 13 and the first transparent conductive film 14 on the other surface side (lower side in FIG. 1) of the n-type crystal semiconductor substrate 11 in the following order, p-type An amorphous semiconductor layer 16 and a second transparent conductive film 17 are provided.
  • the photovoltaic device 10 includes a plurality of linear collector electrodes 18 disposed on the outer surface of the first transparent conductive film 14 and the outer surface of the second transparent conductive film 17.
  • the “outer surface” refers to the surface opposite to the n-type crystal semiconductor substrate 11 with the n-type crystal semiconductor substrate 11 as the center.
  • the “inner surface” refers to a surface on the n-type crystal semiconductor substrate 11 side.
  • the upper side in FIG. 1, that is, the first transparent conductive film 14 side is the light incident surface.
  • the photovoltaic element 10 has at least the first transparent conductive film 14 side as a light incident surface, and may be designed so that light can be incident also from the second transparent conductive film 17 side. That is, the photovoltaic device 10 can be configured such that light is incident from both sides.
  • the n-type crystal semiconductor substrate 11 is formed from an n-type crystal semiconductor.
  • An n-type crystal semiconductor is usually a crystal formed by adding a trace amount of a pentavalent element to a semiconductor such as silicon.
  • Examples of the crystal semiconductor constituting the n-type crystal semiconductor substrate 11 include SiC and SiGe in addition to silicon (Si), but silicon is preferable from the viewpoint of productivity.
  • the n-type crystal semiconductor substrate 11 may be a single crystal or a polycrystal.
  • a pyramidal fine concavo-convex structure is formed on both surfaces of the n-type crystal semiconductor substrate 11.
  • the height and size of the uneven structure may be uneven, and adjacent uneven parts may overlap.
  • a vertex and a trough part may be roundish.
  • the height of the unevenness is about several ⁇ m to several tens of ⁇ m.
  • Such a concavo-convex structure can be obtained, for example, by immersing the substrate material in an etching solution containing about 1 to 5% by mass of sodium hydroxide and anisotropically etching the (100) plane of the substrate material.
  • the average thickness of the n-type crystal semiconductor substrate 11 is not particularly limited.
  • the upper limit of the average thickness is, for example, 300 ⁇ m, and preferably 200 ⁇ m. Moreover, as this minimum, it can be set as 50 micrometers, for example.
  • the first intermediate layer 12 is a layer interposed between the n-type crystal semiconductor substrate 11 and the n-type amorphous semiconductor layer 13 and functions as a passivation layer that suppresses carrier recombination.
  • the first intermediate layer 12 is formed from an intrinsic amorphous semiconductor or an n-type amorphous semiconductor.
  • the first intermediate layer 12 is preferably a lightly doped n-type amorphous semiconductor layer having a smaller doping amount than the n-type amorphous semiconductor layer 13.
  • the first intermediate layer 12 is formed of an intrinsic amorphous semiconductor
  • silicon is usually preferable as the intrinsic amorphous semiconductor.
  • the first intermediate layer 12 is preferably an amorphous layer obtained by adding a trace amount of a pentavalent element to silicon.
  • the first intermediate layer 12 (low-doped n-type amorphous semiconductor layer) formed of a low-doped n-type amorphous semiconductor layer is added with a pentavalent element from the n-type amorphous semiconductor layer 13. The amount (dope amount) is small.
  • the first intermediate layer 12 is a lightly doped n-type amorphous semiconductor layer can be confirmed by the density and concentration of the dopant (pentavalent element), the electrical resistance value, and the like.
  • the electron density and the like of the dopant can be measured by a known method. Further, as will be described in detail later, the doping amount depends on the flow rate of the doping gas. Therefore, a lightly doped n-type amorphous semiconductor can be formed by relatively reducing the flow rate of the doping gas. .
  • a first intermediate layer 12 intrinsic amorphous semiconductor layer or n-type amorphous semiconductor layer
  • carrier recombination can be suppressed and output characteristics can be improved.
  • middle layer 12 it can be set as 1 nm or more and 10 nm or less, for example.
  • the n-type amorphous semiconductor layer 13 is disposed on the light incident surface side of the n-type crystal semiconductor substrate 11 via the first intermediate layer 12.
  • the semiconductor material forming the n-type amorphous semiconductor layer 13 is n-type amorphous silicon oxide.
  • the amorphous silicon oxide as a semiconductor material for forming the n-type amorphous semiconductor layer 13 is amorphous silicon doped with oxygen atoms.
  • the n-type amorphous semiconductor layer 13 is an amorphous layer obtained by adding a trace amount of a pentavalent element to such amorphous silicon oxide. That is, the n-type amorphous semiconductor layer 13 is formed of silicon doped with oxygen atoms and pentavalent elements.
  • the n-type amorphous semiconductor layer 13 disposed on the light incident surface side is formed of n-type amorphous silicon oxide, and thus has excellent output characteristics. However, the temperature dependence can be reduced.
  • the amorphous silicon oxide forming the n-type amorphous semiconductor layer 13 is preferably represented by Si 1-x O x (0.01 ⁇ x ⁇ 0.12).
  • the band gap of the amorphous silicon oxide becomes an appropriate value and the transparency becomes high.
  • output characteristics such as the conversion efficiency of the said photovoltaic device 10, and a maximum output, can be improved more.
  • the lower limit of the oxygen content (x) is more preferably 0.02, further preferably 0.03, still more preferably 0.04, and particularly preferably 0.05.
  • the upper limit of the oxygen content (x) is more preferably 0.1 and even more preferably 0.08.
  • this oxygen content rate (x) can be adjusted with the composition ratio of the raw material gas at the time of forming into a film by plasma CVD method so that it may mention later.
  • the average thickness of the n-type amorphous semiconductor layer 13 is not particularly limited, but can be, for example, 1 nm or more and 20 nm or less.
  • the second intermediate layer 15 is a layer interposed between the n-type crystal semiconductor substrate 11 and the p-type amorphous semiconductor layer 16 and functions as a passivation layer that suppresses carrier recombination.
  • the second intermediate layer 15 is formed from an intrinsic amorphous semiconductor such as silicon. Such a second intermediate layer 15 (intrinsic amorphous semiconductor layer) can suppress carrier recombination and improve output characteristics.
  • middle layer 15 it is 1 nm or more and 10 nm or less, for example.
  • the p-type amorphous semiconductor layer 16 is disposed on the side opposite to the light incident surface side of the n-type crystal semiconductor substrate 11 via the second intermediate layer 15.
  • the p-type amorphous semiconductor layer 16 is an amorphous layer formed by adding a trace amount of a trivalent element to a semiconductor.
  • the semiconductor material for forming the p-type amorphous semiconductor layer 16 may be p-type amorphous silicon, but is preferably p-type amorphous silicon oxide.
  • the amorphous silicon oxide as a semiconductor material for forming the p-type amorphous semiconductor layer 16 is amorphous silicon doped with oxygen atoms.
  • the preferable p-type amorphous semiconductor layer 16 is an amorphous layer obtained by adding a trace amount of a trivalent element to such amorphous silicon oxide. That is, the p-type amorphous semiconductor layer 16 can be formed of silicon doped with oxygen atoms and trivalent elements. In addition to the n-type amorphous semiconductor layer 13, the p-type amorphous semiconductor layer 16 on the back side is also formed of amorphous silicon oxide, so that the output characteristics of the photovoltaic device 10 depend on temperature. The property can be further reduced.
  • the amorphous silicon oxide forming the p-type amorphous semiconductor layer 16 is preferably represented by Si 1-y O y (0.01 ⁇ y ⁇ 0.12).
  • the lower limit of the oxygen content (y) is more preferably 0.02, more preferably 0.03, still more preferably 0.04, and particularly preferably 0.05.
  • the upper limit of the oxygen content (y) is more preferably 0.1 and even more preferably 0.08.
  • this oxygen content rate (y) can be adjusted with the composition ratio of the raw material gas at the time of forming into a film by plasma CVD method, for example.
  • the lower limit of the content of the trivalent element in the p-type amorphous semiconductor layer 16 is preferably 1 ⁇ 10 20 atm / cm 3 and more preferably 2.5 ⁇ 10 20 atm / cm 3 .
  • the upper limit of this content is preferably 10 ⁇ 10 20 atm / cm 3 , more preferably 5 ⁇ 10 20 atm / cm 3 .
  • boron is preferable as the trivalent element doped into the p-type amorphous semiconductor layer 16.
  • the average thickness of the p-type amorphous semiconductor layer 16 can be, for example, 1 nm or more and 20 nm or less.
  • the first transparent conductive film 14 is laminated on the outer surface side of the n-type amorphous semiconductor layer 13.
  • the second transparent conductive film 17 is laminated on the outer surface side of the p-type amorphous semiconductor layer 16.
  • the transparent conductive material constituting the first transparent conductive film 14 and the second transparent conductive film 17 include indium tin oxide (ITO), indium tungsten oxide (IWO), and indium cerium oxide (ICO). be able to. Although it does not restrict
  • Each collector electrode 18 has a plurality of bus bar electrodes formed in parallel to each other, and a plurality of finger electrodes formed orthogonal to these bus bar electrodes and in parallel with each other.
  • the bus bar electrode and the finger electrode are each linear or strip-like, and are made of a conductive material.
  • a conductive adhesive such as a silver paste or a metal wire such as a copper wire can be used.
  • These collector electrodes 18 may have a layer structure.
  • the width of each bus bar electrode is, for example, about 0.5 mm to 2 mm. Further, the width of each finger electrode is, for example, about 10 ⁇ m or more and 300 ⁇ m or less. The interval between the finger electrodes is, for example, about 0.5 mm to 4 mm.
  • the photovoltaic elements 10 are usually used by connecting a plurality of them in series. By using a plurality of photovoltaic elements 10 connected in series, the generated voltage can be increased.
  • the method for manufacturing the photovoltaic device 10 is not particularly limited.
  • the step of laminating the first intermediate layer 12 on one surface side of the n-type crystal semiconductor substrate 11 and the n-type amorphous semiconductor layer 13 are further laminated.
  • a step of further laminating the second transparent conductive film 17 and a step of laminating the collector electrode 18 on each outer surface of the first transparent conductive film and the second transparent conductive film will not be specifically limited as long as it is the order which can obtain the layer structure of the photovoltaic device 10.
  • each amorphous semiconductor layer can be performed by a known method such as chemical vapor deposition.
  • chemical vapor deposition include plasma CVD and catalytic CVD (also called hot wire CVD).
  • a mixed gas of, for example, SiH 4 and H 2 can be used as a source gas.
  • a mixed gas of SiH 4 , H 2, and PH 3 can be used as the source gas.
  • the first intermediate layer 12 formed of an n-type amorphous semiconductor with a small amount of doping is formed by reducing the flow rate (flow rate ratio) of the dopant gas as compared with the n-type amorphous semiconductor layer 13. be able to.
  • the first intermediate layer is formed by forming PH 3 as a dopant based on SiH 4 at 1000 ppm or less.
  • Layer 12 can be obtained.
  • the amount (concentration) of PH 3 introduced when forming the first intermediate layer 12 is 1 / of the amount introduced (concentration) when forming the n-type amorphous semiconductor layer 13 described later. It can be set to 100 or more and 1/5 or less.
  • the n-type amorphous semiconductor layer 13 formed from amorphous silicon oxide having a high oxygen content can be obtained by increasing the mixing ratio of CO 2 .
  • the lower limit of the ratio of the flow rate of CO 2 of SiH 4 to the flow rate (sccm) (sccm) (CO 2 / SiH 4) preferably 0.1, 0.4 is more preferable.
  • the upper limit of this ratio is preferably 2, and more preferably 1.
  • N 2 O or the like can be used instead of CO 2 for doping oxygen atoms.
  • the source gas for example, a mixed gas of SiH 4 , H 2 , B 2 H 6 and CO 2 is used as the source gas.
  • the upper limit of this ratio is preferably 2, and more preferably 1.
  • N 2 O or the like can be used instead of CO 2 for doping oxygen atoms.
  • a mixed gas of SiH 4 , H 2 and B 2 H 6 can be used as the source gas.
  • Examples of the method of laminating the first transparent conductive film 14 and the second transparent conductive film 17 include a sputtering method, a vacuum vapor deposition method, an ion plating method (reactive plasma vapor deposition method), and the like. It is preferable to use an ion plating method.
  • the sputtering method is excellent in film thickness controllability and the like, and can be performed at a lower cost than the ion plating method.
  • the ion plating method film formation in which generation of defects is suppressed can be performed.
  • the arrangement of the collecting electrode 18 can be performed by a known method.
  • a conductive adhesive is used as the material of the collector electrode 18, it can be formed by a printing method such as screen printing or gravure offset printing.
  • a metal lead is used for the collector electrode 18, it can be fixed on the first transparent conductive film 14 or the second transparent conductive film 17 with a conductive adhesive or a low melting point metal (solder or the like).
  • the collector electrode on the back side of the collector electrodes on both sides may be formed of a metal or the like laminated on the entire surface.
  • the first intermediate layer and the second intermediate layer may not be provided.
  • a transparent conductive film may be formed at least on the incident surface side, and the transparent conductive film may not be formed on the back surface side, and may be a metal film, for example.
  • a transparent conductive film by stacking a transparent conductive film on the outer surface of the p-type amorphous semiconductor layer on the back side, generation of defect levels can be suppressed and conversion efficiency can be increased.
  • Example 1 Layer structure comprising first transparent conductive film / n-type amorphous semiconductor layer / first intermediate layer / n-type crystal semiconductor substrate / second intermediate layer / p-type amorphous semiconductor layer / second transparent conductive film was made.
  • n-type crystal semiconductor substrate a single crystal silicon substrate having a fine concavo-convex structure (texture structure) having innumerable pyramid shapes on both surfaces was used. This concavo-convex structure was formed by immersing the substrate material in an etching solution containing about 3% by mass of sodium hydroxide and anisotropically etching the (100) plane of the substrate material.
  • n-type amorphous semiconductor layer SiH 4 , H 2 , PH 3 , and CO 2
  • First intermediate layer low-doped n-type amorphous semiconductor layer
  • Second intermediate layer intrinsic amorphous semiconductor layer
  • SiH 4 and H 2 p-type amorphous semiconductor layer SiH 4 , H 2 , B 2 H 6 , and CO 2
  • the flow rate of SiH 4 was 5 sccm, and the flow rate of CO 2 was 0.9 sccm.
  • the flow rate of SiH 4 was 5 sccm, and the flow rate of CO 2 was 4.1 sccm.
  • the atomic density of boron was 3.5 ⁇ 10 20 atm / cm 3 .
  • the first intermediate layer was formed as a low-doped n-type amorphous semiconductor layer by forming the PH 3 flow rate as 1/10 of the n-type amorphous semiconductor layer based on SiH 4 .
  • Each transparent conductive film was laminated by sputtering using indium oxide containing 3% by mass of tin oxide.
  • Examples 2 to 4 Comparative Example 1>
  • the photovoltaic elements of Examples 2 to 4 and Comparative Example 1 were prepared in the same manner as in Example 1 except that the flow rate of CO 2 was as shown in Table 1. Obtained.
  • Example 5 Example 3 except that a mixed gas of SiH 4 , H 2 and B 2 H 6 was used as the source gas for the p-type amorphous semiconductor layer, and the p-type amorphous semiconductor layer was formed of p-type silicon.
  • the photovoltaic device of Example 5 was obtained.
  • the atomic density of boron was 3.5 ⁇ 10 20 atm / cm 3 .
  • Example 3 in which the n-type amorphous semiconductor layer was formed of amorphous silicon oxide, the decrease in output characteristics was small even at a high temperature of 45 ° C.
  • Example 3 in which both the n-type amorphous semiconductor layer and the p-type amorphous semiconductor layer are formed of amorphous silicon oxide, the output characteristics are very low even under an environment of 70 ° C.
  • the photovoltaic device of this invention it turns out that the fall of an output characteristic can be suppressed also under high temperature.
  • the conversion efficiency and the like can be increased by forming the n-type amorphous semiconductor layer with amorphous silicon oxide having a predetermined range of oxygen content.
  • FIG. 3 shows the external quantum efficiency (EQE), the internal quantum efficiency (IQE), and the reflectance (Reflectance) of the photovoltaic devices of Comparative Example 1, Example 2, and Example 3 obtained.
  • Examples 2 and 3 in which the n-type amorphous semiconductor layer is formed of amorphous silicon oxide are different from Comparative Example 1 in which the n-type amorphous semiconductor layer is formed of silicon.
  • the external quantum efficiency and the internal quantum efficiency at 300 to 600 nm are high. This shows that n-type amorphous silicon oxide has higher transparency than n-type amorphous silicon.
  • the photovoltaic device of the present invention has good output characteristics, has low temperature dependency, can maintain good characteristics even at high temperatures, and can be suitably used for photovoltaic power generation.

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Abstract

Provided is a photovoltaic element of which the output characteristics are less temperature dependent and which is capable of maintaining fine characteristics even at a high temperature. A photovoltaic element (10) according to the present invention is provided with: an n-type crystal semiconductor substrate (11); an n-type amorphous semiconductor layer (13) stacked on the light incident surface side of the n-type crystal semiconductor substrate; and a p-type amorphous semiconductor layer (16) stacked on the surface side opposite to the light incident surface side of the n-type crystal semiconductor substrate, and is characterized in that a semiconductor material forming the n-type amorphous semiconductor layer (13) is an n-type amorphous silicon oxide. The amorphous silicon oxide is preferably represented by Si1-xOx (0.01≤x≤0.12). A semiconductor material forming the p-type amorphous semiconductor layer (16) is preferably a p-type amorphous silicon oxide.

Description

光発電素子Photovoltaic element
　本発明は、光発電素子に関する。 The present invention relates to a photovoltaic device.
　ＣＯ２等の温室効果ガスを発生しないクリーンな発電手段として、あるいは原子力発電に代わる操業安全性の高い発電手段として、太陽電池が近年特に注目されている。太陽電池の一つとして、発電効率の高いヘテロ接合型の太陽電池がある。 In recent years, solar cells have attracted particular attention as clean power generation means that does not generate CO 2 or other greenhouse gases, or as power generation means with high operational safety that can replace nuclear power generation. One type of solar cell is a heterojunction solar cell with high power generation efficiency.
　ヘテロ接合型の太陽電池（光発電素子）は、例えばｎ型結晶半導体基板の一方の面側に第１の真性非晶質系半導体層及びｐ型非晶質系半導体層がこの順に積層され、上記ｎ型結晶半導体基板の他方の面側に第２の真性非晶質系半導体層及びｎ型非晶質系半導体層がこの順に積層された構造を有する。このようなヘテロ接合型の光発電素子において、出力特性をより向上させるために、ｎ型非晶質系半導体層側を光入射面とする光発電素子が提案されている（特開２０１４－２１６３３４号公報及び特開２０１４－２１６３３５号公報参照）。 In a heterojunction solar cell (photovoltaic element), for example, a first intrinsic amorphous semiconductor layer and a p-type amorphous semiconductor layer are stacked in this order on one surface side of an n-type crystal semiconductor substrate, A second intrinsic amorphous semiconductor layer and an n-type amorphous semiconductor layer are stacked in this order on the other surface side of the n-type crystal semiconductor substrate. In such a heterojunction type photovoltaic device, in order to further improve output characteristics, a photovoltaic device having an n-type amorphous semiconductor layer side as a light incident surface has been proposed (Japanese Patent Application Laid-Open No. 2014-216334). And Japanese Unexamined Patent Application Publication No. 2014-216335).
　一方、太陽光発電における生産性等を鑑みると、大規模な発電施設であるメガソーラー等は、日照量の多い地域へ建設することが望ましい。そのため、将来的には、日照量の多い砂漠地帯や赤道付近等へのメガソーラーの建設が進むことが予想される。しかし、光発電素子の変換効率は温度依存性を有し、高温下では発電効率が低下する。従って、砂漠地帯等への建設を考慮し、温度依存性が小さく、高温下でも発電効率が低下しにくい光発電素子の開発が期待されている。 On the other hand, considering the productivity of solar power generation, it is desirable to construct mega-solar power generation facilities in areas with a lot of sunlight. Therefore, in the future, it is expected that mega solar construction will proceed in desert areas with a lot of sunlight and in the vicinity of the equator. However, the conversion efficiency of the photovoltaic device has temperature dependence, and the power generation efficiency decreases at high temperatures. Therefore, in consideration of construction in a desert area, etc., development of a photovoltaic device that is less dependent on temperature and is unlikely to decrease power generation efficiency even at high temperatures is expected.
特開２０１４－２１６３３４号公報JP 2014-216334 A 特開２０１４－２１６３３５号公報JP 2014-216335 A
　本発明は、以上のような事情に基づいてなされたものであり、その目的は、出力特性の温度依存性が小さく、高温下でも良好な特性を保つことができる光発電素子を提供することである。 The present invention has been made based on the above circumstances, and an object of the present invention is to provide a photovoltaic device that has low temperature dependence of output characteristics and can maintain good characteristics even at high temperatures. is there.
　上記課題を解決するためになされた本発明は、ｎ型結晶半導体基板、このｎ型結晶半導体基板の光入射面側に積層されるｎ型非晶質系半導体層、及び上記ｎ型結晶半導体基板の光入射面側とは反対面側に積層されるｐ型非晶質系半導体層を備える光発電素子であって、上記ｎ型非晶質系半導体層を形成する半導体材料が、ｎ型の非晶質系酸化ケイ素であることを特徴とする。 The present invention, which has been made to solve the above problems, includes an n-type crystal semiconductor substrate, an n-type amorphous semiconductor layer stacked on the light incident surface side of the n-type crystal semiconductor substrate, and the n-type crystal semiconductor substrate. A photovoltaic device comprising a p-type amorphous semiconductor layer laminated on the side opposite to the light incident surface side, wherein the semiconductor material forming the n-type amorphous semiconductor layer is an n-type It is characterized by being amorphous silicon oxide.
　当該光発電素子によれば、ｎ型非晶質半導体層が非晶質系酸化ケイ素により形成されていることで、出力特性の温度依存性を低減することができる。 According to the photovoltaic device, the temperature dependence of the output characteristics can be reduced because the n-type amorphous semiconductor layer is formed of amorphous silicon oxide.
　上記非晶質系酸化ケイ素が、Ｓｉ１－ｘＯｘ（０．０１≦ｘ≦０．１２）で表されることが好ましい。上記ｎ型非晶質系半導体層がこのような酸素含有率の非晶質系酸化ケイ素により形成されていることで、変換効率等の出力特性を高めることができる。 The amorphous silicon oxide is preferably represented by Si 1-x O x (0.01 ≦ x ≦ 0.12). Since the n-type amorphous semiconductor layer is formed of amorphous silicon oxide having such an oxygen content, output characteristics such as conversion efficiency can be improved.
　上記ｐ型非晶質系半導体層を形成する半導体材料が、ｐ型の非晶質系酸化ケイ素であることが好ましい。ｎ型非晶質系半導体層に加えて、裏面側のｐ型非晶質系半導体層も非晶質系酸化ケイ素により形成されることで、当該光発電素子の出力特性の温度依存性をより低減することなどができる。 The semiconductor material forming the p-type amorphous semiconductor layer is preferably p-type amorphous silicon oxide. In addition to the n-type amorphous semiconductor layer, the p-type amorphous semiconductor layer on the back side is also formed of amorphous silicon oxide, thereby making the temperature dependence of the output characteristics of the photovoltaic device more It can be reduced.
　上記ｎ型結晶半導体基板とｎ型非晶質系半導体層との間に介在する第１中間層をさらに備え、上記第１中間層が、真性非晶質系半導体、又はｎ型非晶質系半導体から形成されていることが好ましい。さらに、上記第１中間層が、上記ｎ型非晶質系半導体層よりもドープ量が少ないｎ型非晶質系半導体層であることが好ましい。このような第１中間層を設けることにより、キャリアの再結合が抑制され、出力特性をより高めることができる。 A first intermediate layer interposed between the n-type crystal semiconductor substrate and the n-type amorphous semiconductor layer, wherein the first intermediate layer is an intrinsic amorphous semiconductor or an n-type amorphous semiconductor layer; It is preferably formed from a semiconductor. Furthermore, it is preferable that the first intermediate layer is an n-type amorphous semiconductor layer having a smaller doping amount than the n-type amorphous semiconductor layer. By providing such a first intermediate layer, recombination of carriers is suppressed and output characteristics can be further improved.
　上記ｎ型結晶半導体基板とｐ型非晶質系半導体層との間に介在する第２中間層をさらに備え、上記第２中間層が、真性非晶質系半導体から形成されていることが好ましい。このような第２中間層を設けることによっても、キャリアの再結合が抑制され、出力特性をより高めることができる。 Preferably, a second intermediate layer interposed between the n-type crystal semiconductor substrate and the p-type amorphous semiconductor layer is further provided, and the second intermediate layer is formed of an intrinsic amorphous semiconductor. . Providing such a second intermediate layer also suppresses carrier recombination and can further enhance output characteristics.
　ここで、非晶質系半導体における「非晶質系」とは、完全な非晶質体のみならず、非晶質中に微結晶が存在するものも含む意味である。但し、本明細書中において、微結晶を含む非晶質系半導体を単に「非晶質半導体」等と言うこともある。真性非晶質系半導体層における「真性」とは、不純物が意図的にドープされていないことをいい、原料に本来含まれる不純物や製造過程において非意図的に混入した不純物が存在するものも含む意味である。また、半導体材料としての「非晶質系酸化ケイ素」とは、酸素原子とケイ素原子とで形成される半導体特性を有する非晶質系の化合物をいい、酸素原子とケイ素原子との比が特定の比のものに限定する意味では無い。 Here, “amorphous” in an amorphous semiconductor means not only a completely amorphous body but also one having microcrystals in the amorphous body. However, in this specification, an amorphous semiconductor including a microcrystal may be simply referred to as “amorphous semiconductor” or the like. “Intrinsic” in an intrinsic amorphous semiconductor layer means that impurities are not intentionally doped, and includes impurities that are originally contained in raw materials or impurities that are unintentionally mixed in the manufacturing process. Meaning. “Amorphous silicon oxide” as a semiconductor material refers to an amorphous compound having semiconductor characteristics formed by oxygen atoms and silicon atoms, and the ratio of oxygen atoms to silicon atoms is specified. It is not meant to be limited to those of the ratio.
　本発明の光発電素子によれば、出力特性の温度依存性が小さく、高温下でも良好な特性を保つことができる光発電素子を提供することができる。 According to the photovoltaic device of the present invention, it is possible to provide a photovoltaic device that has low temperature dependence of output characteristics and can maintain good characteristics even at high temperatures.
図１は、本発明の一実施形態に係る光発電素子の模式的断面図である。FIG. 1 is a schematic cross-sectional view of a photovoltaic device according to an embodiment of the present invention. 実施例における光発電素子の変換効率を示すグラフである。It is a graph which shows the conversion efficiency of the photovoltaic device in an Example. 実施例における光る発電素子の外部量子効率、内部量子効率及び反射率を示すグラフである。It is a graph which shows the external quantum efficiency, internal quantum efficiency, and reflectance of the power generation element which shines in an Example.
　以下、適宜図面を参照にしつつ、本発明の一実施形態に係る光発電素子について詳説する。 Hereinafter, a photovoltaic device according to an embodiment of the present invention will be described in detail with reference to the drawings as appropriate.
　図１の光発電素子１０は、ｎ型結晶半導体基板１１と、ｎ型結晶半導体基板１１の一方の面側（図１における上側）に以下の順で積層される第１中間層１２、ｎ型非晶質系半導体層１３及び第１透明導電膜１４と、ｎ型結晶半導体基板１１の他方の面側（図１における下側）に以下の順で積層される第２中間層１５、ｐ型非晶質系半導体層１６及び第２透明導電膜１７とを備える。さらに、光発電素子１０は、第１透明導電膜１４の外面及び第２透明導電膜１７の外面に配設される複数の線状の集電極１８を備える。なお「外面」とは、ｎ型結晶半導体基板１１を中心とし、ｎ型結晶半導体基板１１と反対側の面をいう。また、「内面」とは、ｎ型結晶半導体基板１１側の面をいう。 The photovoltaic element 10 in FIG. 1 includes an n-type crystal semiconductor substrate 11, a first intermediate layer 12 stacked in the following order on one surface side (upper side in FIG. 1) of the n-type crystal semiconductor substrate 11, and an n-type crystal. A second intermediate layer 15 laminated on the amorphous semiconductor layer 13 and the first transparent conductive film 14 on the other surface side (lower side in FIG. 1) of the n-type crystal semiconductor substrate 11 in the following order, p-type An amorphous semiconductor layer 16 and a second transparent conductive film 17 are provided. Furthermore, the photovoltaic device 10 includes a plurality of linear collector electrodes 18 disposed on the outer surface of the first transparent conductive film 14 and the outer surface of the second transparent conductive film 17. The “outer surface” refers to the surface opposite to the n-type crystal semiconductor substrate 11 with the n-type crystal semiconductor substrate 11 as the center. The “inner surface” refers to a surface on the n-type crystal semiconductor substrate 11 side.
　当該光発電素子１０においては、図１における上側、すなわち第１透明導電膜１４側が光入射面となる。なお、当該光発電素子１０においては、少なくとも第１透明導電膜１４側を光入射面とするものであり、第２透明導電膜１７側からも光の入射可能に設計されていてもよい。すなわち、当該光発電素子１０は両面から光が入射されるようにすることもできる。 In the photovoltaic element 10, the upper side in FIG. 1, that is, the first transparent conductive film 14 side is the light incident surface. Note that the photovoltaic element 10 has at least the first transparent conductive film 14 side as a light incident surface, and may be designed so that light can be incident also from the second transparent conductive film 17 side. That is, the photovoltaic device 10 can be configured such that light is incident from both sides.
　ｎ型結晶半導体基板１１は、ｎ型結晶半導体から形成されている。ｎ型の基板を用いることで、ｐ型の基板に特有の光劣化現象を回避することができる。ｎ型結晶半導体とは、通常、シリコン等の半導体に微量の５価の元素が添加されてなる結晶体である。ｎ型結晶半導体基板１１を構成する結晶半導体としては、シリコン（Ｓｉ）の他、ＳｉＣ、ＳｉＧｅ等を挙げることができるが、生産性等の点からシリコンが好ましい。ｎ型結晶半導体基板１１は、単結晶体であってもよいし、多結晶体であってもよい。 The n-type crystal semiconductor substrate 11 is formed from an n-type crystal semiconductor. By using the n-type substrate, it is possible to avoid the light deterioration phenomenon peculiar to the p-type substrate. An n-type crystal semiconductor is usually a crystal formed by adding a trace amount of a pentavalent element to a semiconductor such as silicon. Examples of the crystal semiconductor constituting the n-type crystal semiconductor substrate 11 include SiC and SiGe in addition to silicon (Si), but silicon is preferable from the viewpoint of productivity. The n-type crystal semiconductor substrate 11 may be a single crystal or a polycrystal.
　ｎ型結晶半導体基板１１の両面には、ピラミッド状の微細な凹凸構造が形成されている。このような構造により、光の閉じ込め機能を高めることができる。この凹凸構造（テクスチャー構造）の高さや大きさは不揃いであってよく、隣り合う凹凸の一部が重なっていてもよい。また、頂点や谷部が丸みを帯びていてもよい。この凹凸の高さとしては、数μｍ以上数十μｍ以下程度である。このような凹凸構造は、例えば、約１～５質量％の水酸化ナトリウムを含むエッチング液に基板材料を浸漬し、基板材料の（１００）面を異方性エッチングすることにより得ることができる。 On both surfaces of the n-type crystal semiconductor substrate 11, a pyramidal fine concavo-convex structure is formed. With such a structure, the light confinement function can be enhanced. The height and size of the uneven structure (texture structure) may be uneven, and adjacent uneven parts may overlap. Moreover, a vertex and a trough part may be roundish. The height of the unevenness is about several μm to several tens of μm. Such a concavo-convex structure can be obtained, for example, by immersing the substrate material in an etching solution containing about 1 to 5% by mass of sodium hydroxide and anisotropically etching the (100) plane of the substrate material.
　ｎ型結晶半導体基板１１の平均厚さとしては特に制限されない。この平均厚さの上限としては、例えば３００μｍであり、２００μｍが好ましい。また、この下限としては、例えば５０μｍとすることができる。このようにｎ型結晶半導体基板１１を薄型化することにより、光発電素子１０自体の小型化、低コスト化等を図ることができる。 The average thickness of the n-type crystal semiconductor substrate 11 is not particularly limited. The upper limit of the average thickness is, for example, 300 μm, and preferably 200 μm. Moreover, as this minimum, it can be set as 50 micrometers, for example. By reducing the thickness of the n-type crystal semiconductor substrate 11 in this way, the photovoltaic device 10 itself can be reduced in size and cost.
　第１中間層１２は、ｎ型結晶半導体基板１１とｎ型非晶質系半導体層１３との間に介在する層であり、キャリアの再結合を抑制するパッシベーション層として機能する。第１中間層１２は、真性非晶質系半導体、又はｎ型非晶質系半導体から形成されている。第１中間層１２としては、ｎ型非晶質系半導体層１３よりもドープ量が少ない低ドープｎ型非晶質系半導体層であることが好ましい。このような低ドープｎ型非晶質系半導体層を第１中間層１２として設けることによって、光発電素子１０の出力特性をより高めることなどができる。 The first intermediate layer 12 is a layer interposed between the n-type crystal semiconductor substrate 11 and the n-type amorphous semiconductor layer 13 and functions as a passivation layer that suppresses carrier recombination. The first intermediate layer 12 is formed from an intrinsic amorphous semiconductor or an n-type amorphous semiconductor. The first intermediate layer 12 is preferably a lightly doped n-type amorphous semiconductor layer having a smaller doping amount than the n-type amorphous semiconductor layer 13. By providing such a low-doped n-type amorphous semiconductor layer as the first intermediate layer 12, the output characteristics of the photovoltaic element 10 can be further improved.
　第１中間層１２が真性非晶質系半導体から形成されている場合、この真性非晶質系半導体としては、通常、シリコンが好ましい。第１中間層１２がｎ型非晶質系半導体から形成されている場合、第１中間層１２は、シリコンに微量の５価の元素が添加されてなる非晶質層であることが好ましい。低ドープのｎ型非晶質系半導体から形成される第１中間層１２（低ドープｎ型非晶質系半導体層）は、ｎ型非晶質系半導体層１３より、５価の元素の添加量（ドープ量）が少ない。第１中間層１２が低ドープｎ型非晶質系半導体層であることは、ドーパント（５価の元素）の密度や濃度、電気抵抗値等によって確認することができる。ドーパントの電子密度等は公知の方法により測定することができる。また、ドープ量は、後に詳述するように、ドーピングガスの流量に依存するため、ドーピングガスの流量を相対的に少なくすることで、低ドープｎ型非晶質系半導体を形成することができる。このような第１中間層１２（真性非晶質系半導体層又はｎ型非晶質系半導体層）により、キャリアの再結合を抑制し、出力特性を高めることができる。なお、第１中間層１２の平均厚さとしては、例えば１ｎｍ以上１０ｎｍ以下とすることができる。 When the first intermediate layer 12 is formed of an intrinsic amorphous semiconductor, silicon is usually preferable as the intrinsic amorphous semiconductor. When the first intermediate layer 12 is formed of an n-type amorphous semiconductor, the first intermediate layer 12 is preferably an amorphous layer obtained by adding a trace amount of a pentavalent element to silicon. The first intermediate layer 12 (low-doped n-type amorphous semiconductor layer) formed of a low-doped n-type amorphous semiconductor layer is added with a pentavalent element from the n-type amorphous semiconductor layer 13. The amount (dope amount) is small. That the first intermediate layer 12 is a lightly doped n-type amorphous semiconductor layer can be confirmed by the density and concentration of the dopant (pentavalent element), the electrical resistance value, and the like. The electron density and the like of the dopant can be measured by a known method. Further, as will be described in detail later, the doping amount depends on the flow rate of the doping gas. Therefore, a lightly doped n-type amorphous semiconductor can be formed by relatively reducing the flow rate of the doping gas. . With such a first intermediate layer 12 (intrinsic amorphous semiconductor layer or n-type amorphous semiconductor layer), carrier recombination can be suppressed and output characteristics can be improved. In addition, as average thickness of the 1st intermediate | middle layer 12, it can be set as 1 nm or more and 10 nm or less, for example.
　ｎ型非晶質系半導体層１３は、ｎ型結晶半導体基板１１の光入射面側に、第１中間層１２を介して配設されている。このｎ型非晶質系半導体層１３を形成する半導体材料は、ｎ型の非晶質系酸化ケイ素である。このｎ型非晶質系半導体層１３を形成する半導体材料としての非晶質系酸化ケイ素は、酸素原子がドープされた非晶質系ケイ素であると換言することができる。ｎ型非晶質系半導体層１３は、このような非晶質系酸化ケイ素にさらに微量の５価の元素が添加されてなる非晶質層である。すなわち、ｎ型非晶質系半導体層１３は、酸素原子と５価の元素とがドープされたケイ素により形成されている。当該光発電素子１０によれば、光入射面側に配設されるｎ型非晶質系半導体層１３がｎ型の非晶質系酸化ケイ素により形成されることで、良好な出力特性を有しつつ、その温度依存性を低減することができる。 The n-type amorphous semiconductor layer 13 is disposed on the light incident surface side of the n-type crystal semiconductor substrate 11 via the first intermediate layer 12. The semiconductor material forming the n-type amorphous semiconductor layer 13 is n-type amorphous silicon oxide. In other words, the amorphous silicon oxide as a semiconductor material for forming the n-type amorphous semiconductor layer 13 is amorphous silicon doped with oxygen atoms. The n-type amorphous semiconductor layer 13 is an amorphous layer obtained by adding a trace amount of a pentavalent element to such amorphous silicon oxide. That is, the n-type amorphous semiconductor layer 13 is formed of silicon doped with oxygen atoms and pentavalent elements. According to the photovoltaic device 10, the n-type amorphous semiconductor layer 13 disposed on the light incident surface side is formed of n-type amorphous silicon oxide, and thus has excellent output characteristics. However, the temperature dependence can be reduced.
　このｎ型非晶質系半導体層１３を形成する非晶質系酸化ケイ素は、Ｓｉ１－ｘＯｘ（０．０１≦ｘ≦０．１２）で表されることが好ましい。ｎ型非晶質系半導体層１３をこのような酸素含有率の非晶質系酸化ケイ素により形成することにより、非晶質系酸化ケイ素のバンドギャップが適当な値となり、透明性が高くなる。これにより、当該光発電素子１０の変換効率、最大出力等の出力特性をより高めることができる。上記特性をより高めるためには、この酸素含有率（ｘ）の下限としては、０．０２がより好ましく、０．０３がさらに好ましく、０．０４がよりさらに好ましく、０．０５が特に好ましい。一方、この酸素含有率（ｘ）の上限としては、０．１がより好ましく、０．０８がさらに好ましい。なお、この酸素含有率（ｘ）は、後述するように、例えばプラズマＣＶＤ法により製膜する際の原料ガスの組成比などにより調整することができる。 The amorphous silicon oxide forming the n-type amorphous semiconductor layer 13 is preferably represented by Si 1-x O x (0.01 ≦ x ≦ 0.12). By forming the n-type amorphous semiconductor layer 13 with amorphous silicon oxide having such an oxygen content, the band gap of the amorphous silicon oxide becomes an appropriate value and the transparency becomes high. Thereby, output characteristics, such as the conversion efficiency of the said photovoltaic device 10, and a maximum output, can be improved more. In order to further enhance the above characteristics, the lower limit of the oxygen content (x) is more preferably 0.02, further preferably 0.03, still more preferably 0.04, and particularly preferably 0.05. On the other hand, the upper limit of the oxygen content (x) is more preferably 0.1 and even more preferably 0.08. In addition, this oxygen content rate (x) can be adjusted with the composition ratio of the raw material gas at the time of forming into a film by plasma CVD method so that it may mention later.
　ｎ型非晶質系半導体層１３の平均厚さとしては特に制限されないが、例えば１ｎｍ以上２０ｎｍ以下とすることができる。 The average thickness of the n-type amorphous semiconductor layer 13 is not particularly limited, but can be, for example, 1 nm or more and 20 nm or less.
　第２中間層１５は、ｎ型結晶半導体基板１１とｐ型非晶質系半導体層１６との間に介在する層であり、キャリアの再結合を抑制するパッシベーション層として機能する。第２中間層１５は、シリコン等の真性非晶質系半導体から形成されている。このような第２中間層１５（真性非晶質系半導体層）により、キャリアの再結合を抑制し、出力特性を高めることができる。なお、第２中間層１５の平均厚さとしては、例えば１ｎｍ以上１０ｎｍ以下とすることができる。 The second intermediate layer 15 is a layer interposed between the n-type crystal semiconductor substrate 11 and the p-type amorphous semiconductor layer 16 and functions as a passivation layer that suppresses carrier recombination. The second intermediate layer 15 is formed from an intrinsic amorphous semiconductor such as silicon. Such a second intermediate layer 15 (intrinsic amorphous semiconductor layer) can suppress carrier recombination and improve output characteristics. In addition, as average thickness of the 2nd intermediate | middle layer 15, it is 1 nm or more and 10 nm or less, for example.
　ｐ型非晶質系半導体層１６は、ｎ型結晶半導体基板１１の光入射面側とは反対面側に、第２中間層１５を介して配設されている。ｐ型非晶質系半導体層１６は、半導体に微量の３価の元素が添加されてなる非晶質層である。ｐ型非晶質系半導体層１６を形成する半導体材料としては、ｐ型の非晶質系シリコン等であってもよいが、ｐ型の非晶質系酸化ケイ素であることが好ましい。このｐ型非晶質系半導体層１６を形成する半導体材料としての非晶質系酸化ケイ素は、酸素原子がドープされた非晶質系ケイ素であると換言することができる。この好ましいｐ型非晶質系半導体層１６は、このような非晶質系酸化ケイ素にさらに微量の３価の元素が添加されてなる非晶質層である。すなわち、ｐ型非晶質系半導体層１６は、酸素原子と３価の元素とがドープされたケイ素により形成することができる。ｎ型非晶質系半導体層１３に加えて、裏面側のｐ型非晶質系半導体層１６も非晶質系酸化ケイ素により形成されることで、当該光発電素子１０の出力特性の温度依存性をより低減することなどができる。 The p-type amorphous semiconductor layer 16 is disposed on the side opposite to the light incident surface side of the n-type crystal semiconductor substrate 11 via the second intermediate layer 15. The p-type amorphous semiconductor layer 16 is an amorphous layer formed by adding a trace amount of a trivalent element to a semiconductor. The semiconductor material for forming the p-type amorphous semiconductor layer 16 may be p-type amorphous silicon, but is preferably p-type amorphous silicon oxide. In other words, the amorphous silicon oxide as a semiconductor material for forming the p-type amorphous semiconductor layer 16 is amorphous silicon doped with oxygen atoms. The preferable p-type amorphous semiconductor layer 16 is an amorphous layer obtained by adding a trace amount of a trivalent element to such amorphous silicon oxide. That is, the p-type amorphous semiconductor layer 16 can be formed of silicon doped with oxygen atoms and trivalent elements. In addition to the n-type amorphous semiconductor layer 13, the p-type amorphous semiconductor layer 16 on the back side is also formed of amorphous silicon oxide, so that the output characteristics of the photovoltaic device 10 depend on temperature. The property can be further reduced.
　このｐ型非晶質系半導体層１６を形成する非晶質系酸化ケイ素は、Ｓｉ１－ｙＯｙ（０．０１≦ｙ≦０．１２）で表されることが好ましい。ｐ型非晶質系半導体層１６をこのような酸素含有率の非晶質系酸化ケイ素により形成することにより、高温下での特性低下をより低減させることができる。上記特性をより高めるためには、この酸素含有率（ｙ）の下限としては、０．０２がより好ましく、０．０３がさらに好ましく、０．０４がよりさらに好ましく、０．０５が特に好ましい。一方、この酸素含有率（ｙ）の上限としては、０．１がより好ましく、０．０８がさらに好ましい。なお、この酸素含有率（ｙ）は、例えばプラズマＣＶＤ法により製膜する際の原料ガスの組成比などにより調整することができる。 The amorphous silicon oxide forming the p-type amorphous semiconductor layer 16 is preferably represented by Si 1-y O y (0.01 ≦ y ≦ 0.12). By forming the p-type amorphous semiconductor layer 16 with amorphous silicon oxide having such an oxygen content, deterioration in characteristics at high temperatures can be further reduced. In order to further enhance the above characteristics, the lower limit of the oxygen content (y) is more preferably 0.02, more preferably 0.03, still more preferably 0.04, and particularly preferably 0.05. On the other hand, the upper limit of the oxygen content (y) is more preferably 0.1 and even more preferably 0.08. In addition, this oxygen content rate (y) can be adjusted with the composition ratio of the raw material gas at the time of forming into a film by plasma CVD method, for example.
　ｐ型非晶質系半導体層１６における３価の元素の含有量の下限としては、１×１０２０ａｔｍ／ｃｍ３が好ましく、２．５×１０２０ａｔｍ／ｃｍ３がより好ましい。一方、この含有量の上限としては、１０×１０２０ａｔｍ／ｃｍ３が好ましく、５×１０２０ａｔｍ／ｃｍ３がより好ましい。また、ｐ型非晶質系半導体層１６にドープされる３価の元素としては、ホウ素が好ましい。 The lower limit of the content of the trivalent element in the p-type amorphous semiconductor layer 16 is preferably 1 × 10 20 atm / cm 3 and more preferably 2.5 × 10 20 atm / cm 3 . On the other hand, the upper limit of this content is preferably 10 × 10 20 atm / cm 3 , more preferably 5 × 10 20 atm / cm 3 . Further, as the trivalent element doped into the p-type amorphous semiconductor layer 16, boron is preferable.
　ｐ型非晶質系半導体層１６の平均厚さとしては、例えば１ｎｍ以上２０ｎｍ以下とすることができる。 The average thickness of the p-type amorphous semiconductor layer 16 can be, for example, 1 nm or more and 20 nm or less.
　第１透明導電膜１４は、ｎ型非晶質系半導体層１３の外面側に積層されている。また、第２透明導電膜１７は、ｐ型非晶質系半導体層１６の外面側に積層されている。第１透明導電膜１４及び第２透明導電膜１７を構成する透明導電性材料としては、例えばインジウムスズ酸化物（ＩＴＯ）、インジウムタングステン酸化物（ＩＷＯ）、インジウムセリウム酸化物（ＩＣＯ）等を挙げることができる。第１透明導電膜１４及び第２透明導電膜１７の平均膜厚としては特に制限されないが、例えばそれぞれ４０ｎｍ以上２００ｎｍ以下とすることができる。 The first transparent conductive film 14 is laminated on the outer surface side of the n-type amorphous semiconductor layer 13. The second transparent conductive film 17 is laminated on the outer surface side of the p-type amorphous semiconductor layer 16. Examples of the transparent conductive material constituting the first transparent conductive film 14 and the second transparent conductive film 17 include indium tin oxide (ITO), indium tungsten oxide (IWO), and indium cerium oxide (ICO). be able to. Although it does not restrict | limit especially as an average film thickness of the 1st transparent conductive film 14 and the 2nd transparent conductive film 17, For example, it is 40 nm or more and 200 nm or less, respectively.
　各集電極１８は、互いに平行に形成される複数のバスバー電極、及びこれらのバスバー電極に直交し、互いに平行に形成される複数のフィンガー電極を有する。 Each collector electrode 18 has a plurality of bus bar electrodes formed in parallel to each other, and a plurality of finger electrodes formed orthogonal to these bus bar electrodes and in parallel with each other.
　バスバー電極及びフィンガー電極は、それぞれ線状又は帯状であり、導電性材料から形成されている。この導電性材料としては、銀ペースト等の導電性接着剤や、銅線等の金属線を用いることができる。これらの集電極１８は、層構造を有していてもよい。各バスバー電極の幅としては、例えば０．５ｍｍ以上２ｍｍ以下程度である。また、各フィンガー電極の幅としては、例えば１０μｍ以上３００μｍ以下程度である。各フィンガー電極間の間隔としては、例えば０．５ｍｍ以上４ｍｍ以下程度である。 The bus bar electrode and the finger electrode are each linear or strip-like, and are made of a conductive material. As the conductive material, a conductive adhesive such as a silver paste or a metal wire such as a copper wire can be used. These collector electrodes 18 may have a layer structure. The width of each bus bar electrode is, for example, about 0.5 mm to 2 mm. Further, the width of each finger electrode is, for example, about 10 μm or more and 300 μm or less. The interval between the finger electrodes is, for example, about 0.5 mm to 4 mm.
　当該光発電素子１０は、通常、複数を直列に接続して使用される。複数の光発電素子１０を直列接続して使用することで、発電電圧を高めることができる。 The photovoltaic elements 10 are usually used by connecting a plurality of them in series. By using a plurality of photovoltaic elements 10 connected in series, the generated voltage can be increased.
　光発電素子１０の製造方法は、特に限定されないが、例えばｎ型結晶半導体基板１１の一方の面側に第１中間層１２を積層する工程、さらにｎ型非晶質系半導体層１３を積層する工程、さらに第１透明導電膜１４を積層する工程、ｎ型結晶半導体基板１１の他方の面側に第２中間層１５を積層する工程、さらにｐ型非晶質系半導体層１６を積層する工程、さらに第２透明導電膜１７を積層する工程、並びに第１透明導電膜及び第２透明導電膜の各外面に集電極１８を積層する工程を備える。なお、各工程の順は、光発電素子１０の層構造を得ることができる順である限り特に限定されるものではない。 The method for manufacturing the photovoltaic device 10 is not particularly limited. For example, the step of laminating the first intermediate layer 12 on one surface side of the n-type crystal semiconductor substrate 11 and the n-type amorphous semiconductor layer 13 are further laminated. A step, a step of further laminating the first transparent conductive film 14, a step of laminating the second intermediate layer 15 on the other surface side of the n-type crystal semiconductor substrate 11, and a step of laminating the p-type amorphous semiconductor layer 16 And a step of further laminating the second transparent conductive film 17 and a step of laminating the collector electrode 18 on each outer surface of the first transparent conductive film and the second transparent conductive film. In addition, the order of each process will not be specifically limited as long as it is the order which can obtain the layer structure of the photovoltaic device 10. FIG.
　各非晶質系半導体層の積層は、化学気相成長法などの公知の方法により行うことができる。化学気相成長法としては、例えばプラズマＣＶＤ法や触媒ＣＶＤ法（別名ホットワイヤＣＶＤ法）等が挙げられる。 The lamination of each amorphous semiconductor layer can be performed by a known method such as chemical vapor deposition. Examples of chemical vapor deposition include plasma CVD and catalytic CVD (also called hot wire CVD).
　プラズマＣＶＤ法による場合、真性非晶質系半導体層としての第１中間層１２及び第２中間層１５の積層においては、原料ガスとしては例えばＳｉＨ４とＨ２との混合ガスを用いることができる。また、第１中間層１２をｎ型非晶質系半導体から形成する場合は、原料ガスとしては、例えばＳｉＨ４とＨ２とＰＨ３との混合ガスを用いることができる。なお、ドープ量の少ないｎ型非晶質系半導体から形成される第１中間層１２は、ｎ型非晶質系半導体層１３よりもドーパントガスの流量（流量比）を少なくすることにより形成することができる。例えば、ＳｉＨ４とＰＨ３とを含む混合ガスを用いたプラズマＣＶＤ法により形成する場合、ＳｉＨ４を基準としたドーパントとしてのＰＨ３の導入量を１０００ｐｐｍ以下として製膜することにより、第１中間層１２を得ることができる。また、この第１中間層１２を製膜する際の上記ＰＨ３の導入量（濃度）は、後述するｎ型非晶質系半導体層１３を製膜する際の導入量（濃度）の１／１００以上１／５以下とすることができる。 In the case of the plasma CVD method, in the lamination of the first intermediate layer 12 and the second intermediate layer 15 as intrinsic amorphous semiconductor layers, a mixed gas of, for example, SiH 4 and H 2 can be used as a source gas. . Further, when the first intermediate layer 12 is formed of an n-type amorphous semiconductor, for example, a mixed gas of SiH 4 , H 2, and PH 3 can be used as the source gas. The first intermediate layer 12 formed of an n-type amorphous semiconductor with a small amount of doping is formed by reducing the flow rate (flow rate ratio) of the dopant gas as compared with the n-type amorphous semiconductor layer 13. be able to. For example, in the case of forming by a plasma CVD method using a mixed gas containing SiH 4 and PH 3 , the first intermediate layer is formed by forming PH 3 as a dopant based on SiH 4 at 1000 ppm or less. Layer 12 can be obtained. Further, the amount (concentration) of PH 3 introduced when forming the first intermediate layer 12 is 1 / of the amount introduced (concentration) when forming the n-type amorphous semiconductor layer 13 described later. It can be set to 100 or more and 1/5 or less.
　ｎ型非晶質系半導体層１３（ｎ型非晶質系酸化ケイ素層）の積層においては、原料ガスとしては例えばＳｉＨ４、Ｈ２、ＰＨ３及びＣＯ２の混合ガスを用いることができる。なお、この場合、ＣＯ２の混合比率を高めることで、酸素含有率の高い非晶質系酸化ケイ素から形成されるｎ型非晶質系半導体層１３を得ることができる。このｎ型非晶質系酸化ケイ素層の形成の際、ＳｉＨ４の流量（ｓｃｃｍ）に対するＣＯ２の流量（ｓｃｃｍ）の比（ＣＯ２／ＳｉＨ４）の下限としては、０．１が好ましく、０．４がより好ましい。一方、この比の上限としては、２が好ましく、１がより好ましい。また、酸素原子をドープするためのＣＯ２の代わりに、Ｎ２Ｏ等を用いることもできる。 In the lamination of the n-type amorphous semiconductor layer 13 (n-type amorphous silicon oxide layer), for example, a mixed gas of SiH 4 , H 2 , PH 3 and CO 2 can be used as a source gas. In this case, the n-type amorphous semiconductor layer 13 formed from amorphous silicon oxide having a high oxygen content can be obtained by increasing the mixing ratio of CO 2 . During formation of the n-type amorphous-based silicon oxide layer, the lower limit of the ratio of the flow rate of CO 2 of SiH 4 to the flow rate (sccm) (sccm) (CO 2 / SiH 4), preferably 0.1, 0.4 is more preferable. On the other hand, the upper limit of this ratio is preferably 2, and more preferably 1. Further, N 2 O or the like can be used instead of CO 2 for doping oxygen atoms.
　ｐ型非晶質系半導体層１６（ｐ型非晶質系酸化ケイ素層）の積層においては、原料ガスとしては例えばＳｉＨ４、Ｈ２、Ｂ２Ｈ６及びＣＯ２の混合ガスを用いることができる。このｐ型非晶質系酸化ケイ素層の形成の際、ＳｉＨ４の流量（ｓｃｃｍ）に対するＣＯ２の流量（ｓｃｃｍ）の比（ＣＯ２／ＳｉＨ４）の下限としては、０．１が好ましく、０．４がより好ましい。一方、この比の上限としては、２が好ましく、１がより好ましい。また、酸素原子をドープするためのＣＯ２の代わりに、Ｎ２Ｏ等を用いることもできる。なお、ｐ型非晶質系半導体層１６をｐ型非晶質系シリコン層とする場合は、原料ガスとしては、例えばＳｉＨ４、Ｈ２及びＢ２Ｈ６の混合ガスを用いることができる。 In the lamination of the p-type amorphous semiconductor layer 16 (p-type amorphous silicon oxide layer), for example, a mixed gas of SiH 4 , H 2 , B 2 H 6 and CO 2 is used as the source gas. it can. In this case the p-type amorphous-based silicon oxide layer formation, the lower limit of the ratio of the flow rate of CO 2 to the flow rate of SiH 4 (sccm) (sccm) (CO 2 / SiH 4), preferably 0.1, 0.4 is more preferable. On the other hand, the upper limit of this ratio is preferably 2, and more preferably 1. Further, N 2 O or the like can be used instead of CO 2 for doping oxygen atoms. When the p-type amorphous semiconductor layer 16 is a p-type amorphous silicon layer, for example, a mixed gas of SiH 4 , H 2 and B 2 H 6 can be used as the source gas.
　第１透明導電膜１４及び第２透明導電膜１７を積層する方法としては、例えばスパッタリング法、真空蒸着法、イオンプレーティング法（反応性プラズマ蒸着法）等を挙げることができるが、スパッタリング法及びイオンプレーティング法によることが好ましい。スパッタリング法は、膜厚制御性等に優れ、また、イオンプレーティング法等に比べて低コストで行うことができる。一方、イオンプレーティング法によれば、欠陥の発生を抑制した製膜を行うことができる。 Examples of the method of laminating the first transparent conductive film 14 and the second transparent conductive film 17 include a sputtering method, a vacuum vapor deposition method, an ion plating method (reactive plasma vapor deposition method), and the like. It is preferable to use an ion plating method. The sputtering method is excellent in film thickness controllability and the like, and can be performed at a lower cost than the ion plating method. On the other hand, according to the ion plating method, film formation in which generation of defects is suppressed can be performed.
　集電極１８の配設は、公知の方法で行うことができる。集電極１８の材料として導電性接着剤が用いられている場合、スクリーン印刷やグラビアオフセット印刷等の印刷法により形成することができる。また、集電極１８に金属導線を用いる場合、導電性接着剤や低融点金属（半田等）により第１透明導電膜１４や第２透明導電膜１７上に固定することができる。 The arrangement of the collecting electrode 18 can be performed by a known method. When a conductive adhesive is used as the material of the collector electrode 18, it can be formed by a printing method such as screen printing or gravure offset printing. Further, when a metal lead is used for the collector electrode 18, it can be fixed on the first transparent conductive film 14 or the second transparent conductive film 17 with a conductive adhesive or a low melting point metal (solder or the like).
　本発明は上述した実施の形態に限定されるものではなく、本発明の要旨を変更しない範囲でその構成を変更することもできる。例えば、両面の集電極のうちの裏面側の集電極は、全面積層された金属等で形成されていてもよい。また、第１中間層や第２中間層は配設されていなくてもよい。さらに、少なくとも入射面側に透明導電膜を形成すればよく、裏面側は透明導電膜が形成されていなくてもよく、例えば金属膜等であってもよい。但し、裏面側のｐ型非晶質系半導体層外面に透明導電膜を積層することにより、欠陥準位の発生を抑制し、変換効率を高めることができる。 The present invention is not limited to the above-described embodiment, and the configuration can be changed without changing the gist of the present invention. For example, the collector electrode on the back side of the collector electrodes on both sides may be formed of a metal or the like laminated on the entire surface. Further, the first intermediate layer and the second intermediate layer may not be provided. Furthermore, a transparent conductive film may be formed at least on the incident surface side, and the transparent conductive film may not be formed on the back surface side, and may be a metal film, for example. However, by stacking a transparent conductive film on the outer surface of the p-type amorphous semiconductor layer on the back side, generation of defect levels can be suppressed and conversion efficiency can be increased.
　以下、実施例及び比較例を挙げて、本発明の内容をより具体的に説明する。なお、本発明は以下の実施例に限定されるものではない。 Hereinafter, the contents of the present invention will be described more specifically with reference to examples and comparative examples. In addition, this invention is not limited to a following example.
＜実施例１＞
　第１透明導電膜／ｎ型非晶質系半導体層／第１中間層／ｎ型結晶半導体基板／第２中間層／ｐ型非晶質系半導体層／第２透明導電膜からなる層構造体を作製した。ｎ型結晶半導体基板は、両面に無数のピラミッド形状を有する微細な凹凸構造（テクスチャー構造）が形成された単結晶シリコン基板を用いた。この凹凸構造は、約３質量％の水酸化ナトリウムを含むエッチング液に基板材料を浸漬し、基板材料の（１００）面を異方性エッチングすることにより形成した。 <Example 1>
Layer structure comprising first transparent conductive film / n-type amorphous semiconductor layer / first intermediate layer / n-type crystal semiconductor substrate / second intermediate layer / p-type amorphous semiconductor layer / second transparent conductive film Was made. As the n-type crystal semiconductor substrate, a single crystal silicon substrate having a fine concavo-convex structure (texture structure) having innumerable pyramid shapes on both surfaces was used. This concavo-convex structure was formed by immersing the substrate material in an etching solution containing about 3% by mass of sodium hydroxide and anisotropically etching the (100) plane of the substrate material.
　上記核非晶質系半導体層及び中間層は、以下の原料ガスを用いたプラズマＣＶＤ法により積層した。
ｎ型非晶質系半導体層：ＳｉＨ４、Ｈ２、ＰＨ３、及びＣＯ２
第１中間層（低ドープｎ型非晶質系半導体層）：ＳｉＨ４、Ｈ２、及びＰＨ３
第２中間層（真性非晶質系半導体層）：ＳｉＨ４、及びＨ２
ｐ型非晶質系半導体層：ＳｉＨ４、Ｈ２、Ｂ２Ｈ６、及びＣＯ２ The nuclear amorphous semiconductor layer and the intermediate layer were laminated by a plasma CVD method using the following source gas.
n-type amorphous semiconductor layer: SiH 4 , H 2 , PH 3 , and CO 2
First intermediate layer (low-doped n-type amorphous semiconductor layer): SiH 4 , H 2 , and PH 3
Second intermediate layer (intrinsic amorphous semiconductor layer): SiH 4 and H 2
p-type amorphous semiconductor layer: SiH 4 , H 2 , B 2 H 6 , and CO 2
　ｎ型非晶質系半導体層の製膜において、ＳｉＨ４の流量は５ｓｃｃｍ、ＣＯ２の流量は０．９ｓｃｃｍとした。ｐ型非晶質系半導体層の製膜において、ＳｉＨ４の流量は５ｓｃｃｍ、ＣＯ２の流量は４．１ｓｃｃｍとした。なお、得られたｐ型非晶質系半導体層において、ホウ素の原子密度は、３．５×１０２０ａｔｍ／ｃｍ３であった。また、第１中間層は、ＰＨ３の流量をＳｉＨ４基準でｎ型非晶質系半導体層の１／１０として製膜することで、低ドープｎ型非晶質系半導体層とした。各透明導電膜は、酸化錫を３質量％含有した酸化インジウムを用い、スパッタリングにより積層した。 In the formation of the n-type amorphous semiconductor layer, the flow rate of SiH 4 was 5 sccm, and the flow rate of CO 2 was 0.9 sccm. In the formation of the p-type amorphous semiconductor layer, the flow rate of SiH 4 was 5 sccm, and the flow rate of CO 2 was 4.1 sccm. In the obtained p-type amorphous semiconductor layer, the atomic density of boron was 3.5 × 10 20 atm / cm 3 . Further, the first intermediate layer was formed as a low-doped n-type amorphous semiconductor layer by forming the PH 3 flow rate as 1/10 of the n-type amorphous semiconductor layer based on SiH 4 . Each transparent conductive film was laminated by sputtering using indium oxide containing 3% by mass of tin oxide.
　次いで、各透明導電膜の外面に、集電極として、平行な複数のバスバー電極と、このバスバー電極にそれぞれ直交する複数のフィンガー電極を形成した。この集電極は、銀ペーストを用いてスクリーン印刷により形成した。これにより実施例１の光発電素子を得た。 Next, a plurality of parallel bus bar electrodes and a plurality of finger electrodes respectively orthogonal to the bus bar electrodes were formed as collector electrodes on the outer surface of each transparent conductive film. This collector electrode was formed by screen printing using a silver paste. This obtained the photovoltaic device of Example 1.
＜実施例２～４、比較例１＞
　ｎ型非晶質系半導体層の製膜において、ＣＯ２の流量を表１のとおりとしたこと以外は実施例１と同様にして、実施例２～４及び比較例１の各光発電素子を得た。 <Examples 2 to 4, Comparative Example 1>
In the formation of the n-type amorphous semiconductor layer, the photovoltaic elements of Examples 2 to 4 and Comparative Example 1 were prepared in the same manner as in Example 1 except that the flow rate of CO 2 was as shown in Table 1. Obtained.
＜実施例５＞
　ｐ型非晶質系半導体層の原料ガスとしてＳｉＨ４、Ｈ２及びＢ２Ｈ６の混合ガスを用いて、ｐ型非晶質系半導体層をｐ型シリコンにより形成したこと以外は実施例３と同様にして、実施例５の光発電素子を得た。なお、得られたｐ型非晶質系半導体層において、ホウ素の原子密度は、３．５×１０２０ａｔｍ／ｃｍ３であった。 <Example 5>
Example 3 except that a mixed gas of SiH 4 , H 2 and B 2 H 6 was used as the source gas for the p-type amorphous semiconductor layer, and the p-type amorphous semiconductor layer was formed of p-type silicon. In the same manner as described above, the photovoltaic device of Example 5 was obtained. In the obtained p-type amorphous semiconductor layer, the atomic density of boron was 3.5 × 10 20 atm / cm 3 .
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
＜評価＞ <Evaluation>
［出力特性（曲線因子）の温度依存性］
　得られた比較例１、実施例３及び実施例５の各光発電素子の出力特性の温度依存性を評価した。２５℃、４５℃及び７０℃の環境下で、曲線因子（ＦＦ）を測定した。なお、上記第１透明導電膜側を光入射面として測定を行った。結果を表２に示す。なお、各測定値は、２５℃における各光発電素子の実測値を基準（１００％）とした相対値として示している。 [Temperature dependence of output characteristics (curve factor)]
The temperature dependence of the output characteristics of the photovoltaic elements of Comparative Example 1, Example 3 and Example 5 obtained was evaluated. The fill factor (FF) was measured at 25 ° C, 45 ° C and 70 ° C. In addition, it measured by making the said 1st transparent conductive film side into a light-incidence surface. The results are shown in Table 2. In addition, each measured value is shown as a relative value based on an actual measured value of each photovoltaic device at 25 ° C. (100%).
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
　上記表２に示されるように、ｎ型非晶質系半導体層を非晶質系酸化ケイ素により形成した実施例３、５は、４５℃の高温下でも出力特性の低下が小さいことがわかる。特に、ｎ型非晶質系半導体層及びｐ型非晶質系半導体層を共に非晶質系酸化ケイ素により形成した実施例３は、７０℃の環境下でも出力特性の低下が非常に小さい。このように、本発明の光発電素子によれば、高温下においても、出力特性の低下を抑えることができることがわかる。 As shown in Table 2 above, it can be seen that in Examples 3 and 5 in which the n-type amorphous semiconductor layer was formed of amorphous silicon oxide, the decrease in output characteristics was small even at a high temperature of 45 ° C. In particular, in Example 3 in which both the n-type amorphous semiconductor layer and the p-type amorphous semiconductor layer are formed of amorphous silicon oxide, the output characteristics are very low even under an environment of 70 ° C. Thus, according to the photovoltaic device of this invention, it turns out that the fall of an output characteristic can be suppressed also under high temperature.
［出力特性（変換効率）］
　得られた実施例１～４及び比較例１の各光発電素子の変換効率（Ｅｆｆｉｃｉｅｎｃｙ）を計測した。なお、上記第１透明導電膜側を光入射面として測定を行った。結果を図２に示す。図２の横軸は、各光発電素子のｎ型非晶質系半導体層を形成する非晶質系酸化ケイ素における酸素含有率としている。この酸素含有率は、ＰＨＩ社の「ＱｕａｎｔｅｒａＳＸＭ」を用いたＸＰＳ測定により行った。上記酸素含有率は、上記表１にも示している。また、縦軸の各測定値は、比較例１を基準とした相対値として示している。 [Output characteristics (conversion efficiency)]
The conversion efficiency (Efficiency) of each of the photovoltaic devices of Examples 1 to 4 and Comparative Example 1 obtained was measured. In addition, it measured by making the said 1st transparent conductive film side into a light-incidence surface. The results are shown in FIG. The horizontal axis in FIG. 2 represents the oxygen content in the amorphous silicon oxide forming the n-type amorphous semiconductor layer of each photovoltaic device. This oxygen content was measured by XPS measurement using “Quantera SXM” manufactured by PHI. The oxygen content is also shown in Table 1 above. Each measured value on the vertical axis is shown as a relative value based on Comparative Example 1.
　図２に示されるように、ｎ型非晶質系半導体層を所定範囲の酸素含有率の非晶質系酸化ケイ素により形成することで、変換効率等を高めることができることがわかる。 As shown in FIG. 2, it can be seen that the conversion efficiency and the like can be increased by forming the n-type amorphous semiconductor layer with amorphous silicon oxide having a predetermined range of oxygen content.
　得られた比較例１、実施例２及び実施例３の光発電素子の外部量子効率（ＥＱＥ）、内部量子効率（ＩＱＥ）及び反射率（Ｒｅｆｌｅｃｔａｎｃｅ）を図３に示す。図３に示されるように、ｎ型非晶質系半導体層を非晶質系酸化ケイ素で形成した実施例２、３は、ｎ型非晶質系半導体層をケイ素で形成した比較例１と比べて３００～６００ｎｍにおける外部量子効率及び内部量子効率が高い。これより、ｎ型非晶質系酸化ケイ素は、ｎ型非晶質ケイ素に比べて、透明性が高いことがわかる。 FIG. 3 shows the external quantum efficiency (EQE), the internal quantum efficiency (IQE), and the reflectance (Reflectance) of the photovoltaic devices of Comparative Example 1, Example 2, and Example 3 obtained. As shown in FIG. 3, Examples 2 and 3 in which the n-type amorphous semiconductor layer is formed of amorphous silicon oxide are different from Comparative Example 1 in which the n-type amorphous semiconductor layer is formed of silicon. In comparison, the external quantum efficiency and the internal quantum efficiency at 300 to 600 nm are high. This shows that n-type amorphous silicon oxide has higher transparency than n-type amorphous silicon.
　本発明の光発電素子は、良好な出力特性を有し、かつその温度依存性が小さく、高温下でも良好な特性を保つことができ、太陽光発電に好適に用いることができる。 The photovoltaic device of the present invention has good output characteristics, has low temperature dependency, can maintain good characteristics even at high temperatures, and can be suitably used for photovoltaic power generation.
　１０　光発電素子
　１１　ｎ型結晶半導体基板
　１２　第１中間層
　１３　ｎ型非晶質系半導体層
　１４　第１透明導電膜
　１５　第２中間膜
　１６　ｐ型非晶質系半導体層
　１７　第２透明導電膜
　１８　集電極 DESCRIPTION OF SYMBOLS 10 Photovoltaic element 11 N-type crystal semiconductor substrate 12 1st intermediate | middle layer 13 n-type amorphous semiconductor layer 14 1st transparent conductive film 15 2nd intermediate film 16 p-type amorphous semiconductor layer 17 2nd transparent conductive film 18 Current collector

Claims (6)

  1. 　ｎ型結晶半導体基板、このｎ型結晶半導体基板の光入射面側に積層されるｎ型非晶質系半導体層、及び上記ｎ型結晶半導体基板の光入射面側とは反対面側に積層されるｐ型非晶質系半導体層を備える光発電素子であって、
    　上記ｎ型非晶質系半導体層を形成する半導体材料が、ｎ型の非晶質系酸化ケイ素であることを特徴とする光発電素子。     An n-type crystal semiconductor substrate, an n-type amorphous semiconductor layer stacked on the light incident surface side of the n-type crystal semiconductor substrate, and a surface opposite to the light incident surface side of the n-type crystal semiconductor substrate are stacked. A photovoltaic device comprising a p-type amorphous semiconductor layer,
    A photovoltaic element, wherein the semiconductor material forming the n-type amorphous semiconductor layer is n-type amorphous silicon oxide.
  2. 　上記非晶質系酸化ケイ素が、Ｓｉ１－ｘＯｘ（０．０１≦ｘ≦０．１２）で表される請求項１に記載の光発電素子。 The photovoltaic device according to claim 1, wherein the amorphous silicon oxide is represented by Si 1-x O x (0.01 ≦ x ≦ 0.12).
  3. 　上記ｐ型非晶質系半導体層を形成する半導体材料が、ｐ型の非晶質系酸化ケイ素である請求項１又は請求項２に記載の光発電素子。 3. The photovoltaic device according to claim 1, wherein the semiconductor material forming the p-type amorphous semiconductor layer is p-type amorphous silicon oxide.
  4. 　上記ｎ型結晶半導体基板とｎ型非晶質系半導体層との間に介在する第１中間層をさらに備え、
    　上記第１中間層が、真性非晶質系半導体、又はｎ型非晶質系半導体から形成されている請求項１、請求項２又は請求項３に記載の光発電素子。     A first intermediate layer interposed between the n-type crystal semiconductor substrate and the n-type amorphous semiconductor layer;
    The photovoltaic device according to claim 1, wherein the first intermediate layer is formed of an intrinsic amorphous semiconductor or an n-type amorphous semiconductor.
  5. 　上記第１中間層が、上記ｎ型非晶質系半導体層よりもドープ量が少ないｎ型非晶質系半導体層である請求項４に記載の光発電素子。 The photovoltaic element according to claim 4, wherein the first intermediate layer is an n-type amorphous semiconductor layer having a smaller doping amount than the n-type amorphous semiconductor layer.
  6. 　上記ｎ型結晶半導体基板とｐ型非晶質系半導体層との間に介在する第２中間層をさらに備え、
    　上記第２中間層が、真性非晶質系半導体から形成されている請求項１から請求項５のいずれか１項に記載の光発電素子。
          A second intermediate layer interposed between the n-type crystal semiconductor substrate and the p-type amorphous semiconductor layer;
    The photovoltaic device according to any one of claims 1 to 5, wherein the second intermediate layer is formed of an intrinsic amorphous semiconductor.
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