WO2017126002A1

WO2017126002A1 - Common mode filter

Info

Publication number: WO2017126002A1
Application number: PCT/JP2016/051246
Authority: WO
Inventors: 雅明亀谷
Original assignee: 松江エルメック株式会社
Priority date: 2016-01-18
Filing date: 2016-01-18
Publication date: 2017-07-27

Abstract

[Problem] To suppress reflection of common mode noise and enable sufficient removal of common mode noise of 10 GHz and higher. [Solution] A signal coil 1A, which is inserted into one differential signal line, is formed on a layer among a plurality of dielectric layers 11A-11C. A signal coil 1B, which is inserted into another differential signal line, is formed so as to face the signal coil 1A with a dielectric layer therebetween on a layer among the dielectric layers 11A-11C. A control coil 3, which is superimposed with the signal coils 1A, 1B, is formed on a layer among the dielectric layers 11A-11C with dielectric layers interposed between the control coil 3 and the first and second signal coils 1A, 1B. The control coil 3 is bisected into a starting-point-side divided control coil 3A and an end-point-side divided control coil 3B. A four-terminal circuit is connected between a pair of terminals of the starting point of the divided control coil 3A and the ground, and a pair of terminals of the end point of the divided control coil 3B and the ground.

Description

Common mode filter

The present invention relates to a common mode filter, and more particularly to a novel common mode filter capable of suppressing reflection of common mode noise and adjusting common mode rejection characteristics.

Conventionally, a common mode choke coil has been widely used as an electronic component for removing common mode noise in a transmission line for ultra high-speed differential signals.

The common mode noise elimination principle of the common mode choke coil uses a magnetic coupling such as a coil wound with a conductive wire or a spiral coil printed on a flat surface to generate a high series impedance with respect to the common mode signal. Noise is reflected to the input side and not propagated to the previous circuit.

However, since stray capacitance exists between the coil conductors, high-frequency common mode noise bypasses the high-impedance coil and propagates to the output side via this stray capacitance.

Therefore, in the conventional common mode choke coil, the common mode removal capability is particularly easily deteriorated particularly at a frequency of 10 GHz or more.

Furthermore, the method of preventing the propagation to the output side by reflecting the common mode noise to the input side is conductive because the noise is difficult to radiate if the frequency of the transmission signal is low and the circuit pattern is difficult to become an antenna. It is only necessary to remove noise, and noise emission is not a problem.

However, in a device that transmits an ultra-high-speed differential signal in the GHz band, the circuit pattern is likely to be an antenna, so that the own circuit is likely to malfunction due to radioactive noise generated from the own circuit.

Therefore, in ultra high-speed differential signal transmission in the GHz band, it is not preferable to reflect noise with a common mode choke coil.

In order to avoid such a problem, it is effective to reduce reflection by letting common mode noise escape to the ground (common potential: earth). In order to meet such a purpose, common mode filters such as Patent Document 1 (Japanese Patent Laid-Open No. 2009-10729) and Patent Document 2 (WO / 2015/181833) are disclosed.

These common mode filters have the idea of inducing common mode noise in a control coil coupled to a signal coil and letting it escape to ground.

JP 2009-10729 A WO / 2015/181833 publication

However, the common mode filter shown in Patent Document 1 has a configuration in which two signal coils through which a differential signal passes are opposed to each other, and a control coil is disposed and coupled to both outer sides of the signal coils. It tends to adversely affect the signal passing characteristics.

Furthermore, since only one end of the control coil is connected to the ground, there is a difference in the reflection removal ability depending on whether noise comes from the input side or the output side. There is a problem of becoming a so-called directional filter.

On the other hand, the common mode filter shown in Patent Document 2 is configured as shown in the equivalent circuit of FIG. 11. Based on this configuration, the common mode filter is virtually considered for 10 Gbit / second transmission, The analysis result of the modeled one is as shown in FIG.

In FIG. 12, Scc11 is the reflection characteristic of the common mode signal at the input terminals 21A and 21B, Scc22 is the reflection characteristic of the common mode signal at the output terminals 23A and 23B, and Scc21 is the transmission characteristic of the common mode signal. Means.

In FIG. 12A, the resistances R1 and R2 are infinite, that is, the control coil 3 is in a floating state, but the characteristics are hardly changed even if the control coil 3 is removed as it is. That is, it has the same configuration as a general common mode choke coil.

The reflection characteristic Scc11 is approximately 0 dB, and the input common mode signal is in a state of total reflection returning to the input terminals 21A and 21B without being attenuated. The pass characteristic Scc21 achieves a large attenuation of about -25 dB at around 5 GHz, but is about -3 dB at around 15 GHz, and the attenuation is very small. Shows typical characteristics.

FIG. 12B shows the characteristics when the resistors R1 and R2 are set to 60Ω. If the resistances R1 and R2 are set to appropriate values, the pass characteristic Scc21 can secure an attenuation of about −10 dB around 15 GHz. . However, at the same time, Scc21 is -15 dB at 5 GHz, and the attenuation is reduced.

FIG. 12 (C) shows an example in which the resistor R1 is 25Ω and the resistor R2 is infinite, that is, open, and the technique of ground connection only at one end shown in Patent Document 1 is applied to Patent Document 2.

In this way, Scc11 can achieve a significant reflection reduction of -20 dB at 2.5 GHz. Scc21 is about -7.5 dB at around 15 GHz, and a slight improvement is realized as compared with FIG.

However, in Patent Document 2, since the characteristics are different between Scc11 and Scc22 as described above, the reflection characteristics become directional and usability is deteriorated. Moreover, at the frequency at which Scc21 is minimum, that is, the noise removal peak frequency of 5 GHz, Scc11 is about −4 dB, and the reflection does not attenuate so much, and the noise removal peak frequency does not match the reflection reduction frequency.

Further, Patent Document 2 shows that Scc21 does not significantly improve the characteristics of the general common mode choke coil shown in FIG. 12A, and only one end of the control coil is connected to the ground. Therefore, there is no characteristic improvement method other than adjusting the value of the resistor R1 as an optimization method, and the options for characteristic improvement are narrow.

The present invention has been made to solve such problems, and provides a common mode filter capable of suppressing reflection of common mode noise and sufficiently removing common mode noise of 10 GHz or more.

In order to solve such a problem, a common mode filter according to claim 1 of the present invention is formed in a spiral shape in a multilayer dielectric layer, and is inserted and connected in series in a differential signal line of one polarity. The first signal coil is formed in a spiral shape so as to face the first signal coil through the dielectric layer so as to overlap the first signal coil in the thickness direction in the dielectric layer. Formed in a spiral shape so as to be sandwiched between the second signal coil inserted and connected in series in the signal line and the first and second signal coils via the dielectric layer, The control coil is wound in the same direction as the first signal coil and controls the magnetic coupling and coupling capacity between the first and second signal coils. It is divided at one point between the end point and A four-terminal circuit is connected between the terminal pair formed by the start point of the division control coil on the start point side and the ground and the terminal pair formed by the end point of the division control coil on the end point side and the terminal pair formed by the ground. It is a configuration.

In the common mode filter according to claim 2 of the present invention, the four-terminal circuit network includes a π-type or T-type resistor network.

In the common mode filter according to claim 1 of the present invention, a first signal coil inserted and connected in series in a differential signal line of one polarity in a multilayer dielectric layer, and the first signal coil A second signal coil which faces the signal coil in a shape overlapping in the thickness direction and is inserted and connected in series in the differential signal line of the other polarity; and the first and second signal coils For controlling the magnetic coupling and coupling capacitance between the first signal coil and the second signal coil, which are sandwiched between the first signal coil and the first signal coil. The control coil is divided at one point between the start point and the end point of the control coil, and the terminal pair formed by the start point and the ground, and the terminal pair formed by the end point and the ground Since a 4-terminal circuit is connected to Suppressing reflection mode noise can be sufficiently removed common mode noise above 10 GHz.

In the common mode filter according to claim 2 of the present invention, since the four-terminal circuit network includes a π-type or T-type resistor network, it is easy to optimize the common-mode noise removal characteristics.

It is a disassembled perspective view which shows the basic composition of the common mode filter which concerns on this invention. It is an external view of the common mode filter of FIG. FIG. 2 is an equivalent circuit diagram of the common mode filter of FIG. 1. It is a frequency characteristic of the common mode filter of FIG. It is a frequency characteristic of the common mode filter of FIG. FIG. 2 is a line pattern diagram of the common mode filter of FIG. 1. It is an equivalent circuit schematic explaining other embodiment of the common mode filter which concerns on this invention. It is an equivalent circuit schematic explaining other embodiment of the common mode filter which concerns on this invention. It is an equivalent circuit schematic explaining other embodiment of the common mode filter which concerns on this invention. It is another external view of the common mode filter according to the present invention. It is an equivalent circuit diagram of a conventional common mode filter. It is a frequency characteristic figure of the conventional common mode filter.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is an exploded perspective view showing a basic configuration of a common mode filter F according to the present invention.

The dielectric layer 11A has a signal coil (first signal coil) 1A, the dielectric layer 11C has a signal coil (second signal coil) 1B, and the dielectric layer 11B has a control coil 3 Is formed.

These dielectric layers 11A to 11C are formed of a known laminated ceramic having substantially the same shape as a rectangular thin plate, a resin substrate such as polyimide or glass epoxy, or an insulating film for a semiconductor such as silicon dioxide or silicon nitride. The layers 11B are stacked so as to be sandwiched between the dielectric layers 11A and 11C.

The signal coils 1A and 1B and the control coil 3 are formed on one side of each of the dielectric layers 11A to 11C by, for example, a thin film photolithography, damascene process, thick film printing, etching, or the like from a known conductive material. It is formed in a shape.

The control coil 3 is sandwiched between the signal coil 1A and the signal coil 1B in the stacking (thickness) direction of the dielectric layers 11A to 11C, and is disposed at the center position between the signal coil 1A and the signal coil 1B. Has been.

The signal coil 1A and the signal coil 1B are formed with the same winding direction, the same line width, and the same inter-line space, and when viewed from the thickness direction, the line portions excluding both end portions are misprinted or misaligned. It is formed so as to overlap within the error range. That is, the signal coils 1 A and 1 B are wired so that the line portions except for both end portions substantially overlap.

The dielectric layers 11D and 11F are formed, for example, from the same material and in the same shape as the dielectric layers 11A to 11C, and the dielectric layer 11D is superimposed on the dielectric layer 11C on the side opposite to the dielectric layer 11B. The body layer 11E is superimposed on the dielectric layer 11A on the side opposite to the dielectric layer 11B.

The outer peripheral end of the signal coil 1A is led out to the end face of the dielectric layer 11A via the input side lead wire 15A formed on the same surface of the dielectric layer 11A, and is connected to the input terminal 21A shown in FIG. .

In FIG. 2, the dielectric layers 11A to 11C, the dielectric layers 11D and 11E, and cover layers 13A and 13B described later are stacked.

The inner peripheral end of the signal coil 1A is led out to the dielectric layer 11D through the via 9A formed in the dielectric layers 11A, 11B, and 11C, and formed on one surface of the dielectric layer 11D facing the dielectric layer 11C. Is connected to the output lead wire 17A. The output lead line 17A is led out to the end face of the dielectric layer 11D and is connected to the output terminal 23A shown in FIG.

The outer peripheral end of the signal coil 1B is led out to the end surface of the dielectric layer 11C via the input side lead wire 15B formed on the same surface of the dielectric layer 11C so as not to overlap the input side lead wire 15A. It is connected to the input terminal 21B inside.

The inner peripheral end of the signal coil 1B is led out to the dielectric layer 11D through the via 9B formed in the dielectric layer 11C, and is different from this on the same surface as the output lead line 17A in the dielectric layer 11D. It is connected to the output side lead wire 17B formed at the position. The output lead line 17B is led out to the end face of the dielectric layer 11D and connected to the output terminal 23B in FIG.

The control coil 3 is formed in the same winding direction as the signal coils 1A and 1B, and is not necessarily the same line width and the same inter-line space as the signal coils 1A and 1B. However, the pitch is the same as that of the signal coils 1A and 1B.

The control coil 3 is divided into two parts at a dividing point 7 which is approximately the middle (1/2) position of the line length from the start point 5A (outer peripheral end) to the end point 5B (inner peripheral end).

The starting point 5A of the control coil 3 is led to the dielectric layer 11D through the vias 9C formed in the dielectric layers 11B and 11C, and these are on the same surface as the output lead lines 17A and 17B in the dielectric layer 11D. Is connected to a resistance connection pad 19A formed at a different position.

A resistor connection pad 19B is formed in the vicinity of the resistor connection pad 19A on the same surface as the resistor connection pad 19A in the dielectric layer 11D, and this is led out to the end surface of the dielectric layer 11D, and the control terminal 25A in FIG. It is connected to the.

The end point 5B of the control coil 3 is led to the dielectric layer 11D through the vias 9D formed in the dielectric layers 11B and 11C, and is provided in the dielectric layer 11D with the output side lead wires 17A and 17B and the resistance connection pad 19A. , 19B are connected to a resistance connection pad 19C formed at a position different from the same surface as that of 19B. The resistance connection pad 19C is located in the vicinity of the resistance connection pad 19A.

On the same surface as the resistance connection pad 19C in the dielectric layer 11D, a resistance connection pad 19D is formed in the vicinity of the resistance connection pad 19C, and this leads to the end surface of the dielectric layer 11D in the direction opposite to the resistance connection pad 19B. And connected to the control terminal 25B in FIG.

A resistor R1 is connected between the resistor connection pads 19A and 19C, a resistor R2 is connected between the resistor connection pads 19B and 19D, and a resistor R3 is connected between the resistor connection pads 19C and 19D.

These resistors R1 to R3 are passive elements that terminate the electric power induced in the control coil 3, and are printed by a resistance paste, a resistive metal thin film such as nichrome, or a resin substrate with a built-in resistor. Is formed.

The dielectric layers 11A to 11D are stacked, and the cover layer 13A is stacked on the dielectric layer 11A on the side opposite to the dielectric layer 11B, and the cover is provided on the dielectric layer 11D on the side opposite to the dielectric layer 11C. Layer 13B is laminated and integrated as shown in FIG. 2, for example, by baking.

When the cover layers 13A and 13B are magnetic materials, the dielectric layers 11A to 11E are laminated and fired to become the first solid, and the cover layers 13A and 13B are bonded and integrated on the solid.

When the cover layers 13A and 13B are dielectrics, the cover layers 13A and 13B are arranged above and below the dielectric layers 11A to 11E, and are laminated and fired to be integrated.

The common mode filter F integrated by any one of these methods has input terminals 21A and 21B as external terminal electrodes connected to the input lead wires 15A and 15B formed on one outer peripheral side surface, and the other facing the other. The output terminals 23A and 23B to which the output side lead wires 17A and 17B as external terminal electrodes are connected are formed on the outer peripheral side surface of the, thereby constituting a finished chip component.

The common mode filter F is mounted on a printed wiring board or the like, and as shown in FIG. 2, between the differential lines 27A and the differential lines 27B that are formed on the printed wiring board and cut along the way. The terminals 21A and 21B and the output terminals 23A and 23B are connected together.

That is, the input terminal 21A and the output terminal 23A of the common mode filter F are inserted and connected in series in the differential signal line 27A of one polarity, and the input terminal 21B and the output terminal 23B are the differential signal of the other polarity. The line 27B is inserted and connected in series.

The printed wiring board or the like is provided with ground pads 29A and 29B that match the control terminals 25A and 25B, and these control terminals 25A and 25B are connected to a ground (not shown).

3 is an equivalent circuit of the common mode filter F of FIG. From the viewpoint of maintaining symmetry between the two differential lines, the coupling capacitor 31A formed between the signal coil 1A and the control coil 3 with the dielectric layer 11A interposed therebetween, and the signal coil 1B with the dielectric layer 11B interposed therebetween. And the coupling capacitor 31B formed between the control coil 3 and the control coil 3 are preferably equal.

Therefore, the control coil 3 is preferably formed at the center layer position between the signal coils 1A and 1B, and the dielectric layer 11A and the dielectric layer 11B are preferably made of the same material and the same layer thickness.

In such a configuration, when the average potential of the signal coils 1A and 1B is applied to the control coil 3 and a differential signal is input to the signal coils 1A and 1B, the positive and negative potentials are Since the average potential is zero, the control coil 3 cannot be seen from the differential signal.

On the other hand, for the common mode signal, the signal coils 1A and 1B are both positive or negative at the same time, and the intermediate potential does not become “zero”, so that the electromagnetic field reaches the control coil 3; An induced electromotive force is generated in the control coil 3.

In the control coil 3, a resistor R1 is connected between the start point 5A of the split control coil 3A including the start point 5A and the ground, and a resistor R2 is connected between the end point 5B of the split control coil 3B including the end point 5B and the ground. Are connected, and both terminals (start point 5A, end point 5B) are connected by a resistor R3.

That is, between the start point 5A of the split control coil 3A on the start point 5A side and the terminal pair formed by the ground, and the terminal pair formed by the end point 5B of the split control coil 3B on the end point 5B side and the ground. For example, a π-type four-terminal circuit 33 formed of resistors R1 to R3 is connected.

And, the control coil 3 is not formed with a feedback circuit to the ground or a closed loop circuit by the resistor R3 due to the presence of the dividing portion 7.

However, the current due to the induced electromotive force generated in the control coil 3 is fed back to the ground, and is consumed by the resistors R1 and R2 that pass therethrough. As a result, the common mode noise is absorbed and removed.

In FIG. 3, the control coil 3 and its terminal connection are indicated by solid lines for easy understanding. In the subsequent equivalent circuits, only the solid line circuit portion is displayed.

FIG. 4 shows frequency characteristics when the common mode filter F shown in FIG. 1 is designed for 10 Gbit / sec and subjected to electromagnetic field simulation.

In this example, the line width of the signal coils 1A and 1B is 15 μm, the space between the lines is also 15 μm, the outer dimensions of the dielectric 11A are 0.85 mm in the direction between the control terminals 25A and 25B, the input terminal 21A, Wiring was performed in an area of 0.65 mm in the direction between 21B and the output terminals 23A and 23B.

There are two types of control coils 3. The first is a shape in which the line of the control coil 3 completely overlaps that of the signal coils 1 A and 1 B. The second is the signal coil in the center of the line of the control coil 3. Although it coincides with the centers of 1A and 1B, the line width is 25 μm, the space between lines is 5 μm, and the area where the control coil 3 is formed is substantially filled with the conductor. In both cases, the cutting length of the dividing portion 7 is 40 μm.

4A is a frequency characteristic with respect to a differential signal, Sdd11 is a reflection characteristic at the input terminals 21A and 21B, Sdd21 is a differential signal passing characteristic from the input terminals 21A and 21B to the output terminals 23A and 23B, and FIG. (B) and (C) are frequency characteristics with respect to the common mode, Scc11 is the common mode reflection characteristic at the input terminals 21A and 21B, Scc22 is the common mode reflection characteristic at the output terminals 23A and 23B, and Scc21 is from the input terminals 21A and 21B. This is a common mode pass characteristic to the output terminals 23A and 23B.

Since the control coil 3 is not visible from the differential signal, this characteristic is obtained regardless of the line width of the control coil 3 or the space between the lines. Therefore, the characteristic for the differential signal is omitted in the subsequent characteristic display.

As shown in the frequency characteristic of the differential signal shown in FIG. 4A, Sdd11 shows a very low reflection of -15 dB or less in a wide band of 15 GHz or less, and Sdd21 has a passband of -3 dB of about 15 GHz and 10 Gbit / sec. This signal is passed without distortion.

FIG. 4B shows frequency characteristics with respect to the common mode when the line width of the control coil 3 is 15 μm, the space between the lines is 15 μm, the resistors R1 = R2 = 20Ω, and R3 = 50Ω.

The pass characteristic Scc21 shows a maximum attenuation of about −29 dB at 2.6 GHz, that is, a noise removal peak, and shows a sufficient common mode removal capability of about −19 dB even at 5 GHz which is a clock frequency of 10 Gbit / second, In the conventional example, it is shown that the frequency range of 10 G to 16 Hz in which the removal characteristics are rapidly deteriorated is −12 dB or less.

Comparing such characteristic characteristics with the characteristic diagram shown in FIG. 12A, which is a conventional example, the characteristic shown in FIG. It can be seen that the mode removal capability is averaged over a wide band.

Since the noise can be sufficiently removed if the passage of the common mode noise is suppressed to −20 dB or less, a large attenuation pole at a specific frequency as shown in FIG. Rather, the characteristic that suppresses the passage in a wide band on average as shown in FIG. 4B has a certain removal capability for noise generated at any frequency, so that the usability is improved.

Also, the reflection characteristics Scc11 and Scc22 show a large resonance-like attenuation characteristic of about −15 dB at 4 to 5 GHz, and it is shown that the reflection of the common mode noise removed near the noise removal peak frequency of 5 GHz can be suppressed. The reason why the peak frequencies of attenuation do not completely match between Scc11 and Scc22 is that the dividing point 7 is slightly shifted from the accurate intermediate position between the start point 5A and the end point 5B in terms of electrical length.

On the other hand, in FIG. 12 (C), only Scc11 has a resonance attenuation pole, but it is far from the noise removal peak frequency of 5 GHz and is almost half of 2.5 GHz. That is, the phenomenon that the resonance frequency is halved because the line length is doubled has occurred. Presuming from this phenomenon, it is considered that the control coil 3 functions as a kind of receiving antenna.

Therefore, it can be said that it is not desirable to open the one end of the control coil 3 more efficiently because it can induce common mode noise more efficiently.

Although not shown, when analyzing the characteristics of FIG. 12, the conventional configuration is the same as FIG. 1 except that the control coil 3 is not divided and there is no R3. That is, the difference in characteristics between FIG. 4B and FIG. 12 comes from the presence / absence of the division of the control coil 3 and the values of the resistors R1, R2 and R3 in FIG.

FIG. 4C shows frequency characteristics with respect to the common mode when the line width is 25 μm, the space between lines is 5 μm, the resistances R1 = R2 = 50Ω, and R3 = 100Ω. The characteristics slightly change, and the noise removal capability is improved at a value lower than the characteristics shown in FIG. 4B at Scc21 of 2.6 G to 9 GHz.

However, as mentioned above, Scc21 of −20 dB or less is more than necessary noise removal capability. On the other hand, at 12.5 GHz, since the amount of passage is slightly larger than the characteristic shown in FIG. 4B, the overall common mode removal capability is slightly deteriorated.

On the other hand, although not shown, when the line width of the control coil 3 is 5 μm, the space between the lines is 25 μm, and narrower than the line widths of the signal lines 1A and 1B, substantially the same characteristics as FIG. 4B are obtained. It is done.

From the above, the line width of the control coil 3 is preferably equal to or smaller than the line width of the signal coils 1A and 1B, but even if it is equal to or larger than the line width of the signal coils 1A and 1B, as shown in FIG. It is possible to obtain a sufficiently practical common mode filter F. Therefore, it can be said that the line width of the control coil 3 is not so important.

FIG. 5 shows the ratio of the reflected power, the passing ratio, and the internal absorption removal ratio of Scc11 and Scc21 in FIG. 4 when the common mode noise is input to the common mode filter F and the input power is 100%. It is calculated from the characteristics.

The graph calculated from FIG. 4 (B) is FIG. 5 (B), and the graph calculated from FIG. 4 (C) is FIG. 5 (C). As shown in the figure, it can be seen that about 95% of common mode power is absorbed at 5 GHz. FIG. 5 is shown corresponding to FIGS. 4B and 4C.

The configuration described above is a case where the signal coils 1A and 1B and the control coil 3 are all overlapped by the center line in the line length direction, and the cutting length at the dividing point 7 is 40 μm.

However, in an actual product, these center lines do not always overlap in the thickness direction due to printing misalignment or stacking misalignment.

In view of this, when the allowable value of the coil deviation for obtaining the desired characteristics is verified in the present invention, although not shown, at least the control coil is seen when viewed from above with the dielectric layers 11A to 11D being superimposed. It can be said that there is no problem as long as the amount of deviation is such that the center line in the line direction of 3 is within the line width of the signal coils 1A, 1B.

FIG. 6 is a view of the conductor pattern of the control coil 3 as viewed from the upper surface (dielectric layer 11B side) of the dielectric layer 11C.

Further, the pattern of the signal coil 1B in contact with the opposite surface of the dielectric layer 11C is displayed as shown in a perspective view (broken line).

In FIG. 6, the line center line of the control coil 3 is intentionally arranged at an intermediate position in the space between the lines of the signal coil 1 B (1 A), but even in this case, the common mode noise improved over the conventional example It is possible to obtain removal characteristics.

What is important is that the circular pitch of the control coil 3 matches the circular pitch of the signal coils 1A and 1B. If this does not match, not only the improvement of the common mode noise removal characteristic is not expected, but there is a possibility that the differential signal passing characteristic may be deteriorated, which is not desirable.

Therefore, when designing a printing mask for forming the signal coils 1A and 1B and the control coil 3, it is ensured in the process if they are printed and stacked so that their circumferential pitches coincide and overlap in the thickness direction as much as possible. Desired characteristics can be obtained even if a positional deviation within a certain range occurs.

Further, the minimum value of the cutting length of the dividing point 7 of the control coil 3 is the same as the gap that can be realized in the manufacturing process, that is, the minimum inter-line space in many cases. Although not shown, even if the cutting length of the control coil 3 is reduced from 40 μm to 5 μm in the configuration of FIG.

On the contrary, even when the dividing part 7 is spread on both sides and the cutting length becomes one side of the control coil 3, there is no significant change in the characteristics. As the total length of the control coil 3 is shortened, the noise removal peak frequency of Scc21 and the reflection attenuation peak frequencies of Scc11 and Scc22 are shifted slightly to the high range.

In the embodiment described above, the control coil 3 is of course arranged at an intermediate position between the signal coils 1A and 1B in order to maintain symmetry between the two lines with respect to the differential signal. Furthermore, the dielectrics 11A to 11C must be made of the same material, and the cover layers 13A and 13B and the dielectrics 11D and 11E are made of the same material as the dielectrics 11A to 11C.

If the cover layers 13A and 13B are made of a magnetic material, they are magnetically shielded and a stable operation is realized. However, in this embodiment, the cover layer 13A can be incorporated in a semiconductor package or a semiconductor chip so that it can be incorporated in a semiconductor package or a semiconductor chip. , 13B are all described as dielectrics.

By the way, as shown in FIG. 7, the four-terminal circuit 33 described above connects a series circuit of resistors R1 and R2 between the start point 5A of the split control coil 3A and the end point 5B of the split control coil 3B, and the resistor R1 and It is also possible to form a T-type resistor network in which a resistor 3 is connected between the connection point of R2 and the ground.

As shown in FIG. 8, the four-terminal circuit 33 connects a series circuit of resistors R1, R3, and R2 between the start point 5A of the split control coil 3A and the end point 5B of the split control coil 3B, and the resistor R1 It is also possible to form a ladder-type resistor network in which the resistor R4 is connected between the connection point of R3 and the ground, and the resistor R5 is connected between the connection point of the resistors R3 and R2 and the ground.

Further, as shown in FIG. 9, the four-terminal circuit 33 connects only the resistor R1 between the starting point 5A of the split control coil 3A and the ground, and only the resistor R2 between the end point 5B of the split control coil 3B and the ground. In other words, a configuration in which the resistor R3 is infinite in FIG. 3 is possible, and a configuration that can be said to be a modification of the π-type network is also possible.

In the present invention, the important point is that one terminal pair of the four-terminal circuit 33 is connected between the start point of the split control coil 3A having the start point and the ground, and the end point and ground of the split control coil 3B having the end point are connected. If the other terminal pair of the four-terminal circuit 33 is connected between each other, the object of the present invention can be achieved.

Further, although not shown, the four-terminal circuit 33 can adjust the pass characteristics of the common mode Scc21 even with a π-type, T-type, or ladder-type network using resistors and capacitors or resistors and inductors.

Thus, the four-terminal circuit 33 can construct an infinite circuit configuration, and among them, a circuit network formed so as to include a π-type or T-type resistance network is most desirable.

In the configuration of FIG. 1 described above, an example in which the resistors R1, R2, and R3 are all incorporated in the dielectric layer 11D is illustrated.

However, these resistors R1 to R3 are not necessarily built in the common mode filter F. For example, in FIG. 1, the resistors R1 and R2 are “zero Ω”, that is, the resistors are omitted and connected by a conductor, and the control terminal 25A The terminal on the outer peripheral side of the control coil 3 may be directly connected to the control terminal 25B, and the terminal on the inner peripheral side of the control coil 3 may be directly connected to the control terminal 25B.

In this case, as shown in FIG. 10, the passive circuit 35A is connected as an external component between the ground pad 29A and the ground, and the passive circuit 35B is connected as an external component between the ground pad 29B and the ground. The characteristics of the common mode filter F can be freely adjusted.

Of course, it is possible to connect the resistor R3 between the ground pads 29A and 29B as an external component by removing the resistor R3 infinitely, that is, removing the resistor R3.

Thus, the passive circuits 35A and 35B connected to the terminal of the control coil 3 can be external components. If the external configuration is adopted, it is possible to prevent an increase in the dielectric layer or the like containing the inductor, capacitor, etc., and it is difficult to increase the cost of the common mode filter F, and a desired combination of resistors, inductors and capacitors can be freely combined. There is also an advantage that the characteristics can be adjusted.

In the above-described embodiment, the configuration having the input terminals 21A and 21B, the output terminals 23A and 23B, and the control terminals 25A and 25B has been described. However, in the common mode filter F of the present invention, those external terminal electrodes can be omitted, that is, only the internal elements can be incorporated in a semiconductor package such as a printed wiring board or an interposer, or a semiconductor die. .

1A Signal coil (first signal coil)
1B Signal coil (second signal coil)
3 Control coils 3A, 3B Split control coil (control coil)
5A Start point 5B End point 7 Dividing point 9, 9A, 9B, 9C, 9D Via 11A, 11B, 11C, 11D Dielectric layer 13A, 13B Cover layer 15A, 15B Input side lead wire 17A, 17B Output side lead wire 19A, 19B, 19C, 19D Resistance connection pads 21A, 21B Input terminals 23A, 23B Output terminals 25A, 25B Control terminals 27A, 27B Differential lines 29A, 29B Ground pads 31A, 31B Coupling capacitors 33 4-terminal circuits 35A, 35B Passive circuit F Common mode filter R1, R2, R3, R4, R5 resistors (4-terminal circuit)

Claims

A first signal coil formed in a spiral shape in a multilayer dielectric layer and inserted and connected in series in a differential signal line of one polarity;
In the dielectric layer, it is formed in a spiral shape so as to face the first signal coil through the dielectric layer so as to overlap with the first signal coil, and in series in the differential signal line of the other polarity A second signal coil to be inserted and connected;
It is formed in a spiral shape so as to be sandwiched between the first and second signal coils via the dielectric layer, wound in the same direction as the first signal coil, and And a control coil for controlling the magnetic coupling and coupling capacitance between the second signal coil,
Comprising
The control coil is divided at one point between the start point and the end point, and four terminals are formed between the terminal pair formed by the start point and the ground and the terminal pair formed by the end point and the ground. A common mode filter characterized in that a circuit is connected.
The common mode filter according to claim 1, wherein the four-terminal circuit includes a π-type or T-type resistance network.